JP2966740B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device provided with a color filter and a method for driving the solid-state image pickup device.

[0002]

2. Description of the Related Art In an imaging apparatus such as a television camera using a CCD solid-state imaging device, each scanning timing of the solid-state imaging device is set based on a synchronization signal according to a predetermined television system, and a video signal having a predetermined format is output. Taken out. For example, in the case of the NTSC system, the vertical scanning period is set to 1/60 second, the horizontal scanning period is set to 2/525 of the vertical scanning period, and a video signal in which video information is continuous in one horizontal scanning period is output. Is done.

FIG. 7 is a block diagram showing a configuration of an image pickup apparatus using a frame transfer type CCD solid-state image pickup device.
The solid-state imaging device 1 includes an imaging unit 1a that receives information from a subject and generates information charges, a storage unit 1b that temporarily stores information charges, a horizontal transfer unit 1c that transfers and outputs information charges in a horizontal direction, and An output unit 1d converts the information charge amount into a voltage value and outputs the voltage value. Frame transfer clock generation circuit 2
Generates a frame transfer clock φF in synchronization with the vertical scanning timing, supplies the frame transfer clock φF to the imaging unit 1a of the solid-state imaging device 1, and accumulates information charges of the imaging unit 1a for each screen within a vertical scanning retrace period. Transfer to section 1b. The vertical transfer clock generation circuit 3 generates a vertical transfer clock φV in synchronization with the horizontal scanning timing, supplies the vertical transfer clock φV to the storage section 1b of the solid-state imaging device 1, and transfers the information charges in the storage section 1b to the horizontal scanning for each row. The data is transferred to the horizontal transfer unit 1c within the retrace period. The horizontal transfer clock generation circuit 4 generates a horizontal transfer clock φH in synchronization with the horizontal scanning timing, supplies the horizontal transfer clock φH to the horizontal transfer unit 1c, and transfers the information charges for one row transferred from the storage unit 1b within the horizontal scan period. To transfer and output to the output unit 1d. The timing control circuit 5 generates a timing signal of a vertical scanning cycle and a horizontal scanning cycle based on the reference clock CK, and supplies the timing signal to each of the clock generation circuits 2, 3, and 4. As a result, the information charges generated in the imaging unit 1a are transferred to the accumulation unit 1b and accumulated in one screen unit at the timing of the start of the vertical scanning period.
Then, the data is transferred from the storage unit 1b to the horizontal transfer unit 1c in units of one row at the timing of the start of the horizontal scanning period, and transferred from the horizontal transfer unit 1c to the output unit 1d one bit at a time.

The reset clock generation circuit 6 generates a reset clock φR in synchronization with the operation of the horizontal transfer clock generation circuit 4 and supplies the reset clock φR to the output section 1 d of the solid-state imaging device 1. The output section 1d is provided with a diffusion region which is electrically independent of another region called a floating diffusion, and the information charges accumulated in this diffusion region are transferred to a charge discharging drain in response to a reset clock φR. Is discharged. That is, since the output unit 1d accumulates information charges transferred from the horizontal transfer unit 1c in the diffusion region and obtains a voltage value from a change in the potential of the diffusion region, the information charges of the horizontal transfer unit 1c are output from the output unit. Each time one bit is transferred to 1d, information charges are discharged in response to the reset clock φR. As a result, the information charge transferred and output from the horizontal transfer unit 1c is converted into a voltage value for each bit, and a video signal Y1 (t) that repeats a reset level and a signal level corresponding to the information charge amount is output.

[0005] The sampling circuit 7 outputs a video signal Y1 (t).
Is sampled at a timing according to the sampling clock φS, and is output as a video signal Y2 (t).
The sampling clock generation circuit 8 generates a sampling clock φS in synchronization with the operation of the horizontal transfer clock generation circuit 4 and supplies the sampling clock φS to the sampling circuit 7, similarly to the reset clock generation circuit 6. The phase of the sampling clock φS is adjusted to a period during which a voltage value corresponding to the information charge amount is output from the output unit 1d of the solid-state imaging device 1, and the sampling clock φS is used for the video signal Y1 (t) output from the output unit 1d. Of which
Only the signal level is extracted to generate a video signal Y2 (t).

In the above-described imaging apparatus, the period during which information charges for one screen are accumulated in the imaging section 1a is, for example, one.
Although it is set as / 60 seconds, it is also possible to set the accumulation period to 1/60 seconds or less by discharging the information charges of the imaging unit 1a at a specific timing during the vertical scanning period. Therefore, for a bright subject, the information charge accumulation period is set to be short to prevent overflow of the information charges in the imaging unit 1a of the solid-state imaging device 1. Conversely, for a dark subject, the accumulation period of the information charge is set over a plurality of vertical scanning periods, so that the accumulation period is set to 1/60 second or more to compensate for the lack of exposure. in this case,
Since the transfer of the information charges from the imaging unit 1a to the storage unit 1b is performed once in a plurality of vertical scanning periods, the video signal Y1 (t) output from the solid-state imaging device 1 includes video information. An intermittent signal with no periods. Therefore, such intermittent video signal Y1 (t) is subjected to a process of interpolating video information in units of vertical scanning periods. An imaging device having such an exposure control function is proposed by the present applicant in Japanese Patent Application No. 63-66330, for example.

[0007]

When interpolation of video information is performed on the video signal Y1 (t) output from the solid-state imaging device 1, a field memory for storing a signal for one screen is required. There is a problem that the circuit scale becomes large. Therefore, it is conceivable to improve the apparent sensitivity of the solid-state imaging device 1 by increasing the information charge amount without increasing the circuit scale by synthesizing the information charges for the two pixels of the imaging unit 1a. I have. In general, information charges for two pixels are combined in a process of transferring the information charges.

However, the imaging unit 1 of the solid-state imaging device 1
In a solid-state imaging device for color imaging in which each light receiving pixel is associated with a specific color component by attaching a color filter to a, the color components of adjacent light receiving pixels are different, and information charges of a plurality of pixels are reduced. They cannot be combined with each other.
For example, in the case of a solid-state imaging device equipped with a mosaic type color filter composed of four color components a, b, c, and d, the output video signal Y1 (t) is, as shown in FIG.
In each horizontal scanning period, the color components a and b or c and d are alternately repeated at a period corresponding to the horizontal transfer clock φH. Therefore, if information charges of adjacent light receiving pixels are combined in the transfer process, different color components will be mixed, and the reproduction side will not be able to reproduce a desired color.

Accordingly, an object of the present invention is to enable information charges of a plurality of light receiving pixels to be synthesized by a solid-state image pickup device provided with a color filter.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by being arranged in a row direction and a column direction and responding to received light. A plurality of light receiving pixels for generating information charges, a plurality of vertical shift registers arranged corresponding to each column of the light receiving pixels, receiving information charges generated in each light receiving pixel and transferring the information charges in a vertical direction; A horizontal shift register that receives each output of the plurality of vertical shift registers and transfers information charges output from the plurality of vertical shift registers in the horizontal direction, and stores information charges output from the horizontal shift registers in bit units An output unit that outputs a voltage value corresponding to the charge amount; and an output unit that is arranged to cover the plurality of light receiving pixels, and supplies a first color component to an odd column in each row of the plurality of light receiving pixels, To Includes a color filter, the giving to the second color component, said plurality of vertical shift registers,
The information charge is output to the horizontal shift register at a timing that an even-numbered column lags behind an odd-numbered column.

A plurality of light receiving pixels arranged in a row direction and a column direction, wherein a first color component is provided to an odd column and a second color component is provided to an even column in each row; The information charges generated in each light receiving pixel are transferred to a plurality of vertical shift registers arranged corresponding to each column of the light receiving pixels in the vertical direction, and the information charges output from each vertical shift register are transferred to the horizontal shift register. A method for driving a solid-state imaging device that receives each bit, transfers and outputs in the horizontal direction, and accumulates information charges output from the horizontal shift register in an output unit in bit units to extract a voltage value corresponding to the information charge amount. In the plurality of vertical shift registers,
After transferring the information charges for one row from the odd columns to the horizontal shift register and subsequently transferring the information charges for the one row from the even columns to the horizontal shift register, Subsequently, the signal is transferred from the horizontal shift register to an output unit, and the output unit extracts a voltage value by combining information charges for a plurality of bits.

[0012]

According to the present invention, the first color component and the second color component correspond to the odd columns and the even columns in each row of the plurality of light receiving pixels arranged in a matrix, and the vertical shift registers in the even columns are provided. Transfer information charges to the horizontal shift register at a timing delayed with respect to the odd-numbered row of shift registers, whereby information charges are simultaneously transferred to the horizontal shift register from the light receiving pixels associated with the same color component. Become like For this reason, information charges representing the same color component continue in the horizontal shift register, and a video signal in which the same color component continues in units of 1/2 row can be obtained.

According to the method of driving a solid-state imaging device of the present invention, information charges are simultaneously read out from the light receiving pixels associated with the same color component to the horizontal shift register, and the information charges are output to the output unit in a plurality. The bits are combined. Therefore, even in a solid-state imaging device equipped with a color filter, information charges of a plurality of light receiving pixels are combined without mixing color components, and a high-level video signal can be obtained.

[0014]

FIG. 1 is a plan view showing the structure of a solid-state imaging device according to the present invention, and FIG. 2 is a timing chart of each clock for driving the solid-state imaging device. In this figure, the light receiving pixels of the image pickup unit are shown in 6 rows × 8 columns for simplification of the drawing. The imaging unit 11 includes a plurality of vertical shift registers arranged in parallel with each other. Each of the vertical shift registers is divided into a plurality of bits, thereby forming a plurality of light receiving pixels arranged in a matrix. This imaging unit 1
1 is provided with a mosaic type color filter including four color components a, b, c and d. As a result, the odd-numbered light-receiving pixels have the odd-numbered columns associated with the first color component a, the even-numbered columns correspond to the second color component b, and the odd-numbered light-receiving pixels have the third column. The even-numbered row is associated with the fourth color component d in association with the color component c. A frame transfer clock φF synchronized with the vertical scanning timing is applied to each vertical shift register of the imaging unit 11, and information charges generated in each light receiving pixel are transferred to the accumulation unit 12.
The accumulation unit 12 includes a plurality of vertical shift registers that are continuous with the vertical shift registers of the imaging unit 11. These vertical shift registers are divided so as to correspond to the light receiving pixels of the imaging unit 11, and are transferred from the imaging unit 11. The information charge is taken in and temporarily stored. A vertical transfer clock φV is applied to the vertical shift register of the storage unit 12, and the imaging unit 1
The information charges transferred from one vertical shift register are fetched and accumulated, and the accumulated information charges are vertically transferred in units of one row in synchronization with horizontal scanning timing. On the output side of these vertical shift registers, one bit is formed in the even-numbered column more than the odd-numbered column, and the last bit of the even-numbered column is driven by the auxiliary transfer clock φT having a period of の of the vertical transfer clock φV. . Thereby, the transfer timing of the information charges from the storage unit 12 to the horizontal transfer unit 13 is shifted by a half of the horizontal scanning period between the vertical shift registers in the odd columns and the vertical shift registers in the even columns. The horizontal transfer unit 13 includes one column of horizontal shift registers. The horizontal shift register is divided into a plurality of bits corresponding to every two columns of the vertical shift register of the storage unit 12.
The information charge transferred from each vertical shift register is taken into each bit. A horizontal transfer clock φH synchronized with the horizontal scanning timing is applied to the horizontal shift register of the horizontal transfer unit 13, and the information charges transferred from the storage unit 12 to the horizontal transfer unit 13 are sequentially shifted in the horizontal direction every half row. Transfer and output. The output unit 14 includes a capacitor that receives information charges output from the horizontal shift register of the horizontal transfer unit 13, an output amplifier that extracts a change in the potential of the capacitor, and a reset transistor that discharges information charges accumulated in the capacitor. . A reset clock φR synchronized with the horizontal transfer clock φH is applied to the output unit 14, and the horizontal transfer unit 13
, And the information charges stored in the capacitor in bit units are sequentially discharged. As a result, the information charge transferred from the horizontal transfer unit 13 is converted into a voltage value in 1-bit units, and a video signal Y (t) corresponding to the information charge amount is output.

The vertical transfer clock φV is composed of, for example, four-phase clocks φV1 to φV4, and transfers information charges in the storage section 12 in the vertical direction by one row at the start of vertical scanning synchronized with the horizontal synchronization signal HD. . At this time, information charges of the last bit are transferred to the horizontal shift register of the horizontal transfer unit 13 in the vertical shift registers of the odd columns, but in the vertical shift registers of the even columns which are one bit larger than the odd columns, the information charges of the same row are transferred. Charge is held in the last bit of the vertical shift register. Regarding the auxiliary transfer clock φT for driving the last bit of the vertical shift register, for example,
It consists of four-phase clock clocks φT1 to φT4, and when 1/2 of the horizontal scanning period has elapsed after the information charge is taken into the last bit of the vertical shift register at the beginning of horizontal scanning together with the vertical transfer clock φV The information charge is transferred from the last bit of the vertical shift register to the horizontal shift register of the horizontal transfer unit. Then, the horizontal transfer clock φ
H is composed of, for example, two-phase clocks φH1 and φH2. Each time information charges are transferred from the vertical shift register of the accumulation unit 12 to the horizontal shift register of the horizontal transfer unit 13, the H is 1 in a half period of the horizontal scanning. The information charges for / 2 rows are transferred to the output unit 14. The information charges transferred and output in this manner are:
For each horizontal scanning period, the same color component is continuous in a half of the horizontal scanning period. For example, in an odd-numbered horizontal scanning period, information charges representing the first color component a are continuously output in the first half of the horizontal scanning period, and information charges representing the second color component b are continuously output in the latter half of the horizontal scanning period. In the first horizontal scanning period, information charges representing the third color component c are continuous in the first half of the horizontal scanning period, and information charges representing the fourth color component d are continuously output in the second half. Therefore, the video signal Y (t) output from the output unit 14 represents a single color component every half of the horizontal scanning period in each horizontal scanning period, and the video signal Y (t) In signal processing for
The color components can be easily separated.

If the reset clock φR applied to the output unit 14 is thinned out at appropriate intervals, it is possible to synthesize information charges for a plurality of bits. In this case, since the same color component is continuous during a half of the horizontal scanning period, different color components are not mixed. FIG. 3 is a plan view showing a configuration example of a mosaic type color filter, and shows a light receiving section of a frame transfer type CCD solid-state imaging device. FIG. 4 is a cross-sectional view taken along line XX of FIG. In these figures, four pixels per pixel
Four-phase drive full frame type C in which four transfer electrodes are arranged
1 shows a CD solid-state imaging device.

In the surface region of the P-type silicon substrate 21, a plurality of isolation regions 22 each composed of a high-concentration P-type region are formed in parallel with each other. Is diffused to form a channel region 23. On the silicon substrate 21 on which the isolation region 22 and the channel region 23 are formed, a plurality of first-layer transfer electrodes 2 are interposed with the channel region 23 via the oxide film 24.
The fifth and second transfer electrodes 26 are arranged in parallel with each other. In addition, during a period in which information charges generated by photoelectric conversion are accumulated, for example, the even-numbered potential of the second-layer transfer electrode 26 is lowered to form a potential barrier, and the first-layer transfer electrode 25 and the second-layer transfer electrode 25 are stacked. The odd-numbered potential of the eye transfer electrode 26 is raised to form a potential well. As a result, the channel region 23 that is continuous in the vertical direction is electrically separated by the even-numbered transfer electrodes 26 of the second layer, and a plurality of light receiving pixels are formed. Then, for example, a four-phase clock pulse is applied to each of the transfer electrodes 25 and 26, and information charges accumulated in the potential well are sequentially transferred to the output side along the channel region 23. Here, each transfer electrode 2
5 and 26 are two per pixel (4 in total).
The information charges accumulated in each light receiving pixel are independently transferred for each pixel.

The color filter 27 formed to cover each of the transfer electrodes 25 and 26 is divided into a plurality of regions corresponding to each row of the light receiving pixels, and three regions corresponding to two columns of the channel region 23. Is divided into A divided region extending over two light receiving pixels adjacent to each other across the separation region 22 corresponds to １ ／ of each light receiving pixel, and divided regions adjacent on both sides thereof correspond to ／ of each light receiving pixel. These divided areas include Ye (yellow), Cy (cyan) and G
(Green) components are assigned in a predetermined order.
The order of assigning color components to each divided region is the same in each row, but is shifted by one region in the row direction between the even rows and the odd rows.

Incidentally, the G component filter can be constructed by superposing a Ye component filter and a Cy component filter. For this reason, the first colored layer 28 serving as the Ye filter is arranged in the divided region to which the Ye component and the G component are assigned, and the second colored layer 29 serving as the Cy filter is provided as the Cy filter.
The color filter 27 is configured by arranging the components and the G component in the divided areas to which the components are assigned. Thus, the divided region in which only the first colored layer 28 is disposed is associated with the Ye component, and the divided region in which only the second colored layer 29 is disposed is associated with the Cy component. The divided region in which the second colored layer 29 is arranged so as to overlap is associated with the G component.

In the above color filter 27, 4
The two color components a, b, c and d can be expressed as follows: a = 2Cy + Ye b = 2G + Yec = 2G + Cyd = 2Ye + Cy. And such a color component a,
According to the configurations of b, c, and d, from the difference between the color components of each row, | ab | = (2Cy + Ye) − (2G + Ye) = 2Cy−2G = 2B | cd | = (2Ye + Cy) Assuming that-(2G + Cy) = 2Ye-2G = 2R, a B (blue) component and an R (red) component can be obtained. Also, by combining the color components for each row, a + b = (2Cy + Ye) + (2G + Ye) = 2R + 6G + 2B c + d = (2G + Cy) + (2Ye + Cy) = 2R + 6G + 2B, and an equal signal can be obtained for each row. Can be used as a luminance signal. Although the luminance signal in this case does not match the original luminance signal, there is no problem in practical use because each component is synthesized at a rate close to the rate conforming to a predetermined standard.

FIG. 5 is a block diagram showing a configuration of an image pickup apparatus employing the driving method of the solid-state image pickup device of the present invention, and FIG. 6 is an operation timing chart thereof. Solid-state image sensor 31
Has the same configuration as that of FIG. 1, and the imaging unit 31 a equipped with a mosaic type color filter, the even-numbered column vertical shift register is one output side more than the odd-numbered column vertical shift register.
The output unit 31b formed with more bits, the horizontal transfer unit 31c in which each bit of the horizontal shift register is associated with every two columns of the vertical shift register of the output unit 31b, and the video signal Y
An output unit 31d for extracting 1 (t) is provided.

The frame transfer clock generation circuit 32 supplies a frame transfer clock φF generated in synchronization with the vertical scanning timing to the imaging section 31a of the solid-state imaging device 31, and accumulates information charges of the imaging section 31a for each screen. Transfer to section 1b. The vertical transfer clock generation circuit 33 supplies the vertical transfer clock φV to the storage unit 1b, takes in the information charges transferred from the imaging unit 31a into the storage unit 31b,
The acquired information charges are transferred in the vertical direction for each row. At this time, in the accumulation unit 31b, the vertical shift registers of the even columns are formed one bit more on the output side than the vertical shift registers of the odd columns. In the vertical shift registers of the odd columns, the information charges of the last bit are horizontal. The information charges are transferred to the horizontal shift register of the transfer unit 31c, and in the vertical shift registers of the even columns, the information charges of the same row are held in the last bit of the vertical shift register. The auxiliary transfer clock generation circuit 34 supplies the auxiliary transfer clock φT to the last bit of the vertical shift register in the even column of the storage unit 31b,
The information charges captured in the last bit are transferred to the horizontal shift register of the horizontal transfer unit 31c at a timing delayed by a half of the horizontal scanning period with respect to the transfer timing of the vertical shift registers in the odd columns. The horizontal transfer clock generation circuit 35 supplies the horizontal transfer clock φH generated in synchronization with the horizontal scanning timing to the horizontal transfer unit 31c, and transfers and outputs the information charges transferred from the storage unit 31b to the output unit 31d. The timing control circuit 36 determines each timing of vertical scanning and horizontal scanning based on the reference clock CK, and controls the operation timing of each clock generation circuit 32, 33, 34, 35. Thereby, the imaging unit 31a
Is transferred to the storage section 31b in units of one screen at the start of the vertical scanning period and is stored therein, and the horizontal transfer section 31c is transferred from the storage section 31b in units of one row at the start of the horizontal scanning period. Transferred to In the transfer process, the information charges read from the odd-numbered columns of light-receiving pixels and the information charges read from the even-numbered columns of light-receiving pixels are separated, and the information charges representing the same color component are separated during the horizontal scanning period. Output unit 31d continuously for every 1/2 period
Transferred to

The reset clock generation circuit 37 synchronizes with the horizontal transfer clock generation circuit 35 to generate a horizontal transfer clock φ.
A reset clock φR1 having the same cycle as H is generated. The frequency divider 38 divides the reset clock φR1 by 1 / n,
A reset clock .phi.R2 having a period n times as long as the horizontal transfer clock .phi.
To supply. Thus, the operation of discharging the information charges in the output unit 31d has a cycle n times as long as the transfer operation of the horizontal transfer unit 31c, and the information charges for n pixels are accumulated in the output unit 31d. As a result, the video signal Y1 (t) output from the output unit 31d has the same level for n times the period of the horizontal transfer clock φH, but is sufficient even when the information charge amount for one pixel is small. Level can be obtained.

The sampling circuit 39 outputs the video signal Y1
(t) is taken in, sampled at a timing according to the sampling clock φS2, and output as a video signal Y2 (t). The sampling clock generation circuit 40 generates a sampling clock φS1 having the same cycle as the horizontal transfer clock φH in synchronization with the horizontal transfer clock generation circuit 35, similarly to the reset clock generation circuit 37. The dividing circuit 41
Similarly to the frequency dividing circuit 38, the sampling clock φS1 is set to 1
/ N, generates a sampling clock φS2 having the same cycle as the reset clock φR2, and supplies it to the sampling circuit 39. Note that the phase of the sampling clock φS2 is set so as to coincide with the period during which the signal level of the video signal Y1 (t) is output, similarly to the sampling clock φS in FIG.

Here, the frequency dividing operation of each of the frequency dividing circuits 38 and 41 with respect to the reset clock φR1 and the sampling clock φS1 is performed in response to the field identification signal FD which is inverted every vertical scanning period (one field). The timing is set to be shifted by one cycle of the horizontal transfer clock φH in the scanning period. For example, when the reset clock φR1 and the sampling clock φS1 are frequency-divided by し て to synthesize information charges for two pixels at the output unit 31d, in the odd field (ODD), each frequency division is performed at the rising edge of the horizontal scanning signal HD. The circuits 38 and 41 are reset, and the even field (EV)
EN), the frequency divider 12 is reset with a delay of one cycle of the horizontal transfer clock φH from the rise of the horizontal scanning signal HD. Thus, the reset clock φR2 is set to be shifted by one cycle between the odd field and the even field as shown in FIG. Therefore,
The discharge operation of the information charges in the output unit 31d is performed by the horizontal transfer unit 31.
One cycle of the horizontal transfer clock φH is shifted for each field with respect to the transfer operation c, and the combination of the light receiving pixels synthesized in the output unit 31d is inverted for each field. As described above, if the timing of synthesizing the information charges of the light receiving pixels is reversed for each field, the solid-state imaging device 31 is pseudo-interlacedly scanned in the horizontal direction, and the information charges of the two pixels are interlaced. It is possible to suppress a decrease in resolution in the horizontal direction due to the combination.

The cycle of inverting the combination of pixels synthesized in the output section 31d can be performed in units of vertical scanning periods or in units of horizontal scanning periods. In this case, the frequency division operation for the reset clock φR1 and the sampling clock φS1 in each of the frequency division circuits 38 and 41 is set to be shifted by one period of the horizontal transfer clock φH for each horizontal scanning period.

In the above embodiment, by increasing the number of bits of the vertical shift register of the even column of the storage section 31b by one bit with respect to the odd column, the information charges of the odd column and the even column are distributed. The horizontal transfer unit 31c
The information charges may be distributed by controlling the incorporation of the information charges into the information charges. Further, the storage unit 31b
It is also possible to provide a pair of output controls in which the positions of the odd and even columns are inverted on the output side of the vertical shift register, and distribute the information charges by operating the output control electrodes.

In this embodiment, a frame transfer type solid-state image pickup device is exemplified. However, the present invention can be similarly applied to an interline type or frame interline type solid state image pickup device.

[0029]

According to the present invention, in a solid-state image pickup device for color imaging in which light-receiving pixels arranged in a matrix are respectively associated with specific color components, information charges representing the same color component are halved. It can be taken out in units. Therefore, in the process of processing the video signal, the color components can be easily separated, and the configuration of the signal processing circuit can be simplified.

Further, since information charges representing the same color component are continuously output, information charges of a plurality of pixels can be easily synthesized, the luminance of the subject is low, and the information stored in the light receiving pixels is low. Even when the charge is small, a video signal of a sufficient level can be taken out. Furthermore, if the combination of the light receiving pixels for synthesizing the information charges is inverted every vertical scanning period or every horizontal scanning period so as to perform pseudo interlaced scanning, it is possible to suppress a decrease in resolution due to the synthesis of the information charges. it can.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a configuration of a solid-state imaging device of the present invention.

FIG. 2 is a timing chart of a clock for driving the solid-state imaging device of the present invention.

FIG. 3 is a plan view illustrating a configuration example of a color filter used in the solid-state imaging device of the present invention.

FIG. 4 is a sectional view showing a sectional structure taken along line XX of FIG. 3;

FIG. 5 is a block diagram illustrating a configuration of an imaging apparatus that employs a method for driving a solid-state imaging device according to the present invention.

FIG. 6 is a timing chart illustrating a method for driving a solid-state imaging device according to the present invention.

FIG. 7 is a block diagram illustrating a configuration of a conventional solid-state imaging device.

FIG. 8 is a timing chart for explaining the operation of a conventional solid-state imaging device.

[Explanation of symbols]

 1, 31 solid-state imaging device 1a, 11, 31a imaging unit 1b, 12, 31b storage unit 1c, 13, 31c horizontal transfer unit 1d, 14, 31d output unit 2, 32 frame transfer clock generation circuit 3, 33 vertical transfer clock generation Circuit 4, 35 Horizontal transfer clock generation circuit 5, 36 Timing control circuit 6, 37 Reset clock generation circuit 7, 39 Sampling circuit 8, 40 Sampling clock generation circuit 21 Silicon substrate 22 Separation region 23 Channel region 24 Oxide film 25, 26 Transfer Electrode 27 Color filter 28, 29 Color layer 35 Auxiliary transfer clock generation circuit 38, 41 Frequency dividing circuit

Claims (5)

(57) [Claims] 1. A plurality of light receiving pixels which are arranged in a row direction and a column direction and generate information charges in response to received light, are arranged corresponding to each column of the light receiving pixels, and are generated in each light receiving pixel. A plurality of vertical shift registers for receiving information charges to be transferred in the vertical direction, and receiving each output of the plurality of vertical shift registers for each bit, and horizontally transferring information charges output from the plurality of vertical shift registers. A horizontal shift register, an output unit that accumulates information charges output from the horizontal shift register in bit units and outputs a voltage value corresponding to the charge amount, And a color filter that provides a first color component to odd columns and a second color component to even columns in each row of the light receiving pixels. A solid-state imaging device, wherein the information charge is output to the horizontal shift register at a timing delayed with respect to an odd column. 2. A light receiving device which is arranged in a row direction and a column direction and receives light.
A plurality of light-receiving pixels that generate information charges in response to light;
Are arranged corresponding to each column of light receiving pixels of
Multiple verticals that receive generated information charges and transfer them vertically
A shift register and the plurality of vertical shift registers described above for each bit.
Receiving the output of each of the plurality of vertical shift registers
Horizontal shift of information charges output from the
Output from the horizontal shift register
Information charges are stored in bit units, and the voltage corresponding to the charge amount
An output section for outputting a value, and
The odd rows of the plurality of light receiving pixels correspond to the odd columns.
To provide a first color component and to apply a second color component to the even columns.
In the even rows, the third color component is given to the odd columns.
Color filter that provides a fourth color component for even columns
And wherein the plurality of vertical shift registers have an even number
The above information charge is generated at a timing when the row is delayed with respect to the odd row.
Output to the horizontal shift register.
Body imaging device. 3. A plurality of light receiving pixels which are arranged in a row direction and a column direction, and each row is provided with a first color component for odd columns and a second color component for even columns, The information charges generated in each light receiving pixel are transferred to a plurality of vertical shift registers arranged corresponding to each column of the light receiving pixels in the vertical direction, and the information charges output from each vertical shift register are transferred to the horizontal shift register. A method for driving a solid-state imaging device that receives each bit, transfers and outputs in the horizontal direction, and accumulates information charges output from the horizontal shift register in an output unit in bit units to extract a voltage value corresponding to the information charge amount. In the plurality of vertical shift registers, information charges for one row from an odd column are transferred to the horizontal shift register, and then transferred from the horizontal shift register to an output unit. Transfer the information charge to the horizontal shift register, and subsequently transfer the information charge from the horizontal shift register to the output unit, and combine the information charges for a plurality of bits to extract the voltage value at the output unit. Of driving a solid-state imaging device. 4. The timing of synthesizing information charges transferred from the horizontal shift register at the output unit is shifted by one cycle of the transfer operation of the horizontal shift register every vertical scanning period. Driving method of the solid-state imaging device. 5. The timing of synthesizing the information charges transferred from the horizontal shift register at the output unit is shifted by one cycle of the transfer operation of the horizontal shift register every horizontal scanning period. Driving method of the solid-state imaging device.