JPH11196336A - Method for driving common camera for hdtv/sdtv - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a frame rate in a standard television(SDTV) mode and to make it possible to share an output system for a high definition televion(HDTV) signal for a SDTV signal. SOLUTION: In an HDTV/SDTV common camera provided with a CCD solid-state image pickup element 10 consisting of 2,000,000 pixels corresonding to an HDTV system and capable of selectively outputting either one of television(TV) signals for both the HDTV and SDTV systems, a timing generator (TG) 23 generates an HDTV signal from the pixel information on all pixels included in the element 10 in accordance with a TV mode signal applied from the outside at the time of the HDTV mode. At the time of the SDTV mode, timing is controlled so as to generate an SDTV signal by thinning the pixel information on the element 10 e.g. at the rate of one pixel per two pixels in both of row and column directions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an HDTV (high-d
efinition television) / SDTV (standard televis)
ion) A method for driving a shared camera, particularly, including a solid-state imaging device having a number of pixels corresponding to the HDTV system,
The present invention relates to a method for driving an HDTV / SDTV shared camera capable of selectively outputting both TV and SDTV television signals.

[0002]

2. Description of the Related Art In recent years, a CCD (Charge Co., Ltd.) having two million pixels has been developed.
upled Device) An HDTV / SDTV shared camera using a solid-state imaging device as an imaging device has been developed and commercialized. Here, the HDTV system refers to a high-definition television system, which is a next-generation television system that provides a sense of reality with high definition and visual psychology. The SDTV system refers to a current television system such as the NTSC system or the PAL system.

[0003]

This HDTV / SDT
Conventionally, in a V-shared camera, 20
While the HDTV signal is generated based on the pixel information of all the pixels of the CCD solid-state imaging device having 100,000 pixels, in the SDTV mode, the SDTV signal is generated by performing over-Nyquist sampling of the HDTV signal. Therefore, the frame rate of the SDTV signal is limited to 30 frames / sec, which is the same frame rate as the HDTV signal, and a sampling circuit for generating the SDTV signal is required, which complicates the circuit configuration.

[0004] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to make it possible to improve the frame rate in the SDTV mode and to improve the HDTV.
H enabling sharing of signal output system to SDTV signal
An object of the present invention is to provide a driving method of a DTV / SDTV shared camera.

[0005]

According to the present invention, a solid-state image pickup device having a pixel number corresponding to the HDTV system is provided.
In an HDTV / SDTV shared camera capable of selectively outputting both DTV and SDTV television signals, an HDTV signal is generated from pixel information of all pixels of the solid-state imaging device in the HDTV mode, and a solid-state imaging device in the SDTV mode. Is thinned to generate an SDTV signal.

In an HDTV / SDTV shared camera,
In the HDTV mode, as usual, an HDTV signal is generated based on pixel information of all pixels of the solid-state imaging device.
In the SDTV mode, for all pixels of the solid-state imaging device,
In each of the row and column directions, for example, pixel information is thinned out at a ratio of one pixel to two pixels, and an SDTV signal is generated based on the pixel information obtained by the thinning processing.

As described above, thinning out the pixel information is equivalent to a reduction in the total number of pixels in the SDTV mode, and increases the SDTV signal frame rate. As a result, high-speed imaging is realized in the SDTV mode.
Further, the SDTV high-speed imaging mode can also be used to realize a high-speed playback mode during HDTV broadcasting.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, and shows a case where the present invention is applied to an HDTV / SDTV shared camera using, for example, an interline transfer type CCD solid-state imaging device as an imaging device. Here, as the CCD solid-state imaging device, HDTV
A pixel having a pixel number of 2 million pixels corresponding to the method is used.

In FIG. 1, incident light (image light) from a subject is imaged on a light receiving surface of an imaging section 12 of a CCD solid-state imaging device by an optical system such as a lens 11. Imaging unit 12
Are two-dimensionally arranged in a matrix in the row (vertical) direction and the column (horizontal) direction, and convert a plurality of sensor units (pixels) into incident signal light and convert the incident light into signal charges having a charge amount corresponding to the light amount.
13, provided for each vertical column of the sensor units 13,
A plurality of vertical CCDs 1 for vertically transferring signal charges read from each sensor unit 13 via a read gate unit 14
And 5.

In the image pickup section 12, the sensor section 13 is composed of, for example, a PN junction photodiode. The signal charges accumulated in the sensor unit 13 are read out to the vertical CCD 15 by applying a readout pulse XSG described later to the readout gate unit 14. Vertical CC
D15 has, for example, a two-layer electrode, four-phase (φV1 to φV4) drive configuration. The signal charges read from each sensor unit 13 are driven by four-phase vertical transfer pulses φV1 to φV4. In a part of the horizontal blanking period, vertical transfer (line shift) is sequentially performed for a portion corresponding to one scanning line (one line).

Here, in the vertical CCD 15, transfer electrodes corresponding to the first phase (φV1) and the third phase (φV3) are:
The gate also serves as a gate electrode of the read gate unit 14. From this, of the four-phase vertical transfer pulses φV1 to φV4, the first and third phase vertical transfer pulses φV1 and φV3
Are a low level (hereinafter, referred to as “L” level), an intermediate level (hereinafter, referred to as “M” level) and a high level (hereinafter, referred to as “M” level).
(Referred to as “H” level), and the third “H” level pulse becomes the read pulse XSG applied to the read gate unit 14.

Below the imaging unit 12, two horizontal CCDs are provided.
16, 17 are arranged. In addition, two horizontal CCDs 1
Between the pixels 6 and 17, an HH gate unit 18 is provided corresponding to, for example, an even-numbered column in the pixel array of the imaging unit 12. When the HH gate pulse φHHG is applied to the HH gate unit 18, the signal charges of the pixels in the even-numbered columns in the pixel array of the imaging unit 12 are transferred to the horizontal CC.
The data is transferred from D16 to the horizontal CCD 17.

A drain portion 19 is further provided outside the horizontal CCD 17. In addition, a discharge gate section 20 is provided between the horizontal CCD 17 and the drain section 19. When the discharge gate pulse φDrain is applied to the discharge gate section 20, the horizontal CCD 17
The electric charges existing inside are discharged to the drain portion 19 through the discharge gate portion 20.

The two horizontal CCDs 16 and 17 are, for example, 2
The layer electrodes are driven by two phases (φH1, φH2), and the signal charges for one line transferred from the vertical CCD 15 are driven by the two-phase horizontal transfer pulses φH1, φH2 to provide horizontal blanking. Horizontal transfer is sequentially performed in a horizontal scanning period after the period. Horizontal CCD 16,1
For example, charge-voltage converters 21 and 21 having a floating diffusion amplifier configuration
2 are provided.

The charge-voltage converters 21 and 22 sequentially convert signal charges horizontally transferred by the horizontal CCDs 16 and 17 into signal voltages and output the signal charges. These signal voltages are derived as CCD outputs OUT1 and OUT2 according to the amount of incident image light from the subject. From the above,
An interline transfer type CCD solid-state imaging device 10 is configured.

Four-phase vertical transfer pulses φV1 to φV4 for driving the CCD solid-state imaging device 10, two-phase horizontal transfer pulses φH1, φH2, and HH gate pulse φHHG
Various timing signals including the discharge gate pulse φDrain are generated by a timing generator (TG) 23. The timing generator 23 is configured to selectively adopt the HDTV mode and the SDTV mode according to a TV mode signal supplied from the outside.

Here, in the HDTV mode, a field or frame reading process is performed in the CCD solid-state imaging device 10, and in the SDTV mode, of all the pixels of the CCD solid-state imaging device 10, every other pixel in the column direction has a row. In the direction, a process of thinning out pixel information for every two pixels in units of two pixels is performed. For this purpose, the timing generator 23 outputs each timing signal at a timing corresponding to each TV mode. In particular, for the first and third phase vertical transfer pulses φV1 and φV3,
In order to support two TV modes, two systems of vertical transfer pulses (φV1, φV1 ′, φV3, φV3 ′) are generated.

2 output from the CCD solid-state imaging device 10
The system CCD outputs OUT1 and OUT2 are subjected to various signal processing such as CDS (Correlated Double Sampling) and addition of a synchronization signal by a signal processing circuit 24, and then to an HDTV signal corresponding to each TV mode. / S
It is output as a DTV signal.

FIG. 2 is a wiring pattern diagram of the transfer electrodes 31-1, 31-2, 31-3 and 31-4 in one vertical CCD 15. In this wiring system, in order to enable thinning-out reading, the vertical transfer pulse φV of the first and third phases is used.
The wiring of 1, φV3 is devised. Specifically, as described above, two systems of vertical transfer pulses φV1, φV1 ′, φV are used as the first and third phase vertical transfer pulses.
3, φV3 ′, and a vertical transfer pulse φV1,
Six bus lines 32 to 36 are wired to transmit φV1 ′, φV2, φV3, φV3 ′, and φV4.

The bus lines 34 and 37 for transmitting the vertical transfer pulses φV2 and φV4 are connected to the corresponding transfer electrodes 31-2 and 31-4 for all the pixels, respectively. Further, transfer electrodes 31-1 and 31-3 corresponding to two adjacent pixels are connected to the bus lines 32 and 35 for transmitting the vertical transfer pulses φV1 and φV3 every two pixels, respectively. Are connected to the transfer electrodes 31-1 and 31-3 corresponding to two adjacent pixels which are not connected to the bus line 33.
Are connected every two pixels.

FIG. 3 shows a four-phase vertical transfer pulse φV1 (φV
1 ′), φV2, φV3 (φV3 ′), φV4. Here, the vertical transfer pulse φV1 (φV
1 ′) and φV3 (φV3 ′) are readout signals applied to the gate electrode of the readout gate unit 14 when the third “H” level pulse reads out signal charges from the sensor unit 13 as described above. It becomes pulse XSG.

In the HDTV mode, since it is necessary to read out signal charges from all the pixels of the image pickup unit 12, the vertical transfer pulse φV1, as shown in FIG.
The read pulse XSG is set to rise at both φV3 and φV1 ′, φV3 ′. On the other hand, in the SDTV mode, since it is necessary to read out signal charges every two pixels in units of two pixels in the vertical direction (row direction), as shown in FIG. φV
At 1, φV3, φV1 ', and φV3', the read pulse XSG rises alternately in odd and even fields.

That is, in the HDTV mode, the signal charges are read from all the pixels by setting the read pulse XSG to both the vertical transfer pulses φV1, φV3 and φV1 ′, φV3 ′. On the other hand, in the SDTV mode, the vertical transfer pulses φV1, φV3 and φV1 ′, φV
Since the read pulse XSG rises alternately at 3 ', signal charges are read every two pixels in units of two pixels in the vertical direction. In other words, signal charges are thinned out every two pixels in units of two vertical pixels.

Next, for each TV mode of the HDTV mode / SDTV mode, the vertical CCD 15
VH transfer to 6 and 17, HH between horizontal CCD 16 and 17
The operation will be described focusing on the transfer and the horizontal transfer of the horizontal CCDs 16 and 17.

First, referring to the operation explanatory diagram of FIG.
The operation in the V mode will be described. The sensor unit 13
As described above, when the signal charges from the pixels are read out, the signal charges of all the pixels are read out to the vertical CCD 15, and
It is assumed that two adjacent pixels in the vertical direction are mixed as a unit. From this state, the signal charge for one line is transferred to the horizontal C by the line shift operation of the vertical CCD 15.
VH transfer to CD 16 (state 1). Here, among the signal charges for one line, the pixels in the odd columns are schematically indicated by ●, and the signal charges in the even columns are schematically indicated by ○.

At this time, an HH gate pulse φHHG is applied to the gate electrode of the HH gate section 18, whereby, among the signal charges of one line transferred to the horizontal CCD 16 by VH, the signal charges of even-numbered columns are obtained. Is HH-transferred to the horizontal CCD 17 via the HH gate section 18 (state 2). Thereafter, due to the transfer operation of the horizontal CCDs 16 and 17, the signal charges in the odd-numbered columns and the signal charges in the even-numbered columns are horizontally transferred in parallel (state 3).
22 are derived as two systems of CCD outputs OUT1 and OUT2.

As described above, the 20 compatible with the HDTV system is used.
In the CCD solid-state imaging device 10 having 100,000 pixels, the signal charges for one line are divided into two systems of odd columns and even columns.
By performing horizontal transfer by the horizontal CCDs 16 and 17,
The horizontal drive frequency (the frequency of the horizontal transfer pulses φH1 and φH2) can be reduced to half that in the case where horizontal transfer is performed by one horizontal CCD.

Next, the operation of the SDTV mode will be described with reference to the operation explanatory diagrams of FIGS.

First, when reading out signal charges from the sensor section 13, signal charges are read out every two pixels in the row direction (vertical direction) (state 1). At this time, the signal charges of the two vertical pixels are mixed in the vertical CCD 15.
As a result, signal charges are thinned out every two pixels in units of two vertical pixels. That is, in the row direction, the thinning process is performed at a ratio of one pixel to two pixels. Next, the vertical C
By the line shift operation of the CD 15, the signal charges for one line are VH-transferred to the horizontal CCD 16 (state 2).

At this time, the HH gate pulse φHHG is applied to the gate electrode of the HH gate section 18 and the discharge gate pulse φDrain is applied to the gate electrode of the discharge gate section 20, whereby the VH transfer to the horizontal CCD 16 is performed. Of the signal charges of one line, the signal charges of even-numbered columns are transferred to the horizontal CCD through the HH gate unit 18.
17 is transferred to the drain portion 19 via the discharge gate portion 20 (state 3). As a result, signal charges are thinned out every other pixel in the column direction (horizontal direction).

Next, of the signal charges for the next one line,
VH is applied to the horizontal CCD 16 only for the signal charges in the even-numbered columns.
Transferred (state 4). At this time, as in the case of the state 3, the HH gate pulse φHHG is applied to the gate electrode of the HH gate section 18 and the discharge gate pulse φDrain is applied to the gate electrode of the discharge gate section 20. Of the even-numbered column of the HH gate unit 1
8 is transferred to the horizontal CCD 17 via the HH 8 and further swept away to the drain unit 19 via the discharge gate unit 20 (state 5).

Next, the signal charges in the odd-numbered columns for one line before being stored in the horizontal CCD 16 are horizontally transferred by one stage, and an HH gate pulse φHHG is applied to the gate electrode of the HH gate unit 18. The HH gate unit 1
8 to the horizontal CCD 17 via HH (state 6). The signal charge HH transferred to the horizontal CCD 17
Is further horizontally transferred by one stage in the horizontal CCD 17 (state 7).

Next, the signal charges in the odd-numbered columns for the next one line, for which VH transfer has been prohibited, are transferred to the horizontal CCD 16.
VH transfer (state 8). Thereafter, the horizontal CCD 16,
By the transfer operation of No. 17, the odd-numbered signal charges of one line and the odd-numbered signal charges of the next one line are horizontally transferred in parallel (state 9), and the charge voltage detectors 21 and 22 are transferred.
Are derived as two systems of CCD outputs OUT1 and OUT2.

The above series of processing is only an example,
Various changes are possible as the mode. For example, the processing in the state 4 and the state 5 is omitted, and in the processing in the state 8, when the signal charge for the next one line is transferred to the VH, only the signal charge in the odd column is not transferred to the VH. 9
As shown in a state 8 'of FIG.
At this time, the signal charges の in the even-numbered columns may be swept away to the drain unit 19 via the HH gate unit 18, the horizontal CCD 17 and the discharge gate unit 20 as they are.

Although the present embodiment has been described by taking as an example the case of using a CC solid-state imaging device of the interline transfer system, the same applies to the case of using a CCD solid-state imaging device of an all-pixel readout system. It is possible.

As described above, in an HDTV / SDTV shared camera using a 2 million pixel CCD solid-state imaging device 10 compatible with the HDTV system as an imaging device,
In the SDTV mode, signal charges (pixel information) are thinned out at a ratio of one pixel to two pixels in each direction of a row and a column, so that the total number of pixels in the SDTV mode is equivalent to １ ／ of that in the HDTV mode. Become. As a result, the frame rate of the SDTV signal is 4 times the frame rate of the HDTV signal.
Therefore, quadruple speed imaging is realized.

At this time, the driving frequency of the horizontal CCDs 16 and 17 may be the same as that in the HDTV mode, so that the horizontal CCDs 16 and 17 and the charge-voltage converters 21 and 22 can be effectively used even in the SDTV mode. .
In addition, special sampling processing for generating an SDTV signal by over-Nyquist sampling an HDTV signal as in the related art is unnecessary, and the output system (signal processing system) can be driven at high speed for HDTV. ,
There is an advantage that the output system can be shared with the SDTV signal.

In the above embodiment, the signal obtained in the SDTV mode is used as the SDTV signal for quadruple-speed imaging. However, the signal obtained in the SDTV mode is used as it is as an HDTV signal, so that the A high-speed playback mode can also be realized.

[0039]

As described above, the solid-state imaging device having the number of pixels corresponding to the HDTV system is provided.
HDTV / SDTV shared camera capable of selectively outputting both TV signal of SDTV and SDTV, generates an HDTV signal from the pixel information of all the pixels of the solid-state imaging device in the HDTV mode, and generates the solid-state imaging device in the SDTV mode Since the SDTV signal is generated by thinning out the pixel information, the SDTV mode is equivalent to a reduction in the total number of pixels, so that the frame rate of the SDTV signal is increased and high-speed imaging can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.

FIG. 2 is a wiring pattern diagram of three-phase transfer electrodes in a vertical CCD.

FIG. 3 is a waveform diagram showing a phase relationship between three-phase vertical transfer pulses during a line shift period.

FIG. 4 is a timing chart for explaining a read pulse XSG. FIG.
(B) shows the case of the SDTV mode, respectively.

FIG. 5 is an explanatory diagram of an operation in an HDTV mode.

FIG. 6 is an explanatory diagram (1) of an operation in an SDTV mode.

FIG. 7 is an operation explanatory diagram (part 2) in the SDTV mode.

FIG. 8 is an operation explanatory view (3) in the SDTV mode.

FIG. 9 is an operation explanatory view showing a modified example.

[Explanation of symbols]

10: CCD solid-state imaging device, 12: imaging unit, 13: sensor unit, 14: readout gate unit, 15: vertical CCD, 1
6, 17: horizontal CCD, 18: HH gate section, 19: drain section, 20: discharge gate section, 21, 22: charge-voltage converter, 23: timing generator, 24: signal processing circuit

Claims (3)

[Claims] 1. An HDT comprising a solid-state imaging device having a number of pixels corresponding to the HDTV system and capable of selectively outputting television signals of both HDTV and SDTV systems.
In the V / SDTV shared camera, an HDTV signal is generated from pixel information of all pixels of the solid-state imaging device in the HDTV mode, and an SDTV signal is generated by thinning out pixel information of the solid-state imaging device in the SDTV mode. HDT
A method for driving a V / SDTV shared camera. 2. The method of driving an HDTV / SDTV shared camera according to claim 1, wherein the SDTV signal is output through the same output circuit as the HDTV signal. 3. In the SDTV mode, pixel information is thinned out for every pixel of the solid-state imaging device at a ratio of one pixel to two pixels in each of row and column directions.
2. The HD according to claim 1, wherein the HD signal is generated.
A method for driving a TV / SDTV shared camera.