JPH09312849A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an interlaced image output whose frame rate is 60 in the CCD solid-state image pickup device of all picture element read system. SOLUTION: In the entire picture element read system color CCD area sensor 11 having a color filter with primary color chequer array color coding, processing of sweeping out signal charges read by a horizontal transfer register 4 to a charge discharge section 10 and processing of transferring the charges horizontally by the horizontal transfer register 4 are repeated every two-line in the monitoring mode and processing replacing the line with another line to sweep out the signal charge to the charge discharge section 10 for each field is conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a so-called all-pixel readout type CCD in which signal charges independently read from all pixels can be sequentially read out without being mixed in a vertical transfer register. The present invention relates to a solid-state imaging device.

[0002]

2. Description of the Related Art A CCD solid-state image pickup device of all-pixel reading type has an excellent feature of high vertical resolution in order to read out signal charges of all pixels independently for each exposure cycle. Therefore, it is effective when used in the field of still images. In this all-pixel readout type CCD solid-state image pickup device, when the number of horizontal transfer registers is one and the horizontal drive frequency is the same as the horizontal drive frequency of a normal CCD solid-state image pickup device, image output of 30 frame rates is performed. .

However, in the case of outputting an image with a frame rate of 30, it is not possible to monitor the video by using the frame image as it is. For example, it is necessary to provide an external frame memory and its controller, which leads to cost reduction. It is disadvantageous. Frame rate 3
In the 0-pixel all-pixel-reading CCD solid-state imaging device, it is necessary to obtain an image output at a frame rate of 60 in order to enable video monitoring without using a frame memory.

[0004]

In order to output and monitor images of 60 frame rates, conventionally, a method of mixing signal charges of two vertical pixels in a horizontal transfer register has been adopted. However, this method is effective in the case of a monochrome CCD solid-state image pickup device or a CCD solid-state image pickup device having a stripe color filter, but it is a color CCD solid-state image pickup device having a primary color checkered array (Bayer array) color coding color filter. In the image pickup device, since the different colors are mixed by mixing the signal charges of two vertical pixels, there is a problem that the color signal processing cannot be performed.

The present invention has been made in view of the above problems, and an object thereof is a solid-state image pickup device capable of obtaining an interlaced image output with a frame rate of 60 sheets in an all-pixel reading system. To provide.

[0006]

A solid-state image pickup device according to the present invention is an all-pixel read-out type solid-state image pickup device, which is provided adjacent to a horizontal transfer register and selectively outputs signal charges in the horizontal transfer register. The charge discharging means for sweeping out to the charge transfer means, the processing for sweeping out the signal charges transferred to the horizontal transfer register to the charge discharging means and the processing for horizontal transfer are repeated line by line, and the line to be swept away to the charge discharging means for each field. It has a configuration including a driving means for switching.

In the solid-state image pickup device having the above-mentioned structure, the driving unit repeats the process of sweeping out the signal charges transferred to the horizontal transfer register to the charge discharging unit and the process of horizontal transfer in a line unit, so that the frame rate is 60 sheets. An interlaced image output of is obtained. As a result, it is possible to monitor an image without having an external frame memory, and since the signal charges of two vertical pixels are not mixed in the horizontal transfer register, a color CCD solid state having a color filter of primary color checkered array color coding. It can also be applied to an imaging device.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention applied to, for example, an interline transfer type CCD solid-state imaging device.

In FIG. 1, two-dimensionally arranged in a matrix in a row direction (vertical direction) and a column direction (horizontal direction),
A plurality of sensor units (photoelectric conversion units) 1 that convert incident light into signal charges having a charge amount corresponding to the amount of light and accumulate the signal charges, and read from each sensor unit 1 arranged in vertical columns of these sensor units 1. The image section 3 is composed of a plurality of vertical transfer registers 2, 2, ... Which vertically transfer the output signal charges.

In the image section 3, the sensor section 1 is composed of, for example, a PN junction photodiode, and the plurality of vertical transfer registers 2, 2, ... Are composed of CCDs. The signal charges accumulated in the sensor unit 1 are read out to the vertical transfer register 2 via a read gate (not shown). The vertical transfer register 2 is transfer-driven by, for example, three-phase vertical transfer clocks .phi.V1 to .phi.V3, and sequentially reads the read signal charges by a portion corresponding to one scanning line (one line) in a part of the horizontal blanking period. Vertical transfer.

On the lower side of the image portion 3 in the drawing, a horizontal transfer register 4 composed of a CCD is arranged in which signal charges are sequentially transferred from a plurality of vertical transfer registers 2, 2 ,. . The horizontal transfer register 4 is transfer-driven by the two-phase horizontal transfer clocks φH1 and φH2, and sequentially transfers the signal charges for one line transferred from the image section 3 in the horizontal scanning period after the horizontal blanking period.

At the end of the transfer destination of the horizontal transfer register 4,
For example, a floating diffusion amplifier (F
A charge detection unit 5 having a DA (Floating Diffusion Amplifier) configuration is arranged. The charge detection unit 5 detects the signal charge horizontally transferred by the horizontal transfer register 4 and converts it into a signal voltage. After passing through the output amplifier 6, this signal voltage is led to the outside from the output terminal 7 as a CCD output according to the incident amount of light from the subject.

On the opposite side of the horizontal transfer register 4 from the image part 3, a sweeping electrode 8 and a drain part 9 are provided adjacent to each other along the transfer direction of the horizontal transfer register 4. The sweep-out electrode 8 and the drain section 9 constitute a charge discharging section 10 for selectively sweeping out the signal charge in the horizontal transfer register 4, and the sweep-out clock φHHG is applied to the sweep-out electrode 8. Thus, the signal charges for one line in the horizontal transfer register 4 are swept to the drain section 9. A predetermined DC voltage Vdd is applied to the drain section 9.

A color filter (not shown) for primary color checkered array color coding is arranged on the image section 3. As shown in FIG. 2, this color filter has a color coding of G (green) checkered R (red) and B (blue) line sequential. As described above, all pixels can be sequentially read out through one horizontal transfer register 4 without mixing the signal charges read out independently from all the sensor parts (pixels) 1 in the vertical transfer register 2. A read-out type color CCD area sensor 11 is configured.

The all-pixel read-out type color CCD area sensor 11 is driven by a drive circuit 12.
The drive circuit 12 is composed of a timing generator, a driver, etc., and three-phase vertical transfer clocks φV1 to φV based on a reference signal such as a horizontal synchronizing pulse HD.
Various drive signals such as three- and two-phase horizontal transfer clocks φH1 and φH2 and a sweep clock φHHG are generated, and these drive signals are supplied to the CCD area sensor 12.

Then, the drive circuit 12 sequentially horizontally transfers the signal charges transferred from the image section 3 to the horizontal transfer register 4 in the normal mode in which a still image or the like is obtained based on a mode switching signal given from the outside. In a monitoring mode for obtaining a non-interlaced output with a frame rate of 30 sheets and monitoring an image, a signal charge transferred from the image unit 3 to the horizontal transfer register 4 is swept to the charge discharging unit 10 and a horizontal transfer process is performed. By repeating the line-by-line unit and exchanging the lines to be swept out for each field, driving is performed to obtain an interlaced output with a frame rate of 60 sheets.

The concept of the processing in the monitoring mode will be described below with reference to FIG. In the all-pixel readout type color CCD area sensor 11 having a color coding color filter as shown in FIG.
The color filter has 4 vertical lines and 2 horizontal lines.
Since pixels are used as a basic unit, the sweeping process of the signal charges in the horizontal transfer register 4 to the charge discharging unit 10 and the horizontal transfer process are repeated every two lines.

That is, in the first field (A),
The signal charges of the lines 1, 2, 5, 6, ... Are horizontally transferred by the horizontal transfer register 4 and output.
Processing for sweeping out the signal charges of each line to the charge discharging unit 10 via the horizontal transfer register 4. On the contrary, in the second field (B), the signal charges of the lines 1, 2, 5, 6, ...
The signal charges of the lines 3, 4, 7, 8, ... Are swept to 0 and horizontally transferred by the horizontal transfer register 4 to be output.

As described above, in the all-pixel read-out type color CCD area sensor 11 having the color filter of the primary color checkered array color coding, in the normal mode, the signal charges read out independently from all the pixels are transferred vertically. Non-interlaced signal outputs with a frame rate of 30 are obtained by transferring the data to the horizontal transfer register 4 line by line without mixing them and sequentially performing horizontal transfer by the horizontal transfer register 4. As a result, an image with high vertical resolution can be obtained.

On the other hand, in the monitoring mode, the signal charges read out to the horizontal transfer register 4 are transferred to the charge discharging section 10.
The process of sweeping away the signal charges to the charge discharging unit 10 is repeated every two lines, and the line of sweeping out the signal charges to the charge discharging unit 10 is replaced for each field to interlace the frame rate of 60 sheets. Signal output is obtained. As a result, it is possible to monitor an image without providing an external frame memory.

Next, as an example, two vertically adjacent
5 to 7 will be described based on the timing chart of FIG. 4 regarding the operation in which the signal charges for one line are swept to the charge discharging unit 10 and the signal charges for one line are horizontally transferred and output by the horizontal transfer register 4. This will be explained with reference to the potential diagram of FIG.

This processing operation is performed by the horizontal blanking signal H.
-BLK is at a low level (hereinafter referred to as "L" level) and the horizontal window signal H-Window is at "L" level. During this period, the horizontal transfer clock φH1 is fixed to the “L” level and φH2 is fixed to the high level (hereinafter referred to as the “H” level). 5 to 7, the vertical direction in the figures represents the depth of the potential, and the sweep clock φHHG applied to the sweep electrode 8 in FIG.
It is assumed that there are three levels of "L" level, intermediate level (hereinafter referred to as "M" level) and high level.

At time t1, the sweep clock φHHG
Is at the “L” level, the potential under the sweep electrode 8 is shallow. Further, among the three-phase vertical transfer clocks φV1 to φV3, only the second-phase vertical transfer clock φV2 is at a high level, and the potential under the second-phase transfer electrode is deep, so that the signal charge Are accumulated under the transfer electrodes of the second phase.

At time t2, the sweep clock φHHG
Changes from the “L” level to the “H” level, and the potential under the sweeping electrode 8 becomes deep. Then, along with the vertical transfer clock φV2 of the second phase, the vertical transfer clock φV1 of the first phase becomes the “H” level, and the potential under the transfer electrode of the first phase also becomes deeper. Signal charges of the above flow into under the transfer electrodes of the first phase. At time t3, the vertical transfer clock φV2 of the second phase is “L”.
The level becomes a level and the potential under the transfer electrode for the second phase becomes shallow, so that the signal charges under the transfer electrode for the second phase are completely transferred to and accumulated in the transfer electrode for the first phase.

At time t4, the vertical transfer clock φV3 of the third phase becomes the “H” level, and the potential under the transfer electrode of the third phase becomes deep, so that the signal charge under the transfer electrode of the first phase is 3 It flows under the transfer electrodes of the second phase, and further passes under the transfer electrodes of the second phase of the horizontal transfer register 4 and under the sweeping electrode 8, and is discarded to the drain section 9. At time t5, the vertical transfer clock φV1 of the first phase is “L”.
Since the potential under the first-phase transfer electrode becomes shallow, the signal charge under the first-phase transfer electrode is completely transferred under the third-phase transfer electrode, and the drain portion 9
Be swept away. At this time, the signal charge of the next line is accumulated under the transfer electrode of the third phase one line before.

At the time point t6, the vertical transfer clock φV2 of the second phase becomes "H" level, and the potential under the transfer electrode of the second phase becomes deep, so that the transfer electrode of the third phase one line before is transferred. The signal charge of the next line stored in the
It flows under the transfer electrode of the phase. At time t7, the vertical transfer clock φV3 of the third phase becomes the “L” level, and the potential under the transfer electrode of the third phase becomes shallow, so that the signal charge of the next line is below the transfer electrode of the second phase. Accumulated in.

At time t8, the vertical transfer clock φV1 of the first phase becomes “H” level, and the potential under the transfer electrode of the first phase becomes deep, so that the signal charge under the transfer electrode of the second phase is 1 It flows under the transfer electrode of the phase. Time point t9
Then, the vertical transfer clock φV2 of the second phase becomes the “L” level, and the potential under the transfer electrodes of the second phase becomes shallow, so that the signal charges under the transfer electrodes of the second phase are completely in the first phase. It is transferred under the transfer electrode and accumulated there.

At time t10, the vertical transfer clock φV3 of the third phase becomes "H" level, and the potential under the transfer electrode of the third phase becomes deep, so that the signal charge under the transfer electrode of the first phase is 3 It flows under the transfer electrode of the phase and further passes under the horizontal transfer register 4 and the sweeping electrode 8 and is discarded to the drain part 9. At time t11, the vertical transfer clock φV1 of the first phase becomes the “L” level, and the potential under the transfer electrode of the first phase becomes shallow, so that the signal charge under the transfer electrode of the first phase becomes the third phase. It is completely transferred under the transfer electrode and is further swept to the drain part 9.
At this time, the signal charge of the next line is accumulated under the transfer electrode of the third phase one line before.

At time t12, the vertical transfer clock φV2 of the second phase becomes “H” level, and the potential under the transfer electrode of the second phase becomes deep, so that the transfer electrode of the third phase one line before is transferred. The signal charge of the next line, which has been stored in, flows into below the transfer electrode of the second phase. At time t13, the vertical transfer clock φV3 of the third phase becomes “L” level, and the potential under the transfer electrode of the third phase becomes shallow, so that the signal charge of the next line is below the transfer electrode of the second phase. Accumulated in.

At time t14, the sweep clock φHH
As G becomes "M" level, the horizontal transfer clock .phi.H2, which has been fixed at "H" level until then, becomes "L" level. As a result, the potential under the second-phase transfer electrode of the horizontal transfer register 4 becomes shallow, and the potential under the sweep-out electrode 8 becomes an intermediate level. As a result, of the signal charges remaining in the horizontal transfer register 4, some of the signal charges remain below the sweep electrode 8, but most of them are swept to the drain portion 9.

At time t15, the sweep clock φHHG becomes "L" level, and the potential under the sweep electrode 8 becomes shallow, so that all the slight signal charges remaining under the sweep electrode 8 are all reduced. It will be swept to the drain portion 9. As described above, the process for sweeping the signal charges of two lines to the charge discharging unit 10 is completed.

Subsequently, at time t16, the horizontal transfer clock φH2 becomes "H" level again, the vertical transfer clock φV1 of the first phase becomes "H" level, and the potential under the transfer electrode of the first phase becomes high. Becomes deeper, the signal charges under the transfer electrodes of the second phase flow under the transfer electrodes of the first phase. Then, at time t17, the vertical transfer clock φV2 of the second phase becomes the “L” level, and the potential under the transfer electrode of the second phase becomes shallow, so that the signal charge under the transfer electrode of the second phase is completely discharged. It is transferred under the transfer electrode of the first phase.

At time t18, the vertical transfer clock φV3 of the third phase becomes the “H” level, and the potential under the transfer electrode of the third phase becomes deep, so that the signal charge under the transfer electrode of the first phase becomes It flows under the transfer electrodes of the third phase, and is further swept to the drain portion 9 through the transfer electrodes of the second phase of the horizontal transfer register 4 and the discharge electrodes 8. At time t19, the first phase vertical transfer clock φV
1 becomes the “L” level, and the potential under the transfer electrode of the first phase becomes shallow. Therefore, the signal charge under the transfer electrode of the first phase is transferred to the horizontal transfer register 4 under the transfer electrode of the third phase. Of the second phase of the transfer electrode. At this time, 1
The signal charge of the next line is accumulated under the transfer electrode of the third phase before the line.

At time t20, the vertical transfer clock φV2 of the second phase becomes “H” level, and the potential under the transfer electrode of the second phase becomes deep, so that the transfer electrode of the third phase one line before is transferred. Then, the signal charges of the next line accumulated in the above flow into the transfer electrodes below the second phase. Then, time t21
Then, the vertical transfer clock φV3 of the third phase becomes “L” level and the potential under the transfer electrode of the third phase becomes shallow, so that the signal charge under the transfer electrode of the third phase is completely transferred to the horizontal transfer register. No. 4 is transferred below the transfer electrode of the second phase, and the signal charges of the next line are accumulated below the transfer electrode of the second phase.

As described above, the processing for shifting the signal charges for one line to the horizontal transfer register 4 is completed. Then, the horizontal transfer clocks φH1 and φH2, which have been fixed to the “L” level and the “H” level until then, are generated, and the horizontal transfer driving of the horizontal transfer register 4 is started. As a result, the shifted signal charges for one line are sequentially horizontally transferred to the horizontal transfer register 4, converted into a signal voltage by the charge detection unit 5, and led out to the outside as a CCD output.

When the signal charges for the one line are shifted to the horizontal transfer register 4 for horizontal transfer and output without sweeping out the signal charges to the charge discharging section 10, FIG.
As shown in the timing chart of (1), the shift processing of the signal charges for one line to the horizontal transfer register 4 is performed in the above-mentioned two-line sweep-out period and one-line shift period.

[0037]

As described above, according to the present invention,
In the all-pixel readout type solid-state imaging device capable of sequentially reading out through one horizontal transfer register without mixing the signal charges read out independently from all the pixels, the signals are transferred to the horizontal transfer register. By repeating the process of sweeping out the signal charges and the process of horizontally transferring it in units of lines, and by switching the sweep-out lines for each field, it is possible to obtain an interlaced image output with a frame rate of 60 sheets. Video can be monitored without an external frame memory.

Moreover, since the signal charges of two vertical pixels are not mixed in the horizontal transfer register, the present invention can be applied to a color solid-state image pickup device having a color filter of primary color checkered array color coding. As a result, by using this function for image capture applications such as electronic still camera and PC (personal computer) image input, it is possible to monitor the subject before the main image capture, and at the time of image capture, still image of high vertical resolution. Can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention applied to an interline transfer type CCD solid-state imaging device.

FIG. 2 is a diagram showing primary color checkered array color coding.

FIG. 3 is a conceptual diagram of processing in a monitoring mode.

FIG. 4 is a timing chart for explaining an operation in the case of sweeping out two lines and outputting one line.

FIG. 5 is a potential diagram (No. 1) for explaining the operation in the case of sweeping out two lines and outputting one line.

FIG. 6 is a potential diagram (No. 2) for explaining the operation in the case of sweeping out two lines and outputting one line.

FIG. 7 is a potential diagram (No. 3) for explaining the operation in the case of sweeping away two lines and outputting one line.

FIG. 8 is a timing chart for explaining the operation in the case of 1-line output.

[Explanation of symbols]

1 Sensor Section 2 Vertical Transfer Register 3 Image Section 4 Horizontal Transfer Register 5 Charge Detection Section 8 Sweeping Electrode 9 Drain Section 10 Charge Discharge Section 11 CCD
Area sensor 12 drive circuit

Claims (2)

[Claims] 1. A solid-state imaging device capable of sequentially reading out signal charges read out independently from all pixels without being mixed, and sequentially read out through one horizontal transfer register, which is adjacent to the horizontal transfer register. Charge discharging means for selectively sweeping out the signal charges in the horizontal transfer register, processing for sweeping out the signal charges transferred to the horizontal transfer register to the charge discharging means, and processing for horizontal transfer. And a driving means for switching the lines to be discharged to the electric charge discharging means for each field. 2. The solid-state image pickup device according to claim 1, which is a color solid-state image pickup device having a color filter of a primary color checkered pattern color coding, wherein the driving unit sweeps to the charge discharging unit and horizontally transfers. A solid-state imaging device characterized by repeating the above for every two lines.