JP2005354656A - Pixel array apparatus, solid-state imaging apparatus, and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of processing a high-quality video signal at high speed, without generating moires or false signals in the solid-state imaging apparatus that uses a solid-state imaging device capable of at least reducing the number of pixels in the horizontal direction. <P>SOLUTION: A solid-state imaging device 101, comprising two-dimensionally arrayed photoelectric conversion elements outputs signal charges read from the photoelectric conversion elements in an order different from the two-dimensional array, a signal converting section 13 converts the signal charges into pixel data, and a rearrangement section 15 rearranges the converted pixel data for 2n+1 rows so as to match the two-dimensional array. The rearrangement section 15 comprises a plurality of line memories and rearranges the pixel data by writing the pixel data one by one, while selecting each of the line memories in order for the unit of one pixel data transfer period, when writing the pixel data and by reading the pixel data for corresponding to a single one row while selecting each of the line memories in the order for the unit of a pixel data transfer period corresponding to a single row. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device including a solid-state imaging device that converts received light into an electrical signal and outputs the signal as a video signal and a signal processing circuit.

In recent years, development of a solid-state imaging device including a solid-state imaging device that converts received light into an electrical signal and a signal processing circuit that converts the electrical signal into a video signal has been actively promoted.
The solid-state imaging device is widely used in digital cameras such as digital still cameras and digital video cameras. However, there is a strong demand for improving the image quality of digital cameras, and the density of pixels in a solid-state imaging device is rapidly increasing. It is out.

In a digital camera, when a captured image is used as a moving image, there are restrictions on the output speed of the video signal. There has been proposed a method of reducing the number of pixels in the output video signal by thinning out pixels to be read.
For example, in Patent Document 1 (Japanese Patent Application Laid-Open No. 11-234688), signal charges of two pixels (two pixels at both ends) excluding a central pixel in each block are set in a solid-state imaging device, assuming three pixels in the horizontal direction as one block. Drive that reduces the number of pixels in the horizontal direction in the output video signal from the solid-state imaging device by mixing and mixing the signal charge of one pixel at the center of the block with the signal charge of one pixel at the center of the adjacent block A method is disclosed.
Japanese Patent Laid-Open No. 11-234688

  However, at the time of 1/3 decimation in the horizontal direction, a component of one third of the sampling frequency at the time of output of all pixels is folded back and added to the DC component of the signal. However, in the solid-state imaging device by the conventional driving method described above, Since the one-third component of the sampling frequency is not 0, there is a problem that the image quality of the output video signal deteriorates due to the occurrence of moire or the generation of a false signal.

  In view of the above problems, the present invention is a solid-state imaging device using a solid-state imaging device capable of reducing at least the number of pixels in the horizontal direction, and capable of outputting a high-quality video signal at high speed without causing moire or false signals. An object is to provide an imaging device.

  In order to solve the above problem, the present invention is a pixel array device that rearranges a plurality of pixel data received from a solid-state image sensor, and receives a plurality of pixel data sequentially transmitted from the solid-state image sensor. As a result, an acquisition unit that acquires a pixel data sequence, an extraction unit that extracts pixel data from the acquired pixel data sequence at regular intervals, and an array that arranges the extracted pixel data in a single row in the order of extraction Means.

  With the above-described configuration, the pixel array device of the present invention can extract pixel data inserted at regular intervals into a pixel data string received from a solid-state imaging device, and form a continuous data string. In particular, the solid-state imaging device does not continuously output pixel data corresponding to the rows of the two-dimensional array for the two-dimensional array of pixel data related to the captured image, and the pixel data is output to the pixel data string at regular intervals. In the case of inserting and outputting, it is possible to reconstruct the image captured by the solid-state imaging device by rearranging the pixel data related to the pixel data string.

  Here, the extraction means extracts the pixel data as first pixel data every two intervals from a predetermined start position in the acquired pixel data sequence, and further, a position four positions after the start position. The second pixel data is extracted every two intervals, the third pixel data is extracted every two intervals from the eight positions after the start position, and the arrangement means extracts the extracted first pixels The pixel data is arranged in a line in the order of extraction, the extracted second pixel data is arranged in a line in the order of extraction, and the extracted third pixel data is arranged in a line in the order of extraction May be.

  According to this configuration, it is possible to extract pixel data inserted at intervals of two into a pixel data string received from a solid-state imaging device, and form a continuous data string. In particular, the solid-state imaging device does not continuously output pixel data corresponding to the rows of the two-dimensional array for the two-dimensionally arrayed pixel data related to the captured image, and the pixel data string is spaced by two at regular intervals. When inserting and outputting pixel data for three rows, it is possible to reconstruct the image captured by the solid-state imaging device by rearranging the pixel data related to the pixel data string.

Here, the extraction unit extracts a predetermined number of pixel data as the first pixel data, extracts a predetermined number of pixel data as the second pixel data, and sets a predetermined number as the third pixel data. Several pieces of pixel data may be extracted.
According to this configuration, in the pixel data string, pixel data of a portion where screen display is not performed, such as the left and right ends of the image, can be removed, restoration of an image from which invalid pixel data is deleted, deletion of invalid pixel data Can speed up data processing.

Here, the extraction means outputs a storage means, a writing means for writing the pixel data string in a predetermined continuous address area of the storage means in the order of reception, and an address at regular intervals in the continuous address area. And an address control unit that reads the pixel data from each of the output addresses and arranges the pixel data in a line.
The address control means includes a control signal receiving means for receiving a reference clock and a horizontal synchronization signal from outside the device, a horizontal counter for counting and outputting a horizontal counter value in synchronization with the reference clock, and a horizontal counter. A vertical counter that counts and outputs a vertical counter value in synchronization with a synchronization signal, and an address calculation means that calculates and outputs an address indicated by ax + by + c based on the horizontal and vertical counter values (x is the horizontal counter value, y May include the vertical counter value, a and b are predetermined constants, and c is a reading start address corresponding to a position where extraction is started.

  According to this configuration, the pixel data string output from the solid-state imaging device is temporarily held in the continuous address area of the storage unit, and the pixel data is read from the addresses at regular intervals in the continuous address area. Pixel data inserted at regular intervals can be extracted to form a continuous data string, and in particular, a solid-state imaging device including a two-dimensionally arranged photoelectric conversion element has pixel data corresponding to a row of the two-dimensional array. Is not output continuously, but is inserted into the pixel data string at a predetermined interval for output, the image data based on the image image captured by the solid-state image sensor can be restored.

  Here, the extraction means includes storage means including three line memories, and control means for selecting one line memory in order from the three line memories for each pixel data transfer period, The arrangement unit may include a writing unit that extracts one piece of pixel data from the pixel data string based on the order of reception and writes the extracted pixel data to a selected line memory.

  According to this configuration, the pixel data string output from the solid-state imaging device is sequentially input to the first line memory, the second line memory, the third line memory, the first line memory, and the like in the order of reception. Since the data is distributed, the pixel data inserted into the pixel data string at a constant interval can be extracted to form a continuous data string. In particular, the solid-state image sensor has two-dimensionally arranged pixel data related to the captured image. When the pixel data corresponding to the rows of the two-dimensional array is not continuously output, and the pixel data is inserted into the pixel data string at a predetermined interval and output, the pixel data related to the pixel data string is rearranged. Thus, the image captured by the solid-state image sensor can be restored.

Here, the writing means may write pixel data other than a predetermined exclusion position in the pixel data string to the line memory.
According to this configuration, in the pixel data string, pixel data of a portion where screen display is not performed, such as the left and right ends of the image, can be removed, restoration of an image from which invalid pixel data is deleted, deletion of invalid pixel data Can speed up data processing.

Here, the arrangement means may include reading means for reading out a predetermined number of pixel data and reading out a predetermined number of pixel data when reading data written in each line memory.
According to this configuration, among the data written in the line memory, pixels corresponding to a portion that performs screen display are not used even if pixel data corresponding to a portion that does not perform screen display, such as the left and right ends of an image, is read The image data can be restored using only the data, the restoration of the image from which the invalid pixel data is deleted, and the speeding up of the data processing by the deletion of the invalid pixel data can be performed.

Here, the arrangement means may include a reading means for reading data in a continuous address predetermined for each line memory when reading data written in each line memory.
According to this configuration, out of the data written in the line memory, the pixel data corresponding to the portion that does not perform screen display, such as the left and right ends of the image, is not read, but only the pixel data corresponding to the portion that performs screen display is read. Thus, it is possible to restore the image data, and it is possible to restore the image from which the invalid pixel data is deleted and to speed up the data processing by deleting the invalid pixel data.

Here, the arrangement means includes a 2-port memory that processes reading and writing of data in parallel, and a photoelectric conversion unit 2 included in the solid-state imaging device when the pixel data is written to or read from the 2-port memory. And a data processing unit that executes based on the dimensional array.
According to this configuration, by performing rearrangement using a two-port memory, the pixel data read operation from the solid-state image sensor and the pixel data output operation for video output can be performed in parallel. Can be output at high speed in response to an output request.

  In order to solve the above-described problems, the present invention is a solid-state imaging device, and includes a solid-state imaging device including a plurality of two-dimensionally arranged photoelectric conversion units, and a signal processing circuit thereof. In order to transfer the signal charge read from each photoelectric conversion unit in the vertical direction, a vertical transfer unit provided corresponding to each column of the photoelectric conversion unit, and the signal charge received from the vertical transfer unit in the horizontal direction A vertical final stage, which is the transfer stage closest to the horizontal transfer unit in the vertical transfer unit, has the same transfer electrode configuration for every 2n + 1 (n is an integer of 1 or more) columns, Of the 2n + 1 columns, the transfer operation from the vertical final stage to the horizontal transfer unit is performed independently of the other vertical final stages in the 2n + 1 column in the vertical final stage other than one column or in all vertical final stages. To control A transfer electrode that is independent of the other vertical final stage, and the signal processing circuit converts each signal charge transferred from the horizontal transfer unit into pixel data, and sequentially outputs the converted data. The pixel array device, and the pixel array device extracts pixel data from the acquired pixel data sequence at regular intervals from an acquisition unit that acquires a pixel data sequence as a result of receiving a plurality of the pixel data. And extracting means for arranging the extracted pixel data in a line in the order of extraction.

  Here, the vertical final stage, which is the transfer stage closest to the horizontal transfer section in the vertical transfer section, has the same transfer electrode configuration for every three columns, and the vertical final stages other than one of the three columns Alternatively, in order to control the transfer operation from the vertical final stage to the horizontal transfer unit to all vertical final stages independently from the other vertical final stages in the three columns, An independent transfer electrode may be provided. According to this configuration, it is possible to extract pixel data inserted at regular intervals into a pixel data string received from a solid-state imaging device, and form a continuous data string. In particular, the solid-state imaging device does not continuously output pixel data corresponding to the rows of the two-dimensional array for the two-dimensional array of pixel data related to the captured image, and the pixel data is output to the pixel data string at regular intervals. In the case of inserting and outputting, it is possible to restore the image captured by the solid-state imaging device by rearranging the pixel data related to the pixel data string.

  Here, the extraction means extracts the pixel data as first pixel data every two intervals from a predetermined start position in the acquired pixel data sequence, and further, a position four positions after the start position. The second pixel data is extracted every two intervals, the third pixel data is extracted every two intervals from the eight positions after the start position, and the arrangement means extracts the extracted first pixels The pixel data is arranged in a line in the order of extraction, the extracted second pixel data is arranged in a line in the order of extraction, and the extracted third pixel data is arranged in a line in the order of extraction May be.

  According to this configuration, it is possible to extract pixel data inserted at intervals of two into a pixel data string received from a solid-state imaging device, and form a continuous data string. In particular, the solid-state imaging device does not continuously output pixel data corresponding to the rows of the two-dimensional array for the two-dimensionally arrayed pixel data related to the captured image, and the pixel data string is spaced by two at regular intervals. When inserting and outputting pixel data for three rows, it is possible to reconstruct the image captured by the solid-state imaging device by rearranging the pixel data related to the pixel data string.

Here, the extraction unit extracts a predetermined number of pixel data as the first pixel data, extracts a predetermined number of pixel data as the second pixel data, and sets a predetermined number as the third pixel data. Several pieces of pixel data may be extracted.
According to this configuration, in the pixel data string, pixel data of a portion where screen display is not performed, such as the left and right ends of the image, can be removed, restoration of an image from which invalid pixel data is deleted, deletion of invalid pixel data Can speed up data processing.

Here, the extraction means outputs a storage means, a writing means for writing the pixel data string in a predetermined continuous address area of the storage means in the order of reception, and an address at regular intervals in the continuous address area. And an address control unit that reads the pixel data from each of the output addresses and arranges the pixel data in a line.
The address control means includes a control signal receiving means for receiving a reference clock and a horizontal synchronization signal from outside the device, a horizontal counter for counting and outputting a horizontal counter value in synchronization with the reference clock, and a horizontal counter. A vertical counter that counts and outputs a vertical counter value in synchronization with the synchronization signal, and ax + by + c (x is the horizontal counter value, y is the vertical counter value, and a and b are respectively based on the horizontal and vertical counter values. The predetermined constant, c, may include address calculation means for calculating and outputting an address indicated by a reading start address corresponding to a position at which extraction starts.

  According to this configuration, the pixel data string output from the solid-state imaging device is temporarily held in the continuous address area of the storage unit, and the pixel data is read from addresses at regular intervals in the continuous address area. Pixel data inserted at a constant interval can be extracted to form a continuous data string. In particular, a solid-state imaging device including a two-dimensionally arranged photoelectric conversion element has pixel data corresponding to a row of the two-dimensional array. Is not output continuously, but is inserted into the pixel data string at a predetermined interval for output, the image data based on the image image captured by the solid-state image sensor can be restored.

  Here, the extraction means includes storage means including three line memories, and control means for selecting one line memory in order from the three line memories for each pixel data transfer period, The arrangement unit may include a writing unit that extracts one piece of pixel data from the pixel data string based on the order of reception and writes the extracted pixel data to the selected line memory.

  According to this configuration, the pixel data string output from the solid-state imaging device is sequentially input to the first line memory, the second line memory, the third line memory, the first line memory, and the like in the order of reception. Since the data is distributed, the pixel data inserted into the pixel data string at a constant interval can be extracted to form a continuous data string. In particular, the solid-state image sensor has two-dimensionally arranged pixel data related to the captured image. When the pixel data corresponding to the rows of the two-dimensional array is not continuously output, and the pixel data is inserted into the pixel data string at a predetermined interval and output, the pixel data related to the pixel data string is rearranged. Thus, the image captured by the solid-state image sensor can be restored.

Here, the writing means may write pixel data other than a predetermined exclusion position in the pixel data string to the line memory.
According to this configuration, in the pixel data string, pixel data of a portion where screen display is not performed, such as the left and right ends of the image, can be removed, restoration of an image from which invalid pixel data is deleted, deletion of invalid pixel data Can speed up data processing.

Here, when reading out the pixel data written in each line memory, the arrangement means may include a reading means for reading out the remaining number of pixel data by reading out a predetermined number of pixel data for each line memory.
According to this configuration, among the data written in the line memory, pixels corresponding to a portion that performs screen display are not used even if pixel data corresponding to a portion that does not perform screen display, such as the left and right ends of an image, is read The image data can be restored using only the data, the restoration of the image from which the invalid pixel data is deleted, and the speeding up of the data processing by the deletion of the invalid pixel data can be performed.

Here, the arrangement means may include reading means for reading pixel data in a continuous address predetermined for each line memory when reading pixel data written in each line memory.
According to this configuration, out of the data written in the line memory, the pixel data corresponding to the portion that does not perform screen display, such as the left and right ends of the image, is not read, but only the pixel data corresponding to the portion that performs screen display is read. Thus, it is possible to restore the image data, and it is possible to restore the image from which the invalid pixel data is deleted and to speed up the data processing by deleting the invalid pixel data.

Here, the rearrangement unit includes a two-port memory that processes reading and writing of pixel data in parallel, and a photoelectric conversion unit included in the solid-state imaging device when the pixel data is written to or read from the two-port memory. And a data processing unit based on the two-dimensional array.
According to this configuration, by performing rearrangement using a two-port memory, the pixel data read operation from the solid-state image sensor and the pixel data output operation for video output can be performed in parallel. Can be output at high speed in response to an output request.

In addition, the present invention is a camera including the pixel array device.
Moreover, this invention is a camera provided with the said solid-state imaging device.
According to this configuration, since data is output from the solid-state imaging device at high speed, a camera capable of high-speed operation can be realized.

The best embodiment of the present invention will be described with reference to the drawings.
<1. Configuration>
First, the solid-state imaging device according to the present invention will be described.
FIG. 19 is a diagram illustrating a schematic configuration of the solid-state imaging device.
The solid-state imaging device 101 employs an all-pixel simultaneous independent readout method, and includes a photoelectric conversion unit 102, a vertical transfer unit 103, and a horizontal transfer unit 104 that are two-dimensionally arranged corresponding to the pixels.

The photoelectric conversion unit 102 is configured by a photodiode.
In each of the photoelectric conversion units 102, three color filters of red (R), green (G), and blue (B) are periodically arranged every two pixels in the vertical and horizontal directions.
Each of the vertical transfer unit 103 and the horizontal transfer unit 104 is configured by a CCD (Charge Coupled Device).

For example, when a total of 4 pixels of 2 pixels in the vertical direction and 2 pixels in the horizontal direction is taken as one unit, the lower left pixel is R, the lower right and upper left pixels are G, and the upper right pixel is B as shown in FIG. Arrange the color filters as shown.
The solid-state imaging device 101 operates when a control signal is sent from a control unit (not shown) to the transfer electrodes of the vertical transfer unit 103 and the horizontal transfer unit 104.

The control unit is provided outside the solid-state image sensor 101 and is connected to the solid-state image sensor 101 through a signal line.
The control unit may be formed integrally with the solid-state image sensor 101.
The vertical transfer unit 103 sets three rows of the photoelectric conversion units 102 in the vertical direction as one transfer stage.

Here, the pixel mixing operation in the horizontal direction in the solid-state imaging device 101 will be described.
In the solid-state imaging device 101, a control unit (not shown) controls transfer operations of the vertical transfer unit 103 and the horizontal transfer unit 104, thereby mixing signal charges for every third pixel every other pixel in the horizontal direction. The number of pixels in the direction is reduced to 1/3.
FIG. 20 is a diagram schematically showing a combination of pixels for mixing signal charges.

Hereinafter, a combination of pixels to be mixed is referred to as a mixed pixel group.
In the symbol shown as Rxy in FIG. 20, R, G, and B represent the color of the filter of the pixel, and x is the vertical position of the pixel (from the side closer to the horizontal transfer unit 104, the first stage, the second Y) represents the position of the pixel in the mixed pixel group (first, second,... From the side closer to the output side of the horizontal transfer unit 104). To do.

As illustrated in FIG. 20, the solid-state imaging device 101 includes, for example, three green pixels every other pixel as the first mixed pixel group, such as G11, G12, and G13.
Further, the mixed pixel group of blue pixels is determined so as to be equidistant from the center of gravity of the mixed pixel generated by the first mixed pixel group.
That is, B11 between G12 and G13 of the first mixed pixel group, B12 which is a pixel between G13 and G11 of the adjacent mixed pixel group, and G11 and G12 of the adjacent mixed pixel group Three pixels with B13 between them are set as a second mixed pixel group.

In this way, by combining two pixels of two colors alternately arranged in the horizontal direction and mixing them every other pixel, the pixel centroids of each color after mixing are equally spaced. Does not occur.
Next, a driving procedure of the solid-state imaging device 101 for performing pixel mixing with the combination shown in FIG. 20 will be described using the state transition diagrams of FIGS.

The vertical transfer unit 103 of the solid-state image sensor 101 is configured in units of three columns.
In FIG. 21 to FIG. 31, the signal charges of the horizontal transfer unit 104 are output to the left side, and the vertical transfer units 103 in units of three columns are sequentially connected from the side closer to the output side of the horizontal transfer unit 104. , First column, second column, and third column (in the figure, they are expressed as one column, two columns, and three columns).
In the vertical transfer unit 103, the transfer stage closest to the horizontal transfer unit 104 is hereinafter referred to as a vertical final stage.

Of the vertical final stages of the vertical transfer unit 103 configured in units of three columns, the vertical final stages of the second column and the third column are both the other transfer stages of the same column and the vertical final stages of other columns. Each is configured to be able to transfer independently and independently.
That is, it is possible to transfer only the signal charges of the vertical final stage of the second column to the horizontal transfer unit 104 while holding the signal charges in the vertical final stages of the first column and the third column.

Further, only the signal charges at the vertical final stage of the third column can be transferred to the horizontal transfer unit 104 while the signal charges are held in the vertical final stages of the first column and the second column.
First, as shown in FIG. 21, by driving only the vertical final stage of the second column among the vertical final stages in units of three columns, the vertical column of the second column is represented as indicated by an arrow in FIG. Only the signal charge of the final stage is transferred to the horizontal transfer unit 104.

Next, as shown in FIG. 22, the signal charges of the horizontal transfer unit 104 are transferred by two pixels in the forward direction.
Next, as shown in FIG. 23, by driving only the vertical final stage in the third column among the vertical final stages in units of three columns, as indicated by the arrows in FIG. The signal charges of only the vertical final stage are transferred to the horizontal transfer unit 104.

As a result, as shown in FIG. 24, the signal charges of two pixels of G12 and G13 and B12 and B13 are mixed in the horizontal transfer unit 104, respectively.
Further, as shown in FIG. 24, the signal charges of the horizontal transfer unit 104 are transferred by two pixels in the forward direction.
Next, as shown in FIG. 25, by causing all the vertical transfer units 103 to perform vertical transfer for one stage, as shown in FIG. 26, the signal charges of the three pixels G11, G12, and G13, and The signal charges of B11, B12, and B13 are mixed in the horizontal transfer unit 104, respectively.

In this way, since the two color pixels in the same stage are mixed in a combination of three pixels every other pixel, the number of pixels in the horizontal direction is reduced to 1/3.
Further, as can be seen from FIG. 26, since the green mixed pixel and the blue mixed pixel are equally spaced, moire and false signals do not occur.
Further, by repeating the same transfer operation as the operation shown in FIGS. 21 to 25 from the state shown in FIG. 26, the signal charge in the vertical final stage in the state shown in FIG. 26 becomes as shown in FIG. In addition, the horizontal transfer unit 104 mixes every third pixel in a combination of three pixels.

Further, by repeating the same transfer operation as the operation shown in FIGS. 21 to 25 from the state shown in FIG. 27, the signal charge in the vertical final stage in the state shown in FIG. 27 is changed as shown in FIG. In addition, the horizontal transfer unit 104 mixes every third pixel in a combination of three pixels.
As a result, the signal charges of all the pixels for the three stages shown by a in FIG. 20 are transferred to the horizontal transfer unit 104.

Next, as shown in FIG. 29, by sequentially outputting signal charges in the horizontal transfer unit 104, the signal charges for three rows from the solid-state imaging device 101 are reduced to 1/3 of the number of pixels in the horizontal direction. Is output in the processed state.
Thereafter, by repeating the same transfer operation as described above, the signal charges of all the pixels for three stages shown in FIG. 20B are transferred to the horizontal transfer unit 104 in the state shown in FIG. As shown in FIG.

As described above, since the image signal output from the horizontal transfer unit 104 of the solid-state imaging device 101 is one-dimensionally arranged pixels, in order to return this signal to the original two-dimensional array, the solid-state imaging In the image processing apparatus outside the element 101, processing for rearranging the output signals from the horizontal transfer unit 104 two-dimensionally is performed.
The two-dimensional rearrangement method will be described later.

As shown in FIG. 32, if three pixels are arranged every other pixel in the horizontal direction and three pixels are arranged every other row in the vertical direction, for a total of nine pixels as one mixed pixel group, all the photodiode signals Since mixing can be performed without throwing away pixels, sensitivity can be improved, which is preferable.
In this case, the center of gravity of the mixed pixel group for each of RGB is equally spaced as shown in FIG.

Therefore, it is possible to obtain an image with high resolution and little moire.
In this case, for example, a method of mixing signal charges for every three rows in the vertical direction is as follows.
(1) First, the signal charges of 1/3 pixels every two rows are read out to the vertical transfer unit 103 and vertically transferred by two pixels.

(2) Next, the signal charge of the second pixel in the forward direction is read from the previously read pixel to the vertical transfer unit 103, mixed with the previously read pixel, and vertically transferred by two pixels.
(3) Further, the signal charges of the remaining pixels are read out to the vertical transfer unit 103, and the signal charges of three pixels every other pixel are mixed.
Note that the above operation is possible in the case of an electrode structure (six phases) with three vertical transfer stages.

In addition, in the case of an electrode structure (four phases) in which the vertical transfer stage is for two pixels, it is necessary to make all the readout electrodes corresponding to the six pixels included independent of the three stages as one unit. Eight phases are required.
For example, as shown in FIG. 33, a total of 6 pixels obtained by thinning out the middle row in the vertical direction from the 9 pixels shown in FIG. 32 may be used as one mixed pixel group.

Also in this case, since the center of gravity of the mixed pixel group for each of RGB is equally spaced, an image with high resolution and little moire can be obtained.
Further, as shown in FIG. 34, two out of three rows in the vertical direction may be thinned out, and only three pixels in the horizontal direction may be used as one mixed pixel group.
As described above, the signal output speed can be further improved by reducing the number of pixels in the vertical direction by thinning out the rows.

As a method of reducing the number of pixels in the vertical direction, for example, when signal charges are read out from the photodiodes constituting the pixels to the vertical transfer unit 103, unnecessary rows of charges are not accumulated but are accumulated in the photodiodes. There is a method of thinning out pixels in a row that has not been read out.
In this case, the signal charge that has not been read out may be discharged from the photodiode to the substrate or the like.

Here, FIG. 35 shows an example of an electrode structure for realizing the drive described above.
In the electrode structure shown in FIG. 35, each of the vertical transfer stages of the vertical transfer unit 103 is configured by six-phase transfer electrodes (common electrodes) V1 to V6.
However, only the vertical final stage is different in electrode structure from the other vertical transfer stages.
That is, the second column of the vertical final stage performs the transfer operation independently of any of the other vertical transfer stages and the other columns (first column and third column) in the vertical final stage. And the 5th phase is comprised by the independent electrode (VC1, VC2) different from the above-mentioned common electrode.

In addition, the third column of the vertical final stage has a third phase in order to perform the transfer operation independently of any of the other vertical transfer stages and the other columns (first column and second column) in the vertical final stage. The fifth phase includes independent electrodes (VC3, VC4) that are different from both the common electrode and the second row of independent electrodes.
Note that the first column of the vertical final stage is composed of the common electrodes V1 to V6 as in the other vertical transfer stages.

By adopting such an electrode structure, it becomes possible to perform the transfer operation independently in the second and third columns of the vertical final stage every three columns, and the transfer operations as shown in FIGS. Can be realized.
Alternatively, as shown in FIG. 36, the third column and the fifth phase of the first column of the vertical final stage may be configured by independent electrodes (VC5, VC6).

When this configuration is adopted, in the state shown in FIG. 25, all the vertical transfer units 103 perform the transfer operation at the same time. Step transfer may be performed.
When the vertical transfer unit 103 is 6-phase driven, two or three of the six electrodes in the second and third columns (or all of the first to third columns) in the vertical final stage are: An independent electrode is preferred.

A structural example in which three transfer electrodes are used as independent electrodes in the vertical final stage is shown in FIGS.
These two or three independent electrodes may be adjacent to each other, but in consideration of the manufacturing process, it is preferable that at least one common electrode is interposed between the independent electrodes.

Therefore, in the case of 6-phase driving, as shown in FIGS. 35 and 36, for example, the second and fourth from the side closer to the horizontal transfer section 104 are independent electrodes, or, for example, FIGS. As shown in FIGS. 4A and 4B, it is preferable that the second, fourth and sixth from the side closer to the horizontal transfer unit 104 are independent electrodes.
However, the electrode structure of the vertical final stage is not limited to these specific examples.

Further, in the present embodiment, the six-phase driving electrode structure is illustrated, but three-phase or four-phase may be used.
However, in the case of three-phase or four-phase driving, the number of independent electrodes is two.
FIG. 39 is a diagram showing an example of a specific arrangement of the gate electrodes in the electrode structure as shown in FIGS.

In FIG. 39, the transfer path 152 formed between the channel stops 151 becomes the vertical transfer unit 103.
In the example of FIG. 22, in the transfer stage other than the vertical final stage in the vertical transfer unit 103, the three transfer electrodes V2, V4, and V6 are extended over the entire column by the same-layer electrode film (first layer electrode). It is formed as a common electrode.

  Similarly, the three transfer electrodes V1, V3, and V5 are also used as a common electrode across all the columns by the same layer of electrode film (second layer electrode) formed above the first layer electrode. Is formed. On the other hand, in the vertical final stage, the same electrode film as that of the second layer electrode is formed into a pattern shape separated into islands in each column, so that third-phase and fifth-phase transfer electrodes (horizontal transfer unit 104). 2nd and 4th electrodes from the side close to) are formed as independent electrodes.

As shown in FIG. 35, if the first column of the vertical final stage is not driven independently, φV3A and φV5A shown in FIG. 39 may be connected to the same terminal as φV3 and φV5.
Here, taking the electrode structure shown in FIG. 35 as an example, a timing chart of control signals given from the control unit (not shown) to the transfer electrodes of the vertical transfer unit 103 and the horizontal transfer unit 104, and according to this timing chart The state of the transferred charges is shown in FIG.

In the case of this electrode structure, as shown in FIG. 41, signal charges read from the photoelectric conversion unit 102 are accumulated in the transfer electrodes V3 and V4.
In FIG. 40, when the drive pulses applied to V1 to V6 and VC1 to VC4 are at a high level, the electrodes serve as storage units.
Further, when the drive pulse is at a low level, the electrode serves as a barrier portion.

By driving the vertical transfer unit 103 and the horizontal transfer unit 104 in accordance with the timing chart shown in FIG. 40, pixel mixing as described in this embodiment can be realized.
As shown in FIG. 40, it is preferable to set φV2 to the high level (t1) before the timing (t2) to set φV4 to the low level.
By setting φV2 to the high level at time t1, the signal charge storage electrodes become φV3 and φV4 before time t1, and become φV2, φV3 (φVC3), φV4 during times t1 to t2, and times t2 to t3. In this period, φV2 and φV3 (φVC3).

Accordingly, there is an advantage that loss of signal charges in the vertical transfer stage that is not transferred can be prevented during the period in which the signal charges are moved to the horizontal transfer unit 104.
Next, a solid-state imaging device using the solid-state imaging element 101 will be described.
FIG. 1 is a block diagram showing the configuration of the solid-state imaging device of the present invention.
The solid-state imaging device 101 is the above-described solid-state imaging device, converts received light into an electrical signal, and outputs the electrical signal to the signal conversion unit 13.

The solid-state image sensor driving unit 12 controls the solid-state image sensor 101 by outputting a control signal.
The signal conversion unit 13 performs each process of CDS (Correlated Double Sampling), AGC (Auto Gain Control), and A / D (Analog / Digital) conversion on the electric signal input from the solid-state imaging device 101.

The CDS removes noise from the electrical signal output from the solid-state image sensor 101.
The AGC applies a gain to the signal after noise removal by the CDS and adjusts the output level of the signal.
In the A / D conversion, the level-adjusted solid-state imaging data after the AGC is converted into a digital signal.

The signal conversion unit 13 outputs the converted digital signals for three lines at a time to the rearrangement unit 15.
An SSG (Sync Signal Generator) 14 generates a reference signal that determines the drive timing of the solid-state imaging device 101 and the signal processing unit 19.
The SSG 14 outputs a reference signal that determines the start timing of the field (screen) and the start of the horizontal line to the rearrangement unit 15, and the rearrangement unit 15 outputs the digital signal output by the signal conversion unit 13 according to the reference signal. Perform rearrangement processing.

As described above, the digital signal output from the horizontal transfer unit of the solid-state imaging device 101 and processed by the signal conversion unit 13 corresponds to the pixel arranged one-dimensionally, and the signal is converted into the original two-dimensional array. The process of returning to is a rearrangement process.
For example, it is assumed that data corresponding to the pixels for three stages shown in FIGS. 20A and 20B are input to the rearrangement unit 15 in the order shown in FIG.

FIG. 2 is a schematic diagram showing the input order of data from the signal conversion unit 13 to the rearrangement unit 15.
FIG. 3 is a schematic diagram showing a two-dimensional array of pixel data corresponding to the electrical signal generated by the solid-state image sensor 101.
In FIG. 2, a portion denoted by (dummy) refers to a pixel located in the peripheral portion of the vertical transfer unit 103 and in which signal charges for three pixels are not mixed.
Further, a7 to a12, a13 to a18, b7 to b12, and b13 to b18 shown in FIG. 2 are repetitions of a1 to a6 and b1 to b6 shown in FIGS. 29 and 31, respectively, but two-dimensionally arranged. The subscript is changed to make the later position easier to understand.

The rearrangement unit 15 performs rearrangement processing for rearranging the input data shown in FIG. 2 into the original two-dimensional array shown in FIG.
Details of the rearrangement process will be described later.
A DRAM (Dynamic Random Access Memory) 16 holds the digital data rearranged by the rearrangement unit 15.

The DRAM control unit 17 receives from the rearrangement unit 15 the solid-state image sensor data obtained by rearranging the digital signals into signals for each line, and causes the DRAM 16 to hold the data.
Further, the DRAM control unit 17 reads the rearranged solid-state image sensor data from the DRAM 16 and outputs it to the output signal generation unit 18.
The output signal generation unit 18 performs Y signal processing for generating and outputting luminance and C signal processing for generating and outputting color difference, using the solid-state imaging device output data after passing through the rearrangement block as an input.

The output signal generation unit 18 generates and outputs a luminance signal in the Y signal processing. However, since the video after conversion from the solid-state image sensor output data to the Y signal may have a sharp image, further contour correction is performed. Edge enhancement is performed by performing processing.
<2. Operation>
FIG. 4 is a block diagram showing a configuration of the rearrangement unit 15.

As shown in FIG. 2, data from a <b> 1 to b <b> 30 is sequentially input to the input unit 60 from the signal conversion unit 13.
Each of the line memories 51 to 56 holds eight pieces of data input from the signal conversion unit 13 to the rearrangement unit 15 and has a horizontal address (HA) for each data holding area.

Here, in order to simplify the description, the data held in the line memories 51 to 56 is eight, but it is natural that the number of data is not limited to eight, and according to the number of pixel data of the solid-state image sensor. Increase or decrease.
The data held by each line memory corresponds to one horizontal line of the image, and is eight data in this embodiment.

Here, a memory group including the line memories 51 to 53 is referred to as a memory set 81, and a memory group including the line memories 54 to 56 is referred to as a memory set 82.
The switch 41 selects whether the data input from the input unit 60 is output to the memory set 81 or the memory set 82 according to the signal input from the input unit 62.
The signal input to the input unit 62 is a pulse that rises at a time interval at which data for three horizontal lines (3H) is input.

The signal input to the input unit 63 is a pulse that rises at a time interval when data of one pixel is input, and the switch 42 activates one of the line memories 51 to 53 according to the signal input from the input unit 63. select.
A signal input to the input unit 64 is a pulse that rises at a time interval at which data of one pixel is input. select.

The address counter 57 generates a write address or a read address in the line memory based on a signal input to the input units 62, 63, 65, and instructs the line memory selected by the switch 42.
Similarly, the address counter 58 generates a write address or a read address in the line memory based on a signal input to the input units 62, 64, 66 and instructs the line memory selected by the switch 43.

A signal input to the input units 65 and 66 is a pulse that rises at a time interval at which data of one horizontal line (1H) is input, and the switch 44 uses a line memory in accordance with the signal input from the input unit 65. The switch 45 selects any one of the line memories 54 to 56 according to a signal input from the input unit 66.
The switch 46 selects either the memory set 81 or the memory set 82 according to the signal input from the input unit 67.

When the switch 41 selects the memory set 81, the switch 46 selects the memory set 82, and the switch 41 selects the memory set 82. The switch 46 is set to have a reverse phase so that the memory set 81 is selected.
The rearrangement unit 15 reads data from the memory set 82 while writing data to the memory set 81, and conversely, while writing data to the memory set 82. Operates to read data from the memory set 81.

Since reading / writing of data to / from the memory set 81 and reading / writing of data to / from the memory set 82 are duplicated, only reading / writing of data to / from the memory set 81 will be described.
FIG. 5 is a diagram illustrating an operation in which the rearrangement unit 15 rearranges the data from a1 to a30 input from the signal conversion unit 13 in the memory set 81.

I60, I62, I63, I64, and I65 in FIG. 5 indicate signals input to the input units 60, 62, 63, 64, and 65, respectively.
SW 42 indicates which of the line memories 51 to 53 is the line memory selected by the switch 42, and HA indicates the write address of the line memory 51, the line memory 52, and the line memory 53.

The rearrangement unit 15 determines a line memory to be written and a write address from the contents of the SW 42 and the HA.
For example, at timing T101 in FIG. 5, SW42 indicates “51”, HA is “0”, and I60 is “a1”. Therefore, the rearrangement unit 15 stores data at address 0 in the line memory 51. a1 is written.

The HA when the SW 42 is “52” and “53” corresponding to the line memories 52 and 53 is generated from the value that the SW 42 indicates immediately before.
When SW42 is “51”, HA becomes “0” when the pulse of I62 is input, and increments every time SW42 becomes “51”.
The HA of the line memory 52 in which the SW 42 is “52” is a value obtained by subtracting “1” from the HA immediately before corresponding to the line memory 51. Similarly, the HA of the line memory 53 is immediately before corresponding to the line memory 51. This is the value obtained by subtracting “2” from the HA.

When the write address of the line memories 52 and 53 calculated by the subtraction is less than “0”, data is not written to the line memory.
Even when HA is “8” or more, data is not written to the line memory.
At timing T102 in FIG. 5, SW42 is “51” and HA is “0”. At T102, SW42 is “52” and HA is “less than 0”, so data is not written.

Similarly, data is not written to the line memory at T103, T106, T125, T128, and T129.
5, the data for three horizontal lines a1 to a30 are held in the line memories 51 to 53 as shown in FIG.
The line memory 51 is an area corresponding to the vertical address “0” in FIG. 3, and a1, a4, a7, a10, a13, a16, a19 are stored in storage areas corresponding to the horizontal addresses “0” to “7”. , A22 are held.

The line memory 52 is an area corresponding to the vertical address “1” in FIG. 3, and a5, a8, a11, a14, a17, a20, a23 are stored in storage areas corresponding to the horizontal addresses “0” to “7”. , A26 are held.
The line memory 53 is an area corresponding to the vertical address “2” in FIG. 3, and a9, a12, a15, a18, a21, a24, a27 are stored in storage areas corresponding to the horizontal addresses “0” to “7”. , A30.

FIG. 6 is a diagram illustrating an operation in which the rearrangement unit 15 outputs the data rearranged using the memory set 81 to the DRAM control unit 17.
SW 44 in FIG. 6 indicates which of the line memories 51 to 53 is the line memory selected by the switch 44, and HA indicates the read address of the line memory 51, the line memory 52, and the line memory 53.

SW44 indicates “51” when a pulse is input to both I67 and I65, and thereafter indicates “52” and “53” each time a pulse is input to I65.
HA indicates “0” when a pulse is input to I65 and I63, and the value is incremented each time a pulse is input to I63.
I61 indicates the content of data read from the address indicated by HA of the line memory indicated by SW44.

The rearrangement unit 15 outputs the data in a desired arrangement to the DRAM control unit 17 by performing the control shown in FIG.
Further, the rearrangement unit 15 may perform the same processing as that performed on the a1 to a30 using the memory set 82 for the b1 to b30.
<3. Modification>
Although the present invention has been described based on the above embodiment, it is needless to say that the present invention is not limited to the above embodiment.
The following cases are also included in the present invention.
(1) In the above embodiment, the rearrangement unit 15 converts the data a2, a3, a6, a25, a28, a29, b2, b3, b6, b25, b28, b29, which are dummy data in FIG. Although control was performed so that the data was not stored in the line memory and discarded, the data was stored in the line memory including the dummy, the address was adjusted when the stored data was read, and the data in the desired sequence was output. Also good.

In this modification, the operations of the address counters 57 and 58 are different from the operations shown in the above embodiment.
Each line memory has an area for holding 10 data including a dummy.
FIG. 8 is a diagram illustrating an operation in which the rearrangement unit 15 rearranges data input from the signal conversion unit 13 using the memory set 81 in the present modification.

The address counter 57 switches the switch 42 to the line memory 51 when a pulse is input to I62, I65, and I63, and designates “0” as the write address.
The SW 42 changes the connection destination in the order of “51”, “52”, and “53” every time a pulse is input to the I63.
The address counter 57 increments the value of HA every time three pulses are input to I63.

With the above operation, the data shown in FIG. 2 is held in the line memory as shown in FIG.
FIG. 7 is a diagram showing an arrangement of data in the line memory when dummy data is also held in the line memory.
7 corresponds to the line memory 51, and the horizontal addresses “0” to “9” have a1, a4, a7, a10, a13, a16, a19, a22, a25, a28 is held.

The row with the vertical address “1” in FIG. 7 corresponds to the line memory 52, and the horizontal addresses “0” to “9” have a2, a5, a8, a11, a14, a17, a20, a23, a26, a29 is held.
The row with the vertical address “2” in FIG. 7 corresponds to the line memory 53, and the horizontal addresses “0” to “9” have a3, a6, a9, a12, a15, a18, a21, a24, a27, a30 is held.

When data is held in the line memory as shown in FIG. 7, there are two controls for reading the data to the DRAM: (a) read address control and (b) read timing control.
(A) Read Address Control FIG. 9 is a diagram showing an operation when the rearrangement unit 15 performs read address control and outputs the rearranged data using the memory set 81 to the DRAM control unit 17.

The rearrangement unit 15 sets HA to “0” when the pulse is input to I67, I65, and I63, the switch 44 selects the line memory 51, and the data is held in the area where HA is “0”. a1 is output.
The rearrangement unit 15 increments HA each time a pulse is input to I63, and outputs data corresponding to HA.

The increment is repeated seven times, which is a predetermined number (number of data for one line minus 1), and thereafter no data is output until a pulse is input to I65.
Next, when a pulse is input to I65, as shown in FIG. 9, the switch 44 is switched to the line memory 52, HA is set to “1”, data corresponding to HA is output, and a pulse is output to I63. Every time it is input, HA is incremented and data is output.

The increment is repeated seven times, and thereafter no data is output until a pulse is input to I65.
Next, when a pulse is input to I65, as shown in FIG. 9, the switch 44 is switched to the line memory 53, HA is set to “2”, and HA is incremented every time a pulse is input to I63. , Output data.

The rearrangement unit 15 does not need to read dummy data by shifting the initial value of the read address by 1 as described above, depending on which of the line memories 51, 52, and 53 is used to read the data. Data can be output in order.
(B) Read Timing Control FIG. 10 is a diagram illustrating an operation in which the rearrangement unit 15 performs read timing control and outputs the rearranged data using the memory set 81 to the DRAM control unit 17.

The rearrangement unit 15 sets HA to “0” when a pulse is input to I67, I65, and I63, the switch 44 selects the line memory 51, and a1 is data held in the area where HA is “0”. Is output.
The rearrangement unit 15 increments HA each time a pulse is input to I63, and outputs data in the area indicated by HA.

The data output is limited to eight, and when HA becomes “8” “9”, data output is not performed.
Next, when a pulse is input to I65 and I63, the switch 44 switches to connection to the line memory 52 and sets HA to “0”, but at this time, no data is output.
That is, when the switch 44 is switched to the line memory 52, the data corresponding to the HA of “0” is not output.

Subsequently, every time a pulse is input to I63, HA is incremented, and data corresponding to HA is sequentially output.
Further, the data output is limited to eight, and when the HA is “9”, the data output is not performed.
Next, when a pulse is input to I65 and I63, the switch 44 switches to connection to the line memory 53 and sets HA to “0”, but at this time, no data is output.

When a pulse is input twice to I63, that is, from the timing when HA becomes “2” or more, data corresponding to HA is output.
The data output is limited to eight.
(2) Modification Example with One Memory Set FIG. 11 is a block diagram showing a configuration of the rearrangement unit 15 with one memory set.

Since the rearrangement unit 15 has only one memory set, data reading and writing cannot be performed in parallel as described in the best embodiment.
FIG. 12 is a diagram illustrating data writing and reading timings using the rearrangement unit 15 including one memory set.
The pulses described above the write data and read data in FIG. 12 rise at the time interval of 1H.

  In FIG. 12, there is an overlap in timing between “3 line” data read and “4-6 line” data write, but the DRAM controller 17 does not finish reading the address counter 91. For the data, the write address, the read address, and the write timing are adjusted so that the data is not written from the signal converter 13 to avoid the destruction of the data.

Data overwriting can be avoided by controlling using the output start signal so that data input from the signal conversion unit 13 is accepted after data in the line memories 51 to 53 has been read.
The same signals as the input units 62, 63, 65 in FIG. 4 are input to the input units 62, 63, 65 in FIG.
(3) Modification Example Using Two-Port Memory FIG. 13 is a block diagram of the rearrangement unit 15 including the two-port memory 95 and the address control unit 96.

The address control unit 96 holds the correspondence between the storage area indicated by the horizontal and vertical addresses shown in FIG. 3 and the data stored in the storage area in advance.
The 2-port memory 95 writes and reads data input from the signal conversion unit 13 in accordance with the data array image shown in FIG.

The same signals as the input units 62, 63, 65 in FIG. 4 are input to the input units 62, 63, 65 in FIG.
However, the address control unit 96 adjusts the write address and the read address so as to write only to the read address in order to prevent overwriting and erasing unread data in the 2-port memory 95. Control.
(4) Modification concerning Arrangement of Rearrangement Unit 15 The case where the rearrangement unit 15 is built in the signal processing unit 19 has been described. However, the rearrangement unit 15 does not need to be built in the signal processing unit 19, and FIG. It is good also as a structure as shown in FIG.15, FIG.16, FIG.17 and FIG. 18, respectively.

In this case, it is not necessary to change the function of the rearrangement unit 15 in particular, and a slight change occurs in the arrangement and wiring of each block.
FIG. 14 is a block diagram of the solid-state imaging device when the rearrangement unit 15 is built in the DRAM control unit 17.
When the rearrangement unit 15 is built in the DRAM control unit 17, the data rearrangement process may be performed before the data is written from the DRAM control unit 17 to the DRAM 16, or when the data is written to the DRAM 16. Writing may be performed without performing the rearrangement process, and the rearrangement process may be performed when reading data from the DRAM.

FIG. 15 is a block diagram of the solid-state imaging device when the rearrangement unit 15 has an independent configuration.
In this configuration, the data output from the signal conversion unit 13 is rearranged in the rearrangement unit 15 and output to the DRAM control unit 17.
FIG. 16 is a block diagram of the solid-state imaging device when the rearrangement unit 15 is built in the signal conversion unit 13.

In this configuration, the signal charge output from the solid-state imaging device 101 is AD converted by the AD conversion unit in the signal conversion unit 13, and the data after AD conversion is rearranged by the rearrangement unit 15, and then the DRAM. Output to the control unit 17.
FIG. 17 is a block diagram of the solid-state imaging device when the rearrangement unit 15 is built in the solid-state imaging device driving unit 12.

In this configuration, the data output from the signal conversion unit 13 is rearranged in the rearrangement unit 15 built in the solid-state image sensor driving unit 12 and output to the DRAM control unit 17.
FIG. 18 is a block diagram of the solid-state imaging device when the rearrangement unit 15 is integrated with the solid-state imaging device driving unit 12 and the signal conversion unit 13 in one block.
In this configuration, after the signal charge output from the solid-state image sensor 101 is subjected to processing such as AD conversion by the signal conversion unit 13 in the solid-state image sensor driving unit 12, the rearrangement unit 15 performs rearrangement processing, and DRAM This is output to the control unit 17.
(5) Application to Digital Camera The solid-state imaging device described in this embodiment may be applied to a digital camera.

FIG. 42 shows a configuration example of a digital camera according to the present invention.
The solid-state imaging device 300 is the solid-state imaging element described in the embodiment.
The digital camera includes an optical system 301 including a lens for imaging incident light from a subject on the imaging surface of the solid-state imaging device 300, and a control unit that controls the driving of the solid-state imaging device 300 and the operation of the entire digital camera. 302 and an image processing unit 303 that performs various signal processing on the output from the solid-state imaging device 300.

By using the solid-state imaging device of the present invention by switching between a high-speed operation and a normal all-pixel reading operation, a digital camera having both a moving image (high-speed operation) mode and a still image (all-pixel reading operation) mode can be realized.
(6) Modified example related to internal configuration of rearrangement unit 15 In the above-described embodiment, the rearrangement unit 15 rearranges the data output from the signal conversion unit 13 into a desired arrangement and writes it to the line memory. The example in which the rearranged data in the line memory is written to the DRAM 16 via the DRAM control unit 17 has been described. However, when the data is written to the line memory, the rearrangement is not performed and the data is output from the signal conversion unit 13. The pixel data may be written to the line memory in the order in which the pixel data is read and rearranged when the pixel data is read from the line memory.

A block diagram showing a schematic configuration of the solid-state imaging device according to the present modification is the same as FIG.
FIG. 43 is a block diagram illustrating a schematic configuration of the rearrangement unit 15 in the present modification.
As shown in FIG. 43, the rearrangement unit 15 includes a vertical counter 201, a horizontal counter 202, a read address counter 203, an SRAM memory 204 and an SRAM memory 205, each of which constitutes a memory set, a selector 206, a selector 207.

The SRAM memories 204 and 205 are memories in which pixel data is temporarily stored. When data is written in one of the SRAM memories, data is read from the other.
In the SRAM memories 204 and 205, a read address is set from the read address counter 203, and data read from the set read address is output to the DRAM control unit 17.

The switch 206 is a switch for selecting an SRAM memory to which data is written out of the SRAM memories 204 and 205, and the switch 207 is a switch for selecting an SRAM memory from which data is read.
The selector signal is a pulse that is supplied from the SSG 14 and rises at time intervals when data for three horizontal lines (3H) is input. Each time a pulse is input as the selector signal, the switches 206 and 207 The signal to be input and output is switched by switching the switch.

  In addition, the switch 206 and the switch 207 select and connect different SRAM memories. For example, when the switch 206 selects the SRAM memory 205, the switch 207 selects the SRAM memory 204. When the switch 206 selects the SRAM memory 204, the switch 207 selects the SRAM memory 205.

A clock signal (CLK), a horizontal synchronization signal (HD), and a vertical synchronization signal (VD) are input to the vertical counter 201 and the horizontal counter 202, and the output of the vertical counter 201 and the output of the horizontal counter 202 are read. The address is input to the address counter 203.
Each element operates at the rising edge when operating in synchronization with the CLK, HD, and VD signals, but may operate at the falling edge as a matter of course.

The pixel data is written in the order of output from the signal conversion unit 13 without being rearranged in the SRAM memory in synchronization with the signal output from the SSG 14.
Writing pixel data to the SRAM memory starts from an initial address (for example, address value “0”) in the SRAM memory, and starts with address values “1”, “2”, “3”,. Is written to the upper address.

FIG. 44 is a schematic diagram showing data written to the SRAM memory.
Hereinafter, a case where data written in the SRAM memory 204 is read will be described.
A description of the SRAM memory 205 is omitted because it overlaps with the description of the SRAM memory 204.
“A1” and the like indicate data, and the numbers attached to the rectangles surrounding “a1” indicate the addresses of the memory areas in the SRAM memories 204 and 205.

It is assumed that addresses starting from the same initial address value “0” are allocated to the SRAM memories 204 and 205, respectively.
In FIG. 44, for example, the data “a1” is recorded at the address “0” in the memory area of the SRAM memory 204, and the data “a2” is recorded at the address “1” in the SRAM memory. Similarly, data “a3” to “a30” output from the signal conversion unit 13 are written in addresses “2” to “29”.

The vertical counter 201 is reset to the value “0” when both the input HD and VD are at the high level, and thereafter, every time the high level of the HD is detected, the value “1” is incremented. An incrementing counter, and outputs a counted value (hereinafter referred to as a vertical counter value) to the read address counter 203.
The horizontal counter 202 is reset to a value “0” when both the input HD and VD are at a high level, and thereafter, every time a high level of CLK is detected, the value “1” is incremented. The counter is incremented, and the counted value (hereinafter referred to as a horizontal counter value) is output to the read address counter 203.

FIG. 45 is a block diagram showing the configuration of the read address counter 203.
As shown in the drawing, the read address counter 203 includes a comparator 231, a selector 232, an adder 233, a latch 234, a selector 235, an adder 236, and a latch 237.
The comparator 231 receives input of the horizontal counter value output from the horizontal counter 202 and the vertical counter value output from the vertical counter 201, and both the input horizontal counter value and vertical counter value are received. When both values are “1”, the value “1” is output to the selector 232, and when both values are “1”, the value “0” is output to the selector 232.

The selector 232 receives two inputs and outputs the read address initial value to the selector 235 when the output of the comparator 231 is the value “1”, and when the output of the comparator 231 is the value “0”. Outputs the output from the adder 233 to the selector 235.
The initial value of the read address is a read start address of the DRAM 16 and is determined in advance, and is set to a value “0” in the present modification.

When the HD signal is input, the adder 233 adds the second addition value to the input value and outputs the result to the selector 232.
The second addition value is a predetermined value, and here is a value “4”.
The latch 234 receives the vertical counter value and outputs a pulse indicating the value “1” when the vertical counter value changes, and outputs a low level signal indicating the value “0” in other cases. .

The selector 235 outputs the output of the selector 232 to the latch 237 when the output of the latch 234 is “1”, and the output of the adder 236 to the latch 237 when the output of the latch 234 is “0”. Is output.
The added value 236 adds the first added value to the input value when the CLK signal is input, and outputs the result to the selector 235.

The latch 237 outputs the read address that is the output of the selector 235 to the DRAM control unit 17.
The DRAM control unit 17 reads data from the memory area indicated by the read address acquired from the rearrangement unit 15 in the DRAM 16 and outputs the data to the output signal generation unit 18.

FIG. 46 is a timing chart schematically showing changes in VD, HD, CLK, vertical counter value, horizontal counter value, and read address value according to the rearrangement unit 15 in the present modification.
As shown in FIG. 46, the rearrangement unit 15 sequentially outputs values “0”, “3”, “6”, “9”,... To the DRAM control unit 17 as read addresses. The value “a1” stored at the address “0” of the DRAM 16, the value “a4” stored at the address “3”, the value “a7” stored at the address “6”, and the address “9”. The values are read in the order of “a10”.

As described above, the data written to the SRAM memory 204 in the order output from the signal conversion unit 13 can be read from the SRAM memory 204 in a desired order.
The values of the first addition value, the second addition value, and the read address initial value are design matters and may be changed according to the required specifications.
(7) The example in which the vertical transfer units for three columns are defined as one unit and the configuration of the transfer electrode included in each unit is the same has been described, but vertical transfer of 2n + 1 columns (n is a natural number of 2 or more) The unit may be one unit, and the configuration of the transfer electrode included in each unit may be the same.
(8) The present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.
The present invention also provides a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray Disc). ), Recorded in a semiconductor memory or the like. Further, the present invention may be the computer program or the digital signal recorded on these recording media.
In the present invention, the computer program or the digital signal may be transmitted via an electric communication line, a wireless or wired communication line, a network represented by the Internet, or the like.
The present invention may also be a computer system including a microprocessor and a memory, wherein the memory stores the computer program, and the microprocessor operates according to the computer program.
In addition, the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like, and is executed by another independent computer system. It is good.
(9) The above embodiment and the above modifications may be combined.

  The pixel array device and the solid-state imaging device of the present invention are used in electronic equipment such as a digital camera that captures moving images and still images, and are produced by a semiconductor manufacturer, and the camera of the present invention is a manufacturer of electronic equipment. Produced by etc.

It is a block diagram which shows the structure of the solid-state imaging device of this invention. It is a schematic diagram which shows the input order of the data from a signal conversion part to a rearrangement part. It is a schematic diagram which shows the two-dimensional arrangement | sequence of pixel data corresponding to the electrical signal which the solid-state image sensor produced | generated. It is a block diagram which shows the structure of a rearrangement part. It is a figure which shows the operation | movement which the rearrangement part rearranges the data from a1 to a30 input from the signal conversion part in a memory set. It is a figure which shows the operation | movement which the rearrangement part outputs the data rearranged using the memory set to a DRAM control part. It is a figure which shows the arrangement | sequence of the data in a line memory when dummy data is also hold | maintained at a line memory. In this modification, it is a figure which shows the operation | movement which a rearrangement part rearranges the data input from a signal conversion part using a memory set. It is a figure which shows operation | movement in case a rearrangement part performs read-out address control, and outputs the data rearranged using the memory set to a DRAM control part. It is a figure which shows the operation | movement which a rearrangement part performs read-out timing control, and outputs the data rearranged using the memory set to a DRAM control part. It is a block diagram which shows the structure of the rearrangement part at the time of making one memory set. It is a figure which shows the timing of writing and reading of data using the rearrangement part provided with one memory set. It is a block diagram of the rearrangement part which consists of 2 port memory and an address control part. It is a block diagram of a solid-state imaging device when a rearrangement part is built in a DRAM control part. It is a block diagram of a solid-state imaging device in case a rearrangement part is an independent composition. It is a block diagram of a solid-state imaging device when a rearrangement part is built in a signal conversion part. It is a block diagram of a solid-state imaging device when a rearrangement part is built in a solid-state image sensor drive part. It is a block diagram of a solid-state imaging device in a case where a rearrangement unit is integrated with a solid-state imaging device driving unit and a signal conversion unit in one block. It is a figure which shows schematic structure of a solid-state image sensor. It is the figure which showed typically the combination of the pixel which mixes a signal charge. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows one procedure of the pixel mixing operation | movement by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows an example of the pixel mixing pattern by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows an example of the pixel mixing pattern by the solid-state image sensor of one Embodiment of this invention. It is explanatory drawing which shows an example of the pixel mixing pattern by the solid-state image sensor of one Embodiment of this invention. It is a schematic diagram which shows the gate structure of the vertical transfer stage of the solid-state image sensor of one Embodiment of this invention. It is a schematic diagram which shows the gate structure of the vertical transfer stage of the solid-state image sensor of one Embodiment of this invention. It is a schematic diagram which shows the gate structure of the vertical transfer stage of the solid-state image sensor of one Embodiment of this invention. It is a schematic diagram which shows the gate structure of the vertical transfer stage of the solid-state image sensor of one Embodiment of this invention. It is a figure which shows the specific arrangement | positioning of the gate electrode of the vertical transfer stage of the solid-state image sensor of one Embodiment of this invention. It is a drive timing chart of the solid-state image sensor of one embodiment of the present invention. It is a drive timing chart of the solid-state image sensor of one embodiment of the present invention. It is a block diagram which shows the structure of the digital camera of one Embodiment of this invention. It is a block diagram which shows schematic structure of the rearrangement part in this modification. It is a schematic diagram which shows the data written in the SRAM memory. It is a block diagram which shows the structure of a read address counter. 10 is a timing chart schematically showing changes in VD, HD, CLK, vertical counter value, horizontal counter value, and read address value in the rearrangement unit in the present modification.

Explanation of symbols

12 Solid-state image sensor drive unit 13 Signal conversion unit 14 SSG
15 rearrangement part 16 DRAM
17 DRAM control unit 18 output signal generation unit 19 signal processing unit 101 solid-state imaging device 102 photoelectric conversion unit 103 vertical transfer unit 104 horizontal transfer unit 301 optical system 302 horizontal counter 303 image processing unit

Claims (23)

A pixel array device that rearranges a plurality of pixel data received from a solid-state image sensor,
Acquisition means for acquiring a pixel data string as a result of receiving a plurality of pixel data sequentially transmitted from the solid-state imaging device;
Extraction means for extracting pixel data at regular intervals from the acquired pixel data sequence;
A pixel array device comprising: arraying means for arraying the extracted pixel data in a line in the order of extraction. The extraction unit extracts the pixel data as first pixel data every two intervals from a predetermined start position in the acquired pixel data string,
further,
The second pixel data is extracted every two intervals from the four positions after the start position,
Extracting the third pixel data every two intervals from the eight positions after the start position,
The arrangement means arranges the extracted first pixel data in a line according to the extraction order,
further,
The extracted second pixel data is arranged in a line in the order of extraction,
The pixel arrangement apparatus according to claim 1, wherein the extracted third pixel data is arranged in a line in the order of extraction. The extraction means includes
A predetermined number of pixel data is extracted as the first pixel data,
A predetermined number of pixel data is extracted as the second pixel data,
3. The pixel array device according to claim 2, wherein a predetermined number of pieces of pixel data are extracted as the third pixel data. The extraction means includes
Storage means;
Writing means for writing the pixel data string in a predetermined continuous address area of the storage means in the order of reception;
Address control means for outputting addresses at regular intervals in the continuous address area, and
The pixel arrangement device according to claim 3, wherein the arrangement unit reads out pixel data from each of the output addresses and arranges the pixel data in a line. The address control means includes
Control signal receiving means for receiving a reference clock and a horizontal synchronization signal from outside the device;
A horizontal counter that counts and outputs the horizontal counter value in synchronization with the reference clock;
A vertical counter that counts and outputs the vertical counter value in synchronization with the horizontal synchronization signal;
Based on the horizontal and vertical counter values, ax + by + c (x is the horizontal counter value, y is the vertical counter value, a and b are predetermined constants, and c is a read start address corresponding to the position where extraction is started. The pixel array device according to claim 4, further comprising: an address calculation unit that calculates and outputs an address indicated by The extraction means includes
Storage means including three line memories;
Control means for selecting one line memory in order from the three line memories for each one pixel data transfer period;
The arrangement means includes
4. The pixel array device according to claim 3, further comprising a writing unit that extracts one piece of pixel data from the pixel data sequence based on the order of reception and writes the extracted pixel data to a selected line memory. 5. The pixel array device according to claim 6, wherein the writing unit writes pixel data other than a predetermined exclusion position in the pixel data string to the line memory. The arrangement means includes
7. The pixel according to claim 6, further comprising a reading means for discarding a predetermined number of pixel data for each line memory and reading a predetermined number of pixel data when reading data written in each line memory. Array device. The arrangement means includes
7. The pixel array device according to claim 6, further comprising: a reading unit that reads data in a continuous address predetermined for each line memory when reading data written in each line memory. The arrangement means includes
A two-port memory that processes data reading and writing in parallel;
The data processing unit executed when the pixel data is written to or read from the two-port memory, based on a two-dimensional array of photoelectric conversion units included in the solid-state imaging device. Pixel array device. A solid-state imaging device including a solid-state imaging device including a plurality of photoelectric conversion units arranged two-dimensionally and a signal processing circuit thereof,
The solid-state imaging device is
A vertical transfer unit provided corresponding to each column of the photoelectric conversion units in order to transfer the signal charges read from the photoelectric conversion units in the vertical direction;
A horizontal transfer unit that horizontally transfers the signal charge received from the vertical transfer unit,
The vertical transfer unit and the horizontal transfer unit each include a plurality of transfer electrodes,
The vertical final stage, which is the transfer stage closest to the horizontal transfer unit in the vertical transfer unit, has the same transfer electrode configuration for every 2n + 1 (n is an integer of 1 or more) columns,
Of the 2n + 1 columns, the transfer operation from the vertical final stage to the horizontal transfer unit is performed independently of the other vertical final stages in the 2n + 1 column in the vertical final stage other than one column or in all vertical final stages. In order to control, a transfer electrode independent of the other vertical final stage is provided,
The signal processing circuit includes:
Conversion means for converting each signal charge transferred from the horizontal transfer unit into pixel data and sequentially outputting the data;
A pixel array device, and
The pixel array device includes:
Obtaining means for obtaining a pixel data string as a result of receiving a plurality of the pixel data;
Extraction means for extracting pixel data at regular intervals from the acquired pixel data sequence;
A solid-state imaging device comprising: arrangement means for arranging the extracted pixel data in a line in the order of extraction. The vertical final stage, which is the transfer stage closest to the horizontal transfer unit in the vertical transfer unit, has the same transfer electrode configuration every three columns,
Of the three columns, the transfer operation from the vertical final stage to the horizontal transfer unit is performed independently of the other vertical final stages in the three columns. The solid-state imaging device according to claim 11, further comprising a transfer electrode independent of the other vertical final stage. The extraction unit extracts the pixel data as first pixel data every two intervals from a predetermined start position in the acquired pixel data string,
further,
The second pixel data is extracted every two intervals from the four positions after the start position,
Extracting the third pixel data every two intervals from the eight positions after the start position,
The arrangement means arranges the extracted first pixel data in a line according to the extraction order,
further,
The extracted second pixel data is arranged in a line in the order of extraction,
The solid-state imaging device according to claim 12, wherein the extracted third pixel data is arranged in a line in the order of extraction. The extraction means includes
A predetermined number of pixel data is extracted as the first pixel data,
A predetermined number of pixel data is extracted as the second pixel data,
The solid-state imaging device according to claim 13, wherein a predetermined number of pieces of pixel data are extracted as the third pixel data. The extraction means includes
Storage means;
Writing means for writing the pixel data string in a predetermined continuous address area of the storage means in the order of reception;
Address control means for outputting addresses at regular intervals in the continuous address area,
The solid-state imaging device according to claim 14, wherein the arrangement unit reads pixel data from each of the output addresses and arranges the pixel data in a line. The address control means includes
Control signal receiving means for receiving a reference clock and a horizontal synchronization signal from outside the device;
A horizontal counter that counts and outputs the horizontal counter value in synchronization with the reference clock;
A vertical counter that counts and outputs the vertical counter value in synchronization with the horizontal synchronization signal;
Based on the horizontal and vertical counter values, ax + by + c (x is the horizontal counter value, y is the vertical counter value, a and b are predetermined constants, and c is a read start address corresponding to the position where extraction is started. The solid-state imaging device according to claim 15, further comprising: an address calculation unit that calculates and outputs an address indicated by: The extraction means includes
Storage means including three line memories;
Control means for selecting one line memory in order from the three line memories for each one pixel data transfer period;
The arrangement means includes
The solid-state imaging device according to claim 14, further comprising a writing unit that extracts one piece of pixel data from the pixel data sequence based on the order of reception and writes the extracted pixel data to the selected line memory. The solid-state imaging device according to claim 17, wherein the writing unit performs writing to the line memory for pixel data other than a predetermined exclusion position in the pixel data string. The arrangement means includes
18. The solid-state image processing device according to claim 17, further comprising: a reading unit that discards a predetermined number of pixel data for each line memory and reads the remaining pixel data when reading the pixel data written in each line memory Imaging device. The arrangement means includes
18. The solid-state imaging device according to claim 17, further comprising: a reading unit that reads out pixel data in a continuous address predetermined for each line memory when reading out the pixel data written in each line memory. The rearrangement unit includes:
A two-port memory that processes reading and writing of pixel data in parallel;
The data processing unit that performs based on a two-dimensional array of photoelectric conversion units included in the solid-state imaging device when the pixel data is written to or read from the two-port memory. Solid-state imaging device.   A camera comprising the pixel array device according to claim 1.   A camera comprising the solid-state imaging device according to claim 11.

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