JP4499387B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device that improves the frame rate by, for example, thinning-out readout of pixels and suppresses image quality deterioration.

  2. Description of the Related Art Conventionally, in the field of electronic cameras and the like, only necessary and sufficient pixels are read out during image display before imaging from the viewpoint of high-speed reading and low power consumption.

As this type of technology, for example, in Patent Document 1, among a plurality of photoelectric conversion pixels arranged in a matrix, a row group or a column group is selected by a scanning circuit, and selected from the selected row group or column group. A technique related to an electronic camera is disclosed in which only a desired row or column of pixels is accurately thinned and read out by arbitrarily selecting a desired row or column by a circuit.
JP 2000-004406 A

  However, in Patent Document 1, there is no description or suggestion about suppressing the false color in the horizontal direction caused by thinning out readout of pixels.

  The present invention has been made in view of the above-described problems. The object of the present invention is to enable readout at a high frame rate by thinning out readout of pixels, and at that time, average the pixel signals of a predetermined number of pixels of the same horizontal color. It is an object of the present invention to provide a solid-state imaging device capable of suppressing horizontal false color caused by thinning out readout of pixels by converting the output into a pixel.

In order to solve the above-described problem, a solid-state imaging device according to the first aspect of the present invention includes a solid-state imaging device in which a plurality of pixels each having at least a part of a Bayer array color filter are two-dimensionally arranged; In an XY address type solid-state imaging device composed of horizontal and vertical scanning circuits for reading out pixels, pixel signals of pixels having the same color phase in the color phase coding defined by the color filter are averaged. A signal averaging switch unit that performs a mode for sequentially outputting all pixels based on the control of the scanning circuit, performs thinning-out readout of pixels within one frame, and averages the pixels by the signal averaging switch unit And a mode for outputting all the pixels in sequence and a mode for outputting after averaging all the pixels in the horizontal and vertical directions. Performed by the drive control of the査回path and said signal averaging switch unit, wherein the signal averaging switch unit, so that the circuit configuration of each column is uniform, characterized in that it comprises a device that does not function without depending on the control signal .

  According to the present invention, it is possible to perform readout at a high frame rate by decimation readout of pixels, and further, by averaging and outputting pixel signals of a predetermined number of pixels of the same color in the horizontal direction, thereby generating a horizontal direction caused by decimation readout of pixels. It is possible to provide a solid-state imaging device capable of suppressing the false color.

  First, FIG. 1 shows a conceptual diagram of a solid-state imaging device according to an embodiment of the present invention, and FIGS. 2 and 3 show configuration diagrams further embodying the configuration of FIG. Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

  1 to 3, the pixel unit 1 as a solid-state imaging device is configured by a plurality of pixels arranged in a two-dimensional matrix. More specifically, the pixel unit 1 includes a light-shielding pixel unit 1a that outputs a signal corresponding to a black level, and an effective pixel unit 1b that receives subject light, generates charges, and outputs a pixel signal. Yes. The surface of each pixel of the light-shielding pixel portion 1a is covered with a light-shielding film such as aluminum, and a color filter is disposed on the surface of each pixel of the effective pixel portion 1b. Further, P (i−4, k−3) to P (i + 3, k + 4) shown in FIGS. 2 and 3 mean pixel addresses of a plurality of light-shielding pixel portions 1 a arranged in the pixel portion 1. , P (j−8, k−3) to P (j + 7, k + 4) mean pixel addresses of a plurality of effective pixel portions 1 b arranged in the pixel portion 1.

  Further, “R” shown in FIGS. 2 and 3 is a pixel that is sensitive to red light among the effective pixels (hereinafter referred to as “R pixel”), and “G” is green light among the effective pixels. Sensitive pixels (hereinafter referred to as G pixels), and “B” mean pixels that are sensitive to blue light (hereinafter referred to as B pixels) among the effective pixels. Of these R, G, and B pixels, the G pixels are arranged in a checkered pattern, and the R pixels and the B pixels are arranged in a line sequential manner (Bayer arrangement) in the remaining portions. “OB” is a light-shielded pixel.

  The vertical scanning circuit 20 sequentially scans the vertical signal lines according to the row selection signal, and sequentially reads out the pixel signals from the light-shielding pixel portion 1a and the effective pixel portion 1b. The vertical scanning circuit 20 includes n (n is a natural number) vertical scanning circuit units. Reference numerals 20- (k-3) to 20- (k + 4) shown in FIG. 2 indicate k (k is a natural number) vertical scanning circuit units in the n vertical scanning circuit units.

  The signal transfer switch unit 14 is driven and controlled by a signal transfer clock CKT. More specifically, the signal transfer switches 14- (i-4) to 14- (i + 3) and 14- (j-8) to 14- (j + 7) constituting the signal transfer switch unit 14 are the vertical scanning described above. The pixel signals in the row selected by the circuit 20 are transferred to the subsequent capacitive elements 13- (i-4) to 13- (i + 3) and 13- (j-8) to 13- (j + 7).

  The line memory unit 13 includes m (m is a natural number) capacitive elements, and temporarily stores a signal for one row of pixels. Reference numerals 13- (i-4) to 13- (i + 3) and 13- (j-8) to 13- (j + 7) shown in FIGS. 2 and 3 denote i (i is a natural number) among m capacitive elements. ) Capacitance elements in the vicinity of the individual and j (j is a natural number).

  The signal averaging switch unit 12 is a switch for averaging the signal stored in the line memory unit 13 and averages the light-shielded pixel signal for averaging the signal of the light-shielded pixel stored in the line memory unit 13. It is roughly divided into a switch unit 12a and an effective pixel signal averaging switch unit 12b for averaging the effective pixel signals stored in the line memory unit 13.

  The light-shielded pixel signal averaging switch units 12a are arranged every other column, and when the clock CKAVE1 is set to the “H” level, a predetermined number (here, three columns) of light-shielded pixel signals are averaged. For example, the light shielding pixel signal averaging switches 12- (i-1) and 12- (i + 1) are connected to the capacitive elements 13- (i-1), 13- (i + 1) and 13- when the clock CKAVE1 becomes "H" level. It operates to electrically connect (i + 3). Further, for example, the light-shielded pixel signal averaging switches 12- (i-3) and 12- (i + 3) are provided so that the circuit configuration for each column, that is, the layout is uniform, and the clock CKAVE1 is “H”. "It is connected so that it does not function as a switch even if it reaches the level." With this connection, the connection form in the effective pixel signal averaging switch unit 12b is the same.

  On the other hand, the effective pixel signal averaging switch unit 12b is configured so that the signals of the R pixel, the G pixel, and the B pixel are averaged in a predetermined number of pixel units (here, three pixels), and the clock CKAVE2 Connected to be controlled.

  As described above, in this embodiment, the pixel signal averaging switch unit 12 has three pixels for the signal of the light-shielded pixel among the signals stored in the line memory unit 13 by the light-shielded pixel signal averaging switch unit 12a by the clock CKAVE1. Signal averaging is controlled, and the effective pixel signal averaging switch unit 12b controls the signal averaging of three pixels of the same color by the clock CKAVE2.

  The horizontal scanning circuit 10 is for sequentially driving the horizontal selection switch unit 11, and is composed of m horizontal scanning circuit units. That is, reference numerals 10- (i-4) to 10- (i + 3) and 10- (j-8) to 10- (j + 7) denote the i-th neighborhood and the j-th neighborhood among the m horizontal scanning circuit units. The horizontal scanning circuit unit is shown.

  The horizontal selection switch unit 11 is controlled by the output (horizontal selection signal) of the horizontal scanning circuit unit 10 and includes m horizontal selection switches. Reference numerals 11- (i-4) to 11- (i + 3) and 11- (j-8) to 11- (j + 7) in FIGS. 2 and 3 denote the i-th neighborhood and j of the m horizontal selection switches. The horizontal selection switch near the individual is shown. In the horizontal selection switch unit 11, when each horizontal selection switch is turned on by a horizontal selection signal, the pixel signal stored in the line memory unit 13 is transmitted to the horizontal signal line, and further, the output amplifier 30 in the subsequent stage. Amplified and output to the outside.

  In the above configuration, the present embodiment is a solid-state imaging device having the pixel unit 1 including a color filter with a Bayer array, performs pixel thinning-out readout within one frame, and the pixel is subjected to the color filter. The pixel signals of pixels having the same color phase in the specified color phase coding are averaged and output.

  More specifically, a pixel unit 1 in which a plurality of pixels each having at least a part of a Bayer color filter are two-dimensionally arranged, a horizontal scanning circuit 10 for reading out pixel signals of the pixels, and vertical scanning An XY address type solid-state imaging device including a circuit 20 includes a signal averaging switch unit 12 that averages pixel signals of pixels in the same color phase among color phase codings defined by the color filter. Based on the control of the scanning circuits 10 and 20, the pixels are thinned and read out within one frame, and the signal averaged by the signal averaging switch unit 12 is output for the pixels.

  Further, the pixel unit 1 includes a light-shielding pixel unit 1a and an effective pixel unit 1b, and the signal averaging switch unit 12 further averages a signal for a predetermined pixel among signals related to the pixels of the light-shielding pixel unit 1a. . At this time, signals related to the pixels of the light-shielding pixel portion 1a are sequentially read out within one frame. The signal averaging switch unit 12 includes a light-shielded pixel signal averaging switch unit 12a and an effective pixel signal averaging switch unit 12b, and a light-shielded pixel formed by the light-shielded pixel signal averaging switch unit 12a by a first signal (CKAVE1). The pixels having the same color phase among the coding of the color phase defined by the color filter by the effective pixel signal averaging switch unit 12b by the second signal (CKAVE2) The pixel signal is controlled to be averaged.

  Hereinafter, the operation of the solid-state imaging device configured as described above will be described in more detail with reference to the timing charts of FIGS. 4 and 5. Note that the timings indicated by symbols a to p in FIG. 4 correspond to the timings indicated by the same symbols in FIG.

  4 and 5, “VD” is a vertical synchronizing signal, “HD” is a horizontal synchronizing signal, “CKAVE1” is a clock for controlling on / off of the shading pixel signal averaging switch unit 12a, and “CKAVE2” is effective. A clock for controlling on / off of the pixel signal averaging switch section 12b, and “CKT” is a clock for controlling on / off of the signal transfer switch section 14.

  “V-1” to “Vn” are row selection signals and are outputs of the vertical scanning circuit units 20-1 to 20-n. “H-1” to “Hm” are horizontal selection signals for controlling the horizontal selection switches 11-1 to 11-m, and are output signals of the horizontal scanning circuit units 10-1 to 10-m. In addition to the above, “signal output” is a pixel signal output from the output amplifier 30.

  When entering this operation, the vertical scanning circuit 20 is, for example, 20-1... 20- (k-3), 20-k, 20- (k + 3),. Scanning skipped by two lines in the arrangement direction of −1 to 20-n, that is, vertical 1/3 thinning scanning is performed.

  That is, when the row selection signal V− (k−3) output from the vertical scanning circuit 20 becomes “H” level within the horizontal blanking period (period in which the horizontal synchronization signal HD is “L” level), (k− 3) Pixels P (1, k-3) to P (m, k-3) in the row are selected.

  During this time, since the signal transfer clock CKT input to the signal transfer switch unit 14 is at the “H” level, the pixel signals of the selected pixels P (1, k−3) to P (m, k−3) are It memorize | stores in the capacitive elements 13-1 to 13-m. Thereafter, since the clocks CKAVE 1 and CKAVE 2 input to the pixel signal averaging switch unit 12 are at the “H” level, signals for every other three pixels are averaged and stored in the line memory unit 13.

  That is, for example, an average of signals stored in the capacitive elements 13- (i-4), 13- (i-2), and 13-i is an average signal for three light-shielded pixels, for example, the capacitive element 13- (j- 1), averages of signals stored in the memories 13- (j + 1) and 13- (j + 3) are respectively stored in the line memory unit 13 as average signals for three effective pixels. By such an operation, horizontal three-pixel averaging of R pixels and G pixels arranged in a Bayer array is performed.

  Thereafter, when the scanning / selection signal is output toward the horizontal scanning circuit units 10-1 to 10-m within the horizontal effective period (period in which the horizontal synchronization signal HD is at "H" level), the light-shielded pixel signal is selected. In this case, sequential scanning (H-1,... H- (i-4), H- (i-3), H- (i-2), H is performed so that the horizontal selection signal is output one unit at a time. − (I−1), H−i, H− (i + 1), H− (i + 2), H− (i + 3), H− (i + 4),.

  On the other hand, when an effective pixel signal is selected, scanning is performed so that a horizontal selection signal is output from one of the three units, that is, 1/3 thinning scanning (... H- (j-8), H- (j- 5), H− (j−2), H− (j + 1), H− (j + 4), H− (j + 7),.

  When horizontal scanning is performed in this manner, the light-shielded pixel three-pixel average signal and the effective pixel three-pixel average signal stored in the line memory unit 13 are transmitted to the horizontal signal line via the horizontal selection switch unit 11, Further, it is amplified by the output amplifier 30 at the subsequent stage and becomes a signal output.

  At this time, the light-shielded pixel three-pixel average signal is sequentially output, and the effective pixel three-pixel average signal is output with the number of signals reduced to 1/3. In this way, the pixel signals for one row are averaged over three pixels, and a signal corresponding to the number of light-shielded pixels and a signal corresponding to 1/3 of the number of effective pixels are output.

  In the next horizontal blanking period, the vertical scanning circuit 20 performs 1/3 thinning scanning, so that the row selection signal Vk from the vertical scanning circuit 20 is at the “H” level. When the row selection signal Vk becomes “H” level within this vertical blanking period, the pixels P (1, k) to P (m, k) in the k-th row are selected. During this time, since the signal transfer clock CKT input to the signal transfer switch unit 14 is at “H” level, the pixel signals of the selected pixels P (1, k) to P (m, k) are stored in the line memory unit 13. Are stored in the capacitive elements 13-1 to 13-m.

  After that, since the clocks CKAVE1 and CKAVE2 input to the signal averaging switch unit 12 are at the “H” level, the signals for every other three pixels are averaged, and the light-shielded pixel three-pixel average signal and the effective pixel three-pixel average Each signal is stored in the line memory 13.

  With the above operation, the average of three pixels in the same color of the G pixels and B pixels arranged in the Bayer array is performed. Thereafter, when the scanning / selection signal is output toward the horizontal scanning circuit units 10-1 to 10-m within the horizontal effective period, the horizontal selection signal is output one unit at a time in order to select the light-shielded pixel signal. Sequential scanning (H-1,... H- (i-4), H- (i-3), H- (i-2), H- (i-1), Hi, H- ( i + 1), H− (i + 2), H− (i + 3), H− (i + 4),...), and when selecting an effective pixel signal, 1 so that a horizontal selection signal is output from one of the three units. / 3 thinning scan (... H- (j-8), H- (j-5), H- (j-2), H- (j + 1), H- (j + 4), H- (j + 7), ...) Let

  When horizontal scanning is performed in this manner, the light-shielded pixel three-pixel average signal and the effective pixel three-pixel average signal stored in the line memory unit 13 are transmitted to the horizontal signal line via the horizontal selection switch unit 11, Further, it is amplified by an output amplifier to become a signal output.

  At this time, the light-shielding pixel three-pixel average signal is sequentially output, and the effective pixel three-pixel average signal is output with the number of signals reduced by 1/3. In this way, the pixel signals for one row are averaged over three pixels, and a signal corresponding to the number of light-shielded pixels and a signal that is 1/3 of the number of effective pixels are output.

  Thereafter, similarly, the pixels from the (k + 3) -th row to the n-th row are selected skipping two rows during the vertical blanking period, and the pixel signal for each row is output during the horizontal effective period.

  With the above readout operation, the vertical 1/3 thinning readout, the horizontal sequential readout of the average signal for the three light-shielded pixels, and the horizontal 1/3 thinning readout operation of the average signal for the three pixels of the same color of the effective pixels are performed. By operating in this way, the number of effective readout pixels is compressed to horizontal and vertical 1/3, so that readout at a high frame rate is possible.

  At this time, since the signals of three pixels of the same color in the horizontal direction are averaged and output, the false color in the horizontal direction caused by thinning out reading can be suppressed. In addition, the circuit scale can be greatly reduced as compared with the case of averaging in the vertical direction. Further, when reading out the light-shielded pixels, the readout is performed sequentially, so that the same period as when sequentially clamping the light-shielded pixel signal level can be ensured.

  Next, a camera to which the solid-state imaging device according to the above-described embodiment is applied will be described in detail with reference to the conceptual diagram of FIG.

  As shown in FIG. 6, a solid-state imaging device 51 is disposed on the optical path of subject light incident through the photographing lens 50. The output of the solid-state imaging device 51 is connected to the input of a direct current reproducing unit (CDS) 56, and the output of the direct current reproducing unit 56 is supplied to the contrast AF detection unit 57 and the image processing unit 58 via a switch unit. Connected to the input.

  Based on the detection result of the contrast AF detection unit 57, the zoom lens conceptually included in the photographing lens 50 is driven and controlled. An output of the image processing unit 58 is connected to an input of a display unit 60 such as an LCD and a media recording unit 61. The output of the synchronization timing generator 55 that generates the clock signal is connected to the inputs of the DC regenerator 56 and the scan controller 54. The scanning control unit 54 is also connected with a mode switching unit 59 for setting various modes.

  In such a configuration, the subject light incident through the photographing lens 50 is imaged by the solid-state imaging device of the solid-state imaging device 1 and a pixel signal is output.

  At this time, the scanning control unit 54 is controlled based on various modes set by the mode switching unit 59, and the vertical shift register control signal and the horizontal shift register control signal are sent to the solid-state imaging device 1 so as to perform the above-described thinning scanning and the like. Are output to the horizontal scanning circuit 53 and the vertical scanning circuit 52. Based on this control signal, driving as described above is performed, and readout is performed while thinning out pixels.

  The pixel signal is correlated double-sampled by the DC reproducing unit 56, further A / D converted into a digital image signal, and sent to the contrast AF detecting unit 57 or the image processing unit 58 according to the switching state of the switch unit. . The contrast AF detection unit 57 detects the subject distance based on the digital image signal. On the other hand, in the image processing unit 58, for example, color signal generation processing, matrix conversion processing, and other various image processing are performed and output to the display unit 60 or the media recording unit 61. In the display unit 60, various displays are performed based on the digital image signal. On the other hand, the media recording unit 61 includes, for example, a card interface and a memory card, and records a digital image signal.

  In the camera as this application example, reading by 1/3 thinning scanning is performed by a solid-state imaging device inside the camera, thereby improving the frame rate and enabling high-speed area reading. As a result, various modes (AF, A suitable reading method according to display, recording, etc. can be selected. In other words, thinning scanning is suitable when continuous display is performed on the display unit 60 at a short frame rate, but based on the setting of the mode switching unit 59, the scanning control unit 54 uses the vertical shift register control signal and the horizontal shift register. This is easily realized by controlling the output timing of the control signal.

  Although one embodiment of the present invention has been described above, the present invention is not limited to this, and it is needless to say that various improvements and modifications can be made without departing from the spirit of the present invention.

  That is, for example, the circuit configuration illustrated in FIGS. 1 to 3 is not limited to this, and the readout circuit can have a function for canceling the FPN of the pixel.

  In the embodiment, the configuration for enabling horizontal three-pixel averaging is shown. However, by changing the repetition cycle of the signal averaging switch, horizontal five-pixel average or horizontal seven-pixel average can be performed. It is also possible to configure such that a plurality of averaging operations can be selectively performed. Further, in the above-described embodiment, the signal output is configured to be performed by one line, but it is needless to say that the signal output can be configured to be able to output multiple lines.

  In the timing charts of FIGS. 4 and 5, the light-shielded pixel signal can be read out without averaging by setting CKAVE1 to “L” level, and the effective pixel can be read by setting CKAVE2 to “L” level. It is also possible to read out the parts without averaging.

  In the above-described embodiment of the present invention, the operation for performing the 1/3 decimation scanning in the horizontal scanning circuit and the vertical scanning circuit has been described, but in order to perform such an operation, a decoder circuit is used. The use of a shift register in the scanning circuit can be realized, for example, by the thinning scanning method described in JP-A-9-163245, and all pixels can be read out sequentially by performing sequential scanning. Of course.

  Here, FIG. 7 shows a configuration example of a shift register used in a scanning circuit for performing sequential scanning and skip scanning. In FIG. 7, the shift register unit 300 for one stage is composed of a first shift register unit 100 and a second shift register unit 200 including subunits 101 and 102. The input ends of the first and second shift register units 100 and 200 are connected in common. The output terminal of the first shift register unit 100 is connected to the input terminal of the next-stage shift register unit, and the output terminal of the second shift register unit 200 is the input of the subunit 102 that is two stages behind. Connected to the end. The subunits 101 and 102 of the first shift register unit are driven by drive pulses φ1-1 and φ1-2, respectively, and the second shift register unit 200 is driven by a drive pulse φ2.

  In the shift register having such a configuration, a drive signal is given to the drive pulses φ1-1 and φ1-2, and the drive pulse φ2 is set in a state in which the second shift register unit 200 is not operated, so that the shift register starts. When the pulse φST is input, the input signal shifts in the shift register as shown by the one-dot chain line in FIG. 8, so signals are output from the shift register in the order of SRout1, SRout2, SRout3,. Can be done.

  On the other hand, in this shift register, a drive signal is given to the drive pulses φ1-2 and φ2, and the drive pulse φ1-1 is set in a state in which the subunit 101 is inoperative. Since the input signal is shifted in the shift register as indicated by the one-dot chain line in FIG. 9, the signals are output from the shift register in the order of Srout3, Srout6,...

  As described above, by using the shift register configured as shown in FIG. 7 in the scanning circuit and controlling the driving pulse, it is possible to switch between the sequential scanning and the skip scanning. Since switching between sequential scanning and skip scanning can be performed by controlling the driving pulse, changing the driving pulse in the middle of scanning enables switching between sequential scanning and thinning scanning in the middle of scanning. The effective pixel region can also be scanned such that thinning scanning is performed.

1 is a conceptual diagram of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a configuration diagram further illustrating a part of the configuration of FIG. 1. FIG. 2 is a configuration diagram further illustrating a part of the configuration of FIG. 1. 4 is a timing chart showing the operation of the solid-state imaging device according to the embodiment of the present invention. 4 is a timing chart showing the operation of the solid-state imaging device according to the embodiment of the present invention. 1 is a configuration diagram of a camera to which a solid-state imaging device according to an embodiment of the present invention is applied. FIG. 6 is a diagram showing a configuration example of a shift register that can be applied as a scanning circuit for performing sequential scanning and skip scanning in the solid-state imaging device according to the embodiment of the present invention. FIG. 8 is a conceptual diagram illustrating sequential scanning with the configuration of FIG. 7. The conceptual diagram explaining 1/3 skip scanning by the structure of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pixel part, 1a ... Light-shielding pixel part, 1b ... Effective pixel part, 10 ... Horizontal scanning circuit, 11 ... Horizontal selection switch, 12 ... Signal averaging switch part, 12a ... Shading pixel signal averaging switch unit, 12b... Effective pixel signal averaging switch unit, 13... Line memory, 14.

Claims (1)

An XY address type solid-state image pickup device comprising a solid-state image pickup device in which a plurality of pixels each having at least a part of a Bayer color filter are two-dimensionally arranged and a horizontal and vertical scanning circuit for reading out the pixels. In
A signal averaging switch unit that averages pixel signals of pixels in the same color phase among the coding of the color phase defined by the color filter;
Based on the control of the scanning circuit, a mode for sequentially outputting all pixels,
A mode in which pixel readout is performed within one frame and a signal averaged by the signal averaging switch unit is output for the pixel;
Have
Switching between the mode of sequentially outputting all pixels and the mode of outputting after averaging is performed by driving control of the horizontal and vertical scanning circuits and the signal averaging switch unit,
The signal averaging switch unit includes an element that does not function regardless of a control signal so that a circuit configuration for each column is uniform .

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