JP4628174B2 - Imaging device, image signal processing apparatus, and imaging apparatus - Google Patents

Description

  The present invention relates to an image sensor having a plurality of output buses and capable of thinning out pixel signals, and an image signal processing apparatus for performing signal processing of pixel signals output from the image sensor.

  Conventionally, solid-state image sensors are used in copying machines and digital cameras. In recent years, there has been an increasing demand for speeding up of such a solid-state imaging device and simplification of the configuration. For example, an increase in speed and gradation by devising a wiring layout of an image sensor is disclosed (Patent Document 1).

  In addition, the image sensor outputs pixel signals from all pixels when obtaining a detailed image, and outputs pixel signals from some pixels for faster output and reduced pixel signal size compared to the output from all pixels. It is known to thin out the output of.

  For example, an image pickup device 10 ′ illustrated in FIG. 26 is known as an image pickup device capable of outputting all pixels and performing thinning output. A plurality of pixels 20 ′ are arranged in a matrix on the imaging surface of the imaging element 10 ′. Each pixel 20 'is connected to a vertical signal line 17' arranged for each column in which the pixels 20 'are arranged.

The vertical signal line 17 'is connected to the changeover switch 18 having a first, second output line 18 _a, 18 _b. The first and second output lines 18 _a and 18 _b of each column are connected to any _one of the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ , as will be described later.

For example, the first output line 18 _a of the first column from the left is connected to the horizontal signal line 15 _'1 of 1 in FIG. 26, 2-4 column of the first output line 18 _a each 2-4 horizontal signal is connected to line 15 _{'2-15' 4.} In the fifth and subsequent columns, four consecutive first output lines 18 _a are connected to the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ of ₁ to 4 in the column order.

The second output lines _18b in the first and second columns are connected to _one horizontal signal line 15'1. Likewise 3,4 column of the second output line 18 _b is _'2, the second output line 18 _b of the 5,6-row horizontal signal line 15 of the 3' horizontal signal lines 15 of 2 to _3, 7, eighth column of the second output line 18 _b is connected to the horizontal signal line 15 _'4 4.

The vertical signal line 17 'the connection with a possible output of the pixel signals from all the pixels by switching to the first output line 18 _a is, the vertical signal lines 17' connected between the second output line 18 _b By switching, thinning out output becomes possible.

In a configuration in which pixel signals read at a single timing are output via the same horizontal signal line, it is impossible to output pixel signals from all the horizontal signal lines at a single timing. On the other hand, in order to output pixel signals at high speed, pixel signals of separate pixels from _one to _four horizontal signal lines 15 ′ ₁ to 15 ′ ₄ at a single timing in both the output from all the pixels and the thinned-out output. Is preferably output.

  Therefore, by switching the connection between the output of the pixel signals from all the pixels and the output of the thinning-out, the pixel signals of the separate pixels can be obtained from all the horizontal signal lines at a single timing in any output. Output is enabled.

On the other hand, since it is necessary to provide the changeover switch 18 in each vertical signal line 17 ′, the problem is that the structure of the image sensor 10 ′ becomes complicated.
Japanese Patent Laid-Open No. 8-139533

  Therefore, an object of the present invention is to provide an image sensor having a simple configuration that can switch between full output and thinning output.

  The imaging device of the present invention outputs a pixel signal corresponding to the amount of received light received on the light receiving surface and arranges a plurality of pixels arranged on a predetermined array line, 1 to m readout lines for reading out the pixel signal, and a plurality of readout lines. A switching means for switching ON / OFF of the output of the pixel signal from each pixel and a switching control means for switching ON / OFF of the switching means, and divides a plurality of pixels into m pixels lined up continuously. Forming a plurality of pixel groups, and the plurality of pixels are connected to readout lines different from readout lines connected to other pixels forming the same pixel group among any of the readout lines 1 to m, A reference pixel which is a pixel arranged at a predetermined position on the array line and (m−1) pixels separated by α from the reference pixel are any one of 1 to m read lines and are different from each other. The switching control means is connected to the pixel signal In the all output mode in which the force is output from all the pixels, the output of the pixel signal from the pixel for each pixel group is turned ON, and the output of the pixel signal is output from the 1 / α pixel of all the pixels arranged on the array line. In the thinning mode, the switching means is driven so as to turn on the output of pixel signals from the reference pixel and (m−1) pixels that are separated from the reference pixel by α.

  In addition, the reference pixel and (m−1) pixels separated by β from the reference pixel are connected to any one of 1 to m read lines and different read lines, and the switching control means In the second thinning mode in which output is output from 1 / β pixels of all of the plurality of pixels arranged on the array line, pixel signals are output from the reference pixel and (m−1) pixels separated from the reference pixel by β. It is preferable to drive the switching means so as to turn ON.

  Further, the plurality of pixels are alternately arranged on the arrangement line, and the first color pixel that outputs the first color pixel signal corresponding to the received light amount of the first color light and the received light amount of the second color light A second color pixel that outputs a second color pixel signal is preferable.

  The plurality of pixels are first color pixels that output a first color pixel signal corresponding to the amount of received light of the first color, and read lines 1 to m are first lines for reading the first color pixel signal. 1 to 1 m color readout lines for one color, the switching means is a first switching means for switching ON / OFF of the output of the first color pixel signal, and the pixel group is formed by the first color pixels. A plurality of second color pixels for outputting a second color pixel signal corresponding to the amount of received light of the second color received on the light receiving surface, and a second for reading the second color pixel signal. A plurality of first color pixels, comprising: n readout lines for the first to second colors of color; and second switching means for switching ON / OFF of the output of the second color pixel signal from each of the plurality of second color pixels. And a plurality of second color pixels are alternately arranged on the array line, and the plurality of second color pixels are divided into n pixels arranged in a row. A plurality of second color pixel groups are formed, and γ pieces are separated from the second color reference pixels and the second color reference pixels, which are second color pixels arranged at predetermined positions on the array line (n−1). The second color pixels are any one of the first to first color n readout lines and are connected to different readout lines, respectively, and the switching control means is the second color pixel group in the full output mode. The output of the second color pixel signal from each second color pixel is turned ON, and in the first thinning mode, (n−1) number of (n−1) th number of pixels separated from the second color reference pixel and the second color reference pixel by one. It is preferable to drive the second switching means so as to turn on the output of the second color pixel signal from the two color pixels.

  The image signal processing apparatus of the present invention stores reading means for reading pixel signals output from 1 to m reading lines of the image sensor and pixel signals output from each of a plurality of pixels in all input modes. In the first thinning mode, a region for storing pixel signals output from the reference pixel and each of (m−1) pixels separated from the reference pixel by α is determined and read by the reading unit. The memory means for storing the pixel signal to be output and the pixel means for outputting the pixel signal output from each of the plurality of pixels based on the combination of the connection of the 1 to m readout lines and the plurality of pixels in the all input mode are defined in the storage means. In the first thinning mode, the reference pixel and the reference pixel based on the combination of 1 to m readout lines and the reference pixel and (m−1) pixels separated from the reference pixel by α. Picture And an array unit that stores a pixel signal output from each of the pixels separated by α from the element in a predetermined region of the storage unit.

  In addition, the storage means has an area for storing pixel signals output from the reference pixel and each of (m−1) pixels separated by β from the reference pixel in the second thinning mode, In the second thinning mode, the array means is connected to the reference pixel and the reference pixel based on a combination of 1 to m readout lines and a reference pixel and (m−1) pixels separated by β from the reference pixel. The pixel signal output from each of the pixels separated by β is stored in a predetermined area of the storage means.

  According to the present invention, full output and thinning output can be performed without switching the output of a pixel signal from a single pixel to any of a plurality of horizontal signal lines. Therefore, the changeover switch is not required, and the configuration of the image sensor can be simplified.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram schematically showing the overall configuration of a CMOS solid-state imaging device to which the first embodiment of the present invention is applied.

The CMOS solid-state imaging device 10 includes an imaging unit 11, a vertical shift register 12, a first correlated double sampling / sample and hold (CDS / SH) circuit 13 _D , a second CDS / SH circuit 13 _U , a first horizontal shift. Register 14 _D (switching control means), second horizontal shift register 14 _U (switching control means), first horizontal signal line group 15 _D , second horizontal signal line group 15 _U , first column selection switch section 16 _D (first switching means) and a second column selection switch section 16 _U (second switching means).

The imaging unit 11 and the vertical shift register 12 are directly connected. First and second horizontal signal line group 15 _D, 15 _U are first respectively second column selection switch section 16 _D, 16 _U and the first, via the second CDS / SH circuit 13 _D, 13 _U Connected to the imaging unit 11.

  A plurality of pixels 20 are arranged in a matrix on the imaging surface of the imaging unit 11. That is, the plurality of pixels 20 are arranged on a line (array line) along the horizontal direction (left-right direction in FIG. 1) of the imaging surface and on a line along the vertical direction (up-down direction in FIG. 1). The light receiving surface of each pixel 20 is covered with one of R, G, and B color filters (not shown). The R, G, and B color filters are arranged in a Bayer manner.

In each pixel 20, signal charges are generated according to the amount of light received corresponding to the color of each color filter. Reading out the pixel signal corresponding to the generated signal charge is performed for each pixel 20. The pixel 20 to be read is selected directly or indirectly by the vertical shift register 12 and the first and second horizontal shift registers 14 _D and 14 _U.

The vertical shift register 12 selects a row of pixels 20 to be read. The pixel signals output from the pixels 20 arranged in the selected row are correlated double-sampled by the first and second CDS / SH circuits 13 _D and 13 _U via the vertical signal lines 17 of each column.

The pixel signals sampled and held by the first and second CDS / SH circuits 13 _D and 13 _U are selected by the first and second horizontal shift registers 14 _D and 14 _U , and the first and second horizontal signal lines are selected. Read to 15 _D and 15 _U. The pixel signals read out to the first and second horizontal signal lines 15 _D and 15 _U are sent to, for example, a signal processing device (not shown in FIG. 1) that performs signal processing, and subjected to predetermined processing to be performed on the subject. The entire image is processed into an image signal.

The structure of the pixel will be described with reference to FIG. FIG. 2 is a circuit diagram illustrating a configuration of a pixel in the imaging unit. The R pixel 20 _(g , _h) (first color pixel) in the g row and h column and the G pixel 20 _{(g + 1} , _h) (second color pixel) in the (g + 1) row and h column will be described. However, the configuration of other pixels is the same. It should be noted that 1 row, 2 rows,..., G rows, (g + 1) rows,... From the lower end to the upper end of the imaging unit 11, and 1 column, 2 columns,. And count. The h column is an odd number column.

The R pixel 20 _(g , _h) includes a photodiode (PD) 21 _(g , _h) , a floating diffusion (FD) 22 _(g , _h) , a transfer transistor 23 _(g , _h) , a reset transistor 24 _(g , _{h). )} , An amplification transistor 25 _(g , _h) , and a g row selection transistor 26 _(g , _h) .

The opening surface of the PD 21 _(g , _h ) is covered with an R color filter (not shown). In the PD 21 _(g , _h) , charges are generated according to the amount of received light corresponding to R in the pixel 20 _(g , _h) , and the generated charges are accumulated.

FD22 _{(g, h)} are connected transfer transistor 23 _{(g, h)} the PD 21 _{(g, h)} through the. Transfer transistor 23 _{(g, h)} the sub-electrodes of switched transfer signal to the ON · OFF pulsed [Phi _T is input.

Transfer transistor 23 _{(g, h)} when a is ON, PD21 _{(g, h)} the signal charge accumulated in is transferred to the FD22 _{(g, h).} When PD21 _{(g, h)} the signal charges transferred from is received in _{FD22 (g, h), FD22} (g, h) the potential of the changes in potential corresponding to the charge received.

The FD 22 _(g , _h) is connected to the power supply line V _DD via the reset transistor 24 _(g , _h) . A reset signal Φ _{R that} is switched ON / OFF in a pulsed manner is input to the sub-electrode of the reset transistor 24 _(g , _h) .

When the reset transistor 24 _(g , _h) is turned on, the electric charge accumulated in the FD 22 _(g , _h) is swept out to the power supply line V _DD and reset. Further, the potential of the FD 22 _(g , _h) is reset to the potential of the power supply line V _DD .

The FD 22 _(g , _h) is connected to the sub electrode of the amplification transistor 25 _(g , _h) . One main electrode of the amplification transistor 25 _(g , _h) is connected to the power supply line V _DD . The other main electrode is connected to the first vertical signal line 17 _{D (h)} in the h column via the g row selection transistor 26 _(g , _h) in the h column. The potential of the FD 22 _(g , _h) is buffered and amplified by the amplification transistor 25 _(g , _h) , and is output as a pixel signal.

A g-row selection signal Φ _SLg that switches ON / OFF in a pulse shape is input to the sub-electrode of the g-row selection transistor 26 _(g , _h) . When the g row selection transistor 26 _(g , _h) is turned on, the pixel signal is output to the first vertical signal line 17 _{D (h)} in the h column.

The transfer signal Φ _T , the reset signal Φ _R , and the row selection signal Φ _SLg are output from the vertical shift register 12.

The first vertical signal line 17 _{D (h)} in the h column is a line extending vertically through the imaging unit 11 and is connected to the row selection transistor (not shown) of the R pixel (not shown) that forms the same h column. Is done. The first vertical signal line 17 D of h columns _(h) is connected to the constant current source I _SS above the imaging unit 11. Further, the first vertical signal line 17 _{D (h)} in the h column is connected to the first CDS / SH circuit 13 _D below the imaging unit 11.

A pixel signal output via the first vertical signal line 17 _{D (h)} in the h column is subjected to correlated double sampling / sample holding in the first CDS / SH circuit 13 _D. In other words, the pixel signal R ((h + 1) which is the difference between the original pixel signal which is the signal potential when the signal charge is transferred from the PD 21 _(g , _h) and the reset pixel signal which is the signal potential at the reset which becomes the reference level. ) / 2) _(g) is sampled and held.

The light reception sample signal Φ _PHD and the reset sample signal Φ _PHP output from the vertical shift register 12 are input to the first CDS / SH circuit 13 _D , whereby the original pixel signal and the reset pixel signal are sampled, respectively. .

The first CDS / SH circuit 13 _D is connected to the first horizontal signal line group 15 _D via the first h column selection transistor 16 _{D (h)} . When the first h column selection transistor 16 _{D (h)} is turned on, the pixel signal R ((h + 1) / 2) _(g) is output to the first horizontal signal line group 15 _D.

Each column is provided with a first vertical signal line and a first column selection transistor, and the first column selection switch section _16D is formed by the first column selection transistors of all the columns. The switching of the ON · OFF of the first column selection transistors in each column is performed by the first horizontal shift register 14 _D.

The configuration of the G pixel 20 _{(g + 1} , _h) except that the opening surface of the PD 21 _{(g + 1} , _h) is covered by the G color filter instead of the R color filter is the configuration of the R pixel 20 _(g , _h) . Is the same. Further, unlike the configuration of the R pixel 20 _(g , _h) , one main electrode of the (g + 1) row selection transistor 26 _{(g + 1} , _h) is the second vertical signal line 17 _{U (h) in the} h column. Connected to.

The second vertical signal line 17 _{U (h)} in the h column is a line extending vertically through the imaging unit 11 and is connected to a row selection transistor (not shown) of a G pixel (not shown) that forms the same h column. Is done. the second vertical signal line 17 U of h columns _(h) is connected to the constant current source I _SS below the imaging unit 11. Further, the second vertical signal line 17 _{U (h)} in the h column is connected to the second CDS / SH circuit 13 _U above the imaging unit 11.

The pixel signal output via the second vertical signal line 17 _{U in} the h column is subjected to correlated double sampling / sample holding in the second CDS / SH circuit 13 _U. The second CDS / SH circuit 13 _U is connected to the second horizontal signal line group 15 _U via the second h column selection transistor 16 _{U (h)} . When the second h column selection transistor 16 _{U (h)} is turned on, the sampled and held pixel signal G ((h + 1) / 2) _(g) is output to the second horizontal signal line group 15 _U. .

A second vertical signal line and a second column selection transistor are provided in each column, and the second column selection switch unit 16 _U is formed by all the second column selection transistors. In addition, the second horizontal selection register 14 _U performs ON / OFF switching of the second column selection transistor of each column.

The pixel signal G (j / 2) _(g) is output to the second horizontal signal line group 15 _U based on the output from the G pixels (not shown) arranged in the even number j columns.

The internal configuration of the B pixel (not shown ₎ is the same as that of the R pixel 20 _(g , _h) except that the opening surface of the PD (not shown) is covered with the B color filter instead of the R color filter. It is.

The connection from the row selection transistor (not shown) of the B pixel to the first horizontal signal line group 15 _D is the same as the configuration for the R pixel 20 _(g , _h) . The B pixels are arranged in j columns, and the pixel signal B (j / 2) _{(g + 1)} is the first output signal based on the output from the B pixel in (g + 1) rows and j columns. is output to the lines 15 _D.

Next, a connection configuration from each pixel to the first and second horizontal signal line groups 15 _D and 15 _U will be described with reference to FIG. FIG. 3 shows a connection state between R pixels, G pixels, and B pixels arranged in 1 to 4 rows and 1 to 16 columns to the first and second horizontal signal line groups 15 _D and 15 _U. It is a circuit diagram. In addition, although R pixel, G pixel, and B pixel arranged in 1 to 4 rows and 1 to 16 columns will be described, R pixel, G pixel, and B arranged in other rows and other columns. The same applies to the pixel configuration.

The first horizontal signal line group _15D is formed by first to first four horizontal signal lines _15D1 to _15D4 (first color to first color 4 readout lines). Similarly, the second horizontal signal line group 15 _U is formed of second to first to fourth horizontal signal lines 15 _U1 to 15 _U4 (second color to four read lines of first to second colors). The

In the first row, the R pixel 20 ₍₁ , ₁₎ is arranged in the first column, and the G pixel 20 ₍₁ , ₂₎ is arranged in the second column. In the 3rd to 16th columns of the first row, R pixels and G pixels are arranged alternately. Similarly, in the third row, the R pixel 20 ₍₃ , ₁₎ is arranged in the first column, and the G pixel 20 ₍₃ , ₂₎ is arranged in the second column. In 3rd to 16th columns in the third row, R pixels and G pixels are arranged alternately.

In the second row, the G pixel 20 ₍₂ , ₁₎ is arranged in the first column, and the B pixel 20 ₍₂ , ₂₎ is arranged in the second column. In the 3rd to 16th columns of the second row, the G pixels and the B pixels are arranged alternately. Similarly, in the fourth row, the G pixel 20 ₍₄ , ₁₎ is arranged in the first column and the B pixel 20 ₍₄ , ₂₎ is arranged in the second column. In the 4th to 3rd to 16th columns, the G pixels and the B pixels are arranged alternately.

The first vertical signal line 17 _{D (1)} in the first column is connected to the R pixels 20 ₍₁ , ₁₎ and 20 ₍₃ , ₁₎ in the _first and third rows. Similarly, the first vertical signal lines in the odd-numbered columns are connected to the R pixels in the first and third rows in each column. For example, the first vertical signal line 17 _{D (15)} in the 15th column is connected to the R pixels 20 ₍₁ , ₁₅₎ , 20 ₍₃ , ₁₅₎ in the _first and third rows.

The second vertical signal line 17 _{U (1)} in the first column is connected to the G pixels 20 ₍₂ , ₁₎ , 20 ₍₄ , ₁₎ in the second and fourth rows. Similarly, the second vertical signal lines in the odd-numbered columns are connected to the G pixels in the second and fourth rows in each column. For example, the second vertical signal line 17 _{U (15)} in the 15th column is connected to the G pixels 20 ₍₂ , ₁₅₎ and 20 ₍₄ , ₁₅₎ in the second and fourth rows.

The first vertical signal line 17 _{D (2)} in the second column is connected to the B pixels 20 ₍₂ , ₂₎ and 20 ₍₄ , ₂₎ in the _second and fourth rows. Similarly, the first vertical signal lines in even columns are connected to the B pixels in the second and fourth rows in each column. For example, the first vertical signal line 17 _{D (16)} in the 16th column is connected to the B pixels 20 ₍₂ , ₁₆₎ and 20 ₍₄ , ₁₆₎ in the second and fourth rows.

The second vertical signal line 17 _{U (2)} in the second column is connected to the G pixels 20 ₍₁ , ₂₎ , 20 ₍₃ , ₂₎ in the _first and third rows. Similarly, the second vertical signal lines in the even columns are connected to the G pixels in the first and third rows in each column. For example, the second vertical signal line 17 _{U (16)} in the 16th column is connected to the G pixels 20 ₍₁ , ₁₆₎ , 20 ₍₃ , ₁₆₎ in the _first and third rows.

The first vertical signal lines 17 _{D (1)} , 17 _{D (2)} , 17 _{D (15)} , and 17 _{D (16)} in the 1st, _2nd , _15th , and _16th columns are the first horizontal signal lines 15 _D1. Connected to. The first vertical signal lines 17 _{D (3)} , 17 _{D (4)} , 17 _{D (13)} and 17 _{D (14)} in the third, fourth, thirteenth and fourteenth columns are the first two horizontal signal lines 15 _D2. Connected to. The first vertical signal lines 17 _{D (5)} , 17 _{D (6)} , 17 _{D (11)} and 17 _{D (12)} in the _fifth , _sixth , _{eleventh and twelfth} columns are the first three horizontal signal lines 15 _D3. Connected to. The first vertical signal lines 17D ₍₇₎ , _{17D (8)} , _{17D (9)} , and _{17D (10)} in the seventh, eighth, ninth, and tenth columns are the first four horizontal signal lines _15D4. Connected to.

The first vertical signal lines 17 _{D (1) to} 17 _{D (16)} and the first to first four horizontal signal lines 15 _D1 to 15 _D4 in each column are connected to the first CDS / SH circuit ( It is connected via a first column selection switch section (not shown in FIG. 3) and not shown in FIG.

The second vertical signal lines 17 _{U (1)} , 17 _{U (2)} , 17 _{U (15)} and 17 _{U (16)} in the first, second, fifteenth and sixteenth columns are the second horizontal signal line 15 _U1. Connected to. The second vertical signal lines 17 _{U (3)} , 17 _{U (4)} , 17 _{U (13)} and 17 _{U (14)} in the third, fourth, thirteenth and fourteenth columns are the second two horizontal signal lines 15 _U2. Connected to. The second vertical signal lines 17 _{U (5)} , 17 _{U (6)} , 17 _{U (11)} and 17 _{U (12)} in the _fifth , _sixth , _{eleventh and twelfth} columns are the second three horizontal signal lines 15 _U3. Connected to. The second vertical signal lines 17 _{U (7)} , 17 _{U (8)} , 17 _{U (9)} and 17 _{U (10)} in the seventh, eighth, ninth and tenth columns are the second four horizontal signal lines 15 _U4. Connected to.

The second vertical signal lines 17 _{U (1) to} 17 _{U (16)} and the second to fourth horizontal signal lines 15 _U1 to 15 _U4 in each column are connected to the second CDS / SH circuit ( It is connected via a second column selection switch section (not shown in FIG. 3) and not shown in FIG.

The operation of the image sensor 10 having the above configuration will be described with reference to FIGS. First, the operation until the pixel signal is correlated and double-sampled / sampled by the first and second CDS / SH circuits 13 _D and 13 _U will be described using the timing chart of FIG. Next, referring to FIG. 5 to FIG. 12, the pixel signals sampled and held in the first and second CDS / SH circuits 13 _D and 13 _U are first to first 4 and second to first to second. The operation output to the four horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 to 15 _U4 will be described.

First, the pixel 20 ₍₁ , _{1) to} 20 ₍₁ , _{16) in the 1st} row to the _16th column is selected by switching the 1 row selection signal Φ _SL1 to ON at the timing of T1 (see FIG. 4). Is done. That is, the first and second vertical signal lines 17 _{D (1) to} 17 _{D (16)} and 17 _{U (} 1 to 16 columns from the pixels 20 ₍₁ , _{1) to} 20 ₍₁ , ₁₆₎ in the first row. _{1) The} original pixel signal or the reset pixel signal can be output to 17 _{U (16)} . Further, when the reset signal Φ _R and the transfer signal Φ _T are switched ON at the same timing, the FD and the PD are reset, and reset pixel signals are output to the first and second vertical signal lines of all the columns. Is done.

At the timing of T2, the reset sampling signal Φ _SHP is switched to ON, whereby the reset pixel signals of each column are sampled in the first and second CDS / SH circuits 13 _D and 13 _U , respectively.

At timing T3, by the transfer signal [Phi _T is switched to ON, the charge accumulated in PD are transferred to the FD, first of all columns, the original pixel signal is output to the second vertical signal line . At the timing of T4, the received light sampling signal Φ _SHD is switched ON, whereby the original pixel signal is sampled in the first and second CDS / SH circuits 13 _D and 13 _U.

At the timing of T5, the 1 row selection signal is switched OFF, whereby the selection of the pixels 20 ₍₁ , _{1) to} 20 ₍₁ , _{16) in} the _1st to _16th columns of the first row is released. At this timing, the first and second CDS / SH circuits 13 _D and 13 _U can output a pixel signal obtained by subtracting the reset pixel signal from the original pixel signal.

Incidentally, on the basis of the output from the first row 1,3,5,7,9,11,13,15 column of the R pixel, a reset pixel signal from the original pixel signals to the first CDS / SH circuit 13 _D The subtracted pixel signals R1 ₍₁₎ , R2 ₍₁₎ , R3 ₍₁₎ , R4 ₍₁₎ , R5 ₍₁₎ , R6 ₍₁₎ , R7 ₍₁₎ , R8 ₍₁₎ are sampled and held.

Further, based on the output from the G pixel in the first row 2, 4, 6, 8, 10, 12, 14, 16th column, the reset pixel signal is sent from the original pixel signal to the second CDS / SH circuit 13 _U. The subtracted pixel signals G1 ₍₁₎ , G2 ₍₁₎ , G3 ₍₁₎ , G4 ₍₁₎ , G5 ₍₁₎ , G6 ₍₁₎ , G7 ₍₁₎ , G8 ₍₁₎ are sampled and held.

Between timings T5 and T6, pixel signals R1 _{(1) to} R8 ₍₁₎ are sent from the first CDS / SH circuit 13 _D to the first to first four horizontal signal lines 15 _{D1 as described later.} ~ 15 is output to the outside of the image sensor 10 via _D4 . Similarly, the pixel signals _{G1 (1) ~G8} (1) is the imaging device 10 from the second CDS / SH circuit 13 _U through the second 1 second 4 of the horizontal signal line 15 _U1 to 15 _U4 Is output outside of.

When the selection signal in the second row is turned ON at the timing of T6, the pixels 20 ₍₂ , _{1) to} 20 ₍₂ , _{16) in the first} row to the _16th column in the second row are selected. Further, when the reset signal Φ _R and the transfer signal Φ _T are switched ON, the FD and the PD are reset, and reset signals are output to the first and second vertical signal lines of all the columns.

Thereafter, at timings T7 to T9, operations similar to those performed at timings T2 to T4 are performed. At the timing of T10 when the selection of the pixels in the second row is released, the first and second CDS / SH circuits 13 _D and 13 _U can output a pixel signal obtained by subtracting the reset pixel signal from the original pixel signal.

Based on the output from the G pixel in the second row 1, 3, 5, 7, 9, 11, 13, 15th column, the reset pixel signal is sent from the original pixel signal to the second CDS / SH circuit 13 _U. The subtracted pixel signals G1 ₍₂₎ , G2 ₍₂₎ , G3 ₍₂₎ , G4 ₍₂₎ , G5 ₍₂₎ , G6 ₍₂₎ , G7 ₍₂₎ , G8 ₍₂₎ are sampled and held.

Further, based on the output from the B pixel in the second row 2, 4, 6, 8, 10, 12, 14, 16th column, the reset pixel signal is sent from the original pixel signal to the first CDS / SH circuit 13 _D. The subtracted pixel signals B1 ₍₂₎ , B2 ₍₂₎ , B3 ₍₂₎ , B4 ₍₂₎ , B5 ₍₂₎ , B6 ₍₂₎ , B7 ₍₂₎ , B8 ₍₂₎ are sampled and held.

Between timings T10 and T11, as will be described later, the pixel signals G1 _{(2) to} G8 ₍₂₎ are sent from the second CDS / SH circuit 13 _U to the first to second horizontal signal lines 15 _U1. ~ 15 _U4 is output to the outside of the image sensor 10. Similarly, the pixel signals B1 ₍₂₎ ~B8 ₍₂₎ is the image pickup device 10 from the first CDS / SH circuit 13 _D via the horizontal signal line 15 _D1 to 15 _D4 of the first to fourth one-fourth Is output outside of.

Thereafter, at the timings T11 to T15 and T16 to T20, the same operation as the timings T1 to T5 and T6 to T10 is performed, and the pixel signals based on the outputs from the pixels in the third and fourth rows are the first and second CDS / Sampled and held by the SH circuits 13 _D and 13 _U. Further, after the timing of T20, the same operation as that of the timings of T1 to T5 is performed until the pixels in the uppermost row of the imaging unit 11 are reached, and pixel signals based on the outputs from all the pixels 20 are sampled and held.

The imaging device 10 can be switched between a full output mode for outputting pixel signals from all pixels and a thinning mode for outputting pixel signals from half of the pixels in a single row. Is possible. In the overall mode and the thinning-out mode, the first to second horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 to 15 _U4 from the first and second CDS / SH circuits 13 _D and 13 _U to the first to fourth and second to fourth horizontal signal lines. The operation of outputting pixel signals to is different.

The output operation to the horizontal signal line in the full output mode will be described with reference to FIGS. 5 and 7 are timing charts showing the operation of the first and second column selection transistors in the full output mode. FIGS. 6 and 8 show the pixel signals output from the first to first 4 and second to second horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 to 15 _{U4 at} each timing. FIG.

At the timing of t1 ₍₁₎ after the timing of T5 (see FIG. 4), the first 1, 3, 5, and 7 column selection transistors are turned ON (see FIG. 5), and the pixel signal R1 ₍₁₎ , R2 ₍₁₎ , R3 ₍₁₎ , and R4 ₍₁₎ are the first 1, first 2, first 3, and first 4 horizontal signal lines 15 _D1 , 15 _D2 , 15 _D3 , and 15 _{D4, respectively.} To the outside of the image sensor 10 (see FIG. 6).

Further, when the second 2, 4, 6, and 8 column selection transistors are turned ON at the same timing t1 ₍₁₎ (see FIG. 5), the pixel signals G1 ₍₁₎ , G2 ₍₁₎ , G3 _{( 1)} and G4 ₍₁₎ are connected to the outside of the image sensor 10 via the second 1, second 2, second 3, and second 4 horizontal signal lines 15 _U1 , 15 _U2 , 15 _U3 , and 15 _U4. (See FIG. 6).

Next, at the timing of t2 ₍₁₎ , the first 9, 11, 13, and 15 column selection transistors are turned on (see FIG. 5), so that the pixel signals R5 ₍₁₎ , R6 ₍₁₎ , R7 _{( 1)} , R8 ₍₁₎ are external to the imaging device 10 via the first 4, first 3, first 2, first 1 horizontal signal lines 15 _D4 , 15 _D3 , 15 _D2 , 15 _D1 (See FIG. 6).

At the same timing t2 ₍₁₎ , the second 10, 12, 14, and 16 column selection transistors are turned ON (see FIG. 5), so that the pixel signals G5 ₍₁₎ , G6 ₍₁₎ , G7 ₍₁₎ , G8 ₍₁₎ is connected to the imaging element 10 via the second 4, second 3, second 2, second 1 horizontal signal lines 15 _U4 , 15 _U3 , 15 _U2 , 15 _U1 . It is output to the outside (see FIG. 6).

At the subsequent timings, similarly to the timings of t1 ₍₁₎ and t2 ₍₁₎ , the four pixel signals output from the R pixel and the four pixel signals output from the G pixel are output from the image sensor 10. Output to the outside.

  The ON / OFF switching of the column selection transistor in the first row is repeated until the pixel signal of the pixel in the rightmost column of the imaging unit 11 is output. After the pixel signal of the pixel in the rightmost column is output, the pixel in the second row is selected as described above at the timing of T6 (see FIG. 4).

At the timing of t1 ₍₂₎ after the timing of T10 (see FIG. 4), the second 1, 3, 5, and 7 column selection transistors are turned on (see FIG. 7), and the pixel signal G1 ₍₂₎ , G2 ₍₂₎ , G3 ₍₂₎ , and G4 ₍₂₎ are the second 1, second 2, second 3, and second 4 horizontal signal lines 15 _U1 , 15 _U2 , 15 _U3 , and 15 _{U4, respectively.} To the outside of the image sensor 10 (see FIG. 8).

Further, when the first 2, 4, 6, and 8 column selection transistors are turned ON at the same timing t1 ₍₂₎ (see FIG. 7), the pixel signals B1 ₍₂₎ , B2 ₍₂₎ , and B3 _{( 2)} and B4 ₍₂₎ are external to the image sensor 10 via the first 1, first 2, first 3, and first 4 horizontal signal lines 15 _D1 , 15 _D2 , 15 _D3 , and 15 _D4. (See FIG. 8).

Next, at the timing of t2 ₍₂₎ , the second 9, 11, 13, and 15 column selection transistors are turned on (see FIG. 7), so that the pixel signals G5 ₍₂₎ , G6 ₍₂₎ , and G7 _{( 2)} , G8 ₍₂₎ are external to the image sensor 10 via the second 4, second 3, second 2, second 1 horizontal signal lines 15 _U4 , 15 _U3 , 15 _U2 , 15 _U1. (See FIG. 8).

At the same timing t2 ₍₂₎ , the first 10, 12, 14, and 16 column selection transistors are turned on (see FIG. 7), so that the pixel signals B5 ₍₂₎ , B6 ₍₂₎ , B7 ₍₂₎ , B8 ₍₂₎ is the first four, first three, first two, first one horizontal signal lines 15 _D4 , 15 _D3 , 15 _D2 , 15 _D1 of the image sensor 10. It is output to the outside (see FIG. 8).

At the subsequent timings, similarly to the timings of t1 ₍₂₎ and t2 ₍₂₎ , the four pixel signals output from the G pixel and the four pixel signals output from the B pixel are output from the image sensor 10. Output to the outside.

  The ON / OFF switching of the column selection transistors in the second row is repeated until the pixel signal of the pixel in the rightmost column of the imaging unit 11 is output. After the pixel signal of the pixel in the rightmost column is output, the pixel in the third row is selected as described above at the timing of T11 (see FIG. 4).

  Thereafter, in an odd-numbered row, an operation similar to the operation performed between T5 and T6 described above is performed. In the even-numbered row, the same operation as that performed between T10 and T11 described above is performed.

The output operation to the horizontal signal line in the thinning mode will be described with reference to FIGS. 9 and 11 are timing charts showing the operation of the column selection transistor of each column in the thinning mode. 10 and 12 show the pixel signals output from the first to first 4 and second to second horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 to 15 _{U4 at} each timing. FIG.

At the timing of t1 ′ ₍₁₎ after the timing of T5 (see FIG. 4), the first 1, 5, 9, and 13 column selection transistors are switched ON (see FIG. 9), and the pixel signal R1 ₍₁₎ , R3 ₍₁₎ , R5 ₍₁₎ , R7 ₍₁₎ are the first 1, first 3, first 4, and first 2 horizontal signal lines 15 _D1 , 15 _D3 , 15 _D4 , 15 _D2 To the outside of the image sensor 10 (see FIG. 10).

At the same timing t1 ′ ₍₁₎ , the second 2, 6, 10, and ₁₄ column selection transistors are turned ON (see FIG. 9), and the pixel signals G1 ₍₁₎ , G3 ₍₁₎ , G5 _{( 1)} , G7 ₍₁₎ are connected to the outside of the image sensor 10 via the second 1, second 3, second 4, second 2 horizontal signal lines 15 _U1 , 15 _U3 , 15 _U4 , 15 _U2. (See FIG. 10).

  In the thinning mode, the first and second 3, 4, 7, 8, 11, 12, 15, 16 column selection transistors remain OFF, and the pixel signals generated in the pixels of these columns are imaged. It is not output to the outside of the element 10.

At each subsequent timing, similarly to the timing of t1 ′ ₍₁₎ , the pixel signals output from four R pixels separated by two in the R pixels in the first row and the first row The pixel signals output from the four G pixels that are separated by two in the G pixel are output to the outside of the image sensor 10 at the same timing.

  The ON / OFF switching of the column selection transistor in the first row is repeated until the pixel signal in the rightmost column of the imaging unit 11 is output. When the pixel signal of the pixel in the rightmost column is output, the pixel in the second row is selected at the timing T6 (see FIG. 4) as described above.

At the timing of t1 ′ ₍₂₎ after the timing of T10 (see FIG. 4), the second 1, 5, 9, and 13 column selection transistors are switched ON (see FIG. 11), and the pixel signal G1 ₍₂₎ , G3 ₍₂₎ , G5 ₍₂₎ , G7 ₍₂₎ are the second 1, second 3, second 4, second 2 horizontal signal lines 15 _U1 , 15 _U3 , 15 _U4 , 15 _U2 Is output to the outside of the image sensor 10 (see FIG. 12).

At the same timing t1 ′ ₍₂₎ , the first ₂ , 6, 10, and 14 column selection transistors are turned ON (see FIG. 11), and the pixel signals B1 ₍₂₎ , B3 ₍₂₎ , B5 _{( 2)} and B7 ₍₂₎ are external to the image sensor 10 via the first 1, first 3, first 4, and first 2 horizontal signal lines 15 _D1 , 15 _D3 , 15 _D4 , and 15 _D2. (See FIG. 12).

  As in the first row, in the thinning mode, the first and second 3, 4, 7, 8, 11, 12, 15, 16 column selection transistors remain OFF. The generated pixel signal is not output to the outside of the image sensor 10.

In the subsequent timings, similarly to the timing of t1 ′ ₍₂₎ , pixel signals output from four G pixels separated by two in the G pixels in the second row and in the second row Among the B pixels, pixel signals output from four B pixels separated by two are output to the outside of the image sensor 10 at the same timing.

  The ON / OFF switching of the column selection transistors in the second row is repeated until the pixel signal of the pixel in the rightmost column of the imaging unit 11 is output. When the pixel signal of the pixel in the rightmost column is output, the pixel in the third row is selected as described above at the timing of T11 (see FIG. 4).

Thereafter, in the odd-numbered rows, the same operation as that performed at the timing of t1 ′ ₍₁₎ ,. In the even-numbered row, the same operation as that performed at the timing of t1 ′ ₍₂₎ ,.

  The effects of the image sensor of the present embodiment having the above configuration will be described.

First, the operation in the all output mode will be described with reference to FIG. Four R pixels 20 _(g , _{8 × p-7)} , 20 _(g , _{8 × p-5)} , 20 _(g , _{8 × p-3)} , 20 _(g , _{8 × p−1)} (p is an arbitrary natural number) to form the p-th R pixel group (first color pixel group).

Similarly, four G pixels 20 _(g , _{8 × p-6)} , 20 _(g , _{8 × p-4)} , 20 _(g , _{8 × p-2)} , 20 _{( g} , _{8 × p)} forms a p-th G pixel group (second color pixel group). In row (g + 1), four G pixels 20 _{(g + 1} , _{8 × p−7)} , 20 _{(g + 1} , _{8 × p−5)} , 20 _{(g + 1} , _{8 × )} continuously in the horizontal direction. _p-3) and 20 _{(g + 1} , _{8 × p-1)} form the pth G pixel group. In the (g + 1) row, four B pixels 20 _{(g + 1} , _{8 × p-6)} , 20 _{(g + 1} , _{8 × p-4)} , 20 _{(g + 1} , _{8 × p−2)} and 20 _{(g + 1} , _{8 × p)} form a p-th B pixel group (third color pixel group).

As described above, the R pixels 20 _(g , _{8 × p−7)} , 20 _(g , _{8 × p−5)} , 20 _(g , _{8 × p−3)} , 20 constituting the R pixel group in the g row, as described above. _(g , _{8 × p−1)} are a first vertical signal line, a first CDS / SH circuit (not shown in FIG. 13), and a first column selection switch section (not shown in FIG. 13). Are respectively connected to the first to first four horizontal signal lines 15 _D1 to 15 _D4 .

Similarly, the G pixels 20 _(g , _{8 × p-6)} , 20 _(g , _{8 × p-4)} , 20 _(g , _{8 × p-2)} , 20 _{( g} , _{8 × p)} , 20 _{(g + 1} , _{8 × p-7)} , 20 _{(g + 1} , _{8 × p-5)} , 20 _{(g + 1} , _{8 × p-3)} , 20 _{(g +1} , _{8 × p−1)} includes a second vertical signal line, a second CDS / SH circuit (not shown in FIG. 13), and a second column selection switch section (not shown in FIG. 13). Via the first to second horizontal signal lines 15 _U1 to 15 _U4 .

Similarly, the B pixels 20 _{(g + 1} , _{8 × p-6)} , 20 _{(g + 1} , _{8 × p-4)} , 20 _{(g + 1} , _{8 × p )} constituting the B pixel group in each row. _-2) , 20 _{(g + 1} , _{8 × p)} are the first to the first through the first vertical signal line, the first CDS / SH circuit, and the first column selection switch section. Are respectively connected to four horizontal signal lines 15 _D1 to 15 _D4 .

In the full output mode, R pixels 20 _(g , _{8 × p-7)} , 20 _(g , _{8 × p-5)} , 20 _{(g )} constituting the p-th pixel group in the g row at a single timing. , _{8 × p−3)} , 20 _(g , _{8 × p−1), the} pixel signals R (4 × p−3) _(g) , R (4 × p−2) _(g) , R ( 4 × p−1) _(g) and R (4 × p) _(g) are output via any one of the first to first four horizontal signal lines 15 _D1 to 15 _D4 .

At the same timing, G pixels 20 _(g , _{8 × p−6)} , 20 _(g , _{8 × p−4)} , 20 _(g , _{8 × p−2 )} constituting the p-th pixel group in the g row. ₎ , 20 _(g , _{8 × p)} and pixel signals G (4 × p-3) _(g) , G (4 × p-2) _(g) , G (4 × p−1) _{(g )} , G (4 × p) _(g) is output via any one of the second to second horizontal signal lines 15 _U1 to 15 _U4 .

Similarly, G pixels 20 _{(g + 1} , _{8 × p−7)} , 20 _{(g + 1} , _{8 × p−5)} , constituting the p-th pixel group in the (g + 1) row at a single timing, Pixel signals G (4 × p−3) _{(g + 1)} and G (4 × p ₎ output from 20 _{(g + 1} , _{8 × p−3)} and 20 _{(g + 1} , _{8 × p−1)} −2) _{(g + 1)} , G (4 × p−1) _{(g + 1)} and G (4 × p) _{(g + 1)} are the first to second horizontal signal lines 15 _U1. ~ 15 Output via any of _U4 .

At the same timing, the B pixels 20 _{(g + 1} , _{8 × p-6)} , 20 _{(g + 1} , _{8 × p-4)} , 20 _(g Pixel signals B (4 × p−3) _{(g + 1)} and B (4 × p−2) _(g ) output from ₊₁ , _{8 × p−2)} and 20 _{(g + 1} , _{8 × p) +1)} , B (4 × p−1) _{(g + 1)} , B (4 × p) _{(g + 1)} are passed through the first to first four horizontal signal lines 15 _D1 to 15 _D4 . Is output.

Therefore, at all timings in the full output mode, eight pixel signals are output from the first to first four and second to second horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 to 15 _U4. Can be output.

Next, the operation in the thinning mode will be described. As described above, the R pixel 20 _(g , _{8 × p−7)} in the (8 × p−7) column and the R pixel 20 _(g , _{8 × in the} (8 × p−7)) column in the _g row. three R pixels from _p-7) is spaced apart two by two to each other in the R pixel _{20 (g, 8 × p-} 3), 20 (g, 8 × p + 1), 20 (g, _{8 × p + 5) through} the first vertical signal line, the first CDS / SH circuit, and the first column selection switch unit, the first to first four horizontal signal lines 15 _D1 to 15 are individually connected to _D4 .

Similarly, the G pixel 20 _(g , _{8 × p-6)} in the (8 × p-6) column and the G pixel 20 _(g , _{8 × p− )} in the (8 × p-6) column in the _g row. ₆₎ three G pixels 20 _(g , _{8 × p−2)} , 20 _(g , _{8 × p + 2)} , 20 _(g , _{8 × p + 6) through} the second vertical signal line, the second CDS / SH circuit, and the second column selection switch section, the second to the fourth horizontal signal lines 15 _U1 to 15 _U1 . 15 _U4 is connected separately.

Similarly, (g + 1) and (8 × p-7) th column of G pixel _{20 (g + 1, 8 ×} p-7) in a row, (8 × p-7) G pixel th row 20 _{(g + 1} , _{8 × p−7)} to 3 G pixels 20 _{(g + 1} , _{8 × p−3)} , 20 _{(g + 1} , _{8 × p )} that are arranged two by two apart from each other in the G pixel ₊₁₎ and 20 _{(g + 1} , _{8 × p + 5)} are connected to the second 1 through the second vertical signal line, the second CDS / SH circuit, and the second column selection switch section. To the second four horizontal signal lines 15 _U1 to 15 _U4 , respectively.

Similarly, (g + 1) and (8 × p-6) th column of B pixel _{20 (g + 1, 8 ×} p-6) in row, (8 × p-6) th column of B pixel 20 _{(g + 1} , _{8 × p−6)} and three B pixels 20 _{(g + 1} , _{8 × p−2)} , 20 _{(g + 1} , _{8 × p )} that are arranged two by two apart from each other among the B pixels ₊₂₎ , 20 _{(g + 1} , _{8 × p + 6)} are connected to the first 1 through the first vertical signal line, the first CDS / SH circuit, and the first column selection switch section. To the first four horizontal signal lines 15 _D1 to 15 _D4 , respectively.

In the thinning mode, four R pixels 20 _(g , _{8 × p−7)} , 20 _(g , _{8 × p )} that are spaced apart from each other among the R pixels in the g row at a single timing. _-3) , 20 _(g , _{8 × p + 1)} , 20 _(g , _{8 × p + 5)} pixel signals R (4 × p-3) _(g) , R (4 × p−1 ₎ output from 20 _(g , _{8 × p + 5)} ) _(G) , R (4 × p + 1) _(g) , R (4 × p + 3) _(g) is output via any one of the first to first four horizontal signal lines 15 _D1 to 15 _D4 Is done.

Further, at the same timing, four G pixels 20 _(g , _{8 × p−6)} , 20 _(g , _{8 × p−2)} , 20 that are separated from each other among the G pixels in the g row by _two . pixel signals G (4 × p−3) _(g) , G (4 × p−1) _(g) , output from _(g , _{8 × p + 2)} , 20 _(g , _{8 × p + 6 )} , G (4 × p + 1) _(g) and G (4 × p + 3) _(g) are output via any one of the first to second four horizontal signal lines 15 _U1 to 15 _U4 .

Similarly, at a single timing, four G pixels 20 _{(g + 1} , _{8 × p−7)} , 20 _{(g + 1 )} that are spaced apart from each other among the G pixels in the (g + 1) row. , _{8 × p-3)} , 20 _{(g + 1} , _{8 × p + 1)} , 20 _{(g + 1} , _{8 × p + 5)} and the pixel signal G (4 × p-3) _{(g +1)} , G (4 × p−1) _{(g + 1)} , G (4 × p + 1) _{(g + 1)} , G (4 × p + 3) _{(g + 1)} are first to first It is output via any one of the four horizontal signal lines 15 _U1 to 15 _U4 .

In addition, at the same timing, four B pixels 20 _{(g + 1} , _{8 × p−6)} , 20 _{(g + 1} , _{8 × )} that are arranged two by two apart from each other among the B pixels in the (g + 1) row. _p-2) , 20 _{(g + 1} , _{8 × p + 2)} , 20 _{(g + 1} , _{8 × p + 6), the} pixel signal B (4 × p-3) _{(g + 1)} , B (4 × p−1) _{(g + 1)} , B (4 × p + 1) _{(g + 1)} , B (4 × p + 3) _{(g + 1)} are the first to second four horizontal signals. It is output via one of the lines 15 _D1 to 15 _D4 .

Accordingly, at all timings in the thinning mode, eight pixel signals are _output from the first to first four and second to first to fourth horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 to 15 _U4. Can be output.

  As described above, according to the imaging device of the present embodiment, it is possible to perform full output or thinning out without switching the output of a pixel signal from a single pixel to any of a plurality of horizontal signal lines. Therefore, the changeover switch 18 (see FIG. 28) used in the conventional image sensor 10 'is unnecessary.

  Next, an image sensor to which the second embodiment of the present invention is applied will be described. In the second embodiment, the connection between the first and second CDS / SH circuits and the first to first 4, and the first to second horizontal signal lines, and column selection in the thinning mode. The signal output is different from that of the first embodiment. The second embodiment will be described focusing on the differences from the first embodiment. In addition, the same code | symbol is attached | subjected to the site | part which has the same function as 1st Embodiment.

  FIG. 14 shows R pixels and G pixels arranged in odd-numbered columns up to 1st to 31st columns in the first and second rows in the second embodiment, first to first fours, and second to first ones. It is a circuit diagram which shows the connection with the 2nd 4 horizontal signal line. For the sake of simplicity, FIG. 14 shows the R pixel in the first row and the G pixel in the second row, the first and second vertical signal lines, 1 to 1st 4 and second to 1st to 4th horizontal signal lines are illustrated.

  A G pixel and first and second vertical signal lines are arranged between R pixels in consecutive odd columns, and a B pixel is arranged between consecutive G pixels in odd columns. Further, as in the first embodiment, R pixels and G pixels are arranged in odd-numbered rows, and G pixels and B pixels are arranged in a Bayer manner in even-numbered rows.

The first vertical signal lines 17 _{D (1)} , 17 _{D (3)} , 17 _{D (5)} , 17 _{D (7)} , 17 _{D (9)} , 17 _{D (11 )} , 17 _{D (13)} , 17 _{D (15)} and the first to first four horizontal signal lines 15 _D1 to 15 _D4 are the same as those in the first embodiment. Further, the second vertical signal lines 17 _{U (1)} , 17 _{U (3)} , 17 _{U (5)} , 17 _{U (7)} , 17 _{U (9)} , 17 _{U in} odd-numbered columns 1 to 15 are arranged. _{The connections of (11)} , 17 _{U (13)} , 17 _{U (15)} and the second to second horizontal signal lines 15 _U1 to 15 _U4 are the same as those in the first embodiment.

The first vertical signal lines 17 _{D (23)} and 17 _{D (29) in the 23rd} and _29th columns are connected to the first horizontal signal line 15 _D1 . The first vertical signal lines 17 _{D (17)} and 17 _{D (27) in} the 17th and _27th columns are connected to the first two horizontal signal lines 15 _D2 . The first vertical signal lines 17 _{D (19)} and 17 _{D (25) in the 19th} and _25th columns are connected to the first 3 horizontal signal lines 15 _D3 . The first vertical signal lines 17 _{D (21)} and 17 _{D (31) in the 21st} and _31st columns are connected to the first 4 horizontal signal lines 15 _D4 .

The second vertical signal lines 17 _{U (23)} and 17 _{U (29) in the 23rd} and _29th columns are connected to the second horizontal signal line 15 _U1 . The second vertical signal lines 17 _{U (17)} and 17 _{U (27) in} the 17th and _27th columns are connected to the second two horizontal signal lines 15 _U2 . The second vertical signal lines 17 _{U (19)} and 17 _{U (25) in the 19th} and _25th columns are connected to the second 3 horizontal signal lines 15 _U3 . The second vertical signal lines 17 _{U (21)} and 17 _{U (31) in the 21st} and _31st columns are connected to the second 4 horizontal signal lines 15 _U4 .

The first vertical signal lines (not shown) in even-numbered columns up to 2 to 32 and the first to first horizontal signal lines 15 _D1 to 15 _D4 are each connected one by one. This is the same as the connection between the first vertical signal line in the previous odd-numbered column and the first to first four horizontal signal lines 15 _D1 to 15 _D4 .

The second vertical signal lines (not shown) in even-numbered columns up to 2 to 32 and the second to second horizontal signal lines 15 _U1 to 15 _U4 are each connected one by one. The connection is the same as the connection between the second vertical signal line in the previous column and the second to fourth horizontal signal lines 15 _U1 to 15 _U4 .

In the 33rd and subsequent columns, the same connection as the connection between the first vertical signal lines (not shown) and the first to first 4 horizontal signal lines 15 _D1 to 15 _D4 in the 1st to 32nd columns. Is repeated. Similarly, in the 33rd and subsequent columns, it is the same as the connection between the second vertical signal lines (not shown) and the first to second horizontal signal lines 15 _U1 to 15 _U4 in columns 1 to 32. The connection is repeated. That is, after the 33rd row, the connection is the same as the row 32 rows before.

The operation of the image sensor 100 having the above configuration will be described with reference to FIGS. The operation until the pixel signal is correlated and double-sampled / sampled and held by the first and second CDS / SH circuits 13 _D and 13 _U is the same as that in the first embodiment (FIG. 4). reference).

  In the image sensor 100 to which this embodiment is applied, unlike the first embodiment, the whole mode, the first thinning mode for outputting pixel signals from 1/2 pixels, and the pixel signals from 1/4 pixels Can be switched to one of the second thinning-out modes.

In the whole mode, at the timing t1 ₍₁₎ after the timing T5 (see FIG. 4), the first 1, 3, 5, 7 column selection transistor and the second 2, 4, 6, 8 column selection transistor are turned on. By switching to ON (see FIG. 15), pixel signals R1 _{(1) to} R4 ₍₁₎ and G1 _{(1) to} G4 ₍₁₎ are output as in the first embodiment (see FIG. 16). .

Further, the first 9, 11, 13, and 15 column selection transistors and the second 10, 12, 14, and 16 column selection transistors are switched ON at the timing of t2 ₍₁₎ (see FIG. 15), so that the pixel signal R5 _{(1) to} R8 ₍₁₎ and G5 _{(1) to} G8 ₍₁₎ are output in the same manner as in the first embodiment (see FIG. 16).

At the timing of t3 ₍₁₎ , the first 17, 19, 21, and 23 column selection transistors are turned on (see FIG. 15), and based on the output from the R pixels in the 17, 19, 21, and 23 columns. The pixel signals R9 ₍₁₎ , R10 ₍₁₎ , R11 ₍₁₎ , R12 ₍₁₎ generated in this way are the first 2, first 3, first 4, first 1 horizontal signal lines. _15D2 , _15D3 , _15D4 , and _15D1 are output (see FIG. 16).

Further, at the same timing t3 ₍₁₎ , the second 18, 20, 22, and 24 column selection transistors are turned ON (see FIG. 15), so that the G pixels in the 18, 20, 22, and 24 columns are turned on. Pixel signals G9 ₍₁₎ , G10 ₍₁₎ , G11 ₍₁₎ , G12 ₍₁₎ generated based on the output are the second 2, second 3, second 4, second 1 It is output via the horizontal signal lines 15 _U2 , 15 _U3 , 15 _U4 , and 15 _U1 (see FIG. 16).

Next, at the timing of t4 ₍₁₎ , the first 25, 27, 29, and 31 column selection transistors (not shown) are turned on (see FIG. 16), so that the 25, 27, 29, and 31 column selection transistors are turned on. Pixel signals R13 ₍₁₎ , R14 ₍₁₎ , R15 ₍₁₎ , R16 ₍₁₎ generated based on the output from the R pixel are the first 3, the first 2, the first 1, the first, 1 and 4 horizontal signal lines 15 _D3 , 15 _D2 , 15 _D1 , and 15 _D4 (see FIG. 16).

Also, at the same timing t4 ₍₁₎ , the second 26, 28, 30, 32 column selection transistors (not shown) are turned ON (see FIG. 15), so that the 26, 28, 30, 32 columns. Pixel signals G13 ₍₁₎ , G14 ₍₁₎ , G15 ₍₁₎ , G16 ₍₁₎ generated on the basis of outputs from the G pixels of the second, third, second 2, second 1, It is output via the second four horizontal signal lines 15 _U3 , 15 _U2 , 15 _U1 and 15 _U4 (see FIG. 16).

At each subsequent timing, four pixel signals output from the R pixel and four pixel signals output from the G pixel are output in the same manner as t1 _{(1) to} t4 ₍₁₎ . The ON / OFF switching of the column selection transistor in the first row is repeated until the pixel in the rightmost column of the imaging unit 11 is reached. When the pixel signal of the pixel in the rightmost column is output, the pixel in the second row is selected as described above at the timing of T6 (see FIG. 4).

  Similarly, during the timing of T10 and T11 (see FIG. 4), in the second row, four pixel signals output from the G pixels constituting the same G pixel group for each pixel group and the same B pixel Four pixel signals output from the B pixels constituting the group are output to the outside of the image sensor 100.

Thereafter, in the odd-numbered rows, the pixel signal output from the R pixel and the pixel signal output from the G pixel are imaged in the same manner as the operation performed at the timings t1 _{(1) to} t4 ₍₁₎ described above. Output to the outside of the element 100. Similarly, the pixel signal output from the G pixel and the pixel signal output from the B pixel are also output to the outside of the image sensor 100 in the even-numbered rows.

The output operation to the horizontal signal line in the first thinning mode will be described with reference to FIGS. T5 timing at the timing of t1 _'(1) after (see FIG. 4), the pixel signals _{R1 (1), R3 (1} ), R5 (1), R7 (1), and G1 _(1), G3 _{( 1)} , G5 ₍₁₎ , and G7 ₍₁₎ are output as in the first embodiment.

Next, at the timing of t2 ′ ₍₁₎ , the first 17, 21, 25, and 29th column selection signal is switched ON (see FIG. 17), so that the R pixels in the 17, 21, 25, and 29th columns Pixel signals R9 ₍₁₎ , R11 ₍₁₎ , R13 ₍₁₎ , R15 ₍₁₎ generated on the basis of the outputs of the first, second 4, first 3, first 1 horizontal The signal is output to the outside of the image sensor 100 via the signal lines 15 _D2 , 15 _D4 , 15 _D3 , and 15 _D1 (see FIG. 18).

Further, the second 18, 22, 26, 30 column selection transistor (not shown) is turned ON at the same timing t2 ′ ₍₁₎ (see FIG. 17), 18, 22, 26, 30. Pixel signals G9 ₍₁₎ , G11 ₍₁₎ , G13 ₍₁₎ , G15 ₍₁₎ generated based on the output from the G pixel in the column are the second 2, second 4, second 3 The first horizontal signal lines 15 _U2 , 15 _U4 , 15 _U3 , and 15 _U1 are output (see FIG. 18).

  In the first thinning mode, the first and second 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28, 31, 32 columns are selected. The transistors remain OFF, and pixel signals generated based on outputs from the pixels in these columns are not output to the outside of the image sensor 100 (see FIG. 17).

  At subsequent timings, pixel signals output from four R pixels separated by two in the R pixel in the first row, and four G signals separated by two in the G pixel in the first row. A pixel signal output from the pixel is output to the outside of the image sensor 100.

  The ON / OFF switching of the column selection transistor in the first row is repeated until the pixel signal in the rightmost column of the imaging unit 11 is output. When the pixel signal of the pixel in the rightmost column is output, the pixel in the second row is selected at the timing T6 (see FIG. 4) as described above.

  Similarly, during the timings of T10 and T11 (see FIG. 4), pixel signals output from four G pixels separated by two in the G pixels in the second row and B pixels in the second row Pixel signals output from four B pixels that are two by two are output to the outside of the image sensor 100.

Thereafter, in the odd-numbered rows, the pixel signal output from the R pixel and the G pixel are output in the same manner as the operation performed at the timings t1 ′ ₍₁₎ , t2 ′ ₍₁₎ ,. A pixel signal is output to the outside of the image sensor 100. Similarly, the pixel signal output from the G pixel and the pixel signal output from the B pixel are also output to the outside of the image sensor 100 in the even-numbered rows.

The output operation to the horizontal signal line when in the second thinning mode will be described with reference to FIGS. At the timing of t1 ″ after the timing of T5 (see FIG. 4), the first 1, 9, 17, 25th column column selection transistors are turned ON (see FIG. 19), thereby 1, 9, 17, Pixel signals R1 ₍₁₎ , R5 ₍₁₎ , R9 ₍₁₎ , R13 ₍₁₎ generated based on the output from the R pixel in the 25th column are the first 1, the first 4, the first 2. The signal is output to the outside of the image sensor 100 through the first three horizontal signal lines 15 _D1 , 15 _D4 , 15 _D2 , and 15 _D3 (see FIG. 20).

Further, the second 2, 10, 18, 26 column selection transistor (not shown) is turned ON at the same timing t1 ″ ₍₁₎ (see FIG. 19), 2, 10, 18, 26. Pixel signals G1 ₍₁₎ , G5 ₍₁₎ , G9 ₍₁₎ , G13 ₍₁₎ generated based on the output from the G pixel in the column are the second 1, second 4, second 2 _Are output via the second three horizontal signal lines 15 _U1 , 15 _U4 , 15 _U2 , and 15 _U3 (see FIG. 20).

  In the second thinning mode, the first and second 3 to 8, 11 to 16, 19 to 24, and 27 to 32 column selection transistors remain OFF, and output from pixels in these columns is not performed. The pixel signal generated based on this is not output to the outside of the image sensor 100 (see FIG. 19).

  At subsequent timings, pixel signals output from four R pixels separated by four in the R pixel in the first row and four G pixels separated by four in the G pixel in the first row. A pixel signal output from the pixel is output to the outside of the image sensor 100.

  The ON / OFF switching of the column selection transistor in the first row is repeated until the pixel signal in the rightmost column of the imaging unit 11 is output. When the pixel signal of the pixel in the rightmost column is output, the pixel in the second row is selected at the timing T6 (see FIG. 4) as described above.

  Similarly between the timings of T10 and T11 (see FIG. 4), the pixel signals output from four G pixels separated by four among the G pixels in the second row, and the B pixels in the second row Pixel signals output from four B pixels that are separated from each other by four are output to the outside of the image sensor 100.

Thereafter, in an odd-numbered row, the pixel signal output from the R pixel and the pixel signal output from the G pixel are output from the image sensor 100 in the same manner as the operation performed at the timing t1 ″ ₍₁₎ . In the even-numbered rows, the pixel signal output from the G pixel and the pixel signal output from the B pixel are also output to the outside of the image sensor 100.

According to the imaging device 100 of the present embodiment having the above-described configuration, the same function as that of the first embodiment can be exhibited. That is, at all timings in the full output mode and the first thinning mode, the first to first 4, second to second horizontal signal lines 15 _D1 to 15 _D4 , 15 _U1 to 15 It is possible to output eight pixel signals from _U4 .

  Furthermore, the effect which the image pick-up element 100 of this embodiment has is demonstrated.

In g line as (16 × r-15) th column R pixels (r is an arbitrary natural _{number) 20 (g, 16 × r} -15), (16 × r-15) th column of the R pixel 20 _(g, 3 R pixels 20 _(g , ₁₆ × _r-7) , 20 _(g , ₁₆ × _{r + 1)} , 20 ₍ 4), which are arranged apart from each other by 4 from the ₁₆ × _r-15) R pixel. _g , ₁₆ × _{r + 9)} are the first to first four horizontal signal lines via the first vertical signal line, the first CDS / SH circuit, and the first column selection switch unit. 15 _D1 to 15 _D4 are separately connected to each other (see FIG. 16).

Similarly, the G pixel 20 _(g , ₁₆ × _r-14) in the (16 × r-14) column and the G pixel 20 _(g , ₁₆ × _{r− )} in the (16 × r-14) column in the _g row. ₁₄₎ three G pixels 20 _(g , ₁₆ × _r−6) , 20 _(g , ₁₆ × _{r + 2)} , 20 _(g , ₁₆ × _{r + 10) through} the second vertical signal line, the second CDS / SH circuit, and the second column selection switch unit, the second to the fourth horizontal signal lines 15 _U1 to 15 _U1 . 15 _U4 is connected separately.

Similarly, the (16 × r−15) th column G pixel 20 _{(g + 1} , ₁₆ × _r−15) in the (g + 1) th row and the (16 × r−15) th column G pixel 20 _{(g +) 1} , ₁₆ × _r−15) and three G pixels 20 _{(g + 1} , ₁₆ × _r−7) , 20 _{(g + 1} , ₁₆ × _{r )} that are spaced apart from each other by 4 each in the G pixel. ₊₁₎ and 20 _{(g + 1} , ₁₆ × _{r + 9)} are connected to the second 1 through the second vertical signal line, the second CDS / SH circuit, and the second column selection switch section. To the second four horizontal signal lines 15 _U1 to 15 _U4 , respectively.

Similarly, the B pixel 20 _{(g + 1} , ₁₆ × _r-14) in the (16 × r-14) column and the B pixel 20 _{(g +} ) in the (16 × r-14) column in the _{(g + 1} ) row. ₁ , ₁₆ × _r−14) to 3 B pixels 20 _{(g + 1} , ₁₆ × _r−6) , 20 _{(g + 1} , ₁₆ × _{r + )} that are spaced apart from each other by 4 in the B pixel. ₂₎ , 20 _{(g + 1} , ₁₆ × _{r + 10)} are connected to the first 1 to 1 via the first vertical signal line, the first CDS / SH circuit, and the first column selection switch section. The first four horizontal signal lines 15 _D1 to 15 _D4 are separately connected to each other.

In the second thinning mode, four R pixels 20 _(g , ₁₆ × _r−15) , 20 _(g , ₁₆ × _r−7) , 20 _(g , ₁₆ × _{r + 1)} , 20 _(g , ₁₆ × _{r + 9)} output pixel signals R (8 × r−7) _(g) , R (8 × r-3) _(g) , R (8 × r + 1) _(g) , R (8 × r + 5) _(g) is one of the first to first four horizontal signal lines 15 _D1 to 15 _D4. Is output via.

Further, at the same timing, four G pixels 20 _(g , ₁₆ × _r−14) , 20 _(g , ₁₆ × _r−6) , 20 arranged four by four apart from each other in the G pixels in the g row. pixel signals G (8 × r−7) _(g) , G (8 × r−3) _(g) , output from _(g , ₁₆ × _{r + 2)} , 20 _(g , ₁₆ × _{r + 10 )} , G (8 × r + 1) _(g) and G (8 × r + 5) _(g) are output via any one of the second to fourth horizontal signal lines 15 _U1 to 15 _U4 .

Similarly, four G pixels 20 _{(g + 1} , ₁₆ × _r−15) , 20 _{(g + 1 )} that are spaced apart from each other by four among the G pixels in the (g + 1) row at a single timing. , ₁₆ × _r−7) , 20 _{(g + 1} , ₁₆ × _{r + 1)} , 20 _{(g + 1} , ₁₆ × _{r + 9), the} pixel signal G (8 × r−7) _{(g + 1)} , G (8 × r−3) _{(g + 1)} , G (8 × r + 1) _{(g + 1)} , G (8 × r + 5) _{(g + 1)} are the first to second 4 Are output via any one of the horizontal signal lines 15 _U1 to 15 _U4 .

In addition, at the same timing, four B pixels 20 _{(g + 1} , ₁₆ × _r-14) , 20 _{(g + 1} , ₁₆ × ₎ that are spaced apart from each other by four in the B pixels in the (g + 1) row. _r-6) , 20 _{(g + 1} , ₁₆ × _{r + 2)} , pixel signal B (8 × r−7) _{(g + 1)} output from 20 _{(g + 1} , ₁₆ × _{r + 10 )} , B (8 × r−3) _{(g + 1)} , B (8 × r + 1) _{(g + 1)} , B (8 × r + 5) _{(g + 1)} are the first to first four horizontal signals. It is output via one of the lines 15 _D1 to 15 _D4 .

As described above, even in the second thinning mode, the first to first 4 and second to first 4 horizontal signal lines 15 _D1 to 15 _D4 and 15 _U1 at all timings. It is possible to output eight pixel signals from ~ 15 _U4 .

  Therefore, according to the imaging device of the present embodiment having the above-described configuration, the output of a pixel signal from a single pixel is not switched to any of a plurality of horizontal signal lines, and all outputs are also a plurality of patterns. Thinning out output is also possible. Therefore, the changeover switch 18 (see FIG. 26) used in the conventional image sensor 10 'is unnecessary.

  Next, a modification of the first embodiment will be described. FIG. 21 is a circuit diagram showing connections between R pixels, G pixels, and B pixels arranged in 1 to 4 rows and 1 to 16 columns of the image sensor 101 of the present modification to the vertical signal line group 150. .

In this modification, unlike the first embodiment, one vertical signal line 170 _{(1) to} 170 ₍₁₆₎ is provided in each column, and all R, G pixels arranged in a single column, or a single All the G and B pixels arranged in this column are connected to the same vertical signal line. Further, the connections between the vertical signal lines 170 _{(1) to} 170 _{( 16)} and the horizontal signal lines 150 _{1 to} 150 _{4 of 1 to 4} are also different from those of the first embodiment.

The vertical signal lines 170 ₍₁₎ , 170 ₍₈₎ , 170 ₍₉₎ , and 170 ₍₁₃₎ in the first, _eighth , ninth, and thirteenth columns are connected to _one horizontal signal line 1501. The vertical signal lines 170 ₍₂₎ , 170 ₍₇₎ , 170 ₍₁₁₎ , and 170 ₍₁₄₎ in the second, _seventh , eleventh, and fourteenth columns are connected to the _two horizontal signal lines 1502. The vertical signal lines 170 ₍₃₎ , 170 ₍₆₎ , 170 ₍₁₀₎ , and 170 ₍₁₅₎ in the third, _sixth , tenth, and fifteenth columns are connected to _three horizontal signal lines 1503. The vertical signal lines 170 ₍₄₎ , 170 ₍₅₎ , 170 ₍₁₂₎ , and 170 ₍₁₆₎ in the fourth, fifth, twelfth, and sixteenth columns are connected to the _four horizontal signal lines 1504.

As in the first embodiment, each of the vertical signal lines 170 _{(1) to} 170 _{( 16)} and the horizontal signal lines 150 _{1 to} 150 ₄ is a first CDS / SH circuit (not shown in FIG. 21). And a first column selection switch section (not shown in FIG. 21).

In the modified example having the above-described configuration, in the all output mode, four pixels arranged continuously along the row, for example, the pixels 200 ₍₁ , ₁₎ to 200 ₍₁ , ₄₎ in the _first to fourth columns, or 5 The pixel signals are output to 1-4 horizontal signal lines 150 _{1 to} 150 ₄ at a single timing for each pixel group constituted by the pixels 200 ₍₁ , ₅₎ to 200 ₍₁ , _{8) in} the eighth column. Let

In the thinning mode, pixels output from the pixels 200 ₍₁ , ₄₎ , 200 ₍₁ , ₇₎ , 200 ₍₁ , ₁₀₎ arranged every third row from the R pixel 200 ₍₁ , ₁₎ in the first column. A signal is output to the outside of the image sensor 101 via one horizontal signal line 150 ₁ , four horizontal signal lines 150 ₄ , two horizontal signal lines 150 ₂ , and three horizontal signal lines 150 ₃ at a single timing. .

  According to the image sensor 101 that performs the above-described configuration and operation, it is possible to output pixel signals from all horizontal signal lines at all timings in the all-input mode and the thinning-out mode.

  In the imaging device to which the first and second embodiments are applied, the number of horizontal signal lines for outputting pixel signals corresponding to a single color is four, but a plurality of horizontal signal lines may be used. In an imaging device having m first horizontal signal lines (m is an integer of 2 or more), a pixel group is formed by m pixels of the same color adjacent to each other, and each pixel forms the same pixel group. It is configured to be connected to a horizontal signal line different from the pixel, and by reading out the pixel signal through each horizontal signal line for each pixel group, pixel signals are output simultaneously from all m horizontal signal lines in all output modes. It becomes possible to make it. Even if the number of horizontal signal lines in the modification is not four, the same effect can be obtained as long as there are a plurality of horizontal signal lines.

  Note that although there are four horizontal signal lines for outputting pixel signals at the same timing for each color, the same effect as in the first and second embodiments can be obtained even if different. That is, the number of first horizontal signal lines can be m and the number of second horizontal signal lines can be n.

  Further, in the first and second embodiments, in the thinning mode and the first thinning mode, 1/2 reading is performed for each color for each column, that is, every second reading, but every other reading is performed. You may go.

  When reading is performed every α (α is an integer of 2 or more), that is, when 1 / α is read for each color of each column, four pixels arranged in the same color at a distance from each other. Need only be connected to different horizontal signal lines. If a pixel signal is output via each horizontal signal line for each of these four pixels in the thinning mode, it is possible to simultaneously output pixel signals from all horizontal signal lines even in the thinning mode. In addition, the thinning-out in the modification may be 1 / α.

  As described above, when reading is performed every α using m horizontal signal lines, m pixels arranged in the same color at a distance apart from each other are arranged in different horizontal directions. What is necessary is just to be connected to a signal line.

  In the first and second embodiments, in both the thinning mode and the first and second thinning modes, the pixel signals for two colors that are simultaneously read out are thinned at the same rate, for example, 1/2 or Although it is performed at 1/4, it is also possible to make it separate. For example, it is possible to perform one thinning at 1 / α and the other thinning at 1 / γ.

  In the second embodiment, every fourth reading is performed in the second thinning mode. However, any number of readings may be performed regardless of the first thinning mode. That is, in the case where reading is performed every β for every color of each column, the above-described configuration enabling the first thinning mode has four pixels lined up apart from each other by β in the same color pixels. It is sufficient to add a configuration in which are connected to different horizontal signal lines.

  In the imaging devices of the first and second embodiments, pixel signals are output from the R pixels and the G pixels in all odd rows in the thinning mode and the first and second thinning modes. It is also possible to output only one of the R and G pixels in the odd rows. Similarly, it is possible to output only one of the G pixels and B pixels in each even-numbered row.

  In the first and second embodiments, thinning is performed for each column. However, thinning may be performed for each row in the thinning mode and the first and second thinning modes. For example, the pixel signal may be output from the pixels in the first and second rows, and the output of the pixel signal from the pixels in the third and fourth rows may be thinned out. Row thinning is possible by leaving the row selection transistor of the row to be thinned off.

  In the first and second embodiments, each pixel is covered with a color filter. However, the present invention can also be applied to an image sensor that does not cover a pixel with a color filter. Further, although the color filters are arranged in the Bayer system, the same effects as in the present embodiment can be exhibited even if they are arranged in a complementary color checkered difference line sequential system.

  In addition, although the image pickup device in the first and second embodiments is a CMOS solid-state image pickup device, it can also be applied to a conventionally known XY address type image pickup device.

  In addition, the image sensor in the first and second embodiments is an image sensor that outputs a two-dimensional pixel signal, but can be applied to a line sensor that outputs a one-dimensional pixel signal.

  Next, an image signal processing apparatus to which the first embodiment of the present invention is applied will be described with reference to FIG. FIG. 22 is a block diagram showing a configuration of an image pickup apparatus having the image pickup element to which the first embodiment is applied and the image signal processing apparatus of the present embodiment.

  The imaging device 40 includes the imaging device 10 and the image signal processing device 30. The image signal processing device 30 includes an A / D converter 31, a digital signal processor (DSP) 32, a RAM 33, and a CPU 34.

The A / D converter 31 is an output bus for each of the first to first 4 and second to first 4 horizontal signal lines 15 _U1 to 15 _U4 and 15 _D1 to 15 _D4 of the image sensor 10. (Not shown). The pixel signal output from the image sensor 10 is A / D converted by the A / D converter 31 and converted into a digital signal.

  The A / D converter 31 is connected to the DSP 32. The DSP 32 is connected to the RAM 33. The pixel signal converted into a digital signal in the A / D converter 31 is output to the DSP 32. The pixel signal output to the DSP 32 is stored in a RAM 33 that is a working memory. Note that, when the pixel signal is stored in the RAM 33, an array process described later is performed.

  The pixel signal stored in the RAM 33 is output to the DSP 32 again, and predetermined signal processing such as white balance, complement processing, and γ correction is performed. The pixel signal that has undergone predetermined signal processing is D / A converted and then output to an LCD monitor (not shown) to display an image corresponding to the pixel signal. Further, the pixel signal that has undergone predetermined data processing is stored in a storage medium such as a memory card (not shown).

The CPU 34 is connected to the image sensor 10 and the DSP 32. The CPU 34 controls the entire image pickup apparatus 40. For example, the CPU 34 controls the operations of the vertical shift register 12 and the first and second horizontal shift registers 14 _D and 14 _U and the processing of the arrangement described later.

  An array process when storing pixel signals in the RAM 33 will be described. In the RAM 33, an area to be stored for each pixel signal corresponding to each pixel 20 arranged in the imaging unit 11 is determined. In addition, the region for defining each pixel signal is determined separately in the all input mode (see FIG. 23) and the thinning mode (see FIG. 24).

  As shown in FIG. 23, all input mode storage areas WA of the RAM 33 are areas WRA1 and WGA1 for storing pixel signals output from the R pixel and G pixel in the first row, and the G pixels and B pixels in the second row. Regions WGA2 and WBA2 for storing pixel signals output from are determined. An area for storing pixel signals is also determined for the third and subsequent rows. In each row, an area for storing all the pixel signals is determined in order.

  As shown in FIG. 24, the thinning mode storage area TOA of the RAM 33 is different from the all input mode storage area WA, and in each row, areas for storing every second pixel signal are determined in order (TORA1, TOGA1, TOGA2, See TOBA2, ...).

  As shown in FIGS. 6, 8, 10, and 12, the DSP 32 receives a pixel signal of 4 pixels for each color at the same timing via the A / D 31 converter. Based on the combination of the output timing and the output horizontal signal line, the input pixel signal is stored in a predetermined area of the RAM 33.

For example, in the all-output mode, the first 1, first 2, first 3, and first 4 horizontal signal lines 15 _D1 , 15 _D2 , 15 at the timing t1 ₍₁₎ for the first row. _The pixel signals output from _D3 and _15D4 are stored in the areas for R1 ₍₁₎ , R2 ₍₁₎ , R3 ₍₁₎ and R4 _{(1) in} the all input mode confirmation area WA, respectively.

The pixel signals output from the first 1, first 2, first 3, and first 4 horizontal signal lines 15 _{D 1} , 15 _{D 2} , 15 _{D 3} , and 15 _{D 4} at the timing t 2 ₍₁₎ are all It is stored in the area for R8 ₍₁₎ , R7 ₍₂₎ , R6 ₍₃₎ , R5 _{(4) in} the input mode confirmation area WA. The same applies to other timings for outputting pixel signals from the R pixels in the first row.

  For the second to second horizontal signal lines as well, the pixel signal output from the G pixel is stored in an area defined in the all input mode storage area WA in accordance with the output timing.

In the thinning mode, the first 1, first 2, first 3, and first 4 horizontal signal lines 15 _D1 , 15 _D2 , 15 at the timing t1 ′ ₍₁₎ for the first row. _D3, 15 respectively are pixel signals are output from _D4, R1 in the thinning mode storage area _{TOA (1), R7 (1} ), R3 (1), is stored in the area for R5 _(1).

  The effects of the image signal processing device 30 of the present embodiment having the above-described configuration will be described in comparison with the case where a conventional image sensor and image signal processing device are used. For the sake of simplicity, the description will be made assuming that only the conventional single color pixel and R pixel are used.

As described above, the conventional image pickup device 10 ', the entire input mode, i.e. the mode for switching the output of the pixel signals to the first output line 18 _a, 1 to 4 column constituting the first pixel group in the first row The pixels 20 ′ ₍₁ , _{1) to} 20 ′ ₍₁ , ₄₎ are connected to the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ of ₁ to ₄ in the order of the columns.

Also, the horizontal signal lines 15 ′ ₁ to 15 ′ of ₁ to 4 in the order of the columns of the pixels 20 ′ ₍₁ , _{5) to} 20 ′ ₍₁ , _{8) of} the _{fifth to} eighth columns constituting the second pixel group are also included. 'Connected to ₄ .

Similarly, the four pixels constituting each pixel group in the first row are connected to the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ of ₁ to 4 in the order in which the columns are arranged. Similarly, the four pixels constituting each pixel group in each row are also connected to the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ in the order in which the columns are arranged.

Therefore, in the all input mode, the pixel signal output from _one horizontal signal line 15 ′ ₁ is R1 ₍₁₎ , R5 ₍₁₎ ,..., R (4 × p−3) _{( It} may be stored in the area for ₁₎ in order. Similarly, pixel signals output from the _two horizontal signal lines 15 ′ ₂ are R2 ₍₁₎ , R6 ₍₁₎ ,..., R (4 × p−2) _{(1) in} the all input mode storage area WA. It suffices to store them sequentially in the areas.

Similarly, the pixel signals output from the _three horizontal signal lines 15 ′ ₃ are R3 ₍₁₎ , R7 ₍₁₎ ,..., R (4 × p−1) _{(1) in} the all input mode storage area WA. It suffices to store them sequentially in the areas. Similarly, the pixel signals output from the _four horizontal signal lines 15 ′ ₄ are regions for R4 ₍₁₎ , R8 ₍₁₎ ,..., R (4 × p) _{(1) in} the all input mode storage region WA. May be stored in order.

Further, the conventional image pickup device 10 ', the thinning mode, i.e. in the mode for switching the output of the pixel signal to the second output line 18 _b, 4 pixels 20 which are arranged apart every third in the first row of pixels' _{( 1} , ₁₎ , 20 ′ ₍₁ , ₃₎ , 20 ′ ₍₁ , ₅₎ , 20 ′ ₍₁ , ₇₎ are in order 1st 1, 1st 2, 1st 3, 1st 4 horizontal signal lines 15 ' _D1 , 15' _D2 , 15 ' _D3 , 15' _D4 .

Similarly, four pixels arranged at intervals of two in the first row are connected to the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ of ₁ to 4 in the order in which the columns are arranged. Similarly, four pixels arranged at intervals of two in each row are also connected to the horizontal signal lines 15 ′ ₁ to 15 ′ ₄ of 1-4.

Therefore, in the thinning mode, pixel signals output from _one horizontal signal line 15 ′ ₁ are R1 ₍₁₎ , R9 ₍₁₎ ,..., R (8 × p−7) ₍₁ ) in all input mode storage areas WA. _{) In} order in the area for. Similarly, pixel signals output from the _two horizontal signal lines 15 ′ ₂ are R3 ₍₁₎ , R11 ₍₁₎ ,..., R (8 × p−5) _{(1) in} the all input mode storage area WA. It suffices to store them sequentially in the areas.

Similarly, the pixel signals output from the _three horizontal signal lines 15 ′ ₃ are R5 ₍₁₎ , R13 ₍₁₎ ,..., R (8 × p−3) _{(1) in} the all input mode storage area WA. It suffices to store them sequentially in the areas. Similarly, the pixel signals output from the _four horizontal signal lines 15 ′ ₄ are R7 ₍₁₎ , R15 ₍₁₎ ,..., R (8 × p−1) _{(1) in} the all input mode storage area WA. It suffices to store them sequentially in the areas.

  On the other hand, in the imaging device 10 to which the first embodiment is applied, the pixel signals output to the first to first four horizontal signal lines are not in the column order in which the pixels are arranged. Therefore, when storing in the RAM without rearranging, the position of each pixel signal generated in the image sensor differs from the corresponding position on the LCD monitor, so that the captured image cannot be displayed.

  Therefore, according to the image signal processing device 30 of the present embodiment that performs the rearrangement process, the position of the pixel signal output from the image sensor 10 to which the first embodiment is applied and the position corresponding to the LCD monitor Can be matched.

  Next, an image signal processing apparatus to which the second embodiment of the present invention is applied will be described. The image signal processing apparatus of the present embodiment is an image signal processing apparatus for processing a pixel signal output from the image sensor 100 to which the above-described second embodiment is applied, and is a pixel signal in the second thinning mode. This is different from the first embodiment in that the RAM is further provided with an area for storing the. The description will focus on the differences from the image signal processing apparatus of the first embodiment.

  As shown in FIG. 25, the second thinning mode storage area TOA ′ of the RAM 33 is different from the all input mode storage area WA and the first thinning mode storage area TOA, and every fourth pixel signal is sequentially output in each row. The storage area is determined (see TORA′1, TOGA′1, TOGA′2, TOBA′2,...).

  As in the first embodiment, the input pixel signal is stored in a predetermined area of the RAM 33 based on the combination of the output timing in the second thinning mode and the output horizontal signal line.

For example, from the first 1, first 2, first 3, and first 4 horizontal signal lines 15 _D1 , 15 _D2 , 15 _D3 , and 15 _D4 at the timing of t1 ″ ₍₁₎ for the first row. The output pixel signals are stored in the areas for R1 ₍₁₎ , R9 ₍₁₎ , R13 ₍₁₎ , R5 ₍₁₎ in the second thinning mode storage area TOA ′.

  Therefore, according to the image signal processing device of the present embodiment, the pixel signal output from the image sensor 100 to which the second embodiment is applied can be matched with the position corresponding to the pixel signal.

  Note that the image signal processing apparatuses of the first and second embodiments perform signal processing of pixel signals output from the imaging elements of the first and second embodiments, respectively. When the number of thinning-out in m thinning-out mode is 1 / α, storage areas in the all-input mode and the thinning-out mode are determined in the RAM according to the combination of connection between each pixel and each horizontal signal line. What is necessary is just to make it the structure which arranges a pixel signal, when a signal is input.

1 is a configuration diagram schematically illustrating an overall configuration of a CMOS solid-state imaging device to which a first embodiment of the present invention is applied. It is a circuit diagram which shows the structure of the pixel in an imaging part. FIG. 3 is a circuit diagram showing connections between R pixels, G pixels, and B pixels arranged in 1 to 4 rows and 1 to 16 columns to first and second horizontal signal line groups in the first embodiment. . 6 is a timing chart for explaining an operation until a pixel signal is sampled and held in the first and second CDS / SH circuits. 6 is a first timing chart for explaining the operation of the first and second column selection transistors in the full output mode of the image sensor of the first embodiment. FIG. 6 is a diagram for describing pixel signals output from each horizontal signal line at each timing in the timing chart of FIG. 5. 6 is a second timing chart for explaining the operation of the first and second column selection transistors in the full output mode of the image sensor of the first embodiment. FIG. 8 is a diagram for explaining a pixel signal output from each horizontal signal line at each timing in the timing chart of FIG. 7. 6 is a first timing chart for explaining the operation of the first and second column selection transistors in the thinning mode of the image sensor of the first embodiment. It is a figure for demonstrating the pixel signal output from each horizontal signal line in each timing of the timing chart of FIG. 6 is a second timing chart for explaining the operation of the first and second column selection transistors in the thinning mode of the image sensor of the first embodiment. It is a figure for demonstrating the pixel signal output from each horizontal signal line in each timing of the timing chart of FIG. It is a figure for demonstrating the effect which the image sensor of 1st Embodiment has. The circuit diagram which shows the connection between R pixel and G pixel which are arrange | positioned in the odd-numbered column to 1st-31st column of the 1st and 2nd row in 1st Embodiment, and the 1st, 2nd horizontal signal line group. It is. 12 is a timing chart for explaining the operation of the first and second column selection transistors in the full output mode of the image sensor of the second embodiment. FIG. 16 is a diagram for describing pixel signals output from each horizontal signal line at each timing in the timing chart of FIG. 15. 12 is a timing chart for explaining the operation of the first and second column selection transistors in the first thinning mode of the image sensor of the second embodiment. It is a figure for demonstrating the pixel signal output from each horizontal signal line in each timing of the timing chart of FIG. 12 is a timing chart for explaining the operation of the first and second column selection transistors in the second thinning mode of the image sensor of the second embodiment. It is a figure for demonstrating the pixel signal output from each horizontal signal line in each timing of the timing chart of FIG. It is a circuit diagram which shows the connection between the R pixel, G pixel, and B pixel which were arranged in 1-4 rows and 1-16 columns of the image pick-up element of the modification of 1st Embodiment, and a vertical signal line group. . It is a block diagram which shows the structure of the imaging device which has an image sensor to which the first embodiment is applied and an image signal processing device to which the first embodiment is applied. It is a figure which shows the area | region which stores the pixel signal for the time of all the input modes in RAM of the image signal processing apparatus of 1st Embodiment. It is a figure which shows the area | region which stores the pixel signal for the time of the thinning mode in RAM of the image signal processing apparatus of 1st Embodiment. It is a figure which shows the area | region which stores the pixel signal for the time of the 2nd thinning-out mode in RAM of the image signal processing apparatus of 2nd Embodiment. It is a figure which shows the structure of the conventional image pick-up element for demonstrating the background art of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,100 CMOS solid-state image sensor 12 Vertical shift register 13 _D , 13 _U 1st, 2nd correlation double sampling / sample hold (CDS / SH) circuit 14 _D , 14 _U 1st, 2nd horizontal shift register 15 _D , 15 _U first and second horizontal signal line groups 15 _D1 to 15 _D4 first to first four horizontal signal lines 15 _U1 to 15 _U4 second to first four horizontal signal lines _16D , _16U first and second column selection switch sections _{16D (h)} , _{16U (h)} first and second h column selection transistors _{17D (h)} , _{17U (h)} First and second vertical signal lines 20, 20 _(g , _h) pixels 26 _(g , _h) g row selection transistors 30 image signal processing device 31 A / D converter 32 digital signal processor (DSP)
33 RAM
34 CPU
40 Imaging device

Claims (7)

Outputting a first color pixel signal corresponding to the amount of received light of the first color received on the light receiving surface, and a plurality of first color pixels arranged on a predetermined array line;
Outputting a second color pixel signal corresponding to the amount of received light of a second color different from the first color received by the light receiving surface, and a plurality of second color pixels arranged on the array line;
And read lines of the first color of the 1 first color m for reading said first color pixel signal,
A first switching means for switching the ON · OFF of the output of said first color pixel, the first color pixel signal from each
Switching control means for switching ON / OFF of the first switching means,
Said sequence plurality of the first line, a plurality of the first color pixel in the second color pixel is divided every m pieces of said first color pixels arranged in a row in the first color pixel, a plurality Forming a first color pixel group,
The first color pixel is connected to the other of said first color pixels forming the same said first color pixel group in either the first color 1 read lines of the first color m Connected to a different readout line from the readout line,
The first color reference pixel which is the first color pixel arranged at a predetermined position on the array line is separated from the first color reference pixel by α in the first color pixel (m−1). and pieces of the first color pixel, in any of the first color 1 read lines of the first color of m, are connected to different read lines respectively,
Said switching control means, the first arranged on the light receiving surface, the full output mode to be output pixel No. signal corresponding to the received light amount from the total pixels including a second color pixels of each of the first color pixel group wherein from the first color pixel to oN the output of the first color pixel signal, wherein the first color output of 1 / alpha overall plurality of said first color pixels aligned in the arrangement line of the first color pixel signal the first of the decimation mode away from the first color reference pixel and the first color reference pixels by α or in the first color pixel (m-1) and the number of the first color pixel to be output from the pixel The first switching means is driven so as to turn on the output of the first color pixel signal from the image sensor. Wherein a first color reference pixel, the remote from the first color reference pixels by β cells in the first color pixel and the (m-1) number of the first color pixel, the first color 1 of One of the m readout lines of the first color , each connected to a different readout line;
It said switching control means, said output of the first color pixel signal to a second decimation mode to output from said first color pixels of 1 / beta overall plurality of said first color pixels aligned in the arrangement line of the first The output of the first color pixel signal from the (m−1) first color pixels that are separated by β in the first color pixel from the color reference pixel and the first color reference pixel is turned ON. The image pickup device according to claim 1 , wherein the first switching unit is driven as described above. It said plurality of first, second color pixels, the image pickup device according to claim 1 or claim 2, wherein the Turkey arranged alternately in the sequence line. Before SL and read lines of the second color of 1 second color n for reading the second color pixel signals, the ON · OFF of the output of said second color pixel signals from each of the plurality of second color pixel Second switching means for switching,
A plurality of said first pre-Symbol sequence line, a plurality of said second color pixels in the second color pixel is divided for each n-number of pixels arranged in a row in said second color pixels, a plurality of second Forming color pixel groups,
The second color pixel is connected to another second color pixel forming the same second color pixel group in any one of the first to second read lines of the second color. Connected to a different readout line from the readout line,
A second color reference pixel which is the second color pixel arranged at a predetermined position on the array line, and is separated from the second color reference pixel by γ in the second color pixel (n−1). and number of the second color pixel is based on any one of the second color of 1 to read lines of the second color of n, are connected to different read lines respectively,
The switching control means turns on the output of the second color pixel signal from the second color pixel for each second color pixel group in the full output mode, and the second color reference in the first thinning mode. The output of the second color pixel signal from the (n−1) second color pixels that are separated by γ in the second color pixel from the pixel and the second color reference pixel is turned on. imaging device according to any one of claims 1 to 3, characterized in that for driving the second switching means. Said first color 1 first color reading free reading means said first color pixel signal outputted from the read line of m of the imaging device according to claim 1,
The area for storing the first color pixel signal output from each of the plurality of first color pixels in total output mode is defined, the first of said first color and said first color reference pixels in the thinning mode An area for storing the first color pixel signal output from each of the (m−1) first color pixels separated by α pieces from the reference pixel in the first color pixels is determined, and Storage means for storing the first color pixel signal read by the reading means;
Wherein the total output mode based on the combination of connection between the plurality of first color pixel and the read line of 1 to the first color of m of the first color, the output from each of the plurality of first color pixel The first color pixel signal is stored in a predetermined area of the storage means, and in the first thinning mode, the first to first color m readout lines and the first color reference pixel and wherein the first color reference pixel away α or each in the first color pixel (m-1) based on the combination of connections with pieces of the first color pixel, the first color reference pixel and sequence for storing said first color pixel signal output from each of said first color pixel away α or each in the from said first color reference pixel first color pixel area defined of said storage means An image signal processing apparatus. It said reading means reads the first color pixel signal outputted from the read line of the first color to third one-color m of the imaging device according to claim 2,
In the second thinning mode, the storage means stores the first color reference pixel and the (m−1) pieces of the first color reference pixels separated from the first color reference pixel by β in the first color pixel . and area for storing said first color pixel signal output from each is defined between the color pixels,
Said sequence means, said the second thinning mode in the read line and said first color reference pixel and the first color to the reference pixel of 1 to the first color of m of said first color of said first color pixel Based on the combination of connections with the (m−1) first color pixels that are separated by β, the first color reference pixel and the first color reference pixel among the first color pixels are β The image signal processing apparatus according to claim 5, wherein the first color pixel signal output from each of the first color pixels separated from each other is stored in a predetermined region of the storage unit.   An imaging device comprising: the imaging device according to claim 1; and the image signal processing device according to claim 5.

Images