JP6439996B2 - Solid-state imaging device and electronic device - Google Patents

Description

  The present technology relates to a solid-state imaging device and an electronic device, and in particular, a solid-state imaging device capable of ensuring the simultaneity of the entire image and reducing the influence of noise due to signal leakage in the image sensor, And electronic devices.

  In recent years, CMOS image sensors have been widely used as image sensors. However, since CMOS image sensors are generally read sequentially for each pixel, it is not possible to achieve simultaneity of the entire image.

  That is, in the CMOS image sensor, an operation of sequentially scanning and reading out the photoelectric charges generated and accumulated in the photoelectric conversion unit for each pixel or for each row is performed. In the case of this sequential scanning, that is, when a rolling shutter is employed as the electronic shutter, the exposure start time and the end time for accumulating photocharges cannot be made to coincide for all pixels. Therefore, in the case of sequential scanning, there is a problem that a captured image is distorted when a moving subject is imaged.

  In sensing applications that require high-speed moving subject imaging and this type of image distortion that cannot be tolerated, as well as sensing applications that require simultaneous image capture, exposure is started at the same timing for all pixels in the pixel array. A global shutter that executes the end of exposure is employed.

  A global shutter device, which is a device that employs a global shutter as an electronic shutter, is provided with a charge storage unit such as a semiconductor memory in a pixel. In a device that employs a global shutter, electric charges are simultaneously transferred from a photodiode to a semiconductor memory, stored, and then sequentially read to ensure the simultaneity of the entire image.

  In addition, a light receiving surface buried region that is buried in a part of the upper portion of the semiconductor region, and a light receiving surface buried region is buried in a part of the upper portion of the semiconductor region, and the depth of the potential well is larger than that of the light receiving surface buried region. A device having a deep charge storage region for storing signal charges generated by the light receiving surface buried region has also been proposed (see, for example, Patent Document 1).

  In a CMOS image sensor that employs a global shutter, signal charges generated by the light receiving surface buried region are completely transferred to the charge storage region at the same time for all pixels, and then sequentially transferred to the charge readout region for reading. Here, for example, if light is received by a high-brightness object during charge holding, a signal leaks from the light receiving surface embedded region to the charge reading region, resulting in noise.

  For this reason, in a device employing a global shutter, it is important to take measures against noise due to signal leakage. In the technique of Patent Document 1, a light-shielding film is selectively formed on the charge storage region in order to prevent light from leaking into the charge storage region and adding a signal while the signal charge is held in the charge storage region. Is provided.

JP 2011-204878 A

  However, it is known that the output of the light receiving surface embedded region depends on the wavelength and the incident angle of incident light, and becomes, for example, a large value in the order of increasing wavelength.

  For example, when the technique of Patent Document 1 is used, a signal is read for each row of pixels, and thus, for example, RG rows and BG rows are read alternately. Therefore, the retention time of each color becomes equal in the same line. In this case, there is a problem that the magnitude of noise differs for each color depending on the wavelength and the incident angle of incident light.

  Further, considering the influence of noise due to leakage of signals during charge holding, it is desirable that the holding time is the same for pixels at any position in the screen.

  However, the conventional technique has a problem that the difference in holding time between the first read line and the last read line becomes too large.

  The present technology is disclosed in view of such a situation, and is intended to ensure the simultaneity of the entire image and reduce the influence of noise due to signal leakage in the image sensor. .

A solid-state imaging device according to a first aspect of the present technology includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region. , and a plurality of trigger wires provided corresponding to the pixel row of the pixel region, the plurality of trigger wires comprise a first trigger wires and the second trigger wires, the first trigger wires Is connected to a first red pixel in the pixel region, and the second trigger line is connected to a first green pixel provided in the same row as the first red pixel, Each pixel has a light receiving portion and a floating diffusion for each pixel , and the signal charges generated by the light receiving portion are supplied to the floating diffusion through a charge accumulation region.
A solid-state imaging device according to a second aspect of the present technology includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region. A plurality of trigger lines provided corresponding to the pixel rows of the pixel region, the plurality of pixels each having a light receiving portion and a floating diffusion, and the floating diffusion includes a charge The signal charges generated by the light receiving unit are supplied through the storage region, and the plurality of vertical signal lines include a first vertical signal line and a second vertical signal line, and the pixel region includes A first pixel group and a second pixel group that are formed by four adjacent pixels are provided, and the four pixels that form the first pixel group share the first vertical signal line, and the second pixel group. The four pixels forming the same share the second vertical signal line, and Wherein the first pixel group a second group of pixels are provided adjacent to the vertical direction.
A solid-state imaging device according to a third aspect of the present technology includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and a plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region. A plurality of trigger lines provided in correspondence with the pixel rows of the pixel region and a plurality of gate electrodes provided in the pixel region, wherein the plurality of pixels include a plurality of light receiving units and a plurality of floating devices. Each of the plurality of pixels includes the light receiving unit, and each of the plurality of floating diffusions includes a first floating diffusion and a second floating diffusion. The gate electrode includes a first gate electrode and a second gate electrode, and the first floating diffusion is generated by the light receiving unit according to a potential supplied to the first gate electrode. The second floating diffusion receives the charge generated by the light receiving unit according to the potential supplied to the second gate electrode, and the plurality of vertical signal lines are The first pixel group and the second vertical signal line are provided, and the pixel region includes a first pixel group and a second pixel group each including four adjacent pixels, and the first pixel group. 4 pixels that share the first vertical signal line, and the four pixels that form the second pixel group share the second vertical signal line, and the second pixel group and the second pixel group. Are provided adjacent to each other in the vertical direction, the first floating diffusion is connected to the first vertical signal line, and the second floating diffusion is connected to the second vertical signal line. It is connected to the.

An electronic device according to a fourth aspect of the present technology is an electronic device in which a solid-state image sensor is mounted. The solid-state image sensor includes a pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and the pixel region. a plurality of vertical signal lines provided corresponding to the pixel columns of a plurality of trigger wires provided corresponding to the pixel row of the pixel region, the plurality of trigger lines, a first trigger wires And the second trigger line, wherein the first trigger line is connected to a first red pixel in the pixel region, and the second trigger line is in the same row as the first red pixel. Each of the plurality of pixels has a light receiving portion and a floating diffusion for each pixel , and the floating diffusion includes the light receiving portion via a charge storage region. signal charge is supplied tHAT generated
An electronic device according to a fifth aspect of the present technology is an electronic device in which a solid-state image sensor is mounted, in which the solid-state image sensor includes a pixel area in which a plurality of pixels are arranged in a two-dimensional matrix, and the pixel area A plurality of vertical signal lines provided corresponding to the pixel columns and a plurality of trigger lines provided corresponding to the pixel rows of the pixel region, the plurality of pixels including a light receiving unit for each pixel. The floating diffusion is supplied with signal charges generated by the light receiving unit via a charge storage region, and the plurality of vertical signal lines includes a first vertical signal line and a first vertical signal line. 2 vertical signal lines, and in the pixel region, a first pixel group and a second pixel group each including four adjacent pixels are provided, and the four pixels constituting the first pixel group are Sharing the first vertical signal line, The four pixels constituting a pixel group, the second share vertical signal line, the first pixel and the second pixel group and the group is provided adjacent to the vertical direction.
An electronic apparatus according to a sixth aspect of the present technology is the electronic apparatus in which a solid-state image sensor is mounted. The solid-state image sensor includes a pixel area in which a plurality of pixels are arranged in a two-dimensional matrix, and the pixel area. A plurality of vertical signal lines provided corresponding to the pixel columns, a plurality of trigger lines provided corresponding to the pixel rows of the pixel region, and a plurality of gate electrodes provided in the pixel region. The plurality of pixels have a plurality of light receiving portions and a plurality of floating diffusions, the plurality of pixels have the light receiving portions for each pixel, and the plurality of floating diffusions have a first floating state. A plurality of gate electrodes including a first gate electrode and a second gate electrode, wherein the first floating diffusion comprises: a diffusion and a second floating diffusion; The second floating diffusion receives the electric charge generated by the light receiving unit according to the potential supplied to the first gate electrode, and the second floating diffusion receives the light received according to the potential supplied to the second gate electrode. The plurality of vertical signal lines include a first vertical signal line and a second vertical signal line, and the pixel region includes a first pixel including four adjacent pixels. A pixel group and a second pixel group are provided. The four pixels forming the first pixel group share the first vertical signal line, and the four pixels forming the second pixel group are the second pixel group. The first pixel group and the second pixel group are provided adjacent to each other in the vertical direction, and the first floating diffusion is connected to the first vertical signal line. And the second floating diffusion is the second floating diffusion. It is connected to a vertical signal line.

  According to the present technology, it is possible to ensure the simultaneity of the entire image and reduce the influence of noise caused by signal leakage in the image sensor.

It is a figure explaining the structural example of the pixel of the CMOS image sensor which employ | adopts a global shutter. It is a figure explaining the magnitude | size of the noise according to the color of the pixel in the conventional CMOS image sensor. It is a figure explaining the holding | maintenance time of the electric charge of the pixel of each row in the pixel array in which the pixel was arranged in matrix form. It is a block diagram showing an example of composition of a solid imaging device to which this art is applied. It is a figure which shows the example of arrangement | positioning of the pixel in a pixel array. It is a figure explaining the example of a pixel signal generation in an up-and-down reading system. It is a figure explaining the retention time of each pixel at the time of applying this art. It is a figure explaining the magnitude | size of the noise according to the color of the pixel in the CMOS image sensor to which this technique is applied. It is a figure explaining the example of the holding time of each pixel at the time of making it read out a pixel from the center line. It is a block diagram which shows the structural example of an imaging device.

  Hereinafter, embodiments of the technology disclosed herein will be described with reference to the drawings.

  First, problems associated with a CMOS image sensor employing a conventional global shutter will be described.

  FIG. 1 is a diagram illustrating a configuration example of pixels of a CMOS image sensor that employs a global shutter. This figure is a cross-sectional view of a semiconductor element constituting a pixel of a CMOS image sensor.

  As shown in the figure, the semiconductor element includes a first conductivity type (p-type) semiconductor region 1 and a second conductivity type (n-type) that is embedded in a part of the upper portion of the semiconductor region 1 and receives light. ) Of the light receiving surface embedded region (also referred to as a light receiving cathode region as appropriate) 11a. The second conductive layer is embedded in a part of the upper portion of the semiconductor region 1 at a distance from the light receiving cathode region 11a, has a higher impurity density than the light receiving cathode region 11a, and accumulates signal charges generated by the light receiving cathode region 11a. A type (n + -type) charge storage region 12a is provided. Furthermore, a charge readout region 13 for receiving the signal charge accumulated by the charge accumulation region 12a is provided.

  In this example, the case where a first conductivity type semiconductor substrate is used as an example of the “first conductivity type semiconductor region” is illustrated, but the first conductivity type semiconductor region is formed on the first conductivity type semiconductor substrate instead of the semiconductor substrate. A silicon epitaxial growth layer of the first conductivity type having a lower impurity density than the semiconductor substrate may be employed.

  The light receiving cathode region 11a and the semiconductor substrate (anode region) 1 immediately below the light receiving cathode region 11a constitute a photodiode D1. A charge storage diode D2 is configured by the charge storage region (cathode region) 12a and the semiconductor substrate (anode region) immediately below the charge storage region 12a.

  A p + type pinning layer 11b is disposed on the light receiving cathode region 11a. A p + -type pinning layer 12b is disposed on the charge storage region 12a. The p + -type pinning layer 11b and the p + -type pinning layer 12b are layers that suppress the generation of carriers on the dark surface, and are used as preferred layers for reducing dark current. If dark current is not a problem, the p + -type pinning layer 11b and the p + -type pinning layer 12b may be omitted from the structure.

  On the p + -type pinning layer 11b and the p + -type pinning layer 12b, on the semiconductor substrate between the p + -type pinning layer 11b and the p + -type pinning layer 12b, and the light receiving cathode region 11a and the charge readout region 13 An insulating film 2 is formed on the semiconductor substrate. The insulating film 2 is preferably a silicon oxide film (SiO2 film), but has an insulated gate structure of an insulated gate transistor (MIS transistor) using various insulating films other than the silicon oxide film (SiO2 film). Also good. For example, an ONO film composed of a three-layered film of silicon oxide film (SiO2 film) / silicon nitride film (Si3N4 film) / silicon oxide film (SiO2 film) may be used. Furthermore, at least one element of strontium (Sr), aluminum (Al), magnesium (Mg), yttrium (Y), hafnium (Hf), zirconium (Zr), tantalum (Ta), and bismuth (Bi) is contained. An oxide containing or silicon nitride containing these elements can be used as the insulating film 2.

  On the insulating film 2, the transfer of the signal charge from the light receiving cathode region 11a to the charge storage region 12a is controlled by controlling the potential of the first transfer channel formed between the light receiving cathode region 11a and the charge storage region 12a. A gate electrode 31 is disposed and constitutes a first potential control means. Further, the signal charge is transferred from the charge accumulation region 12 a to the charge readout region 13 by controlling the potential of the second transfer channel formed between the charge accumulation region 12 a and the charge readout region 13 on the insulating film 2. The read gate electrode 32 is arranged to constitute second potential control means.

  The charge readout region 13 is connected to the gate electrode of a signal readout transistor (amplification transistor) MA1 constituting the readout buffer amplifier 20. The drain electrode of the signal readout transistor (amplification transistor) MA1 is connected to the power supply VDD, and the source electrode is connected to the drain electrode of the pixel selection switching transistor MS1.

  The source electrode of the pixel selection switching transistor MS1 is connected to the vertical signal line B1, and the horizontal line selection control signal S is applied to the gate electrode. By making the selection control signal S high (H) level, the switching transistor MS1 becomes conductive, and a current corresponding to the potential of the charge reading region 13 amplified by the signal reading transistor (amplifying transistor) MA1 is applied to the vertical signal line B1. Flowing into.

  The charge readout region 13 is connected to the source electrode of the reset transistor TR constituting the read buffer amplifier 20. The drain electrode of the reset transistor TR is connected to the power supply VDD, and the reset signal R is given to the gate electrode. The reset signal is set to a high (H) level, the signal charges accumulated in the light receiving cathode region 11a and the charge accumulation region 12a are discharged, and the light receiving cathode region 11a and the charge accumulation region 12a are reset.

  By the way, if the accumulation time from when the photocharge is read out from the photodiode simultaneously to all pixels is output to the floating diffusion capacitor (FD) is different, the accumulation time becomes longer and the smear component for the signal component is the main component. The amount of noise to be increased.

  As shown in FIG. 1, in a CMOS image sensor employing a global shutter, a charge accumulation region 12a is provided for each pixel. In the charge accumulation region 12a, for example, when light is received from a high-luminance subject within a period in which the charge is held, a signal leaks from the light receiving surface embedded region 11a to the charge accumulation region 12a, and noise is generated. . At this time, when the subject moves, noise (hereinafter referred to as locus-like noise) is generated in a locus shape where the subject moves. The noise magnitude P is defined by equation (1).

・・・（１）

... (1)

  In Expression (1), H and M represent the output of the light receiving surface buried region 11a and the output of the charge storage region 12a per unit time and unit luminance, respectively. Th and Tm represent the accumulation time (exposure time) of the light receiving surface buried region 11a and the holding time of the charge accumulation region 12a.

  Here, M (output of the charge storage region 12a) in the formula (1) is dependent on the wavelength dependency and the incident angle of incident light, and is known to increase in order of increasing wavelength for the following reason. ing.

  That is, since the light absorption coefficient of silicon differs depending on the wavelength of light, photoelectric conversion occurs at a location deeper on the long wavelength side, and as a result, photoelectric conversion occurs at a location other than the light receiving surface embedded region 11a on the long wavelength side. This is because conversion tends to occur.

  Further, the longer the wavelength of light, the larger the diffraction angle, and as a result, light easily enters the charge storage region 12a.

  Thus, since M in Equation (1) becomes a large value in the order of longer wavelengths, for example, in the case of a pixel with a Bayer array, normally, the noise magnitude P also increases in the order of R, G, and B. .

  FIG. 2 is a diagram for explaining the magnitude of noise corresponding to the color of a pixel in a conventional CMOS image sensor. In the example shown in the figure, the magnitude of noise is represented by a bar graph for each pixel color. Since the magnitude of noise is expressed in dB, the magnitude of noise becomes smaller as the height of the bar graph increases. As shown in FIG. 2, the red (R) pixel has the largest noise, followed by green (G) and blue (B).

  In the figure, GB denotes a green pixel arranged in the same row as a blue pixel in a pixel array in which pixels are arranged in a matrix, and GR in the figure denotes a pixel array in which pixels are arranged in a matrix. Means a green pixel arranged in the same row as the red pixel.

  Also, assuming that the total number of rows of pixels arranged in the pixel array is N and the holding time in the charge storage region 12a in the last row is Tl, the holding time Tm in the charge storage region 12a in the nth row is expressed by the formula ( 2).

・・・（２）

... (2)

As can be seen from equation (2), the difference in retention time between the first read line and the last read line increases.
For this reason, Th in equation (1) also varies from line to line.

  FIG. 3 is a diagram for explaining the charge retention time of the pixels in each row in the pixel array in which the pixels are arranged in a matrix. In this figure, the horizontal axis represents time, and the vertical axis represents pixel rows. As shown in FIG. 3, the holding time increases as the reading order becomes later in the first row, the second row,.

  Therefore, it can be seen from the equation (1) that the noise becomes larger in the pixels in the row in which the reading order is later.

  As described above, the conventional CMOS image sensor has a problem that the magnitude of noise varies depending on the color of the pixel, and further, the magnitude of noise varies depending on the reading order.

  Therefore, in the present technology, the noise can be made as small as possible and leveled as much as possible, and the influence of noise caused by signal leakage in the image sensor can be reduced.

  FIG. 4 is a block diagram illustrating a configuration example of a solid-state imaging device to which the present technology is applied. The solid-state imaging device shown in the figure is configured as a CMOS image sensor, for example.

  A CMOS image sensor 110 shown in FIG. 4 includes a pixel array 111 formed on a semiconductor substrate (chip) (not shown) and a peripheral circuit integrated on the same semiconductor substrate as the pixel array 111. Yes. The peripheral circuits include, for example, a vertical drive unit 112, a column processing unit 113, a horizontal drive unit 114, and a system control unit 115.

  The CMOS image sensor 110 is further provided with a signal processing unit 118 and a data storage unit 119. The signal processing unit 118 and the data storage unit 119 may be configured by, for example, an external signal processing unit provided on a substrate different from the CMOS image sensor 110, such as a DSP (Digital Signal Processor). The external signal processing unit can also be realized by processing based on computer-based hardware such as a DSP or CPU and software for controlling the hardware. The external signal processing unit is usually configured to include a memory for realizing the data storage unit 119. The external signal processing unit may be mounted on the same substrate as the CMOS image sensor 110.

  The pixel array 111 is a unit pixel having a photoelectric conversion element that generates photoelectric charges (hereinafter sometimes referred to as “signal charges” or simply “charges”) with a charge amount corresponding to the amount of incident light, and accumulates the photoelectric charges inside. Hereinafter, it may be simply referred to as “pixel”), and is arranged in a two-dimensional array. The basic cross section and circuit configuration of the unit pixel may be, for example, the same configuration as in FIG. 1 or a partially different configuration.

  In the pixel array 111, pixel drive lines 116 are formed in the horizontal direction in the figure (pixel arrangement direction of pixels in the pixel row) for each pixel arranged in a matrix, and a vertical signal line 117 is provided for each column. It is formed in the vertical direction in the figure.

  In FIG. 4, for the sake of convenience, the pixel drive line 116 is shown as a single line, but it is not limited to one in practice. For example, the pixel drive line 116 includes a reset line that applies the reset pulse RST to the gate of the reset transistor and a selection line (scanning line) that applies the selection pulse SEL to the gate of the selection transistor. Furthermore, the pixel drive line 116 also includes a trigger line that supplies a trigger pulse for selectively reading out the signal voltage of the pixels in the same row by being applied together with the selection pulse.

  One end of the pixel drive line 116 is connected to an output end corresponding to each row of the vertical drive unit 112.

  The vertical drive unit 112 is configured by a shift register, an address decoder, and the like, and is a pixel drive unit that drives each pixel of the pixel array 111 simultaneously in a predetermined pixel region (all pixels in this embodiment) or in units of rows. . Although the specific configuration of the vertical driving unit 112 is not illustrated, the vertical driving unit 112 generally has two scanning systems, a reading scanning system and a sweeping scanning system. The readout scanning system and the sweep scanning system are circuits that independently drive scanning lines for each pixel row.

  Unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels in the readout row by sweep scanning by the sweep scanning system. A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge (corresponding to the photodiode 101 in FIG. 2) of the photoelectric conversion element is discarded and exposure is newly started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the previous read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation time (exposure time) in the unit pixel.

  A signal output from each unit pixel of the pixel row selectively scanned by the vertical driving unit 112 is supplied to the column processing unit 113 through each vertical signal line 117. The column processing unit 113 performs predetermined signal processing on signals output from the unit pixels in the selected row through the vertical signal line 117 for each pixel column of the pixel array 111, and temporarily outputs the pixel signals after the signal processing. Hold on.

  Specifically, the column processing unit 113 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing as signal processing. By the CDS processing by the column processing unit 113, pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistor is removed. In addition to the noise removal processing function, the column processing unit 113 may have, for example, an AD (analog-digital) conversion function to convert the signal level into a digital signal and output it.

  The horizontal driving unit 114 includes a shift register, an address decoder, and the like, and selects a unit circuit corresponding to the pixel column of the column processing unit 113. By the selective scanning by the horizontal driving unit 114, the pixel signals subjected to signal processing by the column processing unit 113 are sequentially output.

  The system control unit 115 includes a timing generator that generates various timing signals, and the vertical driving unit 112, the column processing unit 113, the horizontal driving unit 114, and the like based on the various timing signals generated by the timing generator. Drive control is performed.

  The signal processing unit 118 has at least an addition processing function, and performs various signal processing such as addition processing on the pixel signal output from the column processing unit 113. The purpose of the addition processing may be, for example, suppression of random noise by averaging, or addition for other purposes. The data storage unit 119 temporarily stores data necessary for the signal processing in the signal processing unit 118.

  In the example of FIG. 4, the column processing unit 113 and the horizontal driving unit 114 are provided only on the lower side in the drawing. For example, the column processing unit 113 and the horizontal driving unit 114 are respectively provided on each of the upper and lower sides in the drawing. May be provided. That is, the CMOS image sensor 110 may be driven by a so-called vertical readout method.

  By driving the CMOS image sensor 110 using the vertical readout method, for example, signal voltages of red pixels and blue pixels are output to the upper column processing unit, and signal voltages of green pixels are output to the lower column processing unit. Can be output. When the CMOS image sensor 110 is driven by the vertical readout method, two vertical signal lines 117 are provided for each column of pixels.

  In general, a Bayer array is often used as a pixel arrangement method in the pixel array 111. In the Bayer array, a red pixel is arranged in the first row and the first column of the pixels in the second row and the second column, a green pixel is arranged in the first row and the second column, and a green pixel is arranged in the second row and the first column. A blue pixel is arranged in the second row and the second column. That is, in the Bayer array, a set of pixel groups composed of the above-described four pixels (two rows and two columns of red, green, green, and blue) are handled as substantial unit pixels.

  In the pixel array 111 shown in FIG. 4, it is assumed that a Bayer array is adopted, and a set of pixel groups including the four pixels described above is handled as a substantial unit pixel.

  FIG. 5 is a diagram illustrating an arrangement example of pixels in the pixel array 111. The pixel group 131-1, the pixel group 131-2, the pixel group 132-1 and the pixel group 132-2 shown in the figure are a set of pixel groups each composed of the four pixels described above. Treated as a unit pixel. That is, when each pixel group is a substantial unit pixel, the pixel array in FIG. 5 is configured by unit pixels (actually a group of four pixels) arranged in two rows and two columns.

  Here, in order to simplify the description, the arrangement of pixel groups of 2 rows and 2 columns is shown, but in reality, the pixel array 111 is configured by more pixel groups.

  The example shown in the figure is an example in which the vertical readout method is adopted in the CMOS image sensor 110, and the VSL (vertical signal line) 141-1 and the VSL 141-2 are in the first column of the pixel group. VSL 142-1 and VSL 142-2 are provided in the second column of the pixel group. That is, a column processing unit and a horizontal driving unit are provided on the upper side or the lower side of FIG.

  In the pixel group 131-1, the pixel 131-1-1 is a red pixel, the pixel 131-1-2 is a green pixel, the pixel 131-1-3 is a green pixel, and the pixel 131-1. -4 is a blue pixel. A vertically long rectangle 131-1a shown in the figure collectively indicates floating diffusions of the pixels 131-1-1 to 131-1-4.

  Similarly to the case of the pixel group 131-1, the pixel group 131-2, the pixel group 132-1 and the pixel group 132-2 are arranged with red pixels, green pixels, and blue pixels, respectively. Four pixel floating diffusions are collectively shown as one rectangle.

  The floating diffusion 131-1a of the pixel group 131-1 is connected to the VSL 141-2, and the floating diffusion 132-1a of the pixel group 132-1 is connected to the VSL 141-1. In addition, the floating diffusion 131-2a of the pixel group 131-2 is connected to the VSL 142-2, and the floating diffusion 132-2a of the pixel group 132-2 is connected to the VSL 142-1.

  In each Bayer array pixel group, there are two green pixels, one arranged in the same row as the red pixels and one arranged in the same row as the green pixels. When each pixel is simply expressed, a red pixel is indicated by R, a blue pixel is indicated by B, a green pixel in the same row as the red pixel is GR, and a green pixel in the same row as the blue pixel is GB. I will show you.

  Further, as shown in FIG. 5, each of the pixel group 131-1, the pixel group 131-2, the pixel group 132-1, and the pixel group 132-2 is indicated by a reset line RST indicated by a horizontal dotted line in the drawing. And the selection line SEL. Further, each of the pixel group 131-1, the pixel group 131-2, the pixel group 132-1, and the pixel group 132-2 is connected to trigger lines TRG_GR, TRG_R, TRG_B, and TRG_BR indicated by horizontal solid lines in the drawing. Connected.

  The trigger line TRG_GR is a wiring for supplying a trigger pulse to the GR pixels of each pixel group, and the trigger line TRG_R is a wiring for supplying a trigger pulse to the R pixels of each pixel group. The trigger line TRG_B is a wiring for supplying a trigger pulse to the B pixel of each pixel group, and the trigger line TRG_R is a wiring for supplying a trigger pulse to the GB pixel of each pixel group. .

  For example, when the signal of the selection line SEL connected to the pixel group 131-1 and the pixel group 131-2 is set to “H” and the trigger line TRG_GR is set to “H”, the pixel is set via the VSL 141-2 and the VSL 142-2. The signal voltage can be read from 131-1-2 and the pixel 131-2-2. Further, for example, when the signal of the selection line SEL connected to the pixel group 131-1 and the pixel group 131-2 is “H” and the trigger line TRG_R is “H”, the signal passes through the VSL 141-2 and the VSL 142-2. Thus, the signal voltage can be read from the pixel 131-1-1 and the pixel 131-2-1.

  Further, for example, when the signal of the selection line SEL connected to the pixel group 131-1 and the pixel group 131-2 is “H” and the trigger line TRG_B is “H”, the signal passes through the VSL 141-2 and the VSL 142-2. Thus, the signal voltage can be read from the pixel 131-1-4 and the pixel 131-2-4. Further, for example, when the signal of the selection line SEL connected to the pixel group 131-1 and the pixel group 131-2 is “H” and the trigger line TRG_GB is “H”, the signal passes through the VSL 141-2 and the VSL 142-2. Thus, the signal voltage can be read from the pixel 131-1-3 and the pixel 131-2-3.

  For example, when the signal of the selection line SEL connected to the pixel group 132-1 and the pixel group 132-2 is “H” and the trigger line TRG_GR is “H”, the signal passes through the VSL 141-1 and the VSL 142-1. Thus, the signal voltage can be read from the pixel 132-1-2 and the pixel 132-2-2. Further, for example, when the signal of the selection line SEL connected to the pixel group 132-1 and the pixel group 132-2 is “H” and the trigger line TRG_R is “H”, the signal passes through the VSL 141-1 and the VSL 142-1. Thus, the signal voltage can be read from the pixel 132-1-1 and the pixel 132-2-1.

  Furthermore, for example, when the signal of the selection line SEL connected to the pixel group 132-1 and the pixel group 132-2 is “H” and the trigger line TRG_B is “H”, the signal passes through the VSL 141-1 and the VSL 142-1. Thus, the signal voltage can be read from the pixel 132-1-4 and the pixel 132-2-4. For example, when the signal of the selection line SEL connected to the pixel group 132-1 and the pixel group 132-2 is “H” and the trigger line TRG_GB is “H”, the signal passes through the VSL 141-1 and the VSL 142-1. Thus, the signal voltage can be read from the pixel 132-1-3 and the pixel 132-2-3.

  The signal voltage read from the R pixel or B pixel is AD-converted by the upper column processing unit in FIG. 5, and the signal voltage read from the GR pixel or GB pixel is It is assumed that AD conversion is performed by the lower column processing unit in FIG.

  In the present technology, first, the upper selection line SEL in the drawing is set to “H”, the trigger line TRG_R is set to “H”, and the pixel 131-1-1 and the pixel 131-are set via the VSL 141-2 and VSL 142-2. The signal voltage is read from 2-1 to the upper column processing unit in the figure. Thereafter, the selection line SEL on the lower side in the drawing is set to “H”, the trigger line TRG_R is set to “H”, and the pixels 132-1-1 and 132-2 are set via the VSL 141-1 and the VSL 142-1. The signal voltage is read from 1 to the upper column processing unit in the figure. In this way, signal voltages are first read from all R pixels. This will be referred to as a first step, for example.

  In the present technology, next, the upper selection line SEL in the drawing is set to “H”, the trigger line TRG_GR is set to “H”, and the pixels 131-1-2 and the pixel 131-are set via the VSL 141-2 and the VSL 142-2. The signal voltage is read from 2-2 to the lower column processing unit in the figure. Thereafter, the selection line SEL on the lower side in the drawing is set to “H”, the trigger line TRG_GR is set to “H”, and the pixels 132-1-2 and 132-2 are connected via the VSL 141-1 and the VSL 142-1. The signal voltage is read from 2 to the lower column processing unit in the figure. In this way, the signal voltage is read from all the GR pixels. This will be referred to as a second step, for example.

  In the present technology, next, the upper selection line SEL in the drawing is set to “H”, the trigger line TRG_GB is set to “H”, and the pixels 131-1-3 and 131-are connected via the VSL 141-2 and VSL 142-2. The signal voltage is read from 2-3 to the lower column processing unit in the figure. Thereafter, the selection line SEL on the lower side in the drawing is set to “H”, the trigger line TRG_GB is set to “H”, and the pixels 132-1-3 and 132-2 are set via the VSL 141-1 and VSL 142-1. The signal voltage is read from 3 to the lower column processing unit in the figure. In this way, signal voltages are read from all GB pixels. This will be referred to as a third step, for example.

  In the present technology, next, the upper selection line SEL in the drawing is set to “H”, the trigger line TRG_B is set to “H”, and the pixels 131-1-4 and 131-are connected via the VSL 141-2 and VSL 142-2. The signal voltage is read from 2-4 to the upper column processing unit in the figure. Thereafter, the selection line SEL on the lower side in the drawing is set to “H”, the trigger line TRG_B is set to “H”, and the pixels 132-1-4 and 132-2 are connected via the VSL 141-1 and VSL 142-1. The signal voltage is read from 4 to the upper column processing unit in the figure. In this way, signal voltages are read from all the B pixels. This will be referred to as a fourth step, for example.

  By performing the first to fourth steps, for example, as shown in FIG. 6, the pixel processing signal of the R pixel and the pixel signal of the B pixel are generated by the upper column processing unit in the drawing, In the drawing, a pixel signal of the GR pixel and a pixel signal of the GB pixel are generated by the upper column processing unit. For example, the pixel signal of each color generated from the signal voltage of the pixel of each color read for each row is stored in the data storage unit 119 via the signal processing unit 118 in association with the information indicating the pixel position. Is done. Then, the signal processing unit 118 generates image data by rearranging the pixel signals stored in the data storage unit 119.

  By doing in this way, in this art, a signal voltage can be read in order from a pixel in which noise is easy to accumulate.

  In the first to fourth steps, the driving of the vertical driving unit 112, the column processing unit 113, and the horizontal driving unit 114 is controlled by a timing signal generated by the timing generator of the system control unit 115 in FIG. It is realized by doing. That is, the system control unit 115 generates a timing signal that enables reading of the signal voltage in the first to fourth steps.

  In the example of FIG. 5, the description has been made on the assumption that the vertical readout method is adopted in the CMOS image sensor 110, but the vertical readout method is not necessarily adopted in the present technology. When the vertical readout method is not employed in the CMOS image sensor 110, one vertical signal line is provided for each column of pixels. For example, in FIG. 5, VSL 141-2 and VSL 142-2 are not provided, but only VSL 141-1 and VSL 142-1 are provided.

  In the case where the CMOS image sensor 110 does not employ the vertical readout method, the signal voltages of the R, GR, GB, and B pixels in the first to fourth steps are illustrated via the VSL 141-1 and the VSL 142-1. The data is read by the middle and lower column processing units.

  FIG. 7 is a diagram illustrating the retention time of each pixel when the present technology is applied. In FIG. 7, as in FIG. 3, the horizontal axis represents time, and the vertical axis represents a row of pixels. In FIG. 7, the retention time of the R pixel is indicated by a line 211, the retention time of the GR pixel is indicated by a line 212, and the retention time of the GB pixel is indicated by a line 213. The line 214 indicates the retention time of the B pixel. Further, in FIG. 7, the retention time of each conventional pixel is shown by a line 215 for reference.

  For example, the holding time indicated by the line 215 is Tm, and the holding time of the last row is tl. The holding time indicated by the line 211 is Tm (R), the holding time indicated by the line 212 is Tm (GR), the holding time indicated by the line 213 is Tm (GB), and the holding time indicated by the line 214 is set. Let time be Tm (B). When the total number of rows of pixels arranged in the pixel array is N, each holding time in the nth row can be expressed by Equations (3) to (6).

・・・（３）

・・・（４）

・・・（５）

・・・（６）

... (3)

... (4)

... (5)

... (6)

  From Expression (3), Tm (R) can shorten the holding time in all rows of the pixel array 111. As a result, noise included in the signal voltage output from the R pixel can be reduced in all rows.

  From Equation (4), Tm (GR) can shorten the holding time in a row where n> N / 3. As a result, noise included in the signal voltage output from the GR pixel in the row of n> N / 3 can be reduced in all rows.

  From equation (5), the retention time of Tm (GB) increases in rows where n> N / 2, and from equation (6), the retention time of Tm (B) increases in all rows. Therefore, the reduction of noise included in the signal voltage output from the B pixel cannot be expected so much.

  However, by applying the present technology, it is possible to reduce the retention time of the R pixels that are most likely to be mixed with noise in all rows, so that it is possible to reduce noise in the entire image.

  Furthermore, by applying the present technology, the difference in retention time between the first row and the Nth row can be reduced to ¼ Tm compared to the conventional Tm in all color pixels. As a result, the amount of noise can be leveled, and a natural image with less discomfort can be generated.

  FIG. 8 is a diagram illustrating the magnitude of noise according to the color of a pixel in a CMOS image sensor to which the present technology is applied. In the figure, the magnitude of noise observed corresponding to the holding time shown in FIG. 7 is represented by a bar graph for each pixel color. As in the case shown in FIG. 2, the magnitude of noise is expressed in dB. Therefore, the higher the height of the bar graph, the smaller the magnitude of noise. Further, the scale of the vertical axis in the graph of FIG. 8 is the same as that of FIG.

  As shown in FIG. 8, the noise of the GR pixel is the largest, and then the noise increases in the order of B, GB, and R. Compared to the case of FIG. 2, in the case of FIG. 8, noise is reduced in all the color pixels other than the B pixel. As described above, by applying the present technology, it is possible to reduce noise in the entire image.

  In the above, in each of the first to fourth steps, the upper selection line SEL in the drawing is set to “H”, and then the lower selection line SEL in the drawing is set to “H”. An example was described.

  However, for example, in each of the first to fourth steps, the upper selection line SEL and the lower selection line SEL in the figure may be simultaneously set to “H”. In this case, for example, the signal voltage may be read first via the VSL 141-2 and VSL 142-2, and then the signal voltage may be read via the VSL 141-2 and VSL 142-2. That is, instead of selecting the pixel row to be read by the pulse of the selection line SEL, the pixel row to be read may be selected by switching the vertical signal line (VSL) for reading the signal voltage.

  Furthermore, in the above, the example which reads the pixel of each color for every line was demonstrated. For example, the pixel 131-1-1 and the pixel 131-2-1 are read out as the R pixel, and then the pixel 132-1-1 and the pixel 132-2-1 are read.

  However, for example, two rows of pixels of each color may be read simultaneously. For example, the pixel 131-1-1, the pixel 131-2-1, the pixel 132-1-1, and the pixel 132-2-1 may be read simultaneously as the R pixel.

  In this case, for example, in the first step, the upper selection line SEL and the lower selection line SEL in the figure are simultaneously set to “H”, and the trigger line TRG_R is set to “H”. Then, the signal voltage is read to the upper column processing unit in the figure via the VSL 141-2 and VSL 142-2, and simultaneously the signal voltage is read to the lower column processing unit in the figure via the VSL 141-1 and VSL 142-1. .

  By doing so, it becomes possible to simultaneously read out the signal voltage of the R pixel for two rows. Here, the case of the R pixel has been described as an example. However, in the case of the GR pixel, the GB pixel, or the B pixel, two rows can be read simultaneously.

  In this case, unlike the example described with reference to FIG. 6, pixel signals of some of the pixels of each color are generated by the column processing unit on the upper side in the drawing, and the lower column in the drawing is displayed. Pixel signals of other pixels are generated by the processing unit. That is, when two rows of pixels of each color are read out simultaneously, the upper column processing unit in the drawing and the lower column processing unit in the drawing respectively generate R, GR, GB, and B pixel signals.

  The pixel signals of the respective colors are stored in the data storage unit 119 via the signal processing unit 118 in association with information indicating the respective pixel positions, and the signal processing unit 118 stores the pixels stored in the data storage unit 119. Image data is generated by rearranging the signals.

  In the above description, the example in which the pixels of each color are sequentially read from the top row by row (one row at a time or two rows simultaneously) has been described. However, for example, pixels may be read from a row located in the center of the pixel array 111.

  FIG. 9 is a diagram for explaining an example of the holding time of each pixel when the pixel is read from the row located in the center of the pixel array 111. In FIG. 9, as in FIG. 3, the horizontal axis represents time, and the vertical axis represents a row of pixels. In FIG. 9, the retention time of each pixel is indicated by a line 231-1 and a line 231-2. For reference, the retention time of each pixel when sequentially read from the upper row is indicated by a line 232. Has been.

  That is, in the case of FIG. 9, reading is started from the pixel in the nth row, which is a row located in the center of the pixel array 111. Then, the pixels in each row are sequentially read in the upward direction of the pixel array 111 as in the (n−1) th row, the (n−2) th row,. 1). In the case of FIG. 9, when the reading of the pixels in the first row is completed, the pixel array 111 is sequentially turned downward like the (n + 1) th row, the (n + 2) th row, the (n + 3) th row,. The pixels in each row are read out (line 231-2).

  In this way, for example, for the pixels in the α-th row to the n-th row, the holding time can be shortened compared to the case where the pixels are sequentially read from the upper row. That is, it is possible to reduce the noise of the pixel at the upper center that is relatively noticeable on the screen.

  The lines 231-1 and 231-2 shown in FIG. 9 indicate the holding time when each pixel is read without being divided for each color. For example, R, GR, GB, Even when reading is performed in the order of B, the same characteristics as those indicated by the lines 231-1 and 231-2 should be observed for the retention times of the pixels of the respective colors.

  Therefore, even when the pixels are read out in the order of R, GR, GB, and B for each color, by reading the pixels of each color from the row located at the center of the pixel array 111, the retention time of the pixels of each color at the upper center of the screen Can be shortened. That is, it is possible to further reduce the noise of the pixels arranged at positions that are relatively easily noticed on the screen.

  In addition, this technique is not restricted to application to a solid-state image sensor like a CMOS image sensor, for example. That is, the present technology is applied to an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function, or a copying machine using a solid-state imaging device as an image reading unit. The present invention can be applied to all electronic devices using a solid-state image sensor. The solid-state imaging device may be formed as a one-chip, or may be in a module shape having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.

  FIG. 10 is a block diagram illustrating a configuration example of an imaging apparatus as an electronic apparatus to which the present technology is applied.

  An imaging apparatus 600 in FIG. 10 includes an optical unit 601 including a lens group, a solid-state imaging device (imaging device) 602 that employs each of the pixel configurations described above, and a DSP circuit 603 that is a camera signal processing circuit. The imaging apparatus 600 also includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus line 609.

  The optical unit 601 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the amount of incident light imaged on the imaging surface by the optical unit 601 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. As the solid-state imaging device 602, a solid-state imaging device such as the CMOS image sensor 110 according to the above-described embodiment, that is, a solid-state imaging device capable of realizing imaging without distortion by global exposure can be used.

  The display unit 605 includes a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 602. The recording unit 606 records a moving image or a still image captured by the solid-state imaging device 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation unit 607 issues operation commands for various functions of the imaging apparatus 600 under the operation of the user. The power supply unit 608 appropriately supplies various power sources serving as operation power sources for the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, and the operation unit 607 to these supply targets.

  As described above, the CMOS image sensor 110 according to the above-described embodiment is used as the solid-state imaging device 602, so that the second pixel signal can be extracted without performing signal addition. Since the reset noise can be accurately removed also when extracting the pixel signal, the captured image is captured by the imaging device 600 such as a video camera, a digital still camera, or a camera module for a mobile device such as a mobile phone. Image quality can be improved.

  In the above-described embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels that detect signal charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example. However, the present technology is not limited to application to a CMOS image sensor, and can be applied to all column-type solid-state imaging devices in which a column processing unit is arranged for each pixel column of a pixel array unit.

  In addition, the present technology is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image. Applicable to imaging devices and, in a broad sense, solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images as images. is there.

  Note that the series of processes described above in this specification includes processes that are performed in parallel or individually even if they are not necessarily processed in time series, as well as processes that are performed in time series in the order described. Is also included.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  110 CMOS image sensor, 111 pixel array 112 vertical drive unit, 113 column processing unit, 114 horizontal drive unit, 116 pixel drive line, 117 vertical signal line, 118 signal processing unit, 119 data storage unit, 131-1-1 to 132 -2-4 pixels, 141-1, 141-2 VSL, 142-1, 142-2 VSL

Claims (20)

A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A plurality of trigger lines provided corresponding to the pixel rows of the pixel region,
The plurality of trigger lines includes a first trigger line and a second trigger line,
The first trigger line is connected to a first red pixel in the pixel region;
The second trigger line is connected to a first green pixel provided in the same row as the first red pixel,
The plurality of pixels have a light receiving portion and a floating diffusion for each pixel,
The floating diffusion is supplied with signal charges generated by the light receiving unit via a charge storage region. The plurality of trigger lines include a third trigger line and a fourth trigger line,
The third trigger line is connected to a first blue pixel in the pixel region;
The solid-state imaging device according to claim 1, wherein the fourth trigger line is connected to a second green pixel provided in the same row as the first blue pixel. The plurality of trigger lines includes a fifth trigger line;
The fifth trigger line is connected to a second red pixel in the pixel region;
The solid-state imaging device according to claim 1, wherein the first trigger line and the fifth trigger line are provided to receive the same trigger pulse. The plurality of trigger lines includes a sixth trigger line;
The sixth trigger line is connected to a third green pixel provided in the same row as the second red pixel,
The solid-state imaging device according to claim 3, wherein the second trigger line and the sixth trigger line are provided to receive the same trigger pulse. The plurality of trigger lines includes a seventh trigger line;
The seventh trigger line is connected to a second blue pixel in the pixel region;
The solid-state imaging device according to claim 2, wherein the third trigger line and the seventh trigger line are provided to receive the same trigger pulse. The plurality of trigger lines includes an eighth trigger line;
The eighth trigger line is connected to a fourth green pixel provided in the same row as the second blue pixel,
The solid-state imaging device according to claim 5, wherein the fourth trigger line and the eighth trigger line are provided to receive the same trigger pulse. The plurality of vertical signal lines include a first vertical signal line and a second vertical signal line,
The pixel region is provided with a first pixel group and a second pixel group each consisting of four adjacent pixels,
The four pixels forming the first pixel group share the first vertical signal line,
The four pixels forming the second pixel group share the second vertical signal line,
The solid-state imaging device according to claim 1, wherein the first pixel group and the second pixel group are provided adjacent to each other in a vertical direction. The solid-state imaging device according to claim 7, wherein the first pixel group and the second pixel group include four pixels in two rows and two columns. The solid-state imaging device according to claim 8, wherein the four pixels in the two rows and two columns are arranged according to a Bayer array. The solid-state imaging device according to claim 1, wherein the plurality of vertical signal lines are connected to a column processing unit. The column processing unit to which the plurality of vertical signal lines are connected includes a first column processing unit and a second column processing unit,
The plurality of vertical signal lines include a third vertical signal line,
The first vertical signal line and the third vertical signal line are provided corresponding to the first pixel column,
The first column processing unit is connected to the first vertical signal line through a first switch region,
The second column processing unit is connected to the third vertical signal line through a second switch region,
The first column processing unit and the second column processing unit are provided so as to sandwich a pixel region in a vertical direction.
The solid-state imaging device according to claim 7 . A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A plurality of trigger lines provided corresponding to the pixel rows of the pixel region,
The plurality of pixels have a light receiving portion and a floating diffusion for each pixel,
The floating diffusion is supplied with signal charges generated by the light receiving unit through a charge storage region,
The plurality of vertical signal lines include a first vertical signal line and a second vertical signal line,
The pixel region is provided with a first pixel group and a second pixel group each consisting of four adjacent pixels,
The four pixels forming the first pixel group share the first vertical signal line,
The four pixels forming the second pixel group share the second vertical signal line,
The first pixel group and the second pixel group are provided adjacent to each other in the vertical direction.
Solid-state image sensor. The solid-state imaging device according to claim 12, wherein the first pixel group and the second pixel group include four pixels in two rows and two columns. The solid-state imaging device according to claim 13, wherein the four pixels in the two rows and two columns are arranged according to a Bayer array. A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A plurality of trigger lines provided corresponding to the pixel rows of the pixel region;
A plurality of gate electrodes provided in the pixel region,
The plurality of pixels have a plurality of light receiving portions and a plurality of floating diffusions,
The plurality of pixels have the light receiving unit for each pixel,
The plurality of floating diffusions include a first floating diffusion and a second floating diffusion,
The plurality of gate electrodes include a first gate electrode and a second gate electrode,
The first floating diffusion receives a charge generated by the light receiving unit according to a potential supplied to the first gate electrode,
The second floating diffusion receives a charge generated by the light receiving unit according to a potential supplied to the second gate electrode,
The plurality of vertical signal lines include a first vertical signal line and a second vertical signal line,
The pixel region is provided with a first pixel group and a second pixel group each consisting of four adjacent pixels,
The four pixels forming the first pixel group share the first vertical signal line,
The four pixels forming the second pixel group share the second vertical signal line,
The first pixel group and the second pixel group are provided adjacent to each other in the vertical direction,
The first floating diffusion is connected to the first vertical signal line;
The second floating diffusion is connected to the second vertical signal line
Solid-state image sensor. The solid-state imaging device according to claim 15, wherein the first pixel group and the second pixel group include four pixels in two rows and two columns. The solid-state imaging device according to claim 16, wherein the four pixels in the two rows and two columns are arranged according to a Bayer array. In an electronic device equipped with a solid-state image sensor,
The solid-state imaging device is
A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A plurality of trigger lines provided corresponding to the pixel rows of the pixel region,
The plurality of trigger lines includes a first trigger line and a second trigger line,
The first trigger line is connected to a first red pixel in the pixel region;
The second trigger line is connected to a first green pixel provided in the same row as the first red pixel,
The plurality of pixels have a light receiving portion and a floating diffusion for each pixel,
An electronic device in which the floating diffusion is supplied with signal charges generated by the light receiving unit via a charge storage region. In an electronic device equipped with a solid-state image sensor,
The solid-state imaging device is
A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A plurality of trigger lines provided corresponding to the pixel rows of the pixel region,
The plurality of pixels have a light receiving portion and a floating diffusion for each pixel,
The floating diffusion is supplied with signal charges generated by the light receiving unit through a charge storage region,
The plurality of vertical signal lines include a first vertical signal line and a second vertical signal line,
The pixel region is provided with a first pixel group and a second pixel group each consisting of four adjacent pixels,
The four pixels forming the first pixel group share the first vertical signal line,
The four pixels forming the second pixel group share the second vertical signal line,
The first pixel group and the second pixel group are provided adjacent to each other in the vertical direction.
Electronics. In an electronic device equipped with a solid-state image sensor,
The solid-state imaging device is
A pixel region in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of vertical signal lines provided corresponding to the pixel columns of the pixel region;
A plurality of trigger lines provided corresponding to the pixel rows of the pixel region;
A plurality of gate electrodes provided in the pixel region,
The plurality of pixels have a plurality of light receiving portions and a plurality of floating diffusions,
The plurality of pixels have the light receiving unit for each pixel,
The plurality of floating diffusions include a first floating diffusion and a second floating diffusion,
The plurality of gate electrodes include a first gate electrode and a second gate electrode,
The first floating diffusion receives a charge generated by the light receiving unit according to a potential supplied to the first gate electrode,
The second floating diffusion receives a charge generated by the light receiving unit according to a potential supplied to the second gate electrode,
The plurality of vertical signal lines include a first vertical signal line and a second vertical signal line,
The pixel region is provided with a first pixel group and a second pixel group each consisting of four adjacent pixels,
The four pixels forming the first pixel group share the first vertical signal line,
The four pixels forming the second pixel group share the second vertical signal line,
The first pixel group and the second pixel group are provided adjacent to each other in the vertical direction,
The first floating diffusion is connected to the first vertical signal line;
The second floating diffusion is connected to the second vertical signal line
Electronics.

Images