TWI429281B - Solid-state imaging device, signal processing method of solid-state imaging device, and electronic apparatus - Google Patents

Description

Solid-state imaging device, signal processing method of solid-state imaging device, and electronic device

The present invention relates to a solid-state imaging device, a signal processing method of a solid-state imaging device, and an electronic device.

In a solid-state imaging device such as a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor, unit pixels are in a grid pattern at predetermined intervals in vertical and horizontal directions in many cases. Configuration (for example, see Japanese Unexamined Patent Application Publication No. 2007-189085).

A pixel array having the same pitch in the vertical and horizontal directions is easy to perform signal processing, and thus has recently become mainstream. Pixels arranged at the same pitch in the vertical and horizontal directions (i.e., pixels each having the same size in the vertical and horizontal directions) are referred to as square pixels. Meanwhile, pixels arranged at different pitches in the vertical and horizontal directions (that is, pixels each having a different size in the vertical and horizontal directions) are referred to as rectangular pixels.

In a solid-state imaging device used in a conventional video camera or the like, rectangular pixels having a vertical size longer than a horizontal size are used in many cases. This is because in the television broadcasting standard, the number of scan lines running in the vertical direction is specified, but the number of scan lines running in the horizontal direction has a degree of freedom, and thus if the intended purpose is to display on the television The advantage of using square grid pixels for images is small.

At the same time, square pixels are superior to rectangular pixels in order to perform image processing by using a personal computer and perform on-the-fly capture and recognition of the characteristics of the image by using machine vision. In view of this, solid-state imaging devices of this type (i.e., solid-state imaging devices using square pixels) have been increasingly used in video cameras.

Further, in order to provide a solid-state imaging device having a new function or an improved characteristic, a method of performing calculation between pixels adjacent to each other in the vertical or horizontal direction (hereinafter referred to as "adjacent pixels") is employed in some cases. For example, there has been a method of using different accumulation times for the pixels of the even columns and the pixels of the odd columns as a method of increasing the dynamic range (for example, see Japanese Unexamined Patent Application Publication No. 11-150687).

However, according to this method of increasing the dynamic range, if the dynamic range is increased on the basis of one image, the resolution in the vertical direction is reduced by half. In the Japanese Unexamined Patent Application Publication No. 11-150687, two images are used to compensate the resolution in the vertical direction. However, the dynamic resolution is worsened by the time lag. If the calculation is thus performed between adjacent pixels in the vertical or horizontal direction, the resolution in that direction changes. Therefore, the composite output becomes equal to the output from the rectangular pixel.

Recently, it has become common to use small pixel pitches of 2 μm or less in pixel arrays. The pixel pitch of 2 μm or less is smaller than the resolution of the lens (optical system) of the camera. According to the general thinking extension, the miniaturization of pixels is intended to reduce the pixel sensitivity and the amount of signal to be processed, but increase the resolution. However, if the pixel pitch becomes smaller than the resolution of the lens, the resolution does not increase. That is, the resolution of the lens defines the limit of the resolution of the solid-state imaging device.

An example of the resolution of the lens is illustrated in FIG. That is, if the aperture is opened (the F value is decreased), the aberration of the lens is increased, and thus the resolution is reduced. Further, if the aperture is closed (the F value is increased), the wave properties of the light cause diffraction, and thus the resolution is also reduced under such conditions. The limit attributed to the nature of the wave is called the Rayleigh limit.

Figure 27 illustrates an example of a lens in which the resolution is highest at about F4 (F value = 4). Even at F4, it is still difficult to resolve pixel pitches of 2 μm or less. In a single lens reflex camera lens, the resolution is highest at approximately F8, and thus the F value is set to approximately F8 in many conditions. In the single lens reflex camera lens, when the F value is about F8 or less, the limit due to the aberration of the lens exceeds the limit attributed to the wave property. Therefore, it is difficult to resolve a pixel pitch of 5 μm or less. Furthermore, if the lens system includes an optical low pass filter, the resolution of the optical system corresponds to the lower of the resolution of the lens and the resolution of the optical low pass filter.

In this example, the size of each of the pixels is defined by the size of the photoelectric conversion element. Therefore, the pixel pitch refers to the distance between the photoelectric conversion elements. If the incident light is sampled at spatially equal intervals in the vertical and horizontal directions, the pixels are square. If the incident light is sampled at spatially different intervals in the vertical and horizontal directions, the pixels are rectangular. Therefore, the layout shape of the pixels may not necessarily be a square or rectangular shape, but may be, for example, a complicated shape such as the shape of a puzzle piece.

In the present invention, there is a need to provide a solid-state imaging device, a signal processing method of a solid-state imaging device, and an electronic device that perform calculations between adjacent pixels to provide improved characteristics or new functions, thereby substantially achieving manageability of a square pixel product. And make image processing and system construction easier.

In the present invention, there is also a need to provide a solid-state imaging device, a signal processing method of a solid-state imaging device, and an electronic device capable of improving imaging characteristics even when miniaturization of a pixel exceeds a resolution limit.

In view of the above, a solid-state imaging device according to an embodiment of the present invention includes a pixel array section configured to include a plurality of configured rectangular pixels, each of the pixels having vertical and horizontal directions Different sizes, and a plurality of neighbors in the pixels are combined to form square pixels having the same size in the vertical and horizontal directions. In the solid-state imaging device, signals are read out from a plurality of combined rectangular pixels, and a plurality of signals read from a plurality of rectangular pixels are processed and output as a single signal.

A plurality of rectangular pixels are combined to form a square pixel, and a plurality of signals read from the plurality of rectangular pixels are output as a single signal. Thereby, the single signal can be processed as a signal from a square grid (square pixels). If the incident light is sampled at equal intervals in the vertical and horizontal directions, it is possible to make the plurality of rectangular pixels look like a square grid. Since a single signal is processed as a signal from a square grid, it is not necessary to change the configuration of the signal processing system for the square grid at a later stage. Furthermore, if a single signal is selected or synthesized from a plurality of individual pixels of a plurality of rectangular pixels as appropriate, it is possible to perform a process of improving imaging characteristics, such as a process of increasing the dynamic range by using a single signal in a signal processing system at a later stage. . As a result, even if the miniaturization of the pixel exceeds the limit of the resolution, it is possible to improve the imaging characteristics while achieving miniaturization of the pixel.

According to an embodiment of the invention, calculations are performed between adjacent pixels in the vertical or horizontal direction to provide improved characteristics or new functions. Thereby, it is possible to substantially achieve manageability of the square pixel product and to make image processing and system construction easier. It is also possible to improve the imaging characteristics even when the pixel is miniaturized beyond the resolution limit and when the pixel pitch becomes smaller than the resolution of the optical system that receives the incident light.

Embodiments for carrying out the invention (hereinafter described as "embodiments") will be described in detail below with reference to the drawings. The description will be made in the following order: 1. Solid-state imaging device (an example of a CMOS image sensor) according to an embodiment of the present invention, 2. Characteristic features of the embodiment, 3. Modified example, and 4. Electronic device (imaging An example of a device).

<1. Solid-state imaging device according to an embodiment of the present invention>

1 is a system configuration diagram illustrating an overview of a system configuration of a solid-state imaging device (for example, a CMOS image sensor as an X-Y address type solid-state imaging device) according to an embodiment of the present invention. As used herein, a CMOS image sensor refers to an image sensor formed by applying or partially using a CMOS process.

As illustrated in FIG. 1, the CMOS image sensor 10 according to the present embodiment is configured to include a pixel array section 12 formed on a semiconductor substrate (hereinafter occasionally described as "wafer") 11 and integrated on the same wafer. A peripheral circuit portion on the 11 (on which the pixel array section 12 is formed). In the present example, the peripheral circuit portion includes, for example, a vertical drive section 13, a row processing section 14, a horizontal drive section 15, an output circuit section 16, and a system control section 17.

In the pixel array section 12, each includes a unit pixel in which a photoelectric conversion element that generates and accumulates charges generated by photoelectric conversion (hereinafter simply described as "charge") is generated and has a charge amount according to the amount of incident light (at The following occasionally simply describes "pixels" as a column and row two-dimensional configuration. The specific configuration of the unit pixels will be described later.

Further, in the pixel array section 12, the pixel driving line 121 is provided for each column of the pixel array having columns and rows to be in the horizontal direction, that is, the column direction (the direction in which the pixels are arranged in the pixel column) Extend. Further, vertical signal lines 122 are provided for respective lines to extend in the vertical direction, that is, in the row direction (the direction in which the pixels are arranged in the pixel row). The number of pixel driving lines 121 in FIG. 1 is one per column, but is not limited to this number. One of the pixel drive lines 121 is connected to an output terminal of a corresponding column of the vertical drive section 13.

The vertical drive section 13 is configured to include a shift register, an address decoder, etc., and is used as a pixel drive section for driving individual pixels of the pixel array section 12, for example, simultaneously or in column units. . The vertical drive section 13 (not specifically configured herein) is generally configured to include two scanning systems, that is, a readout (from photoelectric conversion element to output circuit) scanning system (described briefly below as "Read Scan System" and reset the scanning system.

The readout scanning system sequentially selects and scans the unit pixels of the pixel array section 12 in units of columns to read signals from the unit pixels. The signal read from the unit pixel is an analog signal. The reset scanning system performs a reset scan on the readout column that will be subjected to the readout scan of the readout scanning system such that the reset scan is preceded by the readout scan at a time corresponding to the shutter speed.

By resetting the reset scan of the scanning system, the photoelectric conversion elements of the unit pixels in the readout column are erased of unnecessary charges. Thereby, the photoelectric conversion element is reset. Then, by resetting the reset of the unnecessary charge by the scanning system, a so-called electronic shutter operation is performed. Herein, the electronic shutter operation refers to an operation of removing the charge of the photoelectric conversion element and newly starting the exposure process (starting accumulation of charges).

The signal read by the readout operation of the readout scanning system corresponds to the amount of light incident after the immediately preceding readout operation or electronic shutter operation. The time period from the readout timing of the immediately preceding readout operation or the reset timing of the electronic shutter operation to the readout timing of the present readout operation corresponds to the accumulation period (exposure period) of the charge in the unit pixel.

The signals output by the respective unit pixels of the pixel columns selected and scanned by the free vertical driving section 13 are supplied to the line processing section 14 via the respective vertical signal lines 122. The row processing section 14 performs predetermined signal processing on the signals output from the respective unit pixels of the selected column via the vertical signal line 122 in pixel unit of the pixel array section 12, and temporarily holds the signal processed pixel signals.

In particular, when a signal is received from a respective unit pixel, the line processing section 14 performs signal processing on the signal, such as, for example, CDS (correlated double sampling) based denoising, signal amplification, and AD (analog to digital) conversion. The noise removal process removes fixed pattern noise that is unique to the pixel, such as resetting the threshold value between the noise and the amplifier transistor. The signal processing exemplified herein is merely an example. Therefore, signal processing is not limited to this.

The horizontal drive section 15 is configured to include a shift register, an address decoder, etc., and the self-processing section 14 sequentially selects the unit circuits corresponding to the pixel rows. Due to the selection and scanning of the horizontal drive section 15, the pixel signals signal processed by the row processing section 14 are sequentially output to the horizontal busbar 18 and transmitted by the horizontal busbar 18 to the output circuit section 16.

Output circuit section 16 processes and outputs the signals transmitted by horizontal bus 18 . The processing performed by output circuit section 16 may be only buffering, or may be a variety of digital signal processing, such as pre-buffer adjustment of black levels and correction of variations between lines.

The output circuit section 16 has, for example, a differential output configuration, the output stage of which outputs a differential signal. That is, the output stage of the output circuit section 16 processes each of the signals transmitted by the horizontal bus 18 and outputs the composite signal as a normal phase signal. Furthermore, the output stage of the output circuit section 16 reverses the polarity of the signal and outputs the composite signal as an inverted phase signal.

The normal phase signal is output to the outside of the wafer 11 via the normal phase output terminal 19A, and the inverted phase signal is output to the outside of the wafer 11 via the inverted phase output terminal 19B. When the output stage of the output circuit section 16 has a differential output configuration, a signal processing section (eg, a signal processing IC (integral circuit)) provided external to the wafer 11 receives a normal phase signal and inverts at its input stage. Bit signal, this input stage is configured as a differential circuit.

The differential circuit configuration of the output stage of the output stage of the output circuit section 16 and the input stage of the signal processing IC as described above can be implemented by the output stage of the output circuit section 16 and the input stage of the signal processing IC. The current between the two is transmitted. Therefore, even if the length of the transmission path between the output stage of the output circuit section 16 and the input stage of the signal processing IC increases, charging and discharging do not occur on the transmission path. Therefore, a high speed system can be provided.

The system control section 17 receives, for example, a clock and an operation mode specifying data supplied from outside the wafer 11, and outputs information such as internal information of the CMOS image sensor 10. In addition, system control section 17 includes timing generators for generating a plurality of timing signals. Based on the various timing signals generated by the timing generator, the system control section 17 performs drive control of peripheral circuit sections including the vertical drive section 13, the row processing section 14, the horizontal drive section 15, and the like.

The peripheral portion of the wafer 11 is provided with respective terminals of the input and output terminal groups 20 and 21, and includes a power supply terminal. The input and output terminal groups 20 and 21 exchange power supply voltages and signals between the inside and the outside of the wafer 11. The mounting positions of the input and output terminal groups 20 and 21 are determined at convenient locations in consideration of, for example, the incoming and outgoing directions of the signals with respect to the wafer 11.

<2. Characteristic Features of the Present Embodiment>

In the CMOS image sensor 10 configured as described above, the characteristic feature of the embodiment is that the aspect ratio of each of the unit pixels is set to be different from 1:1 (square pixel), that is, The shape of the unit pixel is set to have rectangles of different sizes in the vertical direction and the horizontal direction (rectangular pixels); a plurality of neighbors in the unit pixel are combined to form square pixels having the same size in the vertical direction and the horizontal direction; and a combination A plurality of unit pixels output a single signal.

With this configuration, a single signal output from a unit of a plurality of pixels can be processed as a signal from a square grid (square pixel). If the incident light is sampled at equal intervals in the vertical and horizontal directions, it is possible to make the pixel look like a square grid. By processing a single signal as a signal from a square grid, it is not necessary to change the configuration of a typical signal processing system for a square grid at a later stage.

Furthermore, if a single signal is selected or synthesized from the individual signals of the plurality of pixels as appropriate, it is possible to perform a process of improving the imaging characteristics, such as a process of increasing the dynamic range by using a single signal in a signal processing system at a later stage. Specific embodiments will be described below.

[First Embodiment]

FIG. 2 is a configuration diagram illustrating an example of a pixel array in the pixel array section 12 according to the first embodiment. As illustrated in FIG. 2, the pixel array section 12 includes unit pixels 30 each including a photoelectric conversion element and two-dimensionally arranged in a plurality of columns and rows. Herein, each of the unit pixels 30 is a so-called rectangular pixel that is long in the horizontal direction, which is twice the vertical size (row direction) in the horizontal size (column direction), that is, it has 1: 2 vertical to horizontal spacing ratio.

If the CMOS image sensor 10 according to the present embodiment is capable of picking up a color image, color filters (for example, the color filter 40 on the wafer) are provided on the respective light receiving surfaces of the unit pixels 30. Herein, a plurality of (for example, two) unit pixels 30 adjacent in the vertical direction form one set. The upper and lower sets of two pixels have the same color on-wafer color filter 40.

The on-wafer color filter 40 is configured such that respective colors of, for example, R (red), G (green), and B (blue) have a predetermined relationship. For example, color coding is designed herein such that two columns of a repeating GB combination in a color array alternate with two columns of a color array having a repeating RG combination. The upper and lower two pixels have the same color. Therefore, one color filter can cover the upper and lower two pixels.

In the pixel array of the pixel array section 12, each of the unit pixels 30 is a rectangular pixel having a vertical and horizontal size ratio of 1:2 in the horizontal direction. Thus, as illustrated in Figure 2, the individual on-wafer color filters 40 for the upper and lower two pixel groups are square in shape. A square wafer on color filter 40 is provided to the pixel array wherein two columns of repeating GB combinations in the color array alternate with two columns of repeating RG combinations in the color array. Thus, the total color array of color filters 40 on the wafer is a so-called Bayer array.

By configuring the color filter 40 on the wafer to have a color array based on cells of two pixels, the following advantages are obtained. That is, as the CMOS process is miniaturized, pixels have been increasingly miniaturized. However, it has become increasingly difficult to miniaturize color filters in accordance with miniaturization of pixels. This is because it is difficult to miniaturize the color filter while preventing the rounding and peeling of the corners while maintaining its spectral characteristics.

However, the on-wafer color filter 40 of the above-described configuration example can be formed in the size of two pixels combined, and thus is advantageous in miniaturization of pixels. That is, as described above, when the color filter is supplied to each pixel, it is difficult to downsize the color filter in accordance with the miniaturization of the pixel. However, this example provides a color filter to a plurality of pixels, and thus can cope with the miniaturization of the pixels.

(scanning method)

Referring to Fig. 3, a pixel array for a pixel array section 12 according to the first embodiment will now be described (i.e., two columns having a repeating GB combination in a color array and two columns having a repeating RG combination in a color array are alternated. The pixel method) performs the scanning method. Scanning is performed in accordance with the driving operation of the vertical driving section 13 of FIG. The scanning method described with reference to Fig. 3 is a common scanning method.

First, a shutter scan is performed on the odd columns and then on the even columns. Next, a scan is performed on the readout column. Herein, the shutter scan corresponds to a scan called an electronic shutter operation described earlier, and defines the beginning of pixel accumulation. In the shutter scan, different shutter timings are set for the respective pixels of the odd columns and the individual pixels of the even columns.

Specifically, as illustrated in FIG. 3, the shutter timing of the individual pixels of the odd columns is set to increase the accumulation time, and the shutter timing of the individual pixels of the even columns is set to reduce the accumulation time. That is, when two adjacent columns form a unit (a group), the respective pixels for one of the columns (the odd columns in the present example) set the accumulation time to be relatively long and for another column ( The individual pixels of the even-numbered columns in this example set the accumulation time to be relatively short.

Due to the shutter scan described above, the signal from each of the pixels in the odd-numbered columns accumulated over a long period of time is a high-sensitivity signal corresponding to a long accumulation time. That is, light is incident on each of the pixels in the odd columns for a long time. Thus, signals from each of the pixels in the odd columns are capable of capturing sharp images of dark areas. However, in each of the pixels in the odd column (that is, the high sensitivity pixel), the photoelectric conversion element is quickly saturated. At the same time, the signal from each of the pixels in the even-numbered columns accumulated in a short time is a low-sensitivity signal corresponding to a short accumulation time. That is, the amount of light incident on each of the pixels in the even columns is small. Thus, signals from each of the pixels in the even columns are capable of capturing images of the bright regions without saturation.

(line processing section)

Subsequently, a line processing section 14 which processes signals output from the respective pixels 30 of the pixel array section 12 according to the first embodiment on the basis of the scanning performed by the above-described scanning method will be described. . Row processing section 14 is a collection of unit circuits that are provided to correspond to pixel rows of pixel array section 12. Hereinafter, each of the unit circuits constituting the line processing section 14 will be referred to as a row circuit.

Fig. 4 is a block diagram showing an example of the configuration of the line circuit 14A according to the first embodiment. As illustrated in FIG. 4, the row circuit 14A according to the first embodiment is configured to include a CDS circuit 141, a determination circuit 142, an AD conversion circuit 143 for performing predetermined signal processing such as an AD conversion process, and a latch. 144.

According to the driving operation of the vertical driving section 13, the signals of the pixels are sequentially supplied from the pixel array section 12 to the row circuit 14A in descending order of sensitivity of the pixels. In this example, the sensitivity of the pixels of the odd columns is higher than the sensitivity of the pixels of the even columns. Therefore, the signals from the pixels of the odd columns are first input to the row circuit 14A, and then the signals from the pixels of the even columns are input to the row circuit 14A.

As is widely known, the CDS circuit 141 of the row circuit 14A performs signal processing for calculating an on level of a pixel signal (a signal level to be described later) and a turn-off level (a reset level described later). The difference between the two is calculated and the semaphore of the offset is excluded.

In accordance with control of the system control section 17, the determination circuit 142 performs the determination in the readout of each of the signals from the high sensitivity pixels and the signals from the low sensitivity pixels sequentially read from the pixel array section 12. The process of whether the signal is equal to or greater than a predetermined value. For example, the saturation level of the pixel is used as a predetermined value representing the determination criteria of the determination circuit 142.

The determination circuit 142, the AD conversion circuit 143, and the latch 144 perform the following different processing operations on the signals from the pixels of the odd columns and the signals from the pixels of the even columns.

[odd column]

By using the saturation level of the pixel as the determination criterion, the determination circuit 142 determines whether the signal transmitted from the pixel of the odd column is saturated. If the signal is not at the saturation level, then the determination circuit 142 writes a logic "0" to the flag FL. If the signal is at a saturation level, then the determination circuit 142 writes a logic "1" to the flag FL. Next, the determination circuit 142 transmits the flag FL together with the signal received from the CDS circuit 141 to the AD conversion circuit 143.

If the flag FL stores a logic "0" (ie, the signal is not at the saturation level), the AD conversion circuit 143 operates to perform AD conversion on the signal (analog signal) from the pixel and pass the AD converted signal to the latch. 144. If the flag FL stores a logic "1" (i.e., the signal is at the saturation level), the AD conversion circuit 143 is placed in a standby state, and thus the AD conversion process is not performed. The value of the flag FL is written to a portion of the latch 144 via the AD conversion circuit 143.

[even column]

The determination circuit 142 does not perform the determination process on the signals transmitted from the pixels of the even columns, and transmits the signals to the AD conversion circuit 143 together with the determination result of the signals from the pixels of the odd columns (that is, the value of the flag FL). When the self-determining circuit 142 receives a signal from the even-numbered columns along with the value of the flag FL, the AD conversion circuit 143 operates only when the flag FL stores a logic "1" to perform a signal on the pixels from the even-numbered columns. The AD converts and passes the AD converted signal to the latch 144.

Specifically, if the flag FL received from the determination circuit 142 stores a logic "0", that is, if the signal from the pixel of the odd column is not at the saturation level, the AD conversion circuit 143 is placed in the standby state and is incorrect. The signals from the pixels of the even columns perform the AD conversion process. Further, if the flag FL stores a logic "1", that is, if the signal from the pixel of the odd column is at the saturation level, the AD conversion circuit 143 performs an AD conversion process on the signal from the pixel of the even column.

In the manner described above, the signals from the two columns of pixels (i.e., the upper and lower pixels) are processed by the row circuit 14A in the order of the odd and even columns. Thereafter, the value of the synthesized pixel signal and the value of the flag FL are read from the latch 144 to the horizontal bus bar 18 illustrated in FIG. As a result, the signals of either of the upper and lower pixels are AD-converted and output. In this process, the signal of the other pixel is not subjected to the AD conversion process while the AD conversion circuit 143 is placed in the standby state. The upper and lower two pixels share the filter of the same color as previously described.

If the signal from a high-sensitivity pixel accumulated over a long period of time is saturated, a signal from a low-sensitivity pixel accumulated in a short time is used. Herein, the saturated reference signal is primarily in a state where it does not substantially linearly respond to the level of the amount of incident light. In the present example, if the high sensitivity signal read from the pixels of the odd column is not saturated, the signal level of the high sensitivity signal and the value "0" of the flag FL are output from the row circuit 14A to the horizontal bus 18 . If the signal read from the pixel of the odd column is saturated, the signal level of the low sensitivity signal read from the pixels of the even column and the value "1" of the flag FL are output from the row circuit 14A to the horizontal bus 18 .

Next, on the basis of the signal level and the value of the flag FL, the signal processing section (for example, the DSP (Digital Signal Processor) 103 in Fig. 26) performs signal processing in the subsequent stage. Thereby, the dynamic range can be increased. In particular, if the flag FL indicates that the signal from the high sensitivity pixel is not saturated (FL=0), then in the subsequent stage the signal processing section is supplied from the high sensitivity pixel by using the flag FL as a pair. The signal produces a video signal.

If the flag FL indicates that the signal from the high sensitivity pixel is saturated (FL = 1), then in the subsequent stage the signal processing section uses a signal along with the flag FL as a pair of signals from the low sensitivity pixel. The level produces a video signal. With the signal processing described above, the dynamic range with respect to the light input can be increased.

If the distance between the upper and lower pixels is actually equal to or less than the lens resolution, the vertical resolution is not reduced, and the signals from the upper and lower pixels can be regarded as having an increased dynamic range as if from the square pixel output. Signal. Herein, the lens resolution refers to the resolution of an image formed on the imaging surface of the CMOS image sensor 10 via a lens of an optical system that receives incident light.

Strictly speaking, there may be situations where the resolution is determined by components other than the lens, such as an optical low pass filter. Furthermore, if imaging (such as direct imaging using X-rays or transmitted light) is performed without using a so-called "lens", the lens resolution is referred to as being formed on the imaging surface of the CMOS image sensor 10. The resolution of the optical system of the image.

In order for the signals from the upper and lower pixels to appear as signals from a single pixel, the offset and sensitivity characteristics of the upper and lower pixels need to be as similar as possible to each other, and between the upper and lower pixels. The difference in characteristics is smaller than the normal pixel variation. Otherwise, a gap may be caused in the transition region between the signals of the two pixels. In view of this, the upper and lower two pixels share some of the circuit elements constituting the pixel circuit. The sharing of some of the circuit elements of the pixel pair circuit elements will be described later.

Meanwhile, as previously described, the row circuit 14A is configured such that signals forming one of two pixels (high sensitivity pixels and low sensitivity signals in this example) are subjected to AD conversion, and The signal of the other pixel is not subjected to AD conversion while the AD conversion circuit 143 is placed in a standby state. An advantage of this configuration is that power consumption can be reduced due to the standby state of the AD conversion circuit 143 as compared with the case where the AD conversion process is performed on both of the respective signals of the two pixels.

The application of the signal processing technique described above is not limited to the CMOS image sensor 10, which is configured to form a square pixel by combining a plurality of rectangular pixels, and read out from a plurality of rectangular pixels The plurality of signal outputs are a single signal to be processed as a signal of a square pixel. That is, regardless of the shape of the unit pixel 30, the signal processing technique is generally applicable to a CMOS image sensor (in which the unit pixels 30 are arranged in columns and rows in two dimensions).

Further, in the present example, a case where two pixels including a high sensitivity pixel and a low sensitivity pixel are grouped together has been described as an example. However, the number of pixels forming a group is not limited to two. Furthermore, the signal processing performed on the signals of the pixels is not limited to the AD conversion process.

That is, when the number n (2) n) pixels (n=2 in this example) form a group and a number n of pixels from the pixel array section 12 sequentially read a number n of signals, determining circuit 142 in each of the signals It is determined in the reading whether the signal is equal to or greater than a predetermined value. Then, based on the determined result, predetermined signal processing is performed on the number m of signals, where m is less than n (1) m<n). Therefore, power consumption can be reduced due to the predetermined signal processing without a number (nm) of signals.

<<Line processing performed when n=3>>

The line processing according to the first modified example (by the signal processing of the line circuit 14A-1) will be described below with reference to an example, in which the number n is not two (such as three), that is, three having different sensitivity to each other. The pixels form a group.

Figure 5 illustrates an example of a pixel array of pixel array segments 12 in which three pixels having different sensitivities form a group. As illustrated in Figure 5, in this example, color coding is designed such that three columns of a repeating GR combination in a color array alternate with three columns of a color array having a repeating BG combination. Further, three pixels having the same color adjacent in the vertical direction form one group, and have sensitivity of, for example, the uppermost pixel of the three pixels has the highest sensitivity and the lowermost pixel of the three pixels has the lowest sensitivity. Level relationship.

However, the sensitivity level relationship is not limited to this order. In any sensitivity level relationship, the signal from the high sensitivity pixel is first read out according to the driving operation of the vertical driving section 13 and input to the line circuit 14A according to the first modified example of the first embodiment. 1.

Fig. 6 illustrates a configuration example of the line circuit 14A-1 according to the first modified example of the first embodiment. The configuration of the row circuit 14A-1 according to the modified example is basically similar to the configuration of the row circuit 14A according to the first embodiment explained in FIG. The row circuit 14A-1 is different from the row circuit 14A in that the latch 144' is formed by two latches 1 and 2.

The determination circuit 142, the AD conversion circuit 143, and the latch 144' perform the following different processing operations on the signals from the respective pixels of the first column, the second column, and the third column.

[first row]

By using the saturation level of the pixel as the determination criterion, the determination circuit 142 determines whether the signal transmitted from the pixels of the first column is not saturated. If the signal is not at the saturation level, then the determination circuit 142 writes a logic "0" to the flag FL. If the signal is at a saturation level, then the determination circuit 142 writes a logic "1" to the flag FL. Next, the determination circuit 142 transmits the flag FL together with the signal received from the CDS circuit 141 to the AD conversion circuit 143.

If the flag FL stores a logic "0" (ie, the signal is not at the saturation level), the AD conversion circuit 143 operates to perform AD conversion on the analog signal of the pixel and write the AD converted signal to the latch 144' Latch 1. If the flag FL stores a logic "1" (i.e., the signal is at the saturation level), the AD conversion circuit 143 is placed in a standby state, and thus the AD conversion process is not performed. The value of the flag FL is written to one of the latches 144' via the AD conversion circuit 143.

[The second column]

The determination circuit 142 does not perform the determination process on the signals transmitted from the pixels of the second column, and transmits the signals to the AD conversion circuit 143 together with the determination result of the signals from the pixels of the first column (i.e., the value of the flag FL). Upon receipt of the signal from the pixels of the second column by the determination circuit 142 along with the value of the flag FL, the AD conversion circuit 143 operates to perform an AD conversion on the signals from the pixels of the second column regardless of the value of the flag FL. In the process, if the flag FL stores a logic "0", the AD conversion circuit 143 writes the AD conversion result to the latch 2 of the latch 144'. If the flag FL stores a logic "1", the latch 1 of the latch 144' is empty, and thus the AD conversion circuit 143 writes the AD conversion result into the latch 1.

[third column]

The determination circuit 142 does not perform the determination process on the signals transmitted from the pixels of the third column, and transmits the signals to the AD conversion circuit 143 together with the determination result of the signals from the pixels of the first column (i.e., the value of the flag FL). Upon receiving the signal from the third column of pixels from the determination circuit 142 along with the value of the flag FL, the AD conversion circuit 143 operates only when the flag FL stores a logic "1" to perform a signal on the pixels from the third column. AD conversion.

Specifically, if the flag FL received from the determination circuit 142 stores a logic "0", that is, if the signal from the pixels of the first column is not at the saturation level, the AD conversion circuit 143 is placed in the standby state and The AD conversion process is not performed on the signals from the pixels of the third column. In addition, if the flag FL stores a logic "1", that is, if the signal from the pixels of the first column is at the saturation level, the AD conversion circuit 143 performs an AD conversion process on the signals from the pixels of the third column, and The AD conversion result is written to the latch 2 of the latch 144'.

The signals from the three pixels are processed by the line circuit 14A-1 in the manner described above. Thereafter, the value of the flag FL and the value of the signal in the two latches 1 and 2 of the latch 144' are read out to the horizontal busbar 18 illustrated in FIG. Due to the signal processing by the row circuit 14A-1, the signals of two of the three pixels are AD-converted and output.

More specifically, if the initial readout signal of the high sensitivity pixel is saturated, the signal of the high sensitivity pixel is not subjected to the AD conversion process, and the signal of the intermediate sensitivity pixel and the signal of the low sensitivity pixel are AD converted. It is written to the two latches 1 and 2 of the latch 144'. Meanwhile, if the initial read signal of the high sensitivity pixel is not saturated, the signal of the high sensitivity pixel and the signal of the intermediate sensitivity pixel are subjected to AD conversion, and the AD conversion result of the signals is written to the latch 144' In the two latches 1 and 2. Signals of low sensitivity pixels are not subjected to the AD conversion process.

The values of the flag FL and the digital signal written in the two latches 1 and 2 of the latch 144' are output to the horizontal bus 18. Next, the signal processing section (e.g., DSP 103 in Fig. 26) performs signal processing on the basis of the values of the signals and flags FL in subsequent stages. Thereby, the dynamic range can be increased.

In the above-described processing example in which signals of a group of three pixels are sequentially read out, the AD conversion circuit 143 operates only twice and is used once in accordance with the determination of the signal level by the determination circuit 142. Therefore, the present example can reduce power consumption as compared with the case where the AD conversion circuit 143 operates three times for the respective signals of three pixels.

In the above, an example in which AD conversion is normally performed on two of three pixels has been described. However, if the signal level of the signal from the pixels of the second column is also determined by the determining circuit 142, and if the signal from the pixels of the second column and the signal from the pixels of the first column are also saturated, the AD conversion circuit 143 It can also be placed in a standby state for signals from pixels of the second column. Under such conditions, a slight change occurs, such as the flag FL becoming two bits. However, this change can be fully predicted by the designer.

As mentioned above, depending on the designer's philosophy, multiple applications are possible. That is, the technical scope of the present invention is not limited to the scope described in the above embodiments. The above-described embodiments may be modified or modified in various ways without departing from the spirit and scope of the invention, and the technical scope of the invention also includes such modified or modified embodiments. It will be apparent to those skilled in the art that the present invention is also applicable to processing signals from four or more pixels having different sensitivities.

The above summary of the row processing performed when the number n is two or three will now be summarized with reference to Figures 7A and 7B, which respectively illustrate the time sequence of operations. 7A and 7B illustrate two processing examples.

As illustrated in Figure 7A, the signal is first read from the pixel of the ith column having the highest sensitivity. In response thereto, the determination circuit 142 determines whether the signal read from the pixels of the i-th column is saturated. In the process, if it is determined that the signal is not saturated, an AD conversion process is performed on the signal from the pixel of the i-th column during the AD conversion period of the i-th column.

Meanwhile, if it is determined that the signal is saturated, the AD conversion process is not performed on the signal during the AD conversion period of the i-th column, and the AD conversion circuit 143 is placed in the standby state. In this process, a determination is made as to whether each of the pixel rows is saturated with a signal of the pixel. Thus, the signal from the pixels of the i-th column can be from a row of pixels subjected to an AD conversion process or from a row of pixels that have not been subjected to an AD conversion process.

Next, the signal is read from the pixel of the (i+1)th column which is less sensitive than the pixel of the i-th column. In the AD conversion period of the (i+1)th column, the signal from the pixel row subjected to the AD conversion process in the i-th column is not subjected to the AD conversion process while the AD conversion circuit 143 is placed in the standby state. At the same time, the signal from the pixel row in the i-th column that has not been subjected to the AD conversion process is subjected to the AD conversion process.

As described above, for example, in the line processing according to the first embodiment, two AD conversion periods are supplied for reading out signals from pixels of two columns. Further, the AD conversion circuit 143 operates in one of two AD conversion periods. As illustrated in FIG. 7B, in a processing example in which readout of signals from pixels of the next column are performed in parallel during an AD conversion period of signals from pixels of a given column, AD conversion circuit 143 is in two AD conversion cycles. Operate in one of them.

The operation of the AD conversion circuit 143 to perform the AD conversion process in one of the two AD conversion periods instructs the AD conversion circuit 143 to be placed in the standby state in another AD conversion period. Therefore, power consumption can be reduced due to the standby state of the AD conversion circuit 143.

In the processing according to the first embodiment or the first modified example described above (by the signal processing of the row circuit 14A or 14A-1), the AD conversion circuit 143 is not constantly held in the operation state, but is appropriately Put it in a standby state to reduce power consumption. The line processing which achieves the reduction of the signal processing time in addition to the reduction in power consumption as the processing according to the second modified example will be described below.

8A and 8B are timing charts each explaining a time sequence of operations of the line circuit according to the second modified example. 8A and 8B illustrate two processing examples. It is assumed that the line circuit according to the second modified example includes a sample/hold (S/H) circuit.

As illustrated in Figure 8A, for example, a signal is first read from a pixel of the ith column of the odd-numbered column. In response thereto, the determination circuit 142 determines whether the signal read from the pixels of the i-th column is saturated. If it is determined that the signal from the pixel of the i-th column is not saturated, the signal is held by the sample/hold circuit. During this process, the unsaturated signal does not have to be held by the sample/hold circuit.

Next, the signal is read from the pixel of the i+1th column of the even column. During this process, if the signal from the pixel of the i-th column is not saturated, the signal from the pixel of the (i+1)th column is prevented from entering the sample/hold circuit. Conversely, if the signal from the pixel of the i-th column is saturated, the signal from the pixel of the (i+1)th column is held by the sample/hold circuit. Next, the process proceeds to the AD conversion cycle, and the AD conversion circuit 143 performs an AD conversion process on the signal held by the sample/hold circuit.

As described above, for example, when the number n is two, in the line processing according to the second modified example, one AD conversion period is set for the pixel readout signals from the two columns. That is, the AD conversion period can be reduced due to the inactive period for which signals are not read out from the two columns. Therefore, the line processing of the present example can increase the signal processing speed as compared with the line processing of the first embodiment or the first modified example in which two AD conversion periods are set for the readout signals from the two columns.

Further, if the signal processing speed of the present example is allowed to be as low as the signal processing speed of the first embodiment or the first modified example, the accuracy of the low-speed signal processing (for example, the conversion accuracy of the AD conversion process) can be improved. In addition, by setting an AD conversion period for the read signals from the two columns, this example can achieve lower power consumption than setting the conditions of the two AD conversion periods.

As illustrated in FIG. 8B, for example, in a processing example in which readout of signals from pixels of the next two columns are performed in parallel during an AD conversion period of signals from pixels of two columns, read out from pixels of two columns The signal can be set to only one AD conversion cycle.

A specific example of the row circuit 14A for carrying out the line processing according to the second modified example described above will be described below.

Fig. 9 is a block diagram showing a configuration example of the line circuit 14A-2 of the first specific example according to the second modified example. In the drawings, components equivalent to the components of FIG. 4 are designated by the same reference numerals.

As illustrated in FIG. 9, the row circuit 14A-2 according to the first specific example is configured to include, in addition to the CDS circuit 141' including the sample/hold circuit, the determination circuit 142, the AD conversion circuit 143, and the latch 144. Multiplexer (MUX) 145. Hereinafter, the CDS circuit 141' is described as a CDS‧S/H circuit 141'.

The multiplexer 145 suitably selects between supplying a signal input to the pixel thereto to the CDS‧S/H circuit 141' via the corresponding vertical signal line 122 and discharging the signal to the ground via the capacitive element C. The CDS‧S/H circuit 141' is basically the same as the CDS circuit 141 of the first embodiment, except that the CDS.S/H circuit 141' includes a sample/hold circuit. Further, the determination circuit 142, the AD conversion circuit 143, and the latch 144 are also substantially identical to their components of the first embodiment.

Subsequently, signal processing by the above-configured line circuit 14A-2 according to the first specific example will be described. For example, at the arrival timing of the signal from the pixel of the i-th column of the odd-numbered column, the determination circuit 142 controls the multiplexer 145 to supply the signal from the pixel of the i-th column to the CDS‧S/H circuit 141'. Thereby, the signal from the pixel of the i-th column is subjected to the CDS processing by the CDS‧S/H circuit 141' and is held by the sample/hold circuit.

The determination circuit 142 determines whether the signal from the pixel of the i-th column held by the CDS‧S/H circuit 141 ^' is saturated. The determination circuit 142 then writes the determination result to the flag FL and maintains identification information identifying the signal from the pixel of the i-th column. In this process, if it is determined that the signal is not saturated, the determination circuit 142 switches the multiplexer 145 to the capacitive element C. At the same time, if it is determined that the signal is saturated, the determination circuit 142 maintains the current state of the multiplexer 145 (connected to the CDS‧S/H circuit 141').

Next, the signal is read from the pixel of the i+1th column of the even column. If the signal from the pixel of the i-th column is not saturated, the multiplexer 145 has switched to the capacitive element C. Therefore, the signal from the pixel of the (i+1)th column is not input to the CDS‧S/H circuit 141', and is discharged to the ground via the capacitive element C. In addition, the CDS‧S/H circuit 141' continues to hold signals from the pixels of the i-th column. If the signal from the pixel of the i-th column is saturated, the signal from the pixel of the (i+1)th column is input to the CDS‧S/H circuit 141' to undergo the CDS processing by the CDS‧S/H circuit 141', Sample and keep.

Then, the process proceeds to the AD conversion cycle. The AD conversion circuit 143 performs AD conversion on the signal supplied from the CDS‧S/H circuit 141', and delivers the AD converted signal to the latch 144. In the process, the AD conversion circuit 143 receives the identification information from the determination circuit 142 indicating that the AD converted signal is from an odd column or an even column, and passes the identification information to the latch 144. Further, the determination circuit 142 switches the multiplexer 145 to the CDS‧S/H circuit 141'. Next, signal processing is repeatedly performed on the signals from the pixels of the i+2th column and the signals from the pixels of the subsequent columns in a similar manner.

With the sequence of signal processing described above, it is possible to obtain a signal by which the previously described process of increasing the dynamic range can be performed. In the signal processing described above, when the signal from the pixel of the (i+1)th column is unnecessary, the switching of the multiplexer 145 to the capacitive element C is performed instead of simply turning off the vertical signal line 122 and the CDS‧S The connection between the /H circuit 141' prevents substantial changes in the capacitance of the vertical signal line 122.

Fig. 10 is a block diagram showing a configuration example of the line circuit 14A-3 of the second specific example according to the second modified example. In the drawings, components equivalent to the components of FIG. 4 are designated by the same reference numerals.

As illustrated in FIG. 10, the row circuit 14A-3 according to the second specific example is configured such that an S/H circuit 146 is provided between the CDS circuit 141 and the AD conversion circuit 143, and is provided in parallel with the S/H circuit 146. Circuit 142 is determined and calculation circuit 147 is provided instead of latch 144. The CDS circuit 141, the determination circuit 142, and the AD conversion circuit 143 are basically the same as those of the first embodiment. Details of the function of the calculation circuit 147 will be described later.

Subsequently, signal processing by the above-configured line circuit 14A-3 according to the second specific example will be described. For example, a signal from a pixel of the i-th column of the odd-numbered column is input to the CDS circuit 141 to undergo the CDS processing by the CDS circuit 141. The determination circuit 142 determines whether the CDS processed signal from the pixel of the i-th column is saturated and writes the determination result into the flag FL.

In this process, the determination circuit 142 also controls the S/H circuit 146. In particular, if the signal from the pixel of the i-th column is not saturated, the determination circuit 142 operates the S/H circuit 146 to hold the signal in the S/H circuit 146. If the signal from the pixel of the i-th column is saturated, the determination circuit 142 may or may not operate the S/H circuit 146.

Thereafter, the signal is read out from the pixel of the (i+1)th column of the even-numbered column, and subjected to the CDS processing by the CDS circuit 141. In this process, the determination circuit 142 references the flag FL. If the signal from the pixel of the i-th column is saturated, the determination circuit 142 operates the S/H circuit 146 to hold the signal from the pixel of the (i+1)th column therein. If the signal from the pixel of the i-th column is not saturated, then the determination circuit 142 does not operate the S/H circuit 146 and causes the S/H circuit 146 to continue to hold the signal from the pixel of the ith column.

Then, the process proceeds to the AD conversion cycle. The AD conversion circuit 143 performs AD conversion on the signal received from the S/H circuit 146, and passes the AD converted signal to the calculation circuit 147. The calculation circuit 147 refers to the result of the AD conversion by the AD conversion circuit 143 and the value of the flag FL received from the determination circuit 142, and performs a process of increasing the dynamic range. The information of the respective accumulation times of the i-th column and the i+1th column (which is common to all the pixel rows) has been input to the calculation circuit 147. In addition, the calculation circuit 147 directly holds the signals from the odd columns and maintains the signals from the even columns multiplied by the cumulative time ratio.

Therefore, a signal subjected to the dynamic range increasing process as a result of the calculation of the calculation circuit 147 can be obtained. That is, the line range circuit 14A-3 according to the second specific example can also perform the dynamic range increasing process described above with respect to the line circuit 14A-3.

Figure 11 is a block diagram showing a configuration example of a row circuit 14A-4 according to a third specific example of the second modified example. In the drawings, components equivalent to the components of FIG. 10 are designated by the same reference numerals. In the example of the row circuit 14A-2 according to the first specific example and the row circuit 14A-3 according to the second specific example, signals from pixels having different sensitivities in two columns (n=2) are processed. At the same time, signals from pixels having different sensitivities in three columns (n=3) are processed according to the example of the row circuit 14A-4 of the third specific example.

As illustrated in Figure 11, the row circuit 14A-4 according to the third specific example is configured to include two sample/hold (S/H) circuits 146 for each pixel row (S/H circuits 1 and 2) ). In terms of other components, the row circuit 14A-4 is substantially identical to the row circuit 14A-3 of the second specific example. Hereinafter, the two S/H circuits 1 and 2 are collectively described as an S/H circuit 146'.

The signals of the pixels are read out from the pixel array section 12 such that three pixels having the same color are successively read out in the order of the i-th column, the i-th column, and the i-th column (i represents a multiple of three). signal. In addition, the pixel of the i-th column has the highest sensitivity, and the signal of the pixel of the i-th column is initially read out in the signal of three pixels, and the pixel of the i+2 column has the lowest sensitivity, in the signal of three pixels. Finally, the signal of the pixel of the i+2th column is read.

The operation of the CDS circuit 141 is the same as that of the first embodiment. The determination circuit 142, the AD conversion circuit 143, and the calculation circuit 147 perform the following different operations on the signals from the pixels of the i-th column, the i-th column, and the i-th column.

[Tier column]

The determination circuit 142 first determines whether the signal from the pixel of the i-th column subjected to the CDS processing by the CDS circuit 141 is saturated, and writes the determination result into the flag FL. Similar to the second specific example, the determination circuit 142 also controls the S/H circuit 146' (S/H circuits 1 and 2). In particular, if the signal from the pixel of the i-th column is not saturated, the determination circuit 142 operates the S/H circuit 1 to hold the signal from the pixel of the ith column therein. If the signal from the pixel of the i-th column is saturated, the determination circuit 142 does not operate both the S/H circuits 1 and 2.

[column i+1]

The determination circuit 142 refers to the value of the flag FL. If the signal from the pixel of the i-th column is saturated, the determination circuit 142 causes the S/H circuit 1 to receive the signal from the pixel of the (i+1)th column subjected to the CDS processing by the CDS circuit 141. If the signal from the pixel of the i-th column is not saturated, the determination circuit 142 causes the S/H circuit 2 to receive a signal from the pixel of the (i+1)th column subjected to the CDS processing by the CDS circuit 141.

[column i+2]

The determination circuit 142 refers to the value of the flag FL. If the signal from the pixel of the i-th column is saturated, the determination circuit 142 causes the S/H circuit 2 to receive a signal from the pixel of the i+2th column subjected to the CDS processing by the CDS circuit 141. If the signal from the pixel of the i-th column is not saturated, the determination circuit 142 does not operate both the S/H circuits 1 and 2.

[AD conversion and thereafter]

Next, the AD conversion circuit 143 performs an AD conversion process on the signal held by the S/H circuit 1, and passes the AD converted signal to the calculation circuit 147. Next, the AD conversion circuit 143 performs an AD conversion process on the signal held by the S/H circuit 2, and passes the AD converted signal to the calculation circuit 147.

On the basis of the value of the flag FL transmitted by the determination circuit 142 and the results of the two AD conversions performed by the AD conversion circuit 143, the calculation circuit 147 performs a dynamic range increase process. The information of the respective accumulation times of the i-th column, the i-th column, and the i-th column (which is common to all the rows) has been input to the calculation circuit 147.

Further, if the signal to be calculated is a signal from a pixel of the i-th column and a signal from a pixel of the (i+1)th column, the calculation circuit 147 performs S _i ×(1 - α ₁ )+S _i+1 ×r ₁ ×α ₁ calculation process and keep the calculation result.

Herein, S _i represents the signal of the i-th column, S _i+1 represents the signal of the i+1th column, and r ₁ represents the sensitivity ratio between the pixel of the i-th column and the pixel of the (i+1)th column, and α ₁ represents a coefficient. As illustrated in Figure 12, the coefficient α ₁ takes the value in the range from zero to one, which is determined by the signal Si of the _i- th column. In the region close to the saturation level, the coefficient α _{1 is} set to a value, and the contribution ratio is increased (close to a value). In particular, the coefficient α ₁ is zero in the region up to about half of the saturation level, and the signal S _i linearly changes from zero to one in the region of the i-th column in the region above about half the saturation level.

If the signal to be calculated is the signal from the pixel of the i+1th column and the signal from the pixel of the i+2th column, the calculation circuit 147 performs S _i+1 ×r ₁ ×(1−α ₂ )+S _i The calculation process of ₊₂ × r ₂ × α ₂ and the calculation result is maintained.

Herein, S _i+2 represents the signal of the i+2th column, r ₂ represents the sensitivity ratio between the pixel of the i-th column and the pixel of the i+2th column, and α ₂ represents the coefficient. As illustrated in Figure 13, the coefficient α ₂ takes the value in the range from zero to one, which is determined by the signal S _{i+1 of the (i+1)th} column. In the region close to the saturation level, the coefficient α _{2 is} set to a value, and the ratio is increased (close to a value). In particular, the coefficient α ₂ is zero in the region up to about half of the saturation level, and the signal S _i+1 linearly changes from zero to the signal in the region of the i+1 column in the region above about half of the saturation level. One.

The signals from the three pixels are thus processed by the row circuit 14A-4 and the output from the calculation circuit 147 representing the result of the processing is read out to the horizontal busbar 18 illustrated in FIG. Thereby, signals from two of the three pixels are synthesized and read out.

If the initial readout signal of the high sensitivity pixel is saturated, the signal of the high sensitivity pixel is not subjected to the AD conversion process. Therefore, the signals of the intermediate sensitivity pixels and the signals of the low sensitivity pixels are synthesized and output. In addition, if the initial readout signal of the high sensitivity pixel is not saturated, the signal of the high sensitivity pixel and the signal of the intermediate sensitivity pixel are subjected to AD conversion and synthesized. Signals of low sensitivity pixels are not subjected to the AD conversion process. Therefore, the operation of the AD conversion circuit 143 for three signals is reduced to two AD conversion processes.

14A and 14B are timing charts each illustrating a time sequence of operations of the row circuit 14A-4 according to the third specific example. 14A and 14B illustrate two processing examples.

In the first processing example of FIG. 14A, signals are read out from the pixels of the i-th column to the pixels of the i+2th column, and thereafter two AD conversions are performed. The second processing example of Fig. 14B is basically the same as the first processing example of Fig. 14A. However, in the second processing example of FIG. 14B, immediately after the signals are read out from the pixels of the i+2th column, the readout signals from the pixels of the i+3th column are performed so as to be from the i+3th column. The readout process of the signals of the pixels performs the AD conversion process in parallel.

Herein, as previously described, the saturated reference signal is primarily in a state where the signal does not substantially linearly respond to the level of the amount of incident light. In the processing according to the third specific example, the signals are read out from the pixels in descending order of sensitivity. However, the line processing can also be achieved in the case where the signal is read out from the pixel in the order of increasing sensitivity.

As described above, by reducing the operation of the AD conversion circuit 143 for three signals to two AD conversion processes, the number of AD conversion processes can be reduced. Therefore, this example can increase the signal processing speed compared to the case where three AD conversion processes are performed on three signals. In addition, if the processing speed of this example is allowed to be the same processing speed (low speed) as the processing speed of the three AD conversion processes performed on the three signals, the accuracy of the low-speed signal processing can be improved (for example, the conversion of the AD conversion process) Accuracy). Lower power consumption can also be achieved by reducing the number of AD conversion processes.

(pixel circuit)

Fig. 15 is a circuit diagram showing an example of the configuration of a pixel circuit according to the first embodiment. As illustrated in FIG. 15, the upper and lower two pixels 30U and 30L respectively include photodiodes (PD) 31U and 31L which are photoelectric conversion elements, and transmission transistors 32U and 32L. In addition, the upper and lower two pixels 30U and 30L are configured to share some of the circuit elements, including, for example, three transistors that reset transistor 33, select transistor 34, and amplifier transistor 35.

In the present example, each of the pixel transistors 32U, 32L, and 33 to 35 (for example) uses an N-channel MOS transistor, but is not limited thereto. In addition, for the drive control of the transmission transistors 32U and 32L, the reset transistor 33, and the selection transistor 34, transmission control lines 1211U and 1211L, reset control lines 1212, and selection control lines are provided for each of the columns. 1213 is used as the pixel drive line 121 previously described.

The transmission transistor 32U is connected between the cathode electrode of the photodiode 31U and the floating diffusion region (FD: floating diffusion capacitor) 36, and the transmission transistor 32L is connected to the cathode electrode of the photodiode 31L and the floating diffusion region 36. between. The high effective transmission pulse TRGu is supplied to the gate electrode of the transmission transistor 32U via the transmission control line 1211U, and the high effective transmission pulse TRG1 is supplied to the gate electrode of the transmission transistor 32L via the transmission control line 1211L. Thereby, the transfer transistors 32U and 32L respectively transfer charges (herein, electrons) photoelectrically converted by the photodiodes 31U and 31L and accumulated in the photodiodes 31U and 31L to the floating diffusion region 36. The floating diffusion region 36 acts as a charge-voltage conversion unit that converts the charge into a voltage signal.

The drain electrode and the source electrode of the reset transistor 33 are respectively connected to the power supply line of the power supply voltage Vdd and the floating diffusion region 36. The high effective reset pulse RST is supplied to the gate electrode of the reset transistor 33 via the reset control line 1212 before the charge is transferred from the photodiodes 31U and 31L to the floating diffusion region 36. Thereby, the reset transistor 33 resets the potential of the floating diffusion region 36.

The drain electrode and the gate electrode of the selection transistor 34 are respectively connected to the power supply line of the power supply voltage Vdd and the selection control line 1213. The high effective selection pulse SEL is supplied to the gate electrode of the selection transistor 34 via the selection control line 1213. Thereby, the transistor 34 is selected to bring the unit pixel (30U or 30L) into a selected state.

The gate electrode, the drain electrode and the source electrode of the amplifier transistor 35 are connected to the floating diffusion region 36, the source electrode of the selection transistor 34, and the vertical signal line 122, respectively. As the selection transistor 34 brings the unit pixel (30U or 30L) into the selected state, the amplifier transistor 35 outputs a signal from the unit pixel (30U or 30L) to the vertical signal line 122.

Specifically, the amplifier transistor 35 outputs the potential of the floating diffusion region 36 reset by the reset transistor 33 as a reset level. Further, the amplifier transistor 35 outputs the potential of the floating diffusion region 36 as a signal level after the transfer transistor 32U or 32L transfers the charge from the photodiode 31U or 31L thereto.

In the examples described herein, each of the unit pixels 30 is based on a four transistor configuration including a transmission transistor 32U or 32L, a reset transistor 33, a selection transistor 34, and an amplifier transistor 35. However, this example is only an example. That is, the pixel configuration of the unit pixel 30 is not limited to a pixel configuration based on a four-transistor configuration, and thus may be, for example, a pixel configuration based on a three-transistor configuration.

Further, in the pixel circuit configured as described above, the selection transistor 34 is connected between the power supply line of the power supply voltage Vdd and the amplifier transistor 35. However, the select transistor 34 can also be configured to be coupled between the amplifier transistor 35 and the vertical signal line 122.

According to the pixel circuit configured as described above, the charge is detected after being transmitted from the photodiode 31U or 31L to the floating diffusion region 36. Therefore, the two pixels 30U and 30L share the same floating diffusion region 36 as a transfer destination of charges. Thereby, the sensitivity characteristics of the two pixels 30U and 30L are equalized. The floating diffusion region 36 as a node connected to the gate electrode of the amplifier transistor 35 has a parasitic capacitance. Therefore, it is not particularly necessary to prepare a capacitor element.

As described above, in the CMOS image sensor 10 including the unit pixels 30 which are rectangular pixels elongated in the horizontal direction of the column and row arrangement, it is possible to form two sets of upper and lower portions by using The preferred ones of the individual signals of the pixels 30U and 30L achieve the following operational effects. Generally, if a video signal is generated based on a signal (or a signal synthesized from the respective signals of the upper and lower two pixels 30U and 30L), the resolution in the vertical direction (orthogonal direction) is reduced. .

However, in the CMOS image sensor 10 configured as described above, the resolution in the vertical direction and the resolution in the horizontal direction are equal, and the upper and lower pixels 30U can be processed substantially similarly to square pixels. 30L. In the image, the sampling pitch in the vertical direction is not equal only in the transition region between the upper and lower two pixels 30U and 30L, in which the amount of signal changes. Therefore, for the sake of completeness, a small process can be additionally performed on the area.

Meanwhile, if the pixel pitch in the vertical direction decreases along with the miniaturization of the pixel and becomes smaller than the resolution of the optical system that receives the incident light, the resolution of the CMOS image sensor 10 is not caused by the pixel pitch in the vertical direction. The resolution of the optical system is determined. Therefore, if the pixel pitch in the vertical direction is smaller than the resolution of the optical system that receives the incident light, it is substantially unnecessary to perform the small process described above on the transition region between the upper and lower two pixels 30U and 30L (in The amount of signal in this transition area changes).

That is, if the pixel is miniaturized beyond the resolution limit and the pixel pitch in the vertical direction becomes smaller than the resolution of the optical system that receives the incident light, the respective signals from the upper and lower pixels 30U and 30L are used. The better of them. By doing so, it is possible to improve the imaging characteristics which deteriorate in the prior art at the same resolution. For example, if the signal of any of the upper and lower two pixels 30U and 30L is a high sensitivity signal and the signal of the other pixel is a low sensitivity signal, and if the high sensitivity signal is saturated, it will be low. The sensitivity signal is used to generate a video signal. Thereby, the dynamic range with respect to the light input can be increased.

(Modify example)

In many CMOS image sensors, individual on-chip color filters 40 have on-wafer lenses placed thereon for improved sensitivity to individual pixels. In the first embodiment, each of the unit pixels 30 has a shape that is long in the horizontal direction. Therefore, it is difficult to accurately collect light by using a lens on a wafer. This is because it is difficult to produce a non-circular on-wafer lens, and it is first difficult to collect light by using a non-circular lens.

[First modified example]

In order to solve the problem of collecting light by using a lens on a wafer, a pixel structure having an aperture ratio of 100% and not using a lens on a wafer, such as a back incident type pixel structure or a photoelectric conversion film laminated type pixel structure, is preferably used. The back incident type pixel structure receives incident light from the opposite side of the wiring layer. The photoelectric conversion film laminate type pixel structure performs photoelectric conversion at a photoelectric conversion film laminated on the incident light side of the wiring layer. An example of a back side incident type pixel structure will be described below.

Fig. 16 is a cross-sectional view showing an example of a back side incident type pixel structure. In this paper, the cross-sectional structure of two pixels is illustrated.

In FIG. 16, a photodiode 42 and a pixel transistor 43 are formed in the meandering portion 41. That is, the weir portion 41 is a device forming portion. Herein, the photodiode 42 corresponds to the photodiodes 31U and 31L of FIG. Further, the pixel transistor 43 corresponds to the transistors 32U, 32L and 33 to 35 of FIG.

On one side of the meandering portion 41, a color filter 45 is formed while the interlayer film 44 is inserted. With this configuration, light incident from one side of the crucible portion 41 is guided to the respective light receiving surfaces of the photodiode 42 via the color filter 45. On the other side of the meandering portion 41, a wiring portion 46 is formed in which respective gate electrodes of the pixel transistors 43 and metal wirings are provided. The surface of the wiring portion 46 facing away from the dam portion 41 is adhered to the support substrate 48 by the adhesive 47.

In the pixel structure described above, the meandering portion 41 in which the photodiode 42 and the pixel transistor 43 are formed has a side surface which will be referred to as a front side facing the wiring portion 46, and will be referred to as a back side of the back side. The side of the wiring portion 46. On the basis of the above definition, the present pixel structure that receives incident light from the back side of the germanium portion 41 is a back incident type pixel structure.

According to the back-illuminated type pixel structure, incident light is received from the opposite side of the wiring portion 46, and thus the aperture ratio can be increased to 100%. Further, the wiring portion 46 is not located on the incident light receiving side. Therefore, incident light can be collected on the respective light receiving surfaces of the photodiode 42 without using the lens on the wafer. As a result, the present example can solve the problem of collecting light by using a lens on a wafer which occurs when each of the unit pixels 30 has rectangular pixels of different sizes in the vertical direction and the horizontal direction.

[Second modified example]

In the first embodiment described above, the shutter scan is performed on the odd-numbered columns and the even-numbered columns, respectively, causing a difference in the accumulation time and thus providing different sensitivity to the upper and lower two pixels. Alternatively, another method of providing different sensitivities can be employed. For example, the ND (neutral density) filter can be adhered only to the even columns, or the on-wafer lens 49 can be provided only to the unit pixels 30 in the odd columns, as illustrated in FIG. The upper and lower two pixels provide different sensitivities. Herein, the ND filter refers to a light amount adjustment filter that substantially uniformly reduces the amount of light in the visible range without affecting color.

[Second embodiment]

FIG. 18 is a configuration diagram illustrating an example of a pixel array in the pixel array section 12 according to the second embodiment. As illustrated in FIG. 18, the pixel array section 12 includes unit pixels 30 each including a photoelectric conversion element and two-dimensionally arranged in a plurality of columns and rows. Here, each of the unit pixels 30 is a so-called rectangular pixel that is long in the vertical direction, and its vertical size (row direction) is twice the horizontal size (column direction), that is, it has a vertical of 2:1. Ratio to horizontal spacing.

If the CMOS image sensor 10 is capable of picking up a color image, a plurality of (for example, two) unit pixels 30 adjacent in the horizontal direction form a group. The set of left and right pixels is provided with on-wafer color filters 40 having the same color. In particular, each of the odd columns includes a color array having a repeating GGBB combination, and each of the even columns includes a color array having a repeating RRGG combination. The colors of the left and right pixels are the same. Therefore, a color filter can cover the left and right pixels.

In the pixel array of the pixel array section 12, each of the unit pixels 30 is a rectangular pixel having a vertical and horizontal size ratio of 2:1 in the vertical direction. Therefore, as illustrated in FIG. 18, the shape of the individual on-wafer color filters 40 of the group of left and right two pixels is square. The square wafer on color filter 40 is provided to a pixel array in which two rows of repeating GR combinations in the color array alternate with two rows of repeating BG combinations in the color array. Thus, the total color array of color filters 40 on the wafer is a Bayer array.

Advantages similar to those of the first embodiment are obtained by the on-wafer color filter 40 configured to have a color array based on two pixel units. That is, along with the miniaturization of the CMOS process, the pixel has been increasingly miniaturized. However, it has become increasingly difficult to miniaturize color filters in accordance with miniaturization of pixels. This is because it is difficult to miniaturize the color filter while preventing the rounding and peeling of the corners while maintaining its spectral characteristics. However, the on-wafer color filter 40 of the above-described configuration example can be formed in the size of two pixels combined, and thus is advantageous in miniaturization of pixels.

(scanning method)

Referring to Fig. 19, a pixel array of a pixel array section 12 according to the second embodiment will now be described (i.e., two rows having a repeating GR combination in a color array and two rows having a repeated BG combination in a color array are alternated. The pixel method) performs the scanning method. This scanning is performed in accordance with the driving operation by the vertical driving section 13 of FIG.

The scanning according to the second embodiment is performed on the different electronic shutter columns between the even rows and the odd rows. Thereby, the even rows and the odd rows have different accumulation times and thus different sensitivities. A read operation is performed twice for each of the columns, that is, first for odd rows and then for even rows. In this example, the signal from each of the pixels in the odd rows is a high sensitivity signal corresponding to a long time accumulation, and the signal from each of the pixels in the even rows corresponds to a short time accumulation Low sensitivity signal.

(pixel circuit)

Fig. 20 is a circuit diagram showing an example of the configuration of a pixel circuit according to the second embodiment. In the drawings, components equivalent to the components of Fig. 15 are designated by the same reference numerals.

As illustrated in FIG. 20, the pixel circuit according to the second embodiment is configured such that adjacent ones of the left and right pixels having the same color share a portion of the circuit to equalize the offset and sensitivity characteristics between the left and right pixels. And performing a shutter operation and a read operation on the odd-numbered rows and the even-numbered rows, respectively. Hereinafter, the pixel 30 on the left side and the pixel 30 on the right side are referred to as an odd-line pixel 30o and an even-line pixel 30e, respectively.

Specifically, the left and right pixels 30o and 30e include photodiodes (PD) 31o and 31e and transmission transistors 32o and 32e, respectively. In addition, the two pixels 30o and 30e share some of the circuit elements, including, for example, three transistors that reset the transistor 33, select the transistor 34, and the amplifier transistor 35.

Typically, the pixels in the same column are driven by the same line, as in the first embodiment. However, in the second embodiment, odd and even rows are assigned different lines for driving the respective gate electrodes of the transfer transistors 32 (32o and 32e). Specifically, the gate electrode of the transmission transistor 32o of the odd-line pixel 30o is driven by the transmission line 1211o for the odd-numbered rows, and the gate electrode of the transmission transistor 32e of the even-line pixel 30e is driven by the transmission line 1211e for the even-numbered rows.

The connection relationship between the reset transistor 33, the selection transistor 34, and the amplifier transistor 35 is substantially the same as that in the pixel circuit according to the first embodiment. However, in the pixel circuit according to the second embodiment, the selection transistor 34 is connected between the amplifier transistor 35 and the vertical signal line 122. Meanwhile, in the pixel circuit according to the first embodiment, the selection transistor 34 is connected between the power supply line of the power supply voltage Vdd and the amplifier transistor 35. The pixel circuit according to the second embodiment can be alternatively configured such that the selection transistor 34 is connected between the power supply line of the power supply voltage Vdd and the amplifier transistor 35, similarly to the pixel circuit according to the first embodiment.

In the pixel circuit configured as described above, in the shutter operation for the odd-numbered rows, the gate electrode of the reset transistor 33 is supplied with the high-state effective reset pulse RST, and the gate electrode of the transistor 32o for the odd-numbered row is transferred. Supply high-state effective transfer pulse TRGo. Thereby, the charge of the floating diffusion region 36 is removed, and thereafter the accumulation of odd rows is started. Meanwhile, in the shutter operation of the even rows, the gate electrode of the reset transistor 33 is supplied with the high effective reset pulse RST, and the gate electrode of the transfer transistor 32e of the even row is supplied with the high effective transfer pulse TRGe. Thereby, the charge of the floating diffusion region 36 is removed, and thereafter the accumulation of even columns is started.

(line processing section)

Fig. 21 is a block diagram showing an example of the configuration of the line circuit 14B according to the second embodiment. In the drawings, components equivalent to the components of FIG. 4 are designated by the same reference numerals.

In the second embodiment, adjacent ones of the left and right pixels 30o and 30e form a group. Therefore, the row circuit 14B according to the second embodiment is provided for every two adjacent rows. In addition, row circuit 14B is configured to include CDS circuit 141, determination circuit 142, AD conversion circuit 143, and latch 144, and also includes input segments provided to row circuit 14B and, for example, for use in odd rows A switch that is selected between the even rows forms a selected segment 148.

The selection section 148 first selects signals from odd rows and then selects signals from even rows. Due to the selection of the selection section 148, the signals from the odd rows and the signals from the even rows are sequentially processed by the CDS circuit 141, the determination circuit 142, the AD conversion circuit 143, and the latch 144. The CDS circuit 141, the determination circuit 142, the AD conversion circuit 143, and the latch 144 perform processing operations similar to those of the first embodiment.

As described above, even if the CMOS image sensor 10 including the unit pixel 30 which is a rectangular pixel having a vertical and horizontal size ratio of 2:1 and which is long in the vertical direction of the column and row arrangement, the pixel is miniaturized The imaging characteristics can be improved by exceeding the resolution limit and the pixel pitch in the horizontal direction becomes smaller than the resolution of the optical system that receives the incident light. For example, if the signal of any of the left and right pixels 30o and 30e is a high sensitivity signal and the signal of the other pixel is a low sensitivity signal, and if the high sensitivity signal is saturated, the sensitivity is low. The signal is used to generate a video signal. Thereby, the dynamic range with respect to the light input can be increased.

[Third embodiment]

In the second embodiment, one portion of the pixel circuit is shared by the left and right pixels 30o and 30e. Meanwhile, the third embodiment employs a large CMOS image sensor and is configured such that one portion of the pixel circuit is not shared by the left and right pixels 30o and 30e. In a configuration that provides an additional process, such as in a large CMOS image sensor, even if pixels 30o and 30e do not share a portion of the pixel circuit, offset and sensitivity can be made between adjacent left and right pixels 30o and 30e. Degree characteristics are equal. The pixel array and color coding of this embodiment are the same as the pixel array and color coding of the second embodiment.

(pixel circuit)

Fig. 22 is a circuit diagram showing an example of the configuration of a pixel circuit according to the third embodiment. In the drawings, components equivalent to the components of FIG. 20 are designated by the same reference numerals.

As illustrated in FIG. 22, in the pixel circuit according to the third embodiment, the left and right pixels 30o and 30e do not share one portion of the pixel circuit, but assign different lines to the odd and even rows of the same column for driving transmission. The respective gate electrodes of the transistors 32o and 32e. Specifically, the gate electrode of the odd row pixel 30o is driven by the transmission line 1211o for odd rows, and the gate electrode of the even row pixel 30e is driven by the transmission line 1211e for even rows. The respective signals (with signal level and reset level) from the left and right pixels 30o and 30e are respectively read out to different vertical signal lines 122o and 122e for the odd-numbered rows and the even-numbered rows.

(scanning method)

By performing transmission and driving operations performed by different transmission lines 1211o and 1211e for odd-numbered rows and even-numbered rows in the same column, respectively, it is possible to scan odd-numbered rows and even-numbered rows, respectively, in the shutter operation, and simultaneously scan in the readout operation. Odd and even lines. Figure 23 illustrates the procedure for scanning. As illustrated in Fig. 23, the shutter operation is performed on the odd-numbered rows and the even-numbered rows, respectively, but at the same time, the readout operation is performed on each of the columns.

(line processing section)

Fig. 24 is a block diagram showing an example of the configuration of the line circuit 14C according to the third embodiment. In the drawings, components equivalent to the components of FIG. 4 are designated by the same reference numerals.

In the third embodiment, the signal level and the reset level are supplied via the different vertical signal lines 122o and 122e in the left and right two pixels 30o and 30e, respectively. Accordingly, the row circuit 14C according to the third embodiment is configured to include different CDS circuits 141o and 141e for odd and even rows, respectively.

In the row circuit 14C, the CDS circuits 141o and 141e perform denoising processing on the odd-numbered rows and the even-numbered rows, respectively, and supply the odd-numbered rows of the de-noise signals and the even-numbered de-noising signals to the determining circuit 142, respectively. The determination circuit 142 determines which of the signals of the odd rows and the signals of the even rows are to be used. For example, if the signal corresponding to the odd-numbered lines accumulated for a long time does not reach the saturation level, the signals of the odd lines are used. If the signal of the odd line has reached the saturation level, the signal of the even line is used. Next, the determination circuit 142 selects the signal to be used and outputs the signal and the determination result.

The AD conversion circuit 143 performs AD conversion on the signal supplied from the determination circuit 142, and writes the AD-converted signal into the latch 144. The determination result is written into the latch 144 via the AD conversion circuit 143 as a flag FL. The determination results and signals are then processed at a later stage to obtain an image with an increased dynamic range. Compared to the second embodiment, the present embodiment performs only one readout operation for each of the columns, and thus is advantageous in terms of high speed processing.

Also in the third embodiment, an operational effect similar to that of the second embodiment can be obtained. For example, if the signal of any of the left and right pixels 30o and 30e is a high sensitivity signal and the signal of the other pixel is a low sensitivity signal, and if the high sensitivity signal is saturated, the sensitivity is low. The signal is used to generate a video signal. Thereby, the dynamic range with respect to the light input can be increased.

<3. Modify the instance>

The first to third embodiments described above are configured such that rectangular pixels each having a vertical to horizontal size ratio of 1:2 (2:1) are used as the unit pixel 30, and in the unit pixel 30 Each of the upper and lower two pixels or two pixels per left and right forms a group. However, the configuration is not limited to this. For example, the configuration can be modified such that the vertical to horizontal size ratio of the pixels is set to 1:3 or 1:4, and every three or four vertical or horizontally adjacent pixels in the pixel form a group. With this configuration, signals from three or four pixels can be processed.

Moreover, the first to third embodiments are configured to output a signal that forms either of a set of two pixels. This configuration can be modified to synthesize a single signal from individual signals of two pixels. If a single signal is thus selected or synthesized from a signal forming a plurality of pixels, a signal similar to that from a square pixel can be obtained.

Further, in the first to third embodiments, for example, signal processing performed to increase the dynamic range has been described. However, signal processing is not limited to this example. For example, when two pixels form a group, when light is emitted from a light source such as a light emitting diode and applied to an object to detect an object, a signal from one of the pixels can be used to be reflected based on the object. Light object signal. Furthermore, the signal from another pixel can be used as a background signal based on the background light of the object. Then, if subtraction processing is performed on the respective signals from the two pixels to remove the background light from the subtraction result, a signal appearing to be a signal from a square pixel (square grid) can be obtained.

As mentioned above, a variety of other applications are conceivable in addition to the application examples for increasing the dynamic range. In any case, when signals from two pixels are processed as signals from square pixels, it is preferable that the pixel pitch in the vertical direction of the pixel array and the pixel pitch in the horizontal direction are equal to or Less than the resolution of the optical system that receives the incident light.

Moreover, the first to third embodiments are configured to read signals from the R, G, and B pixels to the common vertical signal line 122. This configuration can be modified to read out signals from R, G, and B pixels to different vertical signal lines. For example, as illustrated in FIG. 25, signals from G pixels and signals from B and R pixels can be read out to different vertical signal lines 122g and 122br, respectively.

In this case, for example, a row circuit 14g for G pixels is provided on the lower side of the pixel array section 12, and a row circuit 14br for B and R pixels is provided on the upper portion of the pixel array section 12. On the side. Further, the signal from the G pixel is read out to the lower side of the drawing via the vertical signal line 122g, and the signals from the B and R pixels are read out to the upper side of the drawing via the vertical signal line 122br. Next, signal processing such as denoising is performed at the line circuits 14g and 14br, respectively.

Further, in the first to third embodiments, the example in which the present invention is applied to a CMOS image sensor capable of picking up color images has been described. However, the present invention is equally applicable to a CMOS image sensor capable of picking up a monochrome image.

The example in which the present invention is applied to a CMOS image sensor including a unit pixel arranged in columns and rows and detecting a signal charge according to the amount of visible light as an entity amount has been described above. However, the application of the present invention is not limited to CMOS image sensors. Accordingly, the present invention is generally applicable to a solid-state imaging device such as a CCD image sensor.

The solid-state imaging device may be embodied as a wafer or as a module having an imaging function and including an imaging section and a signal processing section or an optical system as a package.

<4. Electronic equipment>

A solid-state imaging device according to an embodiment of the present invention is generally mountable and used in an electronic device that uses a solid-state imaging device in its image capturing unit (photoelectric conversion unit). The electronic device includes an imaging device (camera system) such as a digital still camera and a video camera, a mobile terminal device having an imaging function such as a mobile phone, a photocopier using a solid-state imaging device in its image reading unit, and the like. In some cases, the above-described modular embodiment (i.e., camera module) mounted in an electronic device forms an imaging device.

(imaging device)

FIG. 26 is a block diagram showing an example of a configuration of one of electronic devices (for example, an imaging device) according to an embodiment of the present invention. As illustrated in FIG. 26, an imaging apparatus 100 according to an embodiment of the present invention includes an optical system including a lens group 101 and the like, an imaging device 102, a DSP circuit 103 serving as a camera signal processing unit, and a frame memory. The body 104, a display device 105, a recording device 106, an operating system 107, a power supply system 108, and the like. The imaging device 100 is configured such that the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operating system 107, and the power supply system 108 are connected to each other via the bus bar 109.

The lens group 101 receives incident light (image light) from an object, and forms an image on the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light of the image formed by the lens group 101 as an image on the imaging surface into an electric signal in units of pixels, and outputs the converted electric signal as a pixel signal. As the imaging device 102, a solid-state imaging device such as the CMOS image sensor 10 according to the above embodiment can be used.

Here, the shorter of the pixel pitch in the vertical direction and the pixel pitch in the horizontal direction of the pixel array in the imaging device 102 is equal to or smaller than the resolution of the optical system including the lens group 101. The DSP circuit 103 receives the pixel signal from the imaging device 102 and indicates that the pixel signal is a signal corresponding to a high-sensitivity signal accumulated for a long time or a low-sensitivity signal corresponding to a short-time accumulation (flags in FIGS. 4, 21, and 24). Mark FL) and perform signal processing for increasing the dynamic range.

In particular, if the flag FL supplied by the imaging device 102 indicates that the high sensitivity signal is not saturated (FL=0), the DSP circuit 103 is generated by using the flag FL as a pair of high sensitivity signals. Video signal. If the flag FL indicates that the high sensitivity signal is saturated (FL = 1), the DSP circuit 103 generates a video signal by synthesizing the saturation level using the signal level with the flag FL as a pair of supplied low sensitivity signals. With the signal processing described above, the dynamic range with respect to the light input can be increased.

The processing performed by DSP circuit 103 is the same as the signal processing performed to process signals from square pixels. It goes without saying that the processing can be designed taking into account the actual configuration of the pixels. However, if the processing is the same as the signal processing performed on the signals from the square pixels, it is not necessary to take into account the signal processing designed for the actual configuration change of the pixels. Thus, substantially the same image can be produced at a lower cost than signal processing designed with the actual configuration of the pixels in mind. In addition, it is possible to make a plurality of pixels look like square pixels while reducing the semaphore of a plurality of pixels. Therefore, this signal processing can be achieved with lower power consumption and is extremely versatile.

The display device 105 includes a panel type display device such as a liquid crystal display device and an organic EL (electroluminescence) display device, and displays moving or still images picked up by the imaging device 102. The recording device 106 records a moving or still image picked up by the imaging device 102 on a recording medium such as a video tape and a DVD (Digital Video Disc).

The operating system 107 issues operational commands regarding various functions of the imaging device 100. The power supply system 108 appropriately supplies a plurality of power sources for operating power to the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operating system 107.

As described above, if the imaging device 100 such as a camera system and a camera module for a mobile device such as a mobile phone uses the CMOS image sensor 10 according to the above embodiment as its imaging device 102, the following operational effects can be obtained. . That is, even if the shorter of the pixel pitch in the vertical direction and the pixel pitch in the horizontal direction of the pixel array in the imaging device 102 is equal to or smaller than the resolution of the optical system including the lens group 101, the imaging characteristics can be improved.

The present application contains Japanese Priority Patent Application No. JP 2008-099111, filed on Jan. 7, 2008, the Japanese Patent Application, and JP-A The subject matter disclosed in the disclosure of 2009-092854, the entire contents of which are hereby incorporated by reference.

Those skilled in the art should understand that various modifications, combinations, sub-combinations and changes in the visual design requirements and other factors may occur as long as they are within the scope of the appended claims or their equivalents.

10. . . CMOS image sensor

11. . . Semiconductor substrate/wafer

12. . . Pixel array section

13. . . Vertical drive section

14. . . Row processing section

14A. . . Row circuit

14A-1. . . Row circuit

14A-2. . . Row circuit

14A-3. . . Row circuit

14A-4. . . Row circuit

14B. . . Row circuit

14br. . . Row circuit

14C. . . Row circuit

14g. . . Row circuit

15. . . Horizontal drive section

16. . . Output circuit section

17. . . System control section

18. . . Horizontal bus

19A. . . Normal phase output terminal

19B. . . Reverse phase output terminal

20. . . Input and output terminal group

twenty one. . . Input and output terminal group

30. . . Unit pixel

30e. . . Even row pixels

30L. . . Lower pixel

30o. . . Odd row pixels

30U. . . Upper pixel

31o, 31e. . . Photodiode (PD)

31U, 31L. . . Photodiode (PD)

32o, 32e. . . Transmission transistor

32U, 32L. . . Transmission transistor

33. . . Reset transistor

34. . . Select transistor

35. . . Amplifier transistor

36. . . Floating diffusion zone

40. . . Color filter on the wafer

41. . .矽 part

42. . . Photodiode

43. . . Pixel transistor

44. . . Interlayer film

45. . . Color filter

46. . . Wiring part

47. . . Adhesive

48. . . Support substrate

49. . . On-wafer lens

100. . . Imaging equipment

101. . . Lens group

102. . . Imaging device

103. . . DSP circuit

104. . . Frame memory

105. . . Display device

106. . . Recording device

107. . . operating system

108. . . Power Systems

109. . . Bus line

121. . . Pixel drive line

122. . . Vertical signal line

122g, 122br. . . Vertical signal line

122o, 122e. . . Vertical signal line

141. . . CDS circuit

141'. . . CDS‧S/H circuit

141o, 141e. . . CDS circuit

142. . . Determination circuit

143. . . AD conversion circuit

144. . . Latches

144'. . . Latches 1 and 2

145. . . Multiplexer (MUX)

146. . . Sample/hold (S/H) circuit

146'. . . S/H circuit 1 and 2

147. . . Calculation circuit

148. . . Select section

1211U, 1211L. . . Transmission control line

1211o, 1211e. . . Transmission line

1212. . . Reset control line

1213. . . Select control line

RST. . . High state effective reset pulse

SEL. . . High effective selection pulse

TRGe. . . High effective transmission pulse

TRGl. . . High effective transmission pulse

TRGo. . . High effective transmission pulse

TRGu. . . High effective transmission pulse

Vdd. . . voltage

1 is a system configuration diagram illustrating an overview of a system configuration of a CMOS image sensor according to an embodiment of the present invention;

2 is a configuration diagram illustrating an example of a pixel array in a pixel array section according to the first embodiment;

3 is a conceptual diagram illustrating a procedure of a scanning method performed on a pixel array in a pixel array section according to the first embodiment;

4 is a block diagram showing an example of a configuration of a line circuit according to the first embodiment;

5 is a configuration diagram illustrating an example of a pixel array in a pixel array section in which three pixels having different sensitivities form a group;

Figure 6 is a block diagram showing a configuration example of a line circuit according to a first modified example of the first embodiment;

7A and 7B are timing charts each illustrating a time sequence of operations of the line circuit according to the first embodiment or the first modified example;

8A and 8B are timing charts each explaining a time sequence of operations of a line circuit according to a second modified example of the first embodiment;

Figure 9 is a block diagram showing a configuration example of a line circuit of the first specific example according to the second modified example;

Figure 10 is a block diagram showing a configuration example of a line circuit according to a second specific example of the second modified example;

Figure 11 is a block diagram showing a configuration example of a line circuit of a third specific example according to a second modified example;

Figure 12 is a diagram for explaining the relationship between the coefficient in the signal processing for the row circuit according to the third specific example and the signal from the pixel of the i-th column;

Figure 13 is a diagram for explaining the relationship between the coefficient in the signal processing for the row circuit according to the third specific example and the signal from the pixel of the (i+1)th column;

14A and 14B are timing charts each illustrating a time sequence of operations of a row circuit according to a third specific example of the second modified example;

15 is a circuit diagram showing an example of a configuration of a pixel circuit according to the first embodiment;

Figure 16 is a cross-sectional view showing an example of a back side incident type pixel structure;

Figure 17 is a configuration diagram for explaining a modified example of the first embodiment;

18 is a configuration diagram illustrating an example of a pixel array in a pixel array section according to the second embodiment;

19 is a conceptual diagram illustrating a procedure of a scanning method performed on a pixel array in a pixel array section according to the second embodiment;

20 is a circuit diagram illustrating an example of a configuration of a pixel circuit according to a second embodiment;

Figure 21 is a block diagram showing an example of the configuration of a line circuit according to the second embodiment;

22 is a circuit diagram illustrating an example of a configuration of a pixel circuit according to a third embodiment;

23 is a conceptual diagram illustrating a procedure of a scanning method performed on a pixel array in a pixel array section according to the third embodiment;

Figure 24 is a block diagram showing an example of the configuration of a line circuit according to the third embodiment;

Figure 25 is a configuration diagram illustrating a modified example of the signal reading system;

26 is a block diagram showing a configuration example of an image forming apparatus as an example of an electronic apparatus according to an embodiment of the present invention; and

Figure 27 is a graph illustrating the relationship between the F value of the lens and the resolution limit.

30. . . Unit pixel

40. . . Color filter on the wafer

Claims (14)

A solid-state imaging device comprising: a pixel array segment configured by a plurality of rectangular pixels, each of the plurality of rectangular pixels having different sizes in a relative vertical direction and a horizontal direction, and more One set of adjacent rectangular pixels are combined to form a square pixel having the same size in the vertical direction and the horizontal direction, wherein the rectangular pixels forming the square pixel have different exposure times, and in the plural One of the pixel pitches in the vertical direction and one of the pixel pitches in the horizontal direction of the rectangular pixels is equal to or less than a resolution of directing incident light to one of the optical system segments. A solid-state imaging device according to claim 1, wherein the rectangular pixels forming the square pixel share a color filter. A solid-state imaging device according to claim 1, wherein the rectangular pixels forming the square pixel have different sensitivities. A solid-state imaging device according to claim 3, further comprising: a signal processing section configured to perform a process of outputting a plurality of signals read from the set of rectangular pixels as a single signal, wherein The plurality of signals are two signals including one signal from a high sensitivity pixel and one signal from a low sensitivity pixel, and the signal processing section is not saturated in the signal from the high sensitivity pixel At time, the signal from the high sensitivity pixel is output, and the signal from the low sensitivity pixel is output when the signal from the high sensitivity pixel is at the saturation level. A solid-state imaging device according to claim 1, wherein the rectangular pixels forming the square pixel share a pixel circuit element. The solid-state imaging device of claim 1, wherein the rectangular pixels forming the square pixel have a back-incident type pixel structure that receives incident light from an opposite side of a wiring forming layer, or is laminated on a wiring forming layer A photoelectric conversion film laminated type pixel structure is performed at one of the photoelectric conversion films on the incident light side. A solid-state imaging device comprising: a pixel array section configured to include pixels arranged in columns and rows in two dimensions; and a signal processing section configured to include a determining circuit When the number n (2 n) when the pixels form a set and sequentially read a number n of signals from the number n of pixels in the pixel array section, the determining circuit determines in the reading of each of the number n of signals Whether a signal is equal to or greater than a predetermined value, and the signal processing section is configured to be a number m (1) based on the determined result of the determining circuit m<n) signals perform predetermined signal processing, where m is less than n, wherein the pixels forming the set have different exposure times, and the signal processing section is provided for the pixels of the pixel array section Each of the lines. A solid-state imaging device according to claim 7, wherein the number n of pixels has different sensitivities. The solid-state imaging device of claim 8, wherein the number n of signals are input to the determining circuit in descending order of sensitivity of the respective pixels, and wherein the signal processing section is not determined by the number of n signals The circuit determines to perform the predetermined signal processing to be equal to or greater than the predetermined value. A solid-state imaging device according to claim 7, wherein the signal processing section maintains for each of the number of m signals to identify which of the number n of signals corresponds to information of the signal. A signal processing method for a solid-state imaging device, the signal processing method comprising the steps of: performing signals on respective rectangular pixels of one pixel array segment configured by a plurality of rectangular pixels via a signal processing section Processing, each of the rectangular pixels has a different size in a relative vertical direction and a horizontal direction, and one of the plurality of adjacent rectangular pixels is combined to form the same size in the vertical direction and the horizontal direction a square pixel, the signal processing comprising: reading a number n of signals from a number of n rectangular pixels of the pixel array segment, determining whether a signal is determined in a readout of each of the number n of signals Equal to or greater than a predetermined value, and based on the result of one of the determinations, a number m (1) m<n) signals perform predetermined signal processing, where m is smaller than n; wherein the rectangular pixels forming the square pixel have different exposure times, and the plurality of signals are read out from the plurality of combined rectangular pixels, the signal A processing segment is provided for each of the pixel rows for the pixel array segment, and the plurality of signals read from the plurality of rectangular pixels are processed and output as a single signal. A signal processing method for a solid-state imaging device according to claim 11, wherein the plurality of signals comprise a signal from a high sensitivity pixel and a signal from a low sensitivity pixel, wherein when the signal is from the high sensitivity When the signal is not at the saturation level, the signal from the high sensitivity pixel is used to generate a video signal, and when the signal from the high sensitivity pixel is at the saturation level, the low sensitivity pixel will be from the low sensitivity pixel. This signal is used to generate a video signal. A signal processing method for a solid-state imaging device, the signal processing method comprising the steps of: processing a signal from one of a plurality of rectangular pixel segments configured by a plurality of rectangular pixels, each of the plurality of rectangular pixels Having different sizes in opposite vertical and horizontal directions, and a set of a plurality of adjacent rectangular pixels are combined to form a square pixel having the same size in the vertical direction and the horizontal direction, wherein the square is formed The rectangular pixels of the pixels have different exposure times, and the plurality of signals of different sensitivities are read from the combined plurality of rectangular pixels, the plurality of signals are processed to form a signal of a square grid, and the rectangle One of the pixel pitches of the set of pixels in the vertical direction and one of the pixel pitches in the horizontal direction is equal to or less than a resolution of an optical system. An electronic device comprising: a solid state imaging device configured to include a pixel array segment having a plurality of rectangular pixels, each of the plurality of rectangular pixels being in a relative vertical direction and horizontal There are different sizes in the direction, and one of a plurality of adjacent ones of the set of rectangular pixels is combined to form a square pixel having the same size in the vertical direction and the horizontal direction, and the solid-state imaging device is configured to process Self-formation The rectangular pixels of the square pixels read the plurality of signals and output the processed signals as a single signal; and an optical system configured to receive light incident on an imaging surface of the solid state imaging device The rectangular pixels forming the square pixel have different exposure times, and one of the pixel pitches in the vertical direction of the set of rectangular pixels and one of the pixel pitches in the horizontal direction is equal to Or less than a resolution of the optical system.