JP2002165136A - Imaging apparatus and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start and finish scanning of shift register operation from voluntary position, by merely using a simple circuit configuration. SOLUTION: This imaging apparatus has plural pixels for carrying out photoelectric conversion from a light information to an electrical signal, a switching means for switching both the first readout mode reading out electrical signals with high resolution from plural pixels, the second readout mode for reading out electrical signals with low resolution from plural pixels, and a readout means for starting and finishing scanning, through read out in a voluntary pixel position among plural pixels in both the first readout mode and the second readout mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus and an image pickup system, and more particularly, to high-resolution image pickup such as a still image, and
The present invention relates to an imaging apparatus and an imaging system that can select an operation that can simultaneously perform low-resolution imaging such as a moving image and that can perform random access.

[0002]

2. Description of the Related Art A digital still camera has an image pickup device exceeding 2 million pixels in the mainstream, while a video camera requires 4 pixels in the image pickup device.
It is about 100,000 pixels. A method disclosed in Japanese Patent Application No. 11-151615 is an example of a method for efficiently creating a low pixel required by the video camera from a high pixel of 2 million pixels. This is not to thin out and read out necessary pixels, but to add pixels of the same color of a color filter arranged in a matrix, enabling low-speed driving at the time of addition, and S / N compared to simple thinning. Is good.

[0003]

SUMMARY OF THE INVENTION The present invention, in the above configuration, has a lower power consumption in a system in which only a certain angle of view needs to be read, such as an electronic zoom, in a low-resolution read mode. An image pickup apparatus and an image pickup system that can be driven by electric power are provided.

[0004]

According to the present invention, there is provided an imaging apparatus comprising: a plurality of pixels for photoelectrically converting optical information into an electric signal; a first read mode for reading the electric signal from the plurality of pixels at a high resolution; Switching means for switching between a plurality of pixels and a second read mode for reading the electric signal at a low resolution; and any one of the plurality of pixels in the first read mode and the second read mode. And a reading means for starting and ending the reading scan at the position.

[0005] An imaging system according to the present invention includes the imaging apparatus according to the present invention, an optical system that forms light on the imaging apparatus, and a signal processing circuit that processes an output signal from the imaging apparatus.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, the overall configuration of an image pickup apparatus to which this embodiment is applied will be described. The configuration of this imaging device is the configuration disclosed in Japanese Patent Application No. 11-151615.

FIG. 8 is a schematic explanatory view showing a pixel signal reading method by the image pickup apparatus according to the present embodiment. In FIG. 8, the output of the image sensor has four channels, the color filters of the pixels arranged in a matrix of the image sensor are arranged in a checkered pattern, the G (green) filter is arranged in half of the checkered pattern, The R (red) filter and the B (blue) filter are respectively arranged in half on the other half of the checkered pattern.

In the case of high-resolution reading (system 1), each pixel signal is read independently. That is, from the output A, the pixel signals G11, G13, G15.
Are output from the output B, and pixel signals G22, G24, G26,...
From the pixel signals B21, B23,
B25... Are output, and the readout circuit 11 is output from the output D.
2 output pixel signals R12, R14, R16,.

In low-resolution reading (system 2), pixel signals of the same color are added and read, and signals from oblique pixels provided with a G filter are added and read for two rows by a reading circuit 111. A signal from a pixel in the horizontal direction provided with the B filter is output to a readout circuit 112.
, Two rows are added and read. That is, from the output A, the pixel signals G11 + G22, G
13 + G24,... And pixel signals G15 + G26, G17 + G
, And the read circuit 11 is output from the output C.
2 output pixel signals B21 + B23, B25 + B27,..., And the output D outputs pixel signals R12 + R14, R16 + R18,. In addition,
Here, no signal is output from output B, but output A
Output pixel signals G11 + G22, G15 + G26,..., And output B outputs pixel signals G13 + G24, G17 + G28.
.. may be output.

The image sensor has a number of pixels of 1000 V × 2000.
H 2 million pixels for high vision sensor.

In the case of the high-definition moving image of the system 1,
Each color signal from each output (A, B, C, D) is about 40 MH
z (2 million pixels x 60 fields / second x (4/3))
(4/3 takes into account the blanking period.) In the case of a high-definition still image (digital still camera) of the system 1, for example, at 6 frames / second, the image is output at about 4 MHz.

Next, assuming that the system 2 performs NTSC interlaced scanning, about 10 MHz for 4-channel output (1/2 for interlaced scanning and 1/2 for addition) (about 1 G when an added signal of G is output on one channel). 20 MHz).

In the system 2, in two pixel rows, the G signal is obliquely added, and the R and B signals are horizontally added. By obliquely adding the G signal, the resolution of G (green) becomes R
(Red) and B (blue) have twice the resolution.

If the high-frequency component of G is used as the high-frequency component of the luminance signal, high resolution can be obtained, and there is no signal to be discarded and discarded, so that power consumption can be reduced by low-speed driving.

FIG. 9 is a circuit diagram showing a CMOS sensor and a read circuit. Since the CMOS sensor has variations in pixel amplifiers and reset noise in the gate section, a signal memory CT1 and a noise memory CT2 are provided in the output section to remove the noise, and the noise is removed by subtraction processing.

In FIG. 9, a broken line area indicates one pixel portion of a CMOS sensor, PD is a photodiode, MTX is a transfer transistor, MRES is a reset transistor, MSF is an amplifying transistor serving as a pixel amplifier, MSE
L is a selection transistor for selecting a pixel. After the reset transistors MRES and MRV are turned on to reset the pixel portion and the vertical output line, a noise signal is accumulated in the noise memory CT2 via the pixel amplifier, the selection transistor MSEL and the transistor MCT2. Further, the transfer transistor MTX is turned on, the signal photoelectrically converted from the photodiode PD is transferred to the gate of the amplification transistor MSF serving as a pixel amplifier, and the signal is transmitted via the pixel amplifier, the selection transistor MSEL, and the transistor MCT1. A signal including a noise signal component is stored in the memory CT1. Then, the signal including the noise signal component stored in the signal memory CT1 and the noise signal stored in the noise memory CT2 are output to a horizontal output line, and the subtraction process is performed to perform the variation of the pixel amplifier and reset the gate unit. A signal from which noise components such as noise have been removed is obtained. φSEL, φTX, φRES, φR
V, φTS, and φTN are a selection transistor MSEL, a transfer transistor MTX, and a reset transistor MRE, respectively.
S, MRV and control signals for controlling the transistors MCT1 and MCT2. The transistor ML is a load of the pixel amplifier MSF. .phi.L may be driven in common with .phi.SEL, or may be always set to the H level as a resistor.

FIG. 10 is a circuit diagram of the image pickup apparatus according to the present embodiment. Each pixel unit in FIG. 10 has the same configuration as that shown in FIG. The noise removing means is omitted for the sake of simplicity, but a memory for noise and a horizontal output line for outputting a noise signal are provided and subtraction processing is performed as in FIG. Can be obtained from which a noise component has been removed.

The upper memory circuit in FIG. 10 stores G signals for two rows. The lower memory circuit stores R and B signals for two rows. Taking the reading of signals from the pixels G11, R12, B21, G22 as an example, the signal from the pixel G11 is transferred to the memory CG1 via the switching transistor MG11.
The signal from the pixel G22 is stored in the memory CG22 via the switching transistor MG12. The signal from the pixel B21 is supplied to the switching transistor MB11.
Is stored in the memory CB21, and the signal from the pixel R12 is stored in the memory CR12 via the switching transistor MR12. The transistor MA1 is a transistor for adding the signals stored in the memories CG11 and CG22, the transistor MA2 is a transistor for adding the signals stored in the memories CG13 and CG24, and the transistor MA3
Is a transistor for adding the signals stored in the memories CB21 and CB23, and the transistor MA4 is a transistor for adding the signals stored in the memory CR12.
And a transistor that adds the signals stored in the memory CR14. φT1, φT2, φA are transistors MG11, MG21, MR12, MR22, transistors MG12,
Control signals for controlling MG22, MB11, MB21 and transistors MA1 to MA4. Φhc is a control signal for controlling the transistors Mhc1 to Mhc4 for resetting the horizontal output line.

FIG. 11 is a timing chart for transferring a pixel signal to a memory, and FIG. 12 is a timing chart for when a memory signal is read independently and when it is added and read.

In a period t1 in FIG. 11, the control signals φRES and φRV of the first row of pixel columns are set to H level to turn on the reset transistors MRES and MRV to reset the pixels and the vertical output lines.

Next, during the period t2, the control signals φTX, φSEL of the first row of pixel columns are set to the H level to turn on the transfer transistors MTX, MSEL, and further, the φT1 is set to the H level, to thereby set the transistors MG11, MG21, MR12, MR22. Are turned on, and signals corresponding to the signal charges photoelectrically converted by the pixels G11, R12,..., G1 (n-1), R1n are stored in the memories CG11 to CG.
1 (n-1), transferred to CR12 to CR1n. The transfer of a noise signal such as a reset noise (not shown) is performed in the period t1 and the period t2.
And between.

Next, in a period t3, the control signals φRES and φRV of the pixel column in the second row are set to the H level to turn on the reset transistors MRES and MRV to reset the pixels and the vertical output lines.

Next, in a period t4, the control signals φTX and φSEL of the pixel column of the second row are set to the H level, and the transfer transistor MT
X and MSEL are turned on, and φT2 is set to H level to turn on the transistors MB11, MB21, MG12 and MG22 to turn on the pixel B2.
1, G22,..., B2 (n-1), signals corresponding to the signal charges photoelectrically converted by G2n are stored in memories CB21 to CB2 (n-1), C2
Transfer to G22 to CG2n. The transfer of a noise signal such as reset noise (not shown) is performed between the period t3 and the period t4.

In the above operation, the G signals from the G pixels arranged obliquely in the two rows of pixel signals are stored in the upper memory, and the R and B signals are stored in the lower memory. Become.

In the system 1, since each pixel signal is independently read, φMode is at the H level as shown in FIG. 12, and the horizontal shift pulses h11 to hn1 and h12 to h12 from the horizontal shift register (H.SR) serving as a horizontal scanning circuit are provided. hn2 are driven in phase. Accordingly, the R, B, and G signals in units of 2 × 2 pixels are transferred to the horizontal output line in the same phase, and noise is removed by the output amplifier and output.

Since the system 2 performs addition reading, φMode is at L level and addition pulse φA is at H level. As a result, two rows of adjacent signals are added to G, and the same color signal is added to R and B by one row. As a result, G is added diagonally, and R and B are added in the same color in the horizontal direction.
That is, G11 and G12, G13 and G24,.
(n-1) and G2n are added, and B21 and B23,.
(n-3) and B2 (n-1) are added, and R12 and R14, respectively.
.., R1 (n-2) and R1n are added. The transfer to the horizontal output line is performed while the horizontal shift pulses h11 to h (n / 2) 1 remain at the H level and the horizontal shift pulses h12 to h (n / 2) 2 remain at the L level.

In this embodiment, the G signal is sent to the A channel,
The B signal is output to the C channel and the R signal is output to the D channel. Since the B channel is not used because no signal is output, the power is controlled to be off. Although the signal addition is performed on the memory, the addition method is not limited to this, and the memory signal may be added on the horizontal output line. Also, the addition may be performed on the pixel.

FIG. 13 is a diagram showing an example of a common amplifier pixel. As shown in FIG. 13, a11, a12, a21, and a22 are photodiodes serving as photoelectric conversion units of each pixel, MSF is an amplifying transistor serving as a common amplifier, and MTX1 to MTX4 share signal charges accumulated in the photodiodes. A transfer transistor for transferring data to a floating diffusion area (FD area) serving as an input part of the amplifier, MRES is a reset transistor for resetting the FD area, and MSEL is a selection transistor for selecting a common amplifier pixel. The transistors MSF and MSEL form a source follower circuit. In such a common amplifier pixel, signals from four photodiodes are output via a common amplifier, and the four pixels constitute one unit cell. One pixel includes a photodiode and a transfer transistor, and includes a part of a common circuit including a common amplifier, a reset transistor, and a selection transistor. G for photodiodes a11 and a22
A filter and a photodiode a21 are provided with a B filter and a photodiode a12 are provided with an R filter. When the transfer transistors MTX1 and MTX4 are turned on, the photodiode a
11 (G11) and the signal from the photodiode a22 (G22) are added by the gate of the common amplifier, the output signal is doubled, and the S / N is improved. When the common amplifier is set in units of 8 pixels, each color (R, B,
G).

The scanning of the color image pickup apparatus shown in FIG.
In non-interlaced (progressive) scanning, the vertical scanning circuit (V / SR) scans the horizontal signal lines V1 and V2 as a set, and thereafter scans the horizontal signal lines V3 and V4 and the horizontal signal line V
Scanning is performed with two horizontal signal lines as a set such as 5 and V6.

In the interlaced scanning, scanning is performed with a set of horizontal signal lines V1 and V2, horizontal signal lines V5 and V6, horizontal signal lines V9 and V10,... In the first field, and horizontal signal line V3 in the second field. And V4, and the horizontal signal lines V7 and V
Scan in the set of 8,. By performing scanning in this way and adding and reading out the pixel signals to perform signal processing, a resolution of 500 vertical lines can be obtained.

In this embodiment, the addition is performed with two pixel rows, but more pixel rows may be added. Similarly, the addition in the horizontal direction is performed by two pixels, but the addition may be performed more than two pixels. That is, it can be arbitrarily set according to the request of the system.

Next, the configuration of the reading system of the image pickup apparatus, which is a characteristic part of this embodiment, will be described.

FIG. 1 shows a reading means representing a structure which can be accessed randomly. Specifically, the reading means comprises a horizontal decoder section as a signal applying section and a shift register as a scanning section. The configuration of the pixel portion other than the horizontal decoder and the shift register, the line memory for storing 1H of pixel data as electric charge, and the like are the same as those in FIG. The horizontal shift register (H-SR) 1 described in FIG.
Corresponds to SR.

As shown in FIG. 1, in this horizontal shift register 1, φH and φMode described in FIG.
In addition, a reset pulse (RES) and a clock pulse (CLK) can be input. In order to start horizontal scanning, a start pulse is input to the horizontal shift register 1 by a horizontal address input (HD0, HD1) input to the horizontal decoder unit 2. Further, the vertical shift register (V.SR) does not need the AND of 161 to 16n as shown in FIG. 1, and the output signal from the DFF becomes a horizontal selection line as it is. The other parts have the same configuration as the H-SR, so that only the horizontal shift register will be described below.

First, the block configuration of the horizontal shift register and the horizontal decoder shown in FIG.
Is input with HD0 as the lower digit and HD1 as the upper digit,
An AND circuit 22, AND circuits 23 ₁ , 23 ₂ ,... And an inverter 21 are provided. Horizontal shift register 1
Are D-type flip-flops DFF1 to DFFn, inverters 11, 12, 13 and AND circuits 14, 16 _{1 to} 16 _n ,
.., An OR circuit 15. The horizontal decoder unit 2 may be configured using an element other than the AND circuit and the inverter, or the horizontal shift register 1 may be configured using a switching element. In this embodiment, the switching means includes AND circuits 16 _{1 to} 16 _n and an inverter 1
2. The reading means corresponds to the horizontal decoder section and the horizontal shift register. In this embodiment, the switching means is described as a part of the horizontal shift register.

The operation will be described with reference to the block diagram of FIG. 1 and the timing chart of FIG. Here, the description will be made from the timing when φH rises in FIG. 11, but the charge transfer from the photodiode, the accumulation timing to the memory, and the addition method are the same as those in FIGS.

FIG. 2 shows the timing of horizontal transfer in the all pixel mode (high resolution mode). Since φMode is the all pixel mode, it is at the Low level. AND circuit 16 _{1 -1}
6 _n ,... Are applied with a High level of an inverted signal of φMode, and are connected to D-type flip-flops DFF1 to DFF.
When the outputs of n sequentially become High level, in addition to the horizontal shift pulses h11, h21,.
, H22,... Are output and all pixel mode is set. In addition,
As shown in FIG. 3, also when random access is performed in the all-pixel mode, φMode is at the Low level.

First, the horizontal address input (HD0, HD1) of the horizontal decoder 2 is <00>, that is, HD0
Is a low level and HD1 is a low level.

First, a D-type flip-flop (DFF1)
And the inverter 11 and the AND circuit 14 capture the rise of φH to generate 1 CLK. Its internal operation is Sig
It is shown in FIG.

Next, the generated signal for 1 CLK and the state signal (the signals of HD1 and HD2 and their inverted signals) of the horizontal decoder unit 2 are ANDed by the AND circuit 22, and further, A
By ANDing with the ND circuit 23 ₁ , ₁ of <00> is obtained.
A pulse signal is created and a D-type flip-flop (DF
Input to F2).

In order to catch the signal of one pulse inputted to the D-type flip-flop (DFF2) at the center, the input C
LK is inverted by the inverter 13 and the inverter signal (S
ig2) operates the D-type flip-flop (DFF2) and thereafter. Thereby, the D-type flip-flop (DFF)
As an output and the output from the AND circuit 16 ₁ from 2), is output horizontal shift pulses h11, h12, then the signal is propagated by the clock pulses, the shift register continue to scan, the horizontal shift pulses h21, h22,
... is output.

When scanning of all pixels is completed, a reset pulse (RES) is input to each D-type flip-flop (D
FF1, DFF2,...) Are reset. Thus, scanning of all pixels is performed.

FIG. 3 is an operation timing chart when the random access function for reading from an arbitrary position is used in the all-pixel mode. In FIG. 1, <01> is input to the horizontal address inputs HD1 and HD0 of the horizontal decoder unit 2, that is, a high level is input to HD0 and a low level is input to HD1. In this case the AND circuit 23 ₁ outputs Low level, AN
The output of D circuit 23 ₂ is High level. Therefore, the start pulse of the horizontal shift register 1 starts from the D-type flip-flop (DFFn), and outputs the horizontal shift pulses hn1 and hn2 at the next rise of the signal Sig2.
With this configuration, scanning can be started from an arbitrary pixel position. At the end of scanning, each D-type flip-flop is reset by applying a reset pulse (RES), so that scanning can be stopped halfway without scanning until the end of one horizontal period. Thus, for example, horizontal 2
If it is possible to have an address line capable of designating all bits of 000 pixels, random access in the all-pixel mode becomes possible.

FIG. 4 shows a pixel addition mode (low resolution mode).
FIG. 4 is a timing chart of horizontal transfer in FIG. The difference from the case of FIG. 2 in the all pixel mode is that φMode is at the High level. The low level of the inverted signal of φMode is applied to one terminal of each of the AND circuits 16 _{1 to} 16 _n ,..., And when the outputs of the D-type flip-flops DFF1 to DFFn sequentially become high, the horizontal shift pulses h11, h21,. Are output, and the horizontal shift pulses h12, h22,... Are not output. This corresponds to the addition mode.

FIG. 5 is an operation timing chart when using the random access function for reading from an arbitrary position in the addition mode. In FIG. 1, <01>, that is, H is input to the horizontal address inputs HD1 and HD0 of the horizontal decoder unit 2.
A high level is input to D0 and a low level is input to HD1. In this case the AND circuit 23 ₁ outputs Low level, the output of the AND circuit 23 ₂ is High level. Therefore, the start pulse of the horizontal shift register 1 starts from a D-type flip-flop (DFFn). Since φMode is High level,
Are output, and the horizontal shift pulses hn2,... Are not output. Thus, in the addition mode, scanning can be started from an arbitrary position, and an arbitrary range can be scanned by inputting a reset pulse (RES) at an arbitrary timing.

Further, this configuration can support a thinning mode. For example, when only G11, R14, B41, and G44 are extracted from 16 pixels of 4 × 4 pixels in FIG. 8 and read out, in FIG. 1, the horizontal shift pulses h12 and h22 are masked in φMode. The horizontal shift pulses h12 and h2
If a mask is applied to only 1 and the vertical shift register (V · SR) has the same structure, thinning can be handled.

In the thinning method, 16 pixels of 4 × 4 pixels are used.
In the case of a method in which only G11, R12, B21, and G22 are read out of the pixels, the readout can be performed with a circuit configuration as shown in FIG. This corresponds to D which outputs the horizontal shift pulses h21 and h22 among the horizontal shift pulses shown in FIG.
Type flip-flop DFF3 itself is connected to AND circuit 1
7. AND circuit 1 with one terminal connected to an inverter
8, the configuration is such that reading is performed while skipping. With this circuit configuration, at the time of thinning, horizontal shift pulses h11, h12, h31, h32,... Can be read, and only necessary pixels can be read at a low drive frequency. At this time, a start pulse (start signal) is not applied to the DFF 3 corresponding to the pixel line to be thinned.

In the low resolution mode, a pixel area (for example, G11, R12, B21,
When reading G22, G11, R12, B21, G2
2 × 2 pixels are pixel areas, G11, R14, B41,
To read G44, use G11, R14, B41, G4
4 × 4 pixels including 4 can be randomly accessed for each pixel area. For example, G11, R12, B
After reading G21, G22, G1n, R1n + 1, B
To read 2n and G2n + 1, use R12 and G22.
, And a horizontal decoder start signal is input so that scanning can be started from the pixel lines including G1n and B2n.

Further, by combining this thinning and the addition mode described above, three modes of an all pixel mode (high-resolution reading mode), an addition mode (low-resolution reading mode), and a thinning mode (low-resolution reading mode) are obtained. It is also possible to correspond to one.

In the random access in these modes, a start pulse from the horizontal decoder circuit is input only to pixels actually read out by thinning or addition. The shift register configuration described with reference to FIG.
Although the description is made in accordance with the addition method disclosed in Japanese Patent No. 151615, the addition method performed inside the sensor is not limited to this. For example, the addition range is expanded in the horizontal direction to three pixels, four pixels, and five pixels. In this case, the horizontal pixel position actually desired to be output changes depending on the thinning method. To cope with this, the decoder circuit may be configured so that the start pulse of the shift register is input only to the pixel output in the low-resolution read mode.

Next, the configuration taking into account the OB section is shown in FIG.
Figure 2 shows the circuit diagram. In this circuit, a D-type flip-flop (DFF1 ') is connected to the output side of the AND circuit 14,
The output of the AND circuit 14 and a D-type flip-flop (DFF)
1 ') are output from horizontal shift pulses OB11, O
B21, these outputs are respectively input to one terminal, and the outputs from the AND circuits 16 ₁ ′, 16 ₂ ′ having input the inverted signal of φMode to the other terminal are horizontal shift pulses OB12, OB22, respectively. With this configuration, it is possible to always drive the first several pixels, which are OB pixels, regardless of the address input. Further, if the horizontal shift pulse output for specifying the OB pixel is provided with the mode switching described with reference to FIGS.
It can also support random access in addition mode and thinning mode.

Note that the address designation described with reference to FIGS. 1 to 7 is only 2 bits of HD0 and HD1, and if up to 4 pixels of <00>, <01>, <10> and <11>, It can be specified directly. Therefore, the pixel section of the sensor is divided into four blocks in the horizontal direction, and the first pixel can be addressed.

In the configuration described above, the horizontal shift pulse h1
Since 1 and h12 are output at 1 CLK, for example, if an address for 1000 pixels out of 2000 horizontal pixels is designated, it can be performed by using a 10-bit address line.

If it is necessary to indicate all 2000 pixels, one horizontal shift pulse is output at 1 CLK, and all pixels can be addressed by 11 bits from HD0 to HD10. It is also possible to start from the horizontal shift pulse of
Further, at this time, the shift register may be configured to directly output the horizontal shift pulse by changing the address designation every 1 CLK by a counter or the like, instead of using a flip-flop.

As an imaging apparatus to which the present invention can be applied, which can perform all-pixel reading, addition reading, and / or thinning-out reading, for example, all-pixel reading, addition reading, and thinning-out reading shown in FIG. Japanese Patent Application No. 11-171136
Japanese Patent Application No. 2000-2000, which performs all-pixel reading, addition reading, and thinning-out reading (showing even and odd fields) as shown in FIG.
Japanese Patent Application No. 10-6782 discloses an image pickup apparatus that performs all-pixel reading, addition reading, and thinning-out reading.
There is an imaging device disclosed in Japanese Patent Application No. -206516.

Further, as other decoder sections and shift registers in the present invention, for example, Japanese Patent Application Nos.
No. 1736. As shown in FIG. 17, this circuit configuration is such that horizontal pixel selection switches 201 to 204 are provided in a shift register 120, and resistors 211 to 214 are provided at the outputs of the switches, and all switches can be simultaneously turned ON and OFF by a horizontal selection pulse HSEL. It was made. In this configuration, for example, scanning can be started from the output line h2 instead of the output line h1.
First, <00> is input to the horizontal decoder unit 110 so that the output line h1 can be selected. However, at this time, the horizontal selection pulse HSEL is set to the low level and is not output from the output line h1. The signal is shifted by the next clock CLK and moves to the output line h2. At this time, the horizontal selection pulse HSE
L is set to High level to enable output.

FIG. 14 shows a schematic diagram of the system. As shown in the figure, the image light incident through the optical system 71 is a CMO
An image is formed on the S sensor 72. The optical information is converted into an electric signal by the pixel array arranged on the CMOS sensor 72. The electric signal is subjected to signal conversion processing by a signal processing circuit 73 by a predetermined method and output. The processed signal is sent to the recording system, communication system 74
Is recorded or transferred by the information recording device. The recorded or transferred signal is reproduced by the reproduction system 77. CMOS sensor 72, signal processing circuit 73
Is controlled by the timing control circuit 75, and the optical system 7
1. The timing control circuit 75, the recording / communication system 74, and the reproduction system 77 are controlled by the system control circuit 76. The timing control circuit 75 can select either independent reading or addition reading.

The horizontal and vertical drive pulses are different between the above-described high pixel readout (all pixel readout) and low pixel readout (additional readout). Therefore, it is necessary to change the drive timing of the sensor, the resolution processing of the signal processing circuit, and the number of recording pixels of the recording system for each reading mode. These controls are performed by the system control circuit 76 in accordance with each read mode.
In addition, in the reading mode, the sensitivity differs depending on the addition. For example, the signal amount is doubled in addition reading in comparison with high pixel reading. In this state, the dynamic range is halved, so that an appropriate signal can be obtained by controlling the aperture (not shown) to a small aperture by half. As a result, at low illuminance, photographing can be performed up to half the brightness. The signal processing circuit and the recording system may be separately provided for high definition and for moving images.

[0060]

As described above, according to the image pickup apparatus of the present invention, the shift register operation can be started and stopped from an arbitrary position with a simple circuit configuration, and a certain arbitrary angle of view can be obtained. Only the area can be output from the sensor.

In a digital camera operated in an all-pixel mode and a high-definition digital video, only half of the number of horizontal and vertical pixels needs to be scanned at the time of double electronic zoom. It can be easily done with the random access function. At the same time, the operation speed of the sensor is reduced to about 1/4, and the sensor itself can be driven with low power consumption.

The zoom position at that time, even if the camera is not directly moved, is within the image pickup area where all pixels are displayed. It is also possible.

In addition, when the normal operation is performed in the addition mode, by scanning only the horizontal and vertical halves of the all pixel mode, it is possible to perform the double electronic zoom without lowering the resolution.
In addition, by reading only a certain area in the sensor in both the addition mode and the thinning mode, the electronic zoom can be supported in these low pixel modes.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a horizontal decoder unit and a shift register which can be randomly accessed according to the present invention.

FIG. 2 is a timing chart of a horizontal decoder unit and a shift register.

FIG. 3 is an operation timing chart when a random access function for reading from an arbitrary position is used in an all-pixel mode.

FIG. 4 is a timing chart of horizontal transfer in a pixel addition mode.

FIG. 5 is an operation timing diagram when a random access function for reading from an arbitrary position is used in the addition mode.

FIG. 6 is a diagram showing a circuit configuration in the case of a thinning method.

FIG. 7 is a circuit configuration diagram in a case where an OB unit is considered.

FIG. 8 is a schematic explanatory view showing a pixel signal reading method by the imaging device according to the present invention.

FIG. 9 is a circuit diagram illustrating a CMOS sensor and a readout circuit.

FIG. 10 is a circuit configuration diagram of an imaging device according to the present invention.

FIG. 11 is a timing chart for transferring a pixel signal to a memory.

FIG. 12 is a timing chart when a memory signal is independently read and when it is added and read.

FIG. 13 is a diagram illustrating an example of a common amplifier pixel.

FIG. 14 is a schematic diagram of an imaging system according to the present invention.

FIG. 15 is a schematic explanatory diagram showing another pixel signal reading method by the imaging device according to the present invention.

FIG. 16 is a schematic explanatory view showing another pixel signal reading method by the imaging device according to the present invention.

FIG. 17 is a diagram showing another example of the configuration of the horizontal decoder unit and the shift register that can be randomly accessed according to the present invention.

[Explanation of symbols]

Reference Signs List 1 horizontal shift register 2 horizontal decoder section 11, 12, 13 inverter 14, 16 _{1 to} 16 _n AND circuit 15 OR circuit 22 AND circuit 23 ₁ , 23 ₂ AND circuit DFF1 to DFFn D flip-flop

 ──────────────────────────────────────────────────続 き Continued on front page F-term (reference) 4M118 AA04 AA10 AB01 BA14 DB20 GB09 GC08 5C022 AA01 AA13 AB13 AB36 AB67 AC41 5C024 AX01 BX01 BX04 CX04 CY12 CY42 DX01 DX02 DX04 GX03 GX22 GY39 GZ24 HX26 JX15 ACC CC CC07 CC08 DD15 DD17 GG21 GG26 GG35 GG36

Claims (11)

[Claims] A plurality of pixels for photoelectrically converting optical information into an electric signal; a first read mode for reading the electric signal from the plurality of pixels at a high resolution; and a low-resolution conversion of the electric signal from the plurality of pixels. Switching means for switching between a second read mode to be read, and read for starting and ending read scan at an arbitrary pixel position of the plurality of pixels in the first read mode and the second read mode. An imaging device comprising: 2. The imaging device according to claim 1, wherein a plurality of color filters are repeatedly arranged on the plurality of pixels, and the plurality of pixels each have a low resolution in the second readout mode. An imaging apparatus comprising a plurality of pixel groups from which signals of a plurality of colors are read, wherein the reading unit starts reading and scanning for any of the pixel groups. 3. The imaging apparatus according to claim 1, wherein the second read mode is a mode in which pixels are read out at a low resolution by thinning out pixels, and
A plurality of scanning means for sequentially reading signals from each pixel; and signal applying means for applying the start signal to the scanning means corresponding to the arbitrary pixel position in order to start reading and scanning from an arbitrary pixel position. An imaging apparatus, wherein, in a mode in which pixels are thinned out and read at a low resolution, the start signal is applied to a scanning unit corresponding to a pixel for which thinning is not performed. 4. The imaging device according to claim 1, wherein the readout unit includes a shift register for sequentially reading signals from pixels, and a decoder circuit that defines a scan start position of the shift register. An imaging device, comprising: 5. An imaging apparatus according to claim 3, wherein said scanning means is a flip-flop, and said signal applying means is a decoder. 6. The imaging device according to claim 1, wherein the second read mode is a mode in which pixels are read out at a low resolution by thinning out the pixels. 7. The imaging apparatus according to claim 1, wherein the second read mode is a mode in which two or more pixels are added and read at low resolution. 8. A plurality of pixels for photoelectrically converting optical information into an electric signal, a first read mode for reading the electric signal from the plurality of pixels at a high resolution, and a low-resolution reading of the electric signal from the plurality of pixels. Switching means for switching between a second read mode to be read, and read for starting and ending read scan at an arbitrary pixel position of the plurality of pixels in the first read mode and the second read mode. Means for scanning, the reading means for sequentially scanning the plurality of pixels, and the scanning means for dividing the scanning means into a plurality of areas, and starting scanning from an arbitrary area in the plurality of areas. And a signal applying means for supplying the scanning start signal to the scanning means. 9. An imaging apparatus according to claim 8, wherein said scanning means includes a shift register, and said signal applying means includes a decoder. 10. The imaging device according to claim 1, wherein the plurality of pixels include an optical black pixel. 11. An image pickup apparatus according to claim 1, an optical system for forming an image on the image pickup apparatus, and a signal processing circuit for processing an output signal from the image pickup apparatus. An imaging system comprising: