JP2007267314A - Data processing device, solid state imaging apparatus, and electronics device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing device for sorting data rows which is small in area. <P>SOLUTION: The data processing device includes data width changing part (latch circuits 2 and 3) which outputs two data elements of received data rows by combining them and make the data width double, a line memory 1 of one port which writes the data elements of the data rows output from the data width changing part, and a data width restoring part (latch circuits 4 and 5) which divides the data elements read out from the line memory 1 into two and restore the data width to original state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing device that rearranges data strings, and a solid-state imaging device and an electronic apparatus including the same.

  A general solid-state imaging device has a Bayer array color filter. In the Bayer array, G (green) is arranged in a checkered pattern, and R (red) and B (blue) are arranged in line sequence. An example of a 10 × 10 pixel Bayer array is shown in FIG. In the Bayer array shown in FIG. 7, the odd rows are repeated in the order of R (red) and Gr (green), and the even rows are repeated in the order of Gb (green) and B (blue).

When all pixel data is read out pixel by pixel from the solid-state imaging device having the Bayer array color filter shown in FIG. 7, the image data sequence read out from the solid-state imaging device is the pixels in the first row as shown in FIG. Data string (R _(1,1) ,..., Gr _(1,10) ), second row pixel data string (Gb _(2,1) ,..., B _(2,10) ) _,. Of the pixel data (Gb _(10,1) ,..., B _(10,10) ). However, R _{(a, b)} , Gr _{(a, b)} , Gb _{(a, b)} , B _{(a, b)} are a row b of the solid-state imaging device having the Bayer array color filter shown in FIG. This is pixel data obtained from the pixels in the column.

  As a Bayer array other than that shown in FIG. 7, Gr (green) and R (red) are repeated in the odd-numbered row, B (blue) and Gb (green) are repeated in the even-numbered row, and B ( Blue) and Gb (green) are repeated in this order, and even rows are repeated in the order of Gr (green) and R (red), and odd rows are repeated in the order of Gb (green) and B (blue). Then, there is an arrangement that is repeated in the order of R (red) and Gr (green).

  In recent years, in a solid-state imaging device, the number of pixels has been increased for higher resolution. When the number of pixels increases, when reading out all pixel data pixel by pixel from the solid-state imaging device, it takes time to read out one frame of image data, and the frame rate decreases.

  For this reason, in moving image shooting using a solid-state imaging device with a large number of pixels, measures may be taken to improve the frame rate by thinning out vertical lines. For example, even when a solid-state imaging device having a Bayer color filter shown in FIG. 7 thins out the number of vertical lines and outputs a reduced number of pixels, the odd-numbered pixel data columns are R (red) image data and Gr. It is possible to repeat (green) image data, and to repeat even-numbered pixel data column Gb (green) image data and B (blue) image data. Therefore, when a solid-state imaging device having a color filter with a Bayer array thins out the number of vertical lines and outputs a reduced number of pixels, the signal processing circuit that processes the image data string output from the solid-state imaging device has a Bayer array. There is an advantage that an existing signal processing circuit for processing an image data sequence in which image data are arranged in the order along the line can be used as it is. However, since the image quality deteriorates when the vertical lines are thinned out, recently, the pixel addition method is frequently used in moving image shooting with a solid-state imaging device having a large number of pixels.

  In the pixel addition method, pixel data is added inside a solid-state imaging device, the number of output pixel data is reduced, and the frame rate is increased. For pixel addition, there is a method in which neighboring same colors (Gb and Gb are considered to be different colors in pixel addition) are added in units of 2 pixels, 4 pixels, 6 pixels, 9 pixels, and the like.

  When a solid-state imaging device having a color filter with a Bayer array performs pixel addition inside, the image data sequence output from the solid-state imaging device does not have image data arranged in the order along the Bayer array, and the color filter Since data for a plurality of rows is packed in the same number of data rows as the number of horizontal pixels, an existing signal processing circuit that processes image data rows in which image data is arranged in an order along the Bayer array Need to be rearranged so that they can be processed. For this reason, a data processing device that rearranges the image data sequence output from the solid-state imaging device in the order along the Bayer array is necessary.

  When pixel addition is performed in a solid-state image pickup device having a Bayer color filter, the output format of the pixel data string output from the solid-state image pickup device will be described below by taking 4 times addition and 9 times addition as examples. Explained.

First, quadruple addition will be described. FIG. 10A shows a pixel data string output from the solid-state image pickup device when four pixels are added in the solid-state image pickup device having a 12 × 12 pixel Bayer array color filter shown in FIG. In addition, two rows of data are packed every two pixel data in the same number of data columns as the number of horizontal pixels of the color filter. The image data obtained by the 4-pixel addition has a 6 × 6 pixel Bayer array, and has a data amount of 1/2 pixel both vertically and horizontally, compared to a case where all pixel data is read out pixel by pixel without performing 4-pixel addition. . In order to use an existing signal processing circuit that processes an image data sequence in which image data is arranged in an order along the Bayer array, a pixel data sequence output from the solid-state imaging device is displayed by a data processing device. 10 (b), the first pixel data string (R _{4 (1,1)} ,..., Gr _{4 (1,6)} ), the second pixel data string (Gb _{4 (2,1),.} , B _{4 (2,6)} ),..., The pixel data string in the sixth row (Gb _{4 (6,1)} ,..., B _{4 (6,6)} ) must be rearranged in this order. Incidentally, R ₄ in FIG. _{10 (m, n), Gr} 4 (m, n), Gb 4 (m, n), B 4 (m, n) is below the respective (1) to (4) It is obtained from the formula. However, R _{(a, b)} , Gr _{(a, b)} , Gb _{(a, b)} , and B _{(a, b)} are solid-state imagings each having a 12 × 12 pixel Bayer array color filter shown in FIG. This is pixel data obtained from the pixels in row a and column b of the element.
R _{4 (m, n)} = R _(2m-1,2n-1) + R _{(2m-1,2n + 1)}
+ R _{(2m + 1,2n-1)} + R _{(2m + 1,2n + 1)} (1)
Gr _{4 (m, n)} = Gr _(2m-1,2n-2) + Gr _(2m-1,2n)
+ Gr _{(2m + 1,2n-2)} + Gr _{(2m + 1,2n)} (2)
Gb _{4 (m, n)} = Gb _(2m-2,2n-1) + Gb _{(2m-2,2n + 1)}
+ Gb _{(2m, 2n-1)} + Gb _{(2m, 2n + 1)} (3)
B _{4 (m, n)} = B _(2m-2,2n-2) + B _(2m-2,2n)
+ B _{(2m, 2n-2)} + B _{(2m, 2n)} (4)

Next, 9-fold addition will be described. A pixel data string output from the solid-state imaging device when 9 pixels are added in the solid-state imaging device having the color filter of the 18 × 18 pixel Bayer array shown in FIG. 11 is as shown in FIG. In addition, pixel data for three rows is packed every other pixel data in the same number of data columns as the number of horizontal pixels of the color filter. The image data obtained by adding 9 pixels has a 6 × 6 Bayer array, and has a data amount of 1/3 pixel in both vertical and horizontal directions compared to reading all pixel data pixel by pixel without adding 9 pixels. . In order to use an existing signal processing circuit that processes an image data sequence in which image data is arranged in an order along the Bayer array, a pixel data sequence output from the solid-state imaging device is displayed by a data processing device. The first pixel data string (R _{9 (1,1)} ,..., Gr _{9 (1,6)} ) and the second pixel data string (Gb _{9 (2,1),.} , B _{9 (2,6)} ),..., The pixel data string in the sixth row (Gb _{9 (6,1)} ,..., B _{9 (6,6)} ) must be rearranged in this order. In addition, R _{9 (m, n)} , Gr _{9 (m, n)} , Gb _{9 (m, n)} , and B _{9 (m, n)} in FIG. 12 are the following formulas (5) to (8), respectively. Obtained from However, R _{(a, b)} , Gr _{(a, b)} , Gb _{(a, b)} , B _{(a, b)} are solid-state imagings each having a 18 × 18 pixel Bayer array color filter shown in FIG. This is pixel data obtained from the pixels in row a and column b of the element.
R _{9 (m, n)} = R _3m-2,3n-2 + R _3m-2,3n + R _{3m-2,3n + 2}
+ R _{3m, 3n-2} + R _{3m, 3n} + R _{3m, 3n + 2}
+ R _{3m + 2,3n-2} + R _{3m + 2,3n} + R _{3m + 2,3n + 2} (5)
Gr _{9 (m, n)} = Gr _3m-2,3n-4 + Gr _3m-2,3n-2 + Gr _3m-2,3n
+ Gr _{3m, 3n-4} + Gr _{3m, 3n-2} + Gr _{3m, 3n}
+ Gr _{3m + 2,3n-4} + Gr _{3m + 2,3n-2} + Gr _{3m + 2,3n} (6)
Gb _{9 (m, n)} = Gb _3m-4,3n-2 + Gb _3m-4,3n + Gb _{3m-4,3n + 2}
+ Gb _3m-2,3n-2 + Gb _3m-2,3n + Gb _{3m-2,3n + 2} (7)
+ Gb _{3m, 3n-2} + Gb _{3m, 3n} + Gb _{3m, 3n + 2}
B _{9 (m, n)} = B _3m-4,3n-4 + B _3m-4,3n-2 + B _3m-4,3n
+ B _3m-2,3n-4 + B _3m-2,3n-2 + B _3m-2,3n (8)
+ B _{3m, 3n-4} + B _{3m, 3n-2} + B _{3m, 3n}
JP 2000-197066 A

  When pixel addition is performed in a solid-state imaging device having a Bayer array color filter with M horizontal pixels and N vertical pixels, an A / D conversion unit outputs a pixel data string output from the solid-state imaging device. As a general data processing apparatus that rearranges the A / D converted data (each pixel data is Abit) in the order along the Bayer array, a data processing apparatus having the configuration shown in FIG. The data processing apparatus shown in FIG. 13A includes an Mword × Abit line memory (for example, SRAM) 101 and an Mword × Abit line memory (for example, SRAM) 102. When data is being written to the line memory 101, the line memory 102 reads while rearranging the order of the data strings, and when data is being written to the line memory 102, the line memory 101 changes the order of the data strings. Data strings can be easily rearranged by reading while rearranging.

  FIG. 13B shows a timing chart in the case of M = N = 12, and 4-pixel addition. In the period T1, the pixel data of the first and second rows are written in the line memory 101 (W1, 2). In the subsequent period T2, the pixel data of the third and fourth rows are written into the line memory 102 (W3, 4), and the pixel data of the first row and the pixel data of the second row are sequentially read from the line memory 101 (R1, R2). ). In the subsequent period T3, the pixel data of the fifth and sixth rows are written into the line memory 101 (W5, 6), and the pixel data of the third row and the pixel data of the fourth row are sequentially read from the line memory 102 (R3, R4). ). In the subsequent period T4, the pixel data of the fifth row and the pixel data of the sixth row are sequentially read from the line memory 102 (R5, R6).

  However, in the data processing apparatus shown in FIG. 13A, the number of words in the line memories 101 and 102 is the same as the number of horizontal pixels of the solid-state imaging device, and two line memories are required. The area increases and the chip cost is affected.

  The data processing apparatus shown in FIG. 13A is provided with two line memories. However, by using a two-port memory, reading and writing can be easily shared. Can do. However, the 2-port memory has a larger area than the 1-port memory.

  In Patent Document 1, a solid-state image sensor that can solve the problems caused by the increase in the number of pixels of the solid-state image sensor is proposed. However, the solid-state image sensor proposed in Patent Document 1 is a Bayer array. No color filter, for example, a 2 × 2 unit array in which a first color (G) and a second color (R) as shown in FIG. 14 are arranged in a checkered pattern, and a first color (G) And a 2 × 2 unit array in which the third color (B) is arranged in a checkered pattern, and has a color filter with M rows and N columns arranged in a checkered pattern. The existing signal processing circuit that processes the image data sequence in which the image data is arranged in the order along the line cannot be used. Moreover, although the data arrangement is corrected in Patent Document 1, no specific method is disclosed (see paragraph 0029 of Patent Document 1).

  In view of the above-described problems, an object of the present invention is to provide a data processing device with a small area for rearranging data strings, and a solid-state imaging device and an electronic apparatus including the data processing device.

  In order to achieve the above object, in the data processing device according to the present invention, a data width changing unit that outputs two combined data elements of an input data string and changes the data width by two times, and the data width changing unit 1 port memory for writing each data element of the data string output from the memory, and a data width restoring unit that divides each data element read from the memory into two and restores the data width to the original. . An embodiment of the data width changing unit includes a configuration including a plurality of latch circuits, and an embodiment of the data width restoring unit includes a configuration including a plurality of latch circuits.

  According to such a configuration, since two data elements are obtained by one writing, the writing side only needs to be written once in two clocks, and the reading side is similarly read by one reading. Since one data element is obtained, it is only necessary to read it once every two clocks, and it is not necessary to increase the clock frequency as compared with the prior art. Further, according to such a configuration, since it is not necessary to provide a plurality of memories, it is not necessary to provide a memory decoder circuit or the like for each memory, and the area can be reduced. In addition, since reading and writing can be shared over time, the memory can be a one-port memory, and the area can be reduced as compared with a configuration using a two-port memory.

  In order to achieve the above object, in the solid-state imaging device according to the present invention, a solid-state imaging device having a Bayer array color filter and performing pixel addition inside, and a pixel data string output from the solid-state imaging device An A / D converter for A / D conversion, and a data processing device for processing a pixel data string output from the A / D converter. The data processing device outputs a data width changing unit that outputs two combined data elements of the pixel data string output from the A / D conversion unit and changes the data width to twice, and the data width changing unit A 1-port memory for writing each data element of the data string output from the data, and a data width restoring unit that divides each data element read from the memory into two and restores the data width to the original. The pixel data string output from the width restoration unit is an image data string in which image data is arranged in the order along the Bayer array. An embodiment of the data width changing unit includes a configuration including a plurality of latch circuits, and an embodiment of the data width restoring unit includes a configuration including a plurality of latch circuits. Furthermore, in the solid-state imaging device having the above-described configuration, the memory has a plurality of divided address spaces, that is, a plurality of divided address spaces, and the same pixel data string output from the A / D conversion unit. All the image data elements belonging to the row are written in the same divided address space, and after reading of the image data element of the a (a is a natural number) row written in a certain divided address space is started, b (b Is a natural number, b> a) The writing of the image data element in the row to the certain divided address space is started, and the image data element in the a row is sequentially updated to the image data element in the b row. It is desirable to make it. Thereby, the memory capacity can be reduced. Further, this prevents a problem that the reading of the image data element in the a-th line can catch up with the writing of the image data element in the b-th line.

  In order to achieve the above object, an electronic apparatus according to the present invention includes the solid-state imaging device having the above-described configuration.

  According to the present invention, it is possible to realize a data processing device with a small area for rearranging data strings, and a solid-state imaging device and an electronic apparatus including the data processing device.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, when pixel addition is performed in a solid-state imaging device having a color filter with a Bayer array of 2048 × 2048 pixels, an A / D conversion unit converts a pixel data string output from the solid-state imaging device to A A description will be given by taking as an example a data processing device that processes data that has been / D converted (each pixel data is 12 bits).

  When the data processing apparatus shown in FIG. 13A performs pixel addition in a solid-state image sensor having a color filter of a 2048 × 2048 pixel Bayer array, a pixel data string output from the solid-state image sensor is obtained. If the A / D converter performs A / D conversion (each pixel data is 12 bits), the line memories 101 and 102 are each a 2048 word × 12 bit line memory.

  Here, consider reducing the capacity and reducing the chip area by reducing the number of words in each line memory. For example, in the case of 4-pixel addition, the number of words in the line memories 101 and 102 is halved and each line memory is changed to 1024 words × 12 bits. When such a change is made, the line memories 101 and 102 must each be a two-port memory. Then, it is preferable to read and write image data as in the timing chart shown in FIG. In the period T1, pixel data of the first row is written to the line memory 101 every two pixels (W1), and pixel data of the second row is written to the line memory 102 every two pixels (W2). In the subsequent period T2, writing is performed by writing pixel data of the third row into the line memory 101 every two pixels (W3), and writing pixel data of the fourth row into the line memory 102 every two pixels (W4). In the readout operation, the pixel data of the first row is read from the line memory 101 continuously with 1024 pixels (R1), and then the pixel data of the second row is read from the line memory 102 (R2). As described above, since there is a period in which writing and reading are simultaneously performed in the same memory, the line memories 101 and 102 need to be two-port memories as described above.

  However, even if the number of words in the line memories 101 and 102 of the data processing apparatus shown in FIG. 13 (a) is reduced, there is no change in the configuration having a plurality of line memories. Therefore, it is necessary to provide a memory decoder for each line memory. When reducing the number of words in the line memories 101 and 102 of the data processing apparatus shown in FIG. 13A, the line memories 101 and 102 need to be two-port memories, respectively. I can't plan. In view of this, the present inventor has intensively studied in order to thoroughly reduce the memory area, and has completed the present invention.

  One configuration example of the data processing circuit according to the present invention is shown in FIG. The data processing circuit according to the present invention shown in FIG. 1A is output from a solid-state image sensor when 4-pixel addition is performed in a solid-state image sensor having a color filter with a 2048 × 2048 pixel Bayer array. Is a data processing circuit that processes an A / D converted pixel data string (each pixel data is 12 bits), a 1024 word × 24 bit 1-port line memory 1, and a 12 bit Latch circuits 2 to 5 and selectors 6 and 7 are provided. The line memory 1 and the latch circuits 2 to 5 have the same clock frequency and are synchronized.

  The number of words in the line memory 1 is half the number of horizontal pixels of the solid-state image sensor, and the data width of the line memory 1 is twice the data width of each pixel data output from the solid-state image sensor. In the data processing circuit according to the present invention shown in FIG. 1A, write data (input data) to the line memory 1 is obtained by combining the two pixel data by the latch circuits 2 and 3 and having a double data width, that is, 24 bits. Data width. The selection signal R / W is inverted in synchronization with the falling timing of the clock signal, and the selector 6 selects the read address RADR and outputs it to the line memory 1 when the selection signal R / W is at the low level. When the signal R / W is at a high level, the write address WADR is selected and output to the line memory 1. The read address RADR is updated in synchronization with the rising timing of the selection signal R / W, and the write address WADR is updated in synchronization with the falling timing of the selection signal R / W.

  By doing this, the writing side can obtain 24-bit data (data for two pixels) by one writing, so it is only necessary to write once in two clocks, and when the selection signal R / W is at a high level. Write data WDATA is written (see FIG. 1B). Similarly, on the reading side, 24 bits of data (data for two pixels) can be obtained by one reading, so it is only necessary to read once every two clocks, and when the selection signal R / W is at a low level. Read data RDATA is read (see FIG. 1B). As a result, the clock frequency used in the data processing device shown in FIG. 13A or the data processing device shown in FIG. The data processing circuit according to the present invention shown in FIG. In addition, in the data processing circuit according to the present invention shown in FIG. 1A, since one line memory 1 can share reading and writing in terms of time, the line memory 1 can be a one-port memory. become.

  Further, since the data processing circuit according to the present invention shown in FIG. 1A includes only one line memory, it is not necessary to provide a memory decoder circuit or the like for each line memory. Since the line memory 1 may be a one-port memory and only one line memory is provided, it is not necessary to provide a memory decoder circuit or the like for each line memory, so that the present invention shown in FIG. The data processing circuit has the same capacity (24576 bits) and two line memories (the number of words in each line memory of the data processing apparatus shown in FIG. 13A is changed to half, and each line memory is changed to a two-port memory. The chip area can be reduced by about 20%.

  Also, in the data processing circuit according to the present invention shown in FIG. 1A, the data processing circuit according to the present invention shown in FIG. The memory capacity is half that of the data processing apparatus shown in FIG.

  The address space of the line memory 1 is divided into two. When writing to the line memory 1, the image data of the odd-numbered rows is written to the address space (address space (1)) of the first half of the line memory 1 and the image data of the even-numbered rows is written so that simple reading is performed at the time of reading. Write to the second half address space (address space (2)) of the line memory 1. For example, the 1st, 2nd, 5th, 6th,..., 2045th, 2046th image data is the first row image data, and the 3rd, 4th, 7th, 8th,. Therefore, the address of the line memory 1 is appropriately selected and stored as shown in FIG.

  The state of data writing to the line memory 1 and the state of data reading from the line memory 1 are as shown in FIG.

  At time t1, half of the image data on the first row is written in the address space (1) of the line memory 1, and half of the image data on the second row is written in the address space (2) of the line memory 1.

  Time t2 is the time when the writing of the image data in the first and second rows is completed. Since the reading of the first row of image data starts after time t1, that is, after half of the writing, the reading of the first row of image data does not overtake the writing of the first row of image data. At t2, the first row of image data that has not yet been read remains in the address space (1) of the line memory 1 only a little. The reading of the image data on the first row is completed by the time writing of the image data on the next third and fourth rows is started.

  At time t3, reading of the image data of the first row has already been completed and reading of the image data of the second row has been started, so that the entire address space (1) of the line memory 1 and the address space ( Data can be updated with the first one in 2). At time t3, writing of the next 3rd and 4th row of image data is started, but since all of the 1st row of image data written in the address space (1) of the line memory 1 has been read, 3 rows. There is no problem even if the image data is updated to the second image data. Since some of the second row image data written in the address space (2) of the line memory 1 has already been read, the second row image data can be read out. There is no need to catch up with writing image data on the fourth line.

  At time t4, half of the image data on the third row is written in the address space (1) of the line memory 1, and half of the image data on the fourth row is written in the address space (2) of the line memory 1. Thereafter, the same operation as described above is repeated while the number of lines of the input image data is updated.

  Thus, since the overtaking does not occur by slightly shifting the time of writing and reading, the data processing circuit according to the present invention shown in FIG. 1A is compared with the data processing apparatus shown in FIG. Half the memory capacity.

  Another configuration example of the data processing circuit according to the present invention is shown in FIG. The data processing circuit according to the present invention shown in FIG. 4A is output from a solid-state image sensor when 9-pixel addition is performed in the solid-state image sensor having a color filter with a 2048 × 2048 pixel Bayer array. Is a data processing circuit that processes an A / D-converted pixel data string (each pixel data is 12 bits), a 1368 word × 24-bit 1-port line memory 11 and a 12-bit line memory 11 Latch circuits 12 to 15, a 24-bit latch circuit 16, 12-bit latch circuits 17 and 18, and selectors 19 and 20 are provided. The line memory 11 and the latch circuits 12 to 18 have the same clock frequency and are synchronized.

The number of words in the line memory 11 is about 2/3 of the number of horizontal pixels of the solid-state image sensor, and the data width of the line memory 11 is twice the data width of each pixel data output from the solid-state image sensor. In the data processing circuit according to the present invention shown in FIG. 4A, write data (input data) to the line memory 11 is latched by four pieces of input pixel data by the latch circuits 12 to 15, whereby the latch circuit 12. The pixel data D1 output from the pixel data D4 and the pixel data D4 output from the latch circuit 15 are combined so as to have a double data width, that is, a 24-bit data width. Thus, the pixel data R _{9 (1,1)} in the first row and the first column and the pixel data Gr _{9 (1,2) in the} first row and the second column are combined and stored in the line memory 11 by one writing. can do. Similarly, the pixel data Gb _{9 (2,1)} in the second row and the first column and the pixel data B _{9 (2,2) in the} second row and the second column are combined and stored in the line memory 11 by one writing. The line memory 11 can be written once by combining the pixel data R _{9 (3,1)} in the third row and the first column and the pixel data Gr _{9 (3,2) in the} third row and the second column. Can be stored. Of course, the pixel data string output from the solid-state imaging device to the data processing circuit according to the present invention shown in FIG. 4A is not limited to the same arrangement as in FIG. If it is not the same as in FIG. 12A, it can be appropriately handled by increasing the number of latch circuits or changing the position where two pixel data are taken from the latch circuit group.

  By doing so, the writing side can obtain 24-bit data (data for two pixels) by one writing, and therefore only needs to be written once every two clocks (see FIG. 4B). Write data WDATA is written when the write address WADR is output from. Similarly, on the reading side, 24 bits of data (data for two pixels) can be obtained by one reading, so it is only necessary to read once every two clocks, and the reading address RADR is output from the selector 19. Sometimes read data RDATA is read. As a result, in the data processing circuit according to the present invention shown in FIG. 4A, the reading and writing can be shared in time by one line memory 1, so that the line memory 1 can be a one-port memory. It will be.

  Since the data processing circuit according to the present invention shown in FIG. 4A includes only one line memory, it is not necessary to provide a memory decoder circuit or the like for each line memory, which is compared with a configuration having a plurality of line memories. Thus, the chip area can be reduced.

  The address space of the line memory 11 is divided into four, and 342 words are assigned to each address space. In the writing to the line memory 1, the image data of the first row is converted into the first address space (address space (1)) of the line memory 11 with respect to the first three rows of image data so that simple reading is performed at the time of reading. ) Is written to the second address space (address space (2)) of the line memory 11, and the image data of the third row is written to the third address space (address space ( 3)), and for the next three rows of image data, the fourth row of image data is written into the fourth address space (address space (4)) of the line memory 11, and the fifth row of image data is lined. The first address space (address space (1)) of the memory 11 is written, and the image data of the sixth row is written to the second address space (address space (2)) of the line memory 11. As described above, the address space of the line memory 11 in which the image data is written is shifted every time the image data for three lines is written. For example, the 1st, 4th, 7th, 10th,... Image data is the 1st row image data, and the 3rd, 6th, 7th, 9th, 12th,. Since the 5th, 8th, 7th, 11th, 14th,... Image data is the image data on the 3rd row, the address of the line memory 11 is appropriately selected and stored.

  The data write status to the line memory 1 and the data read status from the line memory 1 are as shown in FIG.

  At time t1, 2/3 of the first row of image data is written into the address space (1) of the line memory 11, and 2/3 of the second row of image data is written into the address space (2) of the line memory 11. In addition, 2/3 of the image data in the third row is written in the address space (3) of the line memory 11.

  Time t2 is the time when the writing of the image data in the first, second, and third rows is completed. Since reading of the first row of image data has started after time t1, that is, after 2/3 of writing, reading of the first row of image data does not overtake writing of the first row of image data. At time t2, the first row of image data that has not yet been read remains in the address space (1) of the line memory 11 a little. The reading of the image data on the first line is completed by the time the writing of the image data on the next 4, 5, and 6 lines is started.

  At time t3, reading of the image data for the first row has already been completed and reading of the image data for the second row has been started, so that the entire address space (1) of the line memory 11 and the address space ( Data can be updated with the first one in 2). At time t3, writing of the image data for the next 4, 5, and 6 rows starts, but all the image data for the first row written in the address space (1) of the line memory 11 has been read. There is no problem even if the image data stored in the address space (1) of the line memory 11 is updated, and some of the second row of image data written in the address space (2) of the line memory 11 has already been read. Therefore, the image data reading is not caught up with the image data writing in the address space (2) of the line memory 11. However, since it is necessary to store the image data for three rows, the address space (4) of the line memory 11 is also used, the image data for the fourth row is written into the address space (4) of the line memory 11, and the line memory 11 The image data of the fifth row is written in the address space (1) of the image data, and the image data of the sixth row is written in the address space (2) of the line memory 11.

  At time t4, the reading of the image data of the second row has already been completed, and 1/3 of the image data of the fourth row is written into the address space (4) of the line memory 11, and the address space ( 1/3 of the image data of the fifth row is written in 1), and 1/3 of the image data of the sixth row is written in the address space (2) of the line memory 11.

  At time t5, the reading of the image data of the third row has already been completed, and 2/3 of the image data of the fourth row is written into the address space (4) of the line memory 11, and the address space ( 2/3 of the fifth row of image data is written to 1), and 2/3 of the sixth row of image data is written to the address space (2) of the line memory 11.

  Time t6 is the time point when the writing of the image data in the fourth, fifth, and sixth rows is completed. Further, reading of the image data of the fourth row starts after time t5, that is, after 2/3 of writing, and at time t6, the image data of the fourth row that has not yet been read is stored in the line memory 11. Only a little remains in the address space (4). Thereafter, while the number of lines of the input image data is updated, the address space of the in-memory 11 is shifted one by one, and the same operation as described above is repeated.

  In this way, the memory capacity is increased by one line, and the write and read times are slightly shifted so that no overtaking occurs. Therefore, the line memory of the data processing circuit according to the present invention shown in FIG. The memory capacity of 11 (= 1368 × 24) is about 4/3 times the memory capacity (= 2048 × 12) of one row when all pixel data is read from the solid-state imaging device.

  In addition, a pixel data sequence output from the solid-state image sensor is A / D converted by the A / D converter regardless of whether 4-pixel addition or 9-pixel addition is performed in the solid-state image sensor. As an example of a data processing apparatus that can rearrange the data in the order along the Bayer array, as shown in FIG. 6, six 12-bit latch circuits are provided, and each output data of the 12-bit latch circuits 21 to 26 is a selector. The line memory 28 has a memory capacity for adding nine pixels.

  For example, when pixel addition is performed in a solid-state imaging device having a Bayer color filter, the data processing apparatus according to the present invention converts a pixel data string output from the solid-state imaging device into an A / D conversion unit. This is used as a general data processing apparatus that rearranges the D / D converted data in the order along the Bayer array. The solid-state imaging device in which the data processing device according to the present invention is incorporated can be used by being incorporated in various electronic devices such as a camera-equipped mobile phone, a digital camera, and a surveillance camera.

These are figures which show the example of 1 structure of the data processor which concerns on this invention, and its operation timing. These are figures which show the storage condition of the data to the line memory of the data processor shown to Fig.1 (a). These are the figures which show the write-in and read-out condition of the line memory of the data processor shown to Fig.1 (a). These are figures which show the other structural example of the data processor which concerns on this invention, and its operation timing. These are the figures which show the write-in and read-out condition of the line memory of the data processor shown to Fig.4 (a). These are figures which show the further another structural example of the data processor which concerns on this invention. FIG. 4 is a diagram illustrating an example of a 10 × 10 pixel Bayer array. FIG. 8 is a diagram showing an image data string read from a solid-state imaging device having a Bayer array color filter shown in FIG. 7. FIG. 4 is a diagram illustrating an example of a 12 × 12 pixel Bayer array. These are figures which show an image data sequence at the time of performing 4 pixel addition. These are figures which show an example of a Bayer arrangement | sequence of 18x18 pixels. These are figures which show an image data sequence at the time of performing 9 pixel addition. These are figures which show the example of 1 structure of the data processing apparatus which rearranges a data sequence, and its operation timing. These are figures which show the arrangement | sequence of the color filter which the conventional solid-state image sensor has.

Explanation of symbols

1 Line Memory 2-5 Latch Circuit 6, 7 Selector 11 Line Memory 12-18 Latch Circuit 19, 20 Selector 21-26 Latch Circuit 27 Selector 28 Line Memory

Claims (6)

A data width changing unit that outputs two combined data elements of the input data string and changes the data width by a factor of two;
1-port memory for writing each data element of the data string output from the data width changing unit;
A data processing apparatus comprising: a data width restoring unit that divides each data element read from the memory into two and restores the data width.   The data processing apparatus according to claim 1, wherein the data width changing unit includes a plurality of latch circuits, and the data width restoring unit includes a plurality of latch circuits. A solid-state imaging device having a color filter with a Bayer arrangement and performing pixel addition inside, an A / D conversion unit for A / D converting a pixel data string output from the solid-state imaging device, and the A / D conversion unit A solid-state imaging device comprising a data processing device for processing a pixel data string output from
The data processing device outputs two data elements of the pixel data string output from the A / D conversion unit together and outputs a data width changing unit that changes the data width by two times, and outputs from the data width changing unit 1-port memory for writing each data element of the data string to be read, and a data width restoring unit that divides each data element read from the memory into two and restores the data width to the original data width, A solid-state image pickup device, wherein the pixel data sequence output from the unit is an image data sequence in which image data is arranged in an order along a Bayer array.   The solid-state imaging device according to claim 3, wherein the data width changing unit includes a plurality of latch circuits, and the data width restoring unit includes a plurality of latch circuits. The memory has a plurality of divided address spaces, i.e., has a plurality of divided address spaces;
All image data elements belonging to the same row of the pixel data string output from the A / D converter are written in the same divided address space,
After reading of the image data element in the a (a is a natural number) line written in a certain divided address space is started, the certain image data element in the b (b is a natural number, b> a) line 5. The solid-state imaging device according to claim 3, wherein writing to the divided address space is started, and the image data elements in the a-th row are sequentially updated to image data elements in the b-th row.   An electronic apparatus comprising the solid-state imaging device according to claim 3.

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