JP2000020705A - Parallel image processing processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallel image processor capable of processing one period of arithmetic processing without being restricted by one horizontal scanning period and processing the arithmetic processing by an arithmetic processing part having the small number of arrays. SOLUTION: The parallel image processing processor is constituted of an arithmetic processing part 1 constituted of an arithmetic processing means 2 and two registers A, B, temporary registers TA, TB corresponding to respective registers A, B and capable of circularly transferring to respective registers A, B and a program control part 3 for controlling the arithmetic processing part 1 and the temporary registers TA, TB and executes single instruction multiple data stream(SIMD) type image processing of an input signal DATA consisting of N data per period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel image processor for performing digital signal processing of image signals from a video camera, a television, or the like by a software program.

[0002]

2. Description of the Related Art The basic structure of a conventional array type image processor will be described with reference to FIG. The input SAM unit 802 illustrated in FIG. 8 is a register in which N registers each having a bit width of each pixel data are arranged in the horizontal direction (column direction), and has a function of sequentially transferring data from left to right in the figure. . Each of the registers stored in the input SAM unit 802 can similarly transfer data (in the column direction) to each of the registers in the data memory 803, which is composed of N registers arranged in the horizontal direction.

The arithmetic processing unit 804 has a configuration in which N arithmetic circuits having the same arithmetic function are arranged in the column direction. A data memory A 803 and a data memory B 805 composed of N horizontal registers are arranged. Connected in units.

The output SAM section 806 has H registers in the horizontal direction, each having a bit width of each pixel data of the output signal, and has a function of sequentially transferring data from left to right in the figure. , And is output from the right end of the data memory B 805 to the data output terminal 808. Data transfer and processing between the blocks are performed by the processing unit 80 in units of columns.
9 is performed.

[0005] The program control unit 807 is provided with an input SAM unit 802, a data memory A 803, a data memory B 805, and an output SA according to a program stored therein.
A control circuit that outputs a control signal for reading and writing data of the M unit 806 and controls the operation content of the arithmetic processing unit 804.

An image signal to be processed is generally input from a data input terminal 801 in FIG. 8 as a sequential signal in which each pixel data of a two-dimensional image is arranged one-dimensionally in a horizontal scanning direction in synchronization with a pixel clock. . The input data is input S
The pixel data is sequentially stored in the AM unit 802 and transferred to the data memory A 803 when the pixel data for one horizontal scanning period is stored. The pixel signal held in the data memory A 803 is
The arithmetic processing unit 804 performs arithmetic processing based on the program of the program control unit 807, and the data memory 803A
Alternatively, it is stored in the data memory B805. The data is stored in the data memory B 805 when the final arithmetic processing of the program is performed, and the output SAM is output from the data memory B 805 when the data of the previous horizontal scanning period stored in the output SAM unit 806 is read. It is transferred to the unit 806. The output SAM unit 806 sequentially outputs data to the data output terminal 808 according to the pixel clock.

[0007]

The following describes that in the case of the conventional configuration shown in FIG. 8, the cycle at which the calculation is performed is limited to the horizontal scanning period. Generally, an FIR filter is frequently used in image processing. As an example of the filter, a horizontal direction FIR (Finite impulse respo
nse) Filter processing is represented by the following equation (1). In this equation, the order K = 4.

[0008]

(Equation 1)

FIG. 9 shows the contents of processing in the case of generating n output data y0 to yn-1 by performing FIR filter processing on input signals x0 to xn-1 of n pixels.

In FIG. 9, reference numeral 901 denotes an input pixel data memory, reference numeral 905 denotes an output data memory, and reference numerals 902, 903, and 904 denote arithmetic processing contents of an FIR filter processed by an arithmetic processing unit. . The FIR filter for creating the i-th output data Yi is composed of five (Xi-2, Xi-1, Xi, Xi + 1, Xi + 2) addresses in the input pixel data memory 1, as indicated by reference numeral 903. Processing is performed using pixel data.

Here, when the FIR filter processing 902 for creating the 0th output data Y0 is considered, data of two pixels on the left and right of the 0th input data X0 is required.
Since the data on the left does not exist in the input pixel data memory 1, the characteristics of the output data of Y0 are different from the characteristics of Yi.

In the above-described filtering process, pixels having different characteristics are generated at two pixels at both ends of the input pixel data memory 901. Generally, when the order of the FIR filter is the K-th order, the data memory 901 is not used. K / 2 at both ends
Pixels with different characteristics (in the case of even order) and (K + 1) / 2 pixels (in the case of odd order) are generated.

Pixels having different characteristics occur at both ends of a pixel row during one horizontal scanning period, and are masked at the time of producing a final video signal. Therefore, the image does not deteriorate.

However, for example, if the number of pixels in the horizontal scanning period is N
Assuming that the number n of columns of the data memory A803 is (1/2) N (units), the input data Xi divides the pixel column in the horizontal scanning period into two, and firstly, the first half of (1)
/ 2) N (pieces) input data are input to the data memory A 803 and processed, and after the processing is completed, the latter half (1/2) N
Is input and the process is performed. Finally this 2
A set of (1/2) N (pieces) of processing data is connected to
Periodic data is created. At this time, K
There is a problem that a pixel row having different pixel characteristics is generated, and this is generated in the image as a vertical stripe of a two-dimensional image, thereby deteriorating the image.

For this reason, in the array type image processor, it is necessary to match the processing cycle to one horizontal scanning period, and to match the number of columns of a parallel operation array such as a data memory to the number of pixels in one horizontal scanning period. is there. Since the number of horizontal pixels of the image to be processed is in the hundreds and hundreds of pixels, the number of parallel processing arrays is also required in the thousands, and if this is made into an integrated circuit, the circuit scale may become very large. is expected.

For this reason, a conventional array-type image processor has a configuration in which the arithmetic circuit is processed by one bit and one-word operation is performed in several steps in order to reduce the number of gates per array. There were many. In addition, since the processing cycle is defined by the number of horizontal pixels of the image, the number of arrays must be changed according to the number of pixels of the image to be processed. Therefore, an integrated circuit has to be created again according to the image size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is possible to perform processing at a cycle that is not limited to one horizontal scanning period in one cycle of arithmetic processing. An object of the present invention is to provide a parallel image processing processor that can be processed by an arithmetic processing unit.

[0018]

The present invention has the following configuration to achieve the above object. The invention of claim 1 is
S for an input signal consisting of N data per cycle
In a parallel image processor for performing IMD-type image processing, a parallel image processor 1 comprising an arithmetic processing circuit and a base register
An arithmetic processing unit having M data processing units connected in parallel, a temporary register having P base registers provided in parallel, and control means for controlling the arithmetic processing unit and the temporary register; The unit is composed of M arithmetic processing units, and the base register of the M column and the base register of the P column of the temporary register are:
A parallel image processing processor for performing data transfer in the column direction based on a control signal from the control means and cyclically transferring data in the column direction between the base register and the temporary register of M columns. is there.

According to a second aspect of the present invention, when the unit of one cycle for performing image processing is one horizontal scanning period and the number of pixels to be processed in one horizontal scanning period is N, the number M of arithmetic processing units is N 2. The parallel image processor according to claim 1, wherein the value is smaller.

According to a third aspect of the present invention, in the image processing, when the order of the filter process having the maximum order among the filter processes for performing an operation on a plurality of pixels in the horizontal direction is K, the number of base registers in the temporary register P is at least K (for even order) or K + 1 (for odd order)
The parallel image processing processor according to claim 1 or 2, wherein:

According to the present invention, when performing SIMD type image processing on an input signal consisting of N data per cycle, one data is stored in each base register of M columns of base registers, and a temporary register is stored. A predetermined P data of the M data used in the previous processing stored in the previous processing are stored, and the M data of the base register are processed in parallel by the arithmetic processing circuit based on a control signal from the control means, Next, a predetermined number of data is cyclically transferred between the base register and the temporary register, and M data in the base register are again processed in parallel by the arithmetic processing circuit based on a control signal from the control means. After the processing is completed without affecting the M data of the base register, predetermined P data is stored in the temporary register, and the above processing is repeated after the next M data is newly stored in the base register. Done.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic block diagram of a parallel image processing processor. An arithmetic processing unit 2 and an arithmetic processing unit 1 including registers A and B perform data transfer cyclically in correspondence with the registers A / B. SIMD (Sing) is performed on an input signal DATA consisting of a temporary register TA / TB, an arithmetic processing unit 1 and a program control unit 3 for controlling the temporary register TA / TB.
le instruction multiple data stream) type image processing.

The arithmetic processing means 2 is provided with M arithmetic processing circuits in parallel.
B, respectively, and performs processing of data in the registers A and B, for example, FIR filter processing, according to a processing instruction from the program control unit 3.

Each of the registers A and B is a register in which M base registers each having a plurality of bits of registers are provided in parallel, and data to be stored in each base register in accordance with a processing instruction from the program control unit 3 is adjacent to the registers A and B. It is possible to shift to a matching base register.

The arithmetic processing section 1 is composed of the arithmetic processing means 2, the register A and the register B as described above. More specifically, the arithmetic processing unit U (1 arithmetic circuit unit of 1 data unit) , Registers A and B each
(Base registers) are connected in parallel.

The temporary registers TA and TB each have a plurality of base registers each having a plurality of registers arranged in parallel with P columns. Like the registers A and B, the data to be stored in each base register is adjacent to the temporary registers TA and TB. It is possible to shift to a matching base register.

The register A and the temporary register T
A can shift data in each register, and can cyclically transfer data in the column direction between the register A and the temporary register TA based on a control signal from the program control unit 3. I have. Similarly, data can be cyclically transferred in the column direction between the register B and the temporary register TB.

The operation of the above-structured parallel image processor will be described with reference to the block diagrams of FIGS. Steps (1) to (6) in FIGS. 2 and 3 indicate the order of processing. The upper half of step (1) in FIG. 2 shows the pixel data 1 of the number H (pieces) of pixels in one horizontal scanning period to be processed by the image processor, and is provided outside the image processor. Memory (built-in DRA
M). The lower half of step (1) shows data stored in a register A constituting the image processor and a temporary register TA connected to the register A. In addition, the number of the arithmetic processing units U is set to 1/4 of the number N of pixels.

First, in step 1, the built-in DR
BLK # 2 which is a part of the AM pixel data 1 is transferred to the register A. At this time, it is assumed that the temporary register TA holds part (B) and (C) of the pixel data of BLK # 1 in the processing one cycle before.

Next, in step 2, while the temporary register TA and the register A are connected, they are shifted rightward in the column direction, and each image data BLK is stored in the register A from the left.
# 1 (C), BLK # 2 (A) and BLK # 2 (B) are held. Further, the data of the portion (C) of BLK # 2 held in the register A is transferred to the temporary register TA. Thereafter, processing is performed on the pixel data held in the register A, and the data resulting from the arithmetic processing is stored in the register B or a register C described later, and the data in the register A is not updated.

In the processing of the horizontal FIR filter, for example, i
In the case where the FIR filter output of the pixel at the time is created by the filter of the above equation (1), (i-2, i-1, i, i +
The (i, 2) -th five pixel data are used, and the necessary data is connected to the i-th arithmetic processing unit by performing a horizontal shift while the register A and the temporary register TA are connected. You. In the horizontal FIR filter processing on the pixel data held in the register A, when the filter order is K, the K / F
Pixel data of 2 (even order) or (K-1) / 2 (odd order) pixels is required. This is because of the P column in which P is at least K (even order) or K + 1 (odd order). BLK # in the temporary register TA configured by the register
1 (B) and BLK # 2 (C) are held,
Since the data is transferred to the register A by a cyclic shift at a necessary point in time, there is no difference in characteristics due to missing pixels in the filtering process on the pixels at both ends of the register A.

After the signal processing is completed, in step (3),
The part (B) of BLK # 2 held in the register A is transferred to the temporary register TA.
2 (B) and (C) are held, and BLK
The process for the pixel data of # 2 is completed.

Next, referring to FIG. 3, in step (4), B
After the data of LK # 3 is transferred to the register A, the processing of steps (5) and (6) is performed, which is the same as the processing of steps (1), (2) and (3) of FIG. Become.

Although the above is the processing for the register A holding the input pixel data, the same processing operation can be performed for the register B holding the data in the middle of the signal processing.

In the parallel image processor described above, in the case of FIR filter processing in the middle of signal processing, pixel data corresponding to missing pixels at both ends used in the same filter processing in the next block is stored in a temporary register. Save to TA / TB. Then, the data of the next block is input to the registers A / B, and the intermediate FI
Immediately before performing the operation of the R filter, the data in the register A / B and the temporary register TA / T created one cycle before
By cyclically shifting the B data, the effect of missing pixels in the FIR filter can be removed. However, in this case, the pixel data saved in the temporary register TA / TB is only the pixel data created by the past processing. Therefore, at the time when the FIR filter processing is performed, the order K / K of the order K of the FIR filter is obtained. Two-pixel (even-order) or (K + 1) / 2-pixel (odd-order) data whose phase is delayed in the horizontal direction is created. Blocks that perform processing in the same manner as the registers A / B No degradation of pixel characteristics occurs for data at the boundary of.

Next, the parallel image processor described above will be described in more detail. FIG. 4 is a block diagram of the parallel processing array unit 4 including the arithmetic processing unit 1 and the temporary registers TA / TB, FIG. 5 is a block diagram of the program control unit 3, and FIG. 7 and FIG. 7 are block diagrams of the temporary register TA.

In FIG. 4, register A is divided into register banks # 1 and # 2, and one of register banks # 1 / # 2 is connected via a selector 5 to a local bus which is an external bus of the image processor. It is connected.
Register banks not connected to the local bus are connected to the register B and the operation unit 2 via the selector 6.

One of the register banks # 1 / # 2 is also connected to the temporary register TA, so that data can be cyclically transferred in the column direction. The register B is connected to the arithmetic unit 2 and the register A, and is also connected to the temporary register TB so that data can be cyclically transferred.

Below the operation unit 2, a register C for temporarily storing processing data is provided. Each control signal and data buses (DA) to (DH) at the right end in the figure are connected to the program control unit 7 in FIG.

FIG. 5 shows a program control unit 3, which is a program RAM (Random ac) for storing a control program.
process memory 7, work RAM 8, program counter 9 and its control unit 10, and arithmetic unit (ALU (Arithmetic and
Logical Unit) / MLT ((Multiplier) Multiplier) 11 and DMA (Direct Memory Access) for external control
It is composed of a controller 12.

FIG. 6 shows the parallel processing array unit 4 shown in FIG.
In FIG. 1 (each is distinguished by adding a subscript ( ₂ )). The configuration of the base register A ₂ , the base register B ₂ , and the base register C ₂ is, for example, a multi-bit register DFF (0), DFF (1),
A case of a base register including four words of DFF (2) and DFF (3) is shown. The base register is not limited to four words.

The output of the base register A ₂ has a function of performing a column direction of the data transfer to the left and right are adapted to lead to base register A ₂ of the right and left adjacent array. The output of the base register A ₂ is
It is connected to the input of the arithmetic unit B ₂ via the. Like the base register B ₂ also base register A _2, the output has a function of performing a column direction of the data transfer to the left and right are adapted to lead the base register B ₂ array adjacent the left and right.

[0043] The output of the base register B ₂ is connected to an input of the arithmetic unit 3 _2. The figures below the operation portion 3 _2, there are base register C _2, is connected to the input via the operation section 3 ₂ register.

[0044] The arithmetic unit 3 _2, each base register A _2, B
₂ , C ₂ , and a selector 14 for selecting data common to all arrays sent from the program control unit 3 through the common data bus, a multiplier 15, an ALU 16, and a status register 17. Outputs of the ALU 16 and the status register 17 are connected to inputs of a base register A ₂ , a base register B ₂ , and a base register C ₂ , and are written into a register selected by a program by a control signal.

FIG. 7 is a detailed diagram of temporary register TA / TB. As an example, a multi-bit register DFF
Are arranged in three columns in the column direction. Between each base register TA ₂ / TB ₂ , data can be transferred to an adjacent register, and registers TA ₂ at both ends of the temporary register are used.
/ O of TB _2, by being connected to the base register A ₂ / B ₂ at both ends of the register A / B, the register A / B and the temporary register TA / TB is able to perform the cyclically data transfer ing.

As described above, by providing the temporary register TA / TB, it is possible to eliminate the characteristic deterioration due to the pixel omission occurring at both ends of the pixel data to be processed, which occurs in the horizontal FIR filter processing. Thus, division processing can be performed without limiting the processing unit to one horizontal period, and an image processor with a fixed array number capable of processing an image with an arbitrary number of horizontal pixels can be realized.

Although the preferred embodiment of the present invention has been described in the above embodiment, it goes without saying that the present invention is not limited to this. For example, in the present embodiment, as a set of a register and a temporary register which are composed of a plurality of columns of base registers and which can cyclically transfer data in the column direction, a register A and a temporary register TA, and a register B and a temporary register TB are set. Although two sets have been described, the present invention can be implemented as long as at least one set is provided.

[0048]

As described above, according to the present invention, the provision of the temporary register capable of cyclically transferring a predetermined number of data to and from the base register is provided.
For an input signal consisting of N data per cycle, N
Horizontal FIR using less than M columns of base registers
Even if the filtering process is performed, it is possible to eliminate the characteristic deterioration caused by the missing pixels at both ends of the pixel data, which has conventionally occurred.
Therefore, since the division processing can be performed without limiting the processing unit in the image processor to one horizontal period as in the related art, the processing of the image having the number of horizontal pixels is realized by the image processor having an arbitrary fixed array number. This makes it possible to realize a smaller apparatus and a higher function as the processing speed increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of a parallel image processing processor according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an operation of the parallel image processor according to the embodiment of the present invention;

FIG. 3 is an operation explanatory block diagram following FIG. 2 of the parallel image processing processor according to the embodiment of the present invention;

FIG. 4 is a block diagram of a part of the parallel image processor according to the embodiment of the present invention;

FIG. 5 is a block diagram of a program control unit 3 of the parallel image processing processor according to the embodiment of the present invention.

FIG. 6 is a block diagram of an arithmetic processing unit U of the parallel image processing processor according to the embodiment of the present invention.

FIG. 7 is a block diagram of a temporary register TA / TB of the parallel image processor according to the embodiment of the present invention.

FIG. 8 is a block diagram of processing of a conventional parallel image processing processor.

FIG. 9 is an explanatory diagram of a process of an FIR filter.

[Explanation of symbols]

Reference Signs List 1 arithmetic processing unit 2 arithmetic processing means 3 program control unit A, B register A ₂ , B ₂ base register TA, TB temporary register TA ₂ , TB ₂ base register U arithmetic processing unit DATA Data of N pixels in horizontal scanning period

Claims (3)

[Claims] 1. A parallel image processing processor for performing SIMD type image processing on an input signal composed of N data per cycle, comprising: a data processing unit comprising a processing circuit and a base register; An arithmetic processing unit connected in parallel with M units, a temporary register provided with P base registers in parallel, and control means for controlling the arithmetic processing unit and the temporary register; and a base register and a temporary register in the M columns The base registers in the P columns perform data transfer in the column direction based on the control signals from the control means, respectively.
A parallel image processing processor for cyclically transferring data in a column direction between a column base register and a temporary register. 2. When the unit of one cycle for performing image processing is one horizontal scanning period, and the number of pixels to be processed in one horizontal scanning period is N, the number M of arithmetic processing units is a value smaller than N. 2. The parallel image processor according to claim 1, wherein: 3. In image processing, if the order of a filter process having the maximum order among filter processes for performing an operation on a plurality of pixels in the horizontal direction is K, the number P of base registers of the temporary register is at least K The parallel image processor according to claim 1, wherein the number is equal to or more than (in the case of an even order) or K + 1 (in the case of an odd order).