JPS61248164A - Picture processing device - Google Patents

Abstract

PURPOSE:To execute the filtering operation and the mask operation with a micro computer at a high speed by reading once the data of plural picture element parts of the small area composed of a certain picture element and an adjoining picture element. CONSTITUTION:A shift register 16 is composed of 514 bits, delays successively the picture data outputted serially from an image pick-up device 10 for 514 picture elements only, and nine bits of data Dn which are not delayed, data Dn+1 which are delayed for one picture element, data Dn+2 which are delayed for two picture elements, data Dn+256 which are delayed for 256 picture elements (one row part) and data Dn+514 which are delayed for 514 picture elements are taken out in parallel and inputted to a picture memory 18. Change- over switches 12 and 14 and a selector 22 are changed over, the address signal is given from a CPU 24 to a picture memory 18 and the data are read. Thus, since the data of nine bits of the small are of 3X3 can be once read by the single time addressing operation, the filtering operation and the mask operation to add the arithmetic logic processing to the picture data of the small area can be executed at a very high speed.

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to an image processing device that processes digital images using a computer, and particularly to an image processing device that can perform filtering operations and masking operations on digital images with high efficiency. Regarding technology for

[Technical background of the invention and its problems 1 Filtering operations and masking operations are frequently used as basic processing techniques in computer image processing. This is an operation for performing arithmetic processing on image data for a small area formed by a plurality of mutually adjacent pixels on the image plane.

-For example, 1 pixel is 1 bit and 1 screen is 256x25.
Assume a digital image composed of 6 matrices.

This image data is stored in a (256x256) word x 1 bit image memory and processed by a computer. Here, if we perform dilation processing using general 3x3 filtering, we will read data for a total of 9 pixels in a 3x3 small area from the image memory, and if there is even one 111 I+ in the 9-bit data. If there is, "°1" is output as processed data, and when all 9 bits are "0", 0 is output as processed data.

At this time, the CPU calculates the address nine times in order to address nine pixels in a 3x3 small area.

Address output processing is performed to read 9-bit data from the image memory, and predetermined logical operations are performed in parallel. This is the operation to obtain 1 bit of processed data, and the above operation must be performed 256×256 times to process the entire one screen. This processing is a fairly large load, and the processing time required for this on a microcomputer is enormous, which is a major cause of hindering the speeding up of image processing.

In order to speed up the above processing, devices have been developed that additionally use a special parallel processing unit instead of using a computer to process everything sequentially, but this type of parallel processing unit is extremely difficult to use. It is complex, sophisticated hardware, and expensive.

[Object of the Invention] This invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an image processing device that allows filtering operations, mask operations, etc. to be performed at high speed even with a microcomputer. There is a particular thing.

[Summary of the Invention] In order to achieve the above object, in the image processing device according to the present invention, one pixel has a bits and one screen has b×c bits.
Image data consisting of pixels is sequentially input pixel by pixel into a delay means in the same order as raster scanning, and the delay means sequentially delays the image data by a predetermined pixel to form a small area on the b×c image plane. Consisting of mutually adjacent totals of 6
Take out the data for pixels in parallel and d× for that 0 pixels
a-bit data, one word is d×a bits, bXC
The image was configured to be stored in a word-structured image memory.

[Embodiment of the Invention] FIG. 1 shows the configuration of an image processing apparatus according to an embodiment of the invention. Imaging device 1.0 is configured using COD, for example, and one pixel has one bit and one screen has 256 pixels.
As shown in the second factor, image data consisting of X256 pixels is output in synchronization with a clock signal, one pixel per one bit, in the same order as raster scanning (ascending order in the X row direction and Y column direction). Image data and a clock signal from the imaging device 1o are input to the shift register 16 as the delay means via the changeover switch 12.14.

The shift register 16 has a 514-bit configuration, and the shift register 16 has a 514-bit configuration.
Image data serially output from 0 is sequentially delayed by 514 pixels in synchronization with a clock signal. From the shift register 16, input stage data (non-delayed data)
Dn, data Dn+1 delayed by 1 pixel, data [)n+2 delayed by 2 pixels, and 256 pixels (1 row)
Delayed data Dn+256, data Dn+257 delayed by 257 pixels, and data D delayed by 258 pixels.
n+258, data Dn+512 delayed by 512 pixels (2 rows), and data Dn+ delayed by 513 pixels.
513 and data Dn+514 delayed by 514 pixels, a total of 9 bits, are taken out in parallel and become data input to the image memory 18.

The image memory 18 is 256x25 with 9 bits per word.
It consists of a 6-word RAM. This image memory 18
The address input is given from the address counter 20 or the CPU 24 via the selector 22. Address counter 20 counts clock signals from imaging device 10 and creates an address signal for image memory 18 .

The CPU 24 not only reads and processes data from the image memory 18, but also controls the entire device, controlling the changeover switches 12 and 14, and controlling the shift register 1.
6, address counter 20 clear control, selector 22
switching control, read/write control of the image memory 18, etc.

In the above configuration, when 1-bit data [)n of a certain pixel is output from the m-image device 1o, the shift register 16 outputs the aforementioned delayed data Qn+1 to Dn+514.
8-bit data is output, and these 9-bit data in total are input in parallel to the image memory 18, at which time the pixel address ff given from the address counter 20 is
l is written.

This 9-pit data Dn -Dn +514c, the third
As shown in the figure, a total of 9 mutually adjacent pixels constituting a small area of 3 x 3 pixels on an image plane of 256 x 256 pixels.
This is data for pixels. This 9-bit data for 9 pixels is written into the image memory 18 as one word. The image memory 18 has a capacity of 256x2 56 words corresponding to 2 or 56x256 pixels on a one-to-one basis, and one word-9 corresponding to the 3x3 small area mentioned above.
Bit data is written to address m corresponding to the pixel located at the center of each of the 3×3 small areas (corresponding to the pixel with data On+257 in FIG. 3). In other words, data for one screen of 256 x 256 bits from the imaging device 10 is (2
56 x 256) words In the memory 18 of an image with a 9-bit configuration, a 3 x 3 small area consisting of a center pixel and 8 pixels around it.9 pixels - 9 bits as one word. It is converted and stored.
When the processing CPU 24 processes the data in the image memory 18, the selector switch 12
．． 14 and selector 22 to the CPU 24 side, and
An address signal is given from the PU 24 to the image memory 18 to read out the data.
What should be noted here is that the CPU
When an address corresponding to a certain pixel is given from 24 and data is read out from the image memory 18, a total of 9 data is obtained from the image memory 18, including the data of the specified pixel and the pigs for the surrounding 8 pixels.
The point is that bits of data are read out at once.

With conventional image processing devices, address creation and address output operations had to be performed nine times in order to read image data of a 3x3 small area in conjunction with filtering and mask operations. According to the image processing device,
This is because 9-bit data in a 3×3 small area can be read out from the image memory 18 at once with a 1- addressing operation. Therefore, filtering operations and mask operations that apply logical operations to the image data of this small area can be performed at high speed.

In the above operation description, image data serially output from the imaging bag @10 is stored in the image memory 18, but image data processed by the CPU 24 can be stored in the image memory 18 in the same manner. In that case, changeover switch 12.14 is switched to CPU 24 side image processing spring, and the CPU 24 side image processing data is output in series in synchronization with the clock signal.
Input 9 bits of data in parallel. The addresses to be given to the plurality of planes 18 of this digitized image memory may be given from the address counter 20 or from the CPU.
It is also good to give it directly from 24. In the above embodiment, a value image is simply assumed to be 2, where 1 pixel = 1 bit, but the present invention can be implemented similarly to a multi-value image in which 1 pixel is composed of a plurality of bits and image processing is performed. Furthermore, it goes without saying that the pixel configuration of one screen is not limited to the embodiment. Also, extracting from the image plane
The m6 small area shown in Fig. 41 is not limited to 9 pixels of 3×3, but any small area can be set. The configuration of the above delay means is determined according to the set small area. The delay means is not limited to the one shift register in the embodiment, but a similar delay effect can be obtained by using a RAM or the like shown in FIG. 10...
Anti [effect of invention]
16... When a corresponding address is given to the image memory, multiple pixel valves of a small area consisting of that pixel and pixel are read out at once, so this small area 1 It is possible to carry out arithmetic operations on elementary data such as ring operations, mask operations, and Ravellien coding. Therefore,
This type of processing can be performed extremely quickly on a computer without the use of special parallel processing units.

[Brief explanation of drawings]

1 is a diagram of an image processing system according to an embodiment of the present invention;
The figure shows the order in which image 1 is generated in the same device as above.
be. 1-image device's foot register (delay means) Fig. 2 - Fig. 3

Claims (1)

[Claims] Image data consisting of a bit per pixel and bxc pixels per screen is input to a delay means one pixel at a time in the same order as raster scanning, and this delay means sequentially delays the image data by a predetermined pixel. Then, data for a total of d pixels adjacent to each other constituting a small area on the b x c image plane is taken out in parallel, and the data of d x a bits for the d pixels is divided into 1 word with d x a bits. An image processing apparatus characterized in that the image processing apparatus is configured to store data in an image memory having a b×c word structure.