JPH1074141A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process the data of two-dimensional blocks with high efficiency by using an input data replacement means which performs the vertical-horizontal rearrangement of input data in every prescribed number of them to set the data bits in the horizontal direction and to arrange the block data in the vertical direction respectively. SOLUTION: An input data replacement circuit 8 outputs the block data to a data input register 1 and at the same time the next block data are successively given to the circuit 8. Then the input data undergo the vertical-horizontal rearrangement and are outputted to the register 1. At the same time, the write addresses of the register 1 are increased one by one, and 8 pieces of data on the first line of a block are stored in addresses 16 to 23 of the register 1. In other words, a horizontal 8-bit space is secured between two blocks and no data are written in this space. Therefore, 0 is held in the space secured between both blocks as long as the data stored in the register 1 are previously initialized into 0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for digitally processing a video signal or the like according to a program, and more particularly to a signal processing device capable of processing two-dimensional block data.

[0002]

2. Description of the Related Art As a programmable processor for digitally processing a video signal such as a television signal, a 1-bit ALU (arithmetic logic unit) is provided with the number of pixels per line.
SIMD (Single Instruction-stream M) that performs the same processing on the data of all pixels in one line at the same time with the same instruction
ultiple data-stream) processor (for example, "Jim Childers, et al" SVP: Serial Video
Processor ", IEEE Custom Integrated Circuits Confe
rence 17.3, 1990 ").

This processor includes a processor element having a 1-bit ALU and two register files.
With the number of pixels of a line, one line of pixel data is stored in a register file, and each processor element reads 1-bit data from each of the two register files, executes a 1-bit operation, and executes a 1-bit operation. Store the data in one of the register files. Since the same instruction is given to all processor elements,
The same 1-bit processing is performed on all the pixel data of one line. By repeatedly executing the one-bit process, necessary processes such as a filter process are realized. Further, this processor has a left-right communication function of taking in the data of the register files of the left and right processor elements, and can perform a horizontal filtering process using some pixel data in the horizontal direction.

However, two-dimensional DCT (discrete cosine transform) and inverse DCT processing used in image compression and decompression processing are processing in units of two-dimensional blocks, and the product-sum operation is the main processing. The multiplication coefficient differs depending on the pixel position in the above, and cannot be realized by a processor that performs the same processing on all the pixel data of one line.

On the other hand, for example, Japanese Unexamined Patent Publication No.
In the video signal processor of No. 29, a means for converting the input video signal into serial / parallel is provided, and the data obtained by serial / parallel conversion is temporarily stored in the input shift register, and then the data of the two-dimensional block is arranged in one column in the memory. By doing so, calculations can be performed on arbitrary data in the block.

[0006]

However, in the above configuration, if the number of pixels in the line direction of one block is N, for example, N pieces of pixel data are arranged in one column, so that all pixels in one line Compared to the case where the same processing is performed, the width becomes 1 / N and the number of ALUs becomes 1 / N.
Since the processing of the data of N pixels in the line direction is performed by U, there is a problem that the calculation performance is significantly reduced.

Further, the input shift register has a problem that the number of bits in the vertical direction becomes N times, the time required for transfer from the input shift register to the memory becomes N times, and the processing performance is reduced. did.

Further, the ratio of the length and width of the memory and the number of ALUs differ greatly between the case where the same processing is performed on all the pixels of one line and the case where the processing is performed on a block basis. There was a problem that it was difficult to share the components.

[0009] Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a plurality of arithmetic units for performing processing in the SIMD method,
An object of the present invention is to provide a signal processing device that efficiently realizes processing on data of a two-dimensional block.

[0010]

In order to solve the above-mentioned problems, a signal processing apparatus according to the present invention comprises an input data replacing means for rearranging input data by a predetermined number of data and outputting the sorted data; An input data register that continuously stores data output from the data replacement means in a vertical column unit and reads the stored data in a horizontal row unit, a memory for storing a plurality of data, and performs an operation on a plurality of inputs. An arithmetic unit array unit to perform, data to be written in units of horizontal rows, an output data register to read stored data continuously in units of vertical columns, and data read from the output data registers to be read out by a predetermined number of data, Output data replacing means for performing vertical and horizontal rearrangement and outputting the data, the arithmetic unit array unit performs an arithmetic operation by using a plurality of data read from the memory as an input, Mori stores the output of the read data or arithmetic unit array unit from the input data register, the output data register is one to write the output of the read from memory data or the operation unit array unit.

According to the present invention, the data of the same block is arranged in the vertical direction of the memory with the bit direction horizontal to the data of the two-dimensional block, and the processing of each block is performed in parallel by the arithmetic unit array unit. It has the effect of doing. As a result, a signal processing device that efficiently processes data of the two-dimensional block can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a signal processing apparatus according to Embodiment 1 of the present invention.

In FIG. 1, reference numeral 1 denotes a data input register for storing successively applied data in units of H words in units of one column and reading out the stored data in units of one row.

Reference numerals 2 and 6 denote memories for holding the data read from the data input register 1 and the data of the operation result, and store H-bit data horizontally and V-word data vertically. Reading and writing are performed on a horizontal row basis.

Reference numerals 3 and 5 denote shifters which shift and output data read from the memories 2 and 6, respectively.

Numeral 4 denotes an arithmetic unit array unit which performs an arithmetic operation on the data output from the shifters 3 and 5, and outputs the result to the memories 2 and 6.

Reference numeral 7 denotes an output data register for writing the output of the arithmetic unit array section 4 or the H-bit data read from the memories 2 and 6 in units of horizontal rows and reading and outputting H words in units of vertical columns in order. is there.

Reference numeral 8 denotes an input data replacement circuit that rearranges the input data vertically or horizontally or outputs the data as it is to the data input register.

Reference numeral 9 denotes an output data replacement circuit that rearranges the data output from the output data register 7 vertically or horizontally or outputs the data as it is.

Reference numeral 10 denotes a program control unit for reading and writing the memories 2 and 6, controlling the shift amounts of the shifters 3 and 5, controlling the operation of the arithmetic unit array unit 4, and the like in accordance with the program.

In the DCT processing, one screen is divided into several two-dimensional blocks, and processing is performed in block units. For example, as shown in FIG. 2, when the size of a block is 8 pixels in the horizontal direction and 8 lines in the vertical direction, one block is composed of 64 data from data d0 to data d63. To perform DCT processing.

An operation in which input data is rearranged vertically and horizontally by the input data replacing circuit 8 and written into the data input register 1 will be described. The block size is 8 pixels horizontally and 8 lines vertically. FIG. 3 is a diagram showing the input and output timings of the input data replacement circuit 8.

One line of pixel data is sequentially input to the inputs IN [7] -IN of the input data replacement circuit 8 in synchronization with the clock signal CLK.
Given to [0]. Each input data is composed of 8 bits, and 8 bits are input in parallel. Therefore, it can be said that the data is input in a bit parallel word serial manner. The input data is data of a different block for every eight pixels.

The input data replacing circuit 8 is configured to input the first block BL
Eight 8-bit data d0 to d7 on the first line of K0 are input IN
, Each data is converted to serial data, and eight bits of data are output one bit at a time in order from the most significant bit d0 [7], d1 [7],..., D7 [7]. It is given to the inputs DIN [0] to DIN [7] of the data input register 1. That is,
It is converted into bit serial and word parallel and output. In other words, data input as a data bit arrangement vertically and a word arrangement horizontally is rearranged vertically and horizontally, such as a bit arrangement horizontally and a word arrangement vertically, and is output.

The write address of the data input register 1 is incremented by one from 0, and the data given to the input DIN is stored at the address specified by the write address. Therefore, the eight data of the first line of the first block BLK0 are stored at addresses 0 to 7.

In parallel with the input data replacing circuit 8 outputting the data of the block BLK0 to the data input register 1,
Data d0 to d7 of the next block BLK1 are sequentially supplied to the input data replacement circuit 8. Eight data d0 ~ of block BLK1
When the input of d7 is completed, vertical and horizontal sorting is performed in the same way,
Output to the data input register 1. At this time, the write address of the data input register 1 is incremented from 16 by one. Therefore, the eight data of the first line of the block BLK1 are stored at addresses 16 to 23 of the data input register 1. That is, a space of 8 bits in the horizontal direction is provided between the two blocks. Since writing is not performed in the space between the blocks, if the data of the data input register 1 is initialized to 0 in advance, 0 is held in the space between the blocks.

Data storage is performed in a similar manner for the blocks BLK2 and thereafter. When one line of data is stored in the data input register 1, this data is transferred to the memory 2 or the memory 6. In the transfer, data of one row in the data input register 1 is read at a time and stored in the memory 2 or the memory 6. That is, once, the data of all blocks
d0 is transferred, then data d1 of all blocks is transferred,
This is repeated, and data of all blocks in one line is transferred by eight transfers.

When the transfer from the data input register 1 to the memory 2 or 6 is completed, the data of the next line is supplied to the input data replacing circuit 8.

When these processes are repeated for eight lines, the memory 2 or 6 stores 64 pixel data of d0 to d63 of the same block in the vertical direction in the most significant bit (MSB) as shown in FIG. Is stored with the direction from the least significant bit (LSB) to the side. A value of 0 is embedded in the horizontal direction between the blocks for 8 bits.

In this example, in order to insert a value 0 between two blocks stored in the data input register 1, after storing data of one block, the write address is increased by the number of bits for inserting 0s. Alternatively, 0 may be written while increasing the write address by one. In this case, data is written to the data input register 1 at a frequency higher than the frequency at which data is input to the input data replacement circuit 8.

FIG. 5 is a block diagram showing the structure of the input data replacement circuit 8. In FIG. 5, reference numeral 30 denotes a flip-flop with a selector, which selects one of two inputs D1 and D2, takes in the selected data in synchronization with a clock signal, and outputs it from an output Q. A control circuit 31 generates a control signal 32 for controlling selection of an input of the flip-flop 30 and selection of an output to the data input register 1 and a data input register write address 33.
Note that the clock signal is omitted in this figure.

The 8-bit data given to the inputs IN [7] to IN [0] by the control signal 32 of the control circuit 31 is given to the left end of the flip-flops 30 arranged in a two-dimensional array. Is shifted to the right each time is taken. When eight data are captured, the control signal 32 switches, and the input data is captured from the lower end of the array of flip-flops 30 and is shifted upwards each time data is captured. At this time, the output Q of the top eight flip-flops 30 is output to the input DIN of the data input register 1. When eight data are taken in from the lower end, the control signal 32 switches, and the input data is taken in again from the left end of the array of flip-flops 30 and shifted to the right. At this time, the rightmost eight flip-flops 30
Is output to the input DIN of the data input register 1. By switching the control signal 32 for every eight data, it is possible to rearrange bit-parallel / word-serial data into bit-serial / word-parallel data for each block, that is, perform vertical / horizontal rearrangement. The data input register write address 33 is increased by the number of bits for inserting 0 each time eight data are stored in the data input register 1.

Although not shown in the figure, when processing is not performed in units of two-dimensional blocks, the input data replacing circuit 8 outputs the input data as it is.

The operation in the case where the arithmetic operation is performed on the data of the block arranged in the memory 2 by using the shifter 3 and the arithmetic unit array unit 4 will be described.

For example, eight data d0-d in each block
Consider a case where a product-sum operation of multiplying d7 by an appropriate coefficient and adding the results is performed. Assuming that the coefficients are a0 to a7, the result S of the product-sum operation is represented by (Equation 1).

[0037]

(Equation 1)

The multiplication in this operation is realized by shifting and adding. For example, if the coefficient a0 is 3/8, 3/8 = 1
Since / 4 + 1/8, a0 * d0 is obtained by adding a value obtained by shifting d0 to the right by 2 bits and a value shifted to the right by 3 bits. The program control unit 10 gives the address of the data d0 to the memory 2 and reads the data d0. The read data d0 is provided to the shifter 3. The program control unit 10 gives the shift amount 2 to the shifter 3. As a result, the shifter 3 shifts the data d0 to the right by 2 bits and supplies the data d0 to the arithmetic unit array unit 4. The arithmetic unit array unit 4 outputs the output of the shifter 3 to the memory 6 as it is, and the program control unit 1
0 is stored in the address specified. Next, the program control unit 10 reads the data d0 from the memory 2 again. The program control unit 10 gives the shift amount 3 to the shifter 3, and the shifter 3 shifts the data d0 to the right by 3 bits and gives it to the array unit 4. At the same time, a value obtained by shifting the data d0 to the right by 2 bits is read from the memory 6 and supplied to the arithmetic unit array unit 4 via the shifter 5. In this case, the shifter 5 outputs the data read from the memory 6 without shifting. Arithmetic unit array unit 4 adds two data provided from shifters 3 and 5, that is, data obtained by shifting data d 0 to the right by 3 bits and data shifted to the right by 2 bits, and stores the result in memory 6. This gives a0
x d0 is obtained. Similarly, by shifting the data d1 to d7 for the coefficients a1 to a7 and accumulating the data in the memory 6, the result S of the product-sum operation for the eight data is finally obtained in the memory 6. Can be Since these coefficients are the same for all blocks, it is possible to process data of all blocks stored in the memory 2 in parallel. Since the shifter 3 and the arithmetic unit array unit 4 also perform the same processing on the N-bit data read from the memory 2, the program control for the bit-wise constituent elements of the shifter 3 and the arithmetic unit array unit 4 is performed. The control signal from the unit 10 may be the same.

8 between blocks on the memory
Since the bit area is opened, even if the number of bits of the data is increased by performing the shift addition, the data of the adjacent blocks do not overlap and are not destroyed.
If there is a possibility that the data overflows to the upper bit, the data is arranged on the memory with an appropriate area left on the upper bit side of the data.

FIG. 6 shows an example of the configuration of the arithmetic unit array section 4. The arithmetic unit array unit 4 includes a total of H arithmetic units ALU, one for each bit of the outputs of the memories 2 and 6.

Each arithmetic unit ALU has three inputs 21, 22,
23 and the sum output SM and carry output C
Outputs Y. 24 is a selection circuit, 25, 26, 2
Latches 7 and 28 temporarily hold data. The outputs of shifters 3 and 5 are connected to latches 25 and 2 respectively.
6 and provided to inputs 21 and 22. The sum output SM is stored at a specified address in the memory 2 or 6 under the control of the program control unit 10. The carry output CY is taken into the latch 27 or the next-stage latch 28, and, via the selection circuit 24, its own arithmetic unit AL
U or the input 23 of the next-stage arithmetic unit ALU.
If the processing is not a two-dimensional block unit, that is, if the data is arranged in the memory 2 or 6 in the vertical direction and given as serial data to the same arithmetic unit ALU in order from the lower bit, and an operation such as addition is performed, carry The output CY is given to the input 23 of its own arithmetic unit ALU, and is used for the operation as a carry signal from the lower bit to the upper bit. On the other hand, when data is arranged in the memory 2 or 6 in the horizontal direction and each bit is provided as parallel data to a plurality of arithmetic units ALU as in the case of a block unit operation, the carry output CY is the left operation ALU input 23
And used as a carry signal from the lower bit (right ALU) to the upper bit (left ALU). As a result, arithmetic operations such as addition can be performed on data given as parallel data from shifters 3 and 5.

The subtraction can be realized by giving a borrow signal to the input 23 via the selection circuit 24 instead of the carry signal CY. Alternatively, the subtraction can be realized by applying the subtraction to one of the inputs 21 and 22 of the arithmetic unit ALU in a bit-reversed manner, performing addition, and further adding 1 to the least significant bit. In order to add 1 to the least significant bit, the position of the least significant bit is stored in the memory 2 or 6 in advance.
The data can be realized by preparing data in which the others are set to 0 and adding this data in the arithmetic unit array unit 4.
In the case of subtraction, in the arithmetic unit ALU corresponding to the least significant bit, the input of the carry signal or the borrow signal of the right arithmetic unit ALU is masked so that the carry signal or the borrow signal does not propagate beyond the block. .

When the carry output CY is supplied to the arithmetic unit ALU on the left, the carry output CY is stored by the latch 27 in FIG. 6, so that the carry propagates only for one bit. Therefore, after the accumulation is repeated, a cycle for propagating the carry to the most significant bit is required to finally obtain the operation result. To reduce this cycle, the number of latches to be inserted may be reduced according to the operation speed of the arithmetic unit ALU. For example, as shown in FIG. 7, a latch is inserted every other arithmetic unit ALU and 1
A carry may propagate two bits in a cycle.

In the example of FIG. 6, the sum output SM of the result of the addition is obtained.
Is temporarily stored in the memory 2 or 6, read out again, and used for accumulation with the next data. Instead of storing the sum output SM in the memory 2 or 6 as shown in FIG. Is directly stored in the latch 25 or 26 provided in the arithmetic unit array unit 4 and the input 21 or 2 of the arithmetic unit ALU is stored.
2 and may perform accumulation with the next data.
Thus, even when it takes time to read data written to the memory 2 or 6 due to pipeline processing, accumulation can be performed at high speed.

The data resulting from the processing as described above is stored in the output data register 7. One row of data in the memory 6 or all the arithmetic units A in the arithmetic unit array unit 4
The H-bit data of the LU output is stored in one horizontal row of the output data register 7. The stored data is sequentially read out as H-word data with respect to the horizontal address, and output to the output data replacement circuit 9. In the output data replacement circuit 9, on the contrary to the input data replacement circuit 8,
The bit serial / word parallel data is converted to bit parallel / word serial data and output as 8-bit data. This conversion is the same as the vertical / horizontal rearrangement by the input data replacement circuit 8, and can be realized by the same circuit configuration as that of FIG.

Thus, two-dimensional block data obtained by processing the two-dimensional block data can be output in the order of the pixels on the line.

It is also possible to omit one of the two shifters, shift only the data from one memory, and use the data in the other memory for accumulation.

The two shifters may be omitted, and the arithmetic unit array may have a function of shifting data or a function of performing multiplication.

In the first embodiment, the signal processing device is provided with two separate memories, but a single memory from which a plurality of data can be read may be provided as shown in FIG. The memory 11 in FIG. 8 may have, for example, two read ports, read two data at the same time with respect to two addresses specified by the program control unit 10, and supply the two data to the shifters 3 and 5, respectively. Alternatively, the memory 11 has one read port, and reads two data successively one by one in a time-sharing manner at two addresses designated by the program control unit 10, and shifters 3 and 5 respectively. It may be given to.

As described above, the data of the same block is arranged vertically on the memory with respect to the data of the two-dimensional block, and the bit arrangement of the data is horizontal, as in the DCT processing. Parallel processing is possible for all bits of data, and the arrangement of data bits is 1 in the vertical direction.
An extremely high processing capability can be realized as compared with a conventional signal processing device that performs sequential processing for each bit.

If the two-dimensional block is 8 pixels × 8 lines and the data is 8 bits, the bit width before and after performing the vertical / horizontal rearrangement is the same 8 bits. As compared with the case where the bit width is increased by eight times, it can be realized with a configuration closer to a signal processing device that does not perform processing in units of two-dimensional blocks. In other words, when the processing is performed in units of two-dimensional blocks and when the parallel processing is performed on all the pixel data of one line, the aspect ratio of the input data register, the output data register, the memory, etc., and the number of arithmetic units are different. Since they do not change much, these processes can be switched and executed efficiently using the same signal processing device, which is extremely useful for a system that processes a video signal of a television broadcast or a digitally compressed signal. It is informative.

[0052]

As described above, according to the present invention, by providing input data replacing means for rearranging input data vertically and horizontally for each predetermined number of data, the direction of data bits can be changed with respect to the data of a two-dimensional block. Since the data of the blocks can be arranged vertically and horizontally, processing in units of two-dimensional blocks can be realized, and processing of each block is processed in parallel by using the arithmetic unit array unit, achieving high processing capacity. It is extremely useful.

In addition, since all bits of each pixel data are given to a plurality of arithmetic units in parallel and arithmetic operations are performed, extremely high processing capability can be realized.

Further, by providing a shifter, a product-sum operation can be processed at high speed in units of two-dimensional blocks.

Further, since the data is arranged in the memory with a certain interval between the two-dimensional blocks, even when the bit length of the data is increased due to shift addition or the like, the data overlaps and is destroyed. There is no.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a two-dimensional block in one screen.

FIG. 3 is an input / output timing diagram of the input data replacement circuit according to the first embodiment of the present invention;

FIG. 4 is a layout diagram of data of a two-dimensional block on a memory according to the first embodiment of the present invention;

FIG. 5 is a configuration diagram of an input data replacement circuit according to the first embodiment of the present invention.

FIG. 6 is a diagram showing an example of a configuration of a computing unit array according to the first embodiment of the present invention;

FIG. 7 is a diagram showing another example of the configuration of the arithmetic unit array according to the first embodiment of the present invention;

FIG. 8 is a diagram showing another example of the configuration of the signal processing device according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 data input register 2, 6, 11 memory 3, 5 shifter 4 operation unit array unit 7 output data register 8 input data replacement circuit 9 output data replacement circuit 10 program control unit 25, 26, 27, 28 latch 24 selection circuit 30 selector With flip-flop 31 control circuit 32 control signal 33 data input register write address

Claims (11)

[Claims] An input data replacing means for rearranging and outputting input data every predetermined number of data and outputting the data, and successively storing data output from the input data replacing means in a unit of one column and storing the data. An input data register that reads out the stored data row by row, a memory that stores multiple data, a computing unit array that performs operations on multiple inputs, and a row of data that is written row by row, and the stored data is written vertically. An output data register that is continuously read in units of one row; and an output data replacement unit that rearranges and outputs data read from the output data register every predetermined number of data in a vertical / horizontal manner. Performs an operation by using a plurality of data read from the memory as an input, and the memory performs a data read or an operation from the input data register. A signal processing device for storing an output of the arithmetic unit array unit and writing the data read from the memory or the output of the arithmetic unit array unit in the output data register. 2. An input data replacing means for rearranging the input data for every predetermined number of data and outputting the data, and successively storing the data outputted from the input data replacing means in a unit of one column and storing the data. An input data register for reading the input data in units of a row, first and second memories for storing a plurality of data, an operation unit array unit for performing an operation on a plurality of inputs, and writing data in units of a row An output data register for continuously reading stored data in units of columns, and an output data replacement means for rearranging the data read from the output data register for every predetermined number of data, and rearranging and outputting the data. The arithmetic unit array unit performs an arithmetic operation by using data read from the first and second memories as inputs, and the first and second memories store The output data register stores the data read from the input data register or the output of the arithmetic unit array unit.
A signal processing device for writing data read from a memory or an output of the arithmetic unit array unit. 3. The signal processing device according to claim 1, wherein the arithmetic unit array unit includes a plurality of arithmetic units that perform a 1-bit operation. 4. The signal processing device according to claim 3, wherein the arithmetic unit outputs a sum of the operation result and a carry, and the arithmetic unit determines whether the carry of the arithmetic unit is the carry of an adjacent arithmetic unit. A signal processing device characterized by selecting and providing one of the inputs. 5. The signal processing device according to claim 3, wherein the arithmetic unit outputs a sum of operation results and a borrow, and the arithmetic unit determines which of the borrow of the arithmetic unit and the borrow of an adjacent arithmetic unit is to be used. A signal processing device characterized by selecting and providing one of the inputs. 6. The signal processing device according to claim 3, wherein the plurality of arithmetic units perform operations according to the same instruction. 7. The signal processing device according to claim 1, wherein the arithmetic unit array unit includes a data holding unit that temporarily holds data of a calculation result, and the data held by the data holding unit. A signal processing device characterized in that is used for calculation as required. 8. The signal processing device according to claim 1, further comprising a shifter between the memory and the arithmetic unit array unit, wherein the data read from the memory is provided to the shifter before being supplied to the arithmetic unit array unit. A signal processing device characterized by being shifted by: 9. The signal processing device according to claim 2, further comprising: a first shifter between the first memory and the arithmetic unit array unit, wherein a first shifter is provided between the second memory and the arithmetic unit array unit. A second shifter interposed therebetween, wherein data read from the first memory is shifted by the first shifter before being applied to the arithmetic unit array section, and data read from the second memory is subjected to the arithmetic operation. A signal processing unit that shifts the signal by the second shifter before the signal is supplied to the array unit. 10. The signal processing device according to claim 1, wherein the input data register stores data blocks rearranged for each predetermined number of data at a predetermined interval. Signal processing device. 11. The signal processing device according to claim 1, wherein said input data replacing means outputs a fixed period 0 between data blocks rearranged every predetermined number of data. Signal processing device.