JP2011192305A - Semiconductor signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a processor for efficiently performing arithmetic processing of a large amount of data at high speed. <P>SOLUTION: Arithmetic processing instructions to a main arithmetic circuit (20) are stored in a form of a microprogram in a micro-instruction memory (21), and the operation control of the main arithmetic circuit is carried out under the control of a controller 22 according to the microprogram. In the main arithmetic circuit (20), a memory cell mat (30) is divided into entries each storing a plurality of bits of data, and arithmetic and logic units (ALUs) are arranged corresponding to the respective entries. Arithmetic processing is carried out between the entries and the ALUs in a bit serial mode in parallel to the respective entries. The large amount of data can be efficiently processed according to a microprogram control system. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor signal processing device, and more particularly to a configuration of an integrated circuit device for signal processing using a semiconductor memory that performs arithmetic processing of a large amount of data at high speed.

  In recent years, with the widespread use of portable terminal devices, the importance of digital signal processing for processing a large amount of data such as sound and images at high speed has increased. For such digital signal processing, a DSP (Digital Signal Processor) is generally used as a dedicated semiconductor device. In digital signal processing for audio and image data, data processing such as filter processing is performed, and in such processing, there are many arithmetic processes that repeat product-sum operations. Therefore, in general, in the configuration of the DSP, a multiplication circuit, an addition circuit, and an accumulation register are provided. If such a dedicated DSP is used, the product-sum operation can be executed in one machine cycle, and high-speed operation processing is possible.

  Japanese Patent Laid-Open No. 6-324862 discloses a configuration in which a register file is used when performing such product-sum operation. In Patent Document 1, two operand data stored in a register file are read and added by an arithmetic unit, and then the addition result is written into the register file via a write data register. In the configuration shown in Patent Document 1, a write address and a read address are simultaneously given to a register file, and data writing and data reading are performed in parallel, whereby data writing cycle and data reading are performed. The processing time is shortened compared to a configuration in which a cycle is provided separately to perform arithmetic processing.

  A configuration intended to process a large amount of data at high speed is disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 5-197550). In the configuration shown in Patent Document 2, a plurality of arithmetic devices are arranged in parallel, and a memory is built in each arithmetic device. By individually generating a memory address in each arithmetic unit, parallel arithmetic is performed at high speed.

  Further, a signal processing apparatus that aims to perform processing such as DCT transformation (discrete cosine transformation) of image data at high speed is disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 10-74141). In the configuration disclosed in Patent Document 3, since image data is input in a bit-parallel and word-serial sequence, that is, in units of words (pixel data), it is word-parallel and bit-serial using a serial / parallel conversion circuit. Convert to data string and write to memory array. Data is transferred to an arithmetic unit (ALU) arranged corresponding to the memory array to execute parallel processing. The memory array is divided into blocks according to image data blocks, and image data constituting the corresponding image block in each block is stored in units of words for each row of the memory array.

  In the configuration shown in Patent Document 3, data is transferred in units of words (data corresponding to one pixel) to an arithmetic unit corresponding to a memory array. By executing the same processing on the transferred word in an arithmetic unit corresponding to each block, it is possible to execute filter processing such as DCT conversion at high speed. The result of the arithmetic processing is written again into the memory array, parallel / serial conversion is performed again to convert bit serial and word parallel data into bit parallel and word serial data, and data for each line is sequentially output. In normal processing, bit position conversion of data is not performed, and normal arithmetic processing is performed in parallel on a plurality of data in an arithmetic unit.

  Further, Patent Document 4 (Japanese Patent Application Laid-Open No. 2003-114797) discloses a data processing apparatus intended to execute a plurality of different arithmetic processes in parallel. In the configuration disclosed in Patent Document 4, a plurality of logic modules each having a limited function are connected to a multi-port data memory. The connection between these logic modules and the multi-port data memory limits the ports and memories of the multi-port memory to which the logic modules are connected. Therefore, each logic module accesses the multi-port memory and reads data. And the address area where writing can be performed is limited. The result of the operation in each logic module is written in the memory to which access is permitted, and the data is processed in a pipeline manner by sequentially transferring the data through the logic module via these multi-port memories. Plan.

JP-A-6-324862 Japanese Patent Laid-Open No. 5-197550 Japanese Patent Laid-Open No. 10-74141 JP 2003-114797 A

  When the amount of data to be processed is very large, it is difficult to dramatically improve the performance even if a dedicated DSP is used. For example, when there are 10,000 sets of calculation target data, even if the calculation for each piece of data can be executed in one machine cycle, at least 10,000 cycles are required for the calculation. Therefore, in the configuration in which the product-sum operation is performed using the register file as shown in Patent Document 1, although each processing is performed at a high speed, the data processing is performed in series. As the number increases, the processing time increases in proportion to this, and high-speed processing cannot be realized. In addition, when such a dedicated DSP is used, the processing performance greatly depends on the operating frequency. Therefore, when high-speed processing is prioritized, power consumption increases.

  Further, when using a register file and an arithmetic unit as disclosed in Patent Document 1, it is often designed specifically for a certain application, and the arithmetic bit width and the configuration of the arithmetic circuit are fixed. Therefore, when diverting to other applications, it is necessary to redesign the bit width and the configuration of the arithmetic circuit, and there arises a problem that it becomes impossible to flexibly cope with a plurality of arithmetic processing applications.

  Further, in the configuration shown in Patent Document 2, each arithmetic device has a built-in memory, and each arithmetic device accesses a different memory address area for processing. However, the data memory and the arithmetic unit are arranged in different areas, and it is necessary to transfer data between the arithmetic unit and the memory in the logic module to perform data access, which takes time. As a result, the machine cycle cannot be shortened and high-speed processing cannot be performed.

  In the configuration disclosed in Patent Document 3, the processing such as DCT conversion of image data is speeded up, and pixel data of one line of the screen is stored in one row of memory cells and aligned in the row direction. Processing is executed in parallel on the image block to be processed. Therefore, when the number of pixels in one line increases for high definition of the image, the memory array becomes enormous. For example, even if the data of one pixel is 8 bits and the number of pixels in one line is 512, the number of memory cells in one row of the memory array is 8 · 512 = 4K bits, and the memory cells in one row are connected. The load on the row selection line (word line) increases, and it becomes impossible to select a memory cell at high speed and transfer data between the arithmetic unit and the memory cell, thereby realizing high-speed processing accordingly. The problem of disappearing arises.

  Further, Patent Document 3 shows a configuration in which the memory cell arrays are arranged on both sides of the arithmetic circuit group, but does not show a specific structure of the memo cell array, and the arithmetic units are arranged in an array in the arithmetic circuit. Although the arrangement is shown, no details are given on how to arrange the arithmetic units.

  In the configuration disclosed in Patent Document 4, a plurality of multi-port data memories and a plurality of low-function arithmetic units (ALUs) whose access areas are restricted for these multi-port data memories are provided. Yes. However, the arithmetic unit (ALU) and the memory are arranged in different areas, and data cannot be transferred at high speed due to wiring capacity or the like. Even if pipeline processing is executed, this pipeline machine The problem arises that the cycle cannot be shortened.

  Further, in these Patent Documents 1 to 4, no consideration is given to how to deal with the case where the word structure of the data to be processed is different.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor signal processing apparatus capable of processing a large amount of data at high speed.

  Another object of the present invention is to provide a semiconductor signal processing apparatus capable of executing arithmetic processing at high speed irrespective of the word configuration of data and the content of the arithmetic operation.

  Still another object of the present invention is to provide a semiconductor signal processing device with a built-in arithmetic function that can change processing contents flexibly.

  A semiconductor signal processing device according to the present invention includes a memory array having a plurality of memory cells arranged in a matrix and divided into a plurality of entries each having a plurality of memory cells, and each entry of the memory array. A main arithmetic circuit including a plurality of arithmetic circuits arranged correspondingly, a microinstruction memory for storing microinstructions, and controlling the operation of the memory array and the plurality of arithmetic circuits according to the microinstructions from the microinstruction memory. A control circuit is provided.

  The memory array is divided into a plurality of entries, and an arithmetic circuit is arranged for each entry. The data transfer between the memory array and the arithmetic circuit, the data writing / reading, and the arithmetic processing are controlled according to the microinstruction from the microinstruction memory, and the processing is performed at a speed similar to that of normal wired logic. Can be executed. In addition, the contents of the arithmetic processing can be changed according to the application purpose by the microprogram instruction, so that different arithmetic contents can be flexibly dealt with.

  In addition, since arithmetic processing is executed in parallel for a plurality of entries, high-speed arithmetic processing of a large amount of data can be realized.

  In addition, by storing the same data word in each entry and performing arithmetic processing in a corresponding arithmetic circuit in a bit serial manner, a large amount of hardware can be used for changing the data word configuration (bit width). Accordingly, the arithmetic processing can be performed without changing the above.

It is a figure which shows schematically the structure of the signal processing system according to Embodiment 1 of this invention. It is a figure which shows the structure of the principal part of the main arithmetic circuit shown in FIG. FIG. 2 is a diagram showing an example of a configuration of a memory cell included in the memory mat shown in FIG. 1. It is a figure which shows the processing operation of the main arithmetic circuit shown in FIG. It is a figure which shows the process sequence of the processing operation shown in FIG. It is a figure which shows roughly the structure of the basic arithmetic block according to Embodiment 1 of this invention. It is a figure which shows an example of the microprogram in Embodiment 1 of this invention. FIG. 8 is a timing chart showing an address update operation shown in FIG. 7. It is a figure which shows an example of a structure of ALU shown in FIG. It is a figure which shows roughly the structure of the basic arithmetic block according to Embodiment 2 of this invention. It is a figure which shows an example of the microprogram used in Embodiment 2 of this invention. It is a flowchart which shows the processing operation of the microprogram shown in FIG. It is a figure which shows roughly the structure of the basic arithmetic block according to Embodiment 3 of this invention. FIG. 14 is a diagram showing an example of a configuration of memory cells included in the memory cell mat shown in FIG. 13. It is a figure which shows roughly an example of a structure of ALU shown in FIG. It is a figure which shows typically the data transfer operation | movement of the main arithmetic circuit shown in FIG. It is a figure which shows an example of the microprogram of the semiconductor signal processing apparatus in Embodiment 3 of this invention. It is a figure which shows an example of the image data process in Embodiment 4 of this invention. It is a figure which shows roughly the structure of the principal part of the semiconductor signal processing apparatus according to Embodiment 4 of this invention. It is a flowchart which shows the data processing sequence of the semiconductor signal processing apparatus according to Embodiment 4 of this invention. It is a figure which shows typically the flow of the data in the processing sequence shown in FIG. It is a figure which shows typically the area | region of the storage data and transfer data in the memory cell mat in Embodiment 4 of this invention. It is a figure which shows roughly the structure of the arithmetic circuit according to Embodiment 5 of this invention. FIG. 24 is a diagram showing a specific configuration of the main arithmetic circuit shown in FIG. 23. It is a figure which shows roughly the structure of the semiconductor signal processing apparatus according to Embodiment 6 of this invention. FIG. 26 schematically shows allocation of data storage areas of the memory cell mat shown in FIG. 25. It is a figure which shows roughly the structure of the semiconductor signal processing apparatus according to Embodiment 7 of this invention. FIG. 28 schematically shows a configuration of a transposition circuit shown in FIG. 27. FIG. 29 is a flowchart showing a data transfer operation of the transposition circuit shown in FIG. 28. It is a figure which shows typically the data flow at the time of the data transfer of the transposition circuit in Embodiment 7 of this invention. FIG. 29 is a diagram illustrating an example of a configuration of a memory cell included in the transposition memory illustrated in FIG. 28.

[Embodiment 1]
FIG. 1 is a diagram schematically showing an overall configuration of a processing system in which a semiconductor signal processing device according to the present invention is used. In FIG. 1, the signal processing system 1 includes a system LSI 2 that realizes an arithmetic function for executing various processes, and an external memory connected to the system LSI 2 via an external system bus 3. The external memory includes a large-capacity memory 4, a high-speed memory 5, and a read-only memory (read-only memory: ROM) 6 that stores fixed information such as an instruction at startup. The large-capacity memory 4 is composed of, for example, a clock synchronous dynamic random access memory (SDRAM), and the high-speed memory 5 is composed of, for example, a static random access memory (SRAM).

  The system LSI 2 includes basic operation blocks FB1-FBh that are coupled in parallel to the internal system bus 7, a host CPU 8 that is coupled to the internal system bus 7 and controls processing operations of these basic operation blocks FB1-FBh, and this system 1 includes an input port 9 that converts an external input signal IN into internal processing data, and an output port 10 that receives output data supplied from the internal system bus 7 and generates an output signal OUT to the outside of the system. . The input port 9 and the output port 10 are configured by, for example, an IP (Intellectual Property) block formed as a library, and realize functions necessary for data / signal input / output.

  The system LSI 2 further receives an interrupt signal from the basic operation blocks FP1-FBh and notifies the host CPU 8 of the interrupt, and a CPU peripheral that performs a control operation necessary for each processing of the host CPU 8. 12, a DMA (direct memory access) controller 13 for transferring data to an external memory in accordance with a transfer request from basic operation blocks FB1 to FBh, and an external system bus 3 in accordance with an instruction from CPU 8 or DMA controller 13 An external bus controller 14 for controlling access to the memory 4-6 and a dedicated logic 15 for assisting data processing of the host CPU 8 are included.

  The CPU peripheral 12 has functions necessary for a program and debugging use in the host CPU 8 such as a timer and serial IO (input / output). The dedicated logic 15 is configured by, for example, an IP block, and implements a necessary processing function using an existing function block. These functional blocks 9-15 are connected to the internal system bus 7. The DMA controller 13 is given a DMA request signal from the basic operation blocks FB1-FBh.

  Since basic operation blocks FB1-FBh have the same configuration, FIG. 1 representatively shows the configuration of basic operation block FB1.

  The basic arithmetic block FB1 includes a main arithmetic circuit 20 that performs arithmetic processing on actual data, a microinstruction memory 21 that stores microinstructions that specify arithmetic processing in the main arithmetic circuit 20, and a microinstruction from the microinstruction memory 21. According to the controller 22 for controlling the arithmetic processing of the main arithmetic circuit 20, the work data memory 23 for storing intermediate processing data or work data of the controller 22, and the basic arithmetic block FB1 and the internal system bus 7. A system bus interface (I / F) 24 for transferring data / signals is included.

  The main arithmetic circuit 20 includes a memory cell mat 30 in which a plurality of memory cells are arranged in a matrix and divided into a plurality of entries, and an arithmetic processing that is arranged corresponding to each entry of the memory cell mat 30 and designated. An arithmetic unit (ALU) 31 to perform and an inter-ALU interconnection switch circuit 32 for setting a data transfer path between the arithmetic units 31 are included.

  Basically, each row of the memory cell mat 30 constitutes one entry, and each bit of multi-bit data is stored in one entry. Therefore, the arithmetic unit (hereinafter referred to as ALU as appropriate) 31 receives the data from the corresponding entry in bit serial and performs arithmetic processing, and the processing result is assigned to the specified entry (for example, the corresponding entry) of the memory cell mat 30. ).

  The inter-ALU interconnection switch circuit 32 switches the connection path of the ALU 31 so that data of different bit lines (different entries) can be calculated. By storing different data in each entry and performing parallel arithmetic processing by the ALU 31, data processing can be performed at high speed.

  The controller 22 performs an operation in accordance with the microprogram method in accordance with the microinstruction stored in the microinstruction memory 21. Work data necessary for the microprogram operation is stored in the work data memory 23.

  The system bus I / F 24 allows the host CPU 8 or the DMA controller 13 to access the memory cell mat 30, the control register in the controller 22, the microinstruction memory 21 and the work data memory 23.

  Different address areas (CPU address areas) are allocated to the basic operation blocks FB1 to FBh. Similarly, different addresses (CPU addresses) are assigned to the memory cell mat 30 in the basic operation blocks FB1 to FBh, the control register in the controller 22, the microinstruction memory 21 and the work data memory 23, respectively. Accordingly, different arithmetic processes can be executed in parallel by storing microinstructions having different contents in each of the basic arithmetic blocks FB1 to FBh. In the basic operation blocks FB1 to FBh, microinstructions having the same operation content may be stored in the microinstruction memory 21 so that the same operation processing is performed on data in different address areas.

  In accordance with each assigned address, the host CPU 8 and the DMA controller 13 identify the basic arithmetic block FB (FB1-FBh) to be accessed and execute access to the basic arithmetic block to be accessed.

  FIG. 2 schematically shows a configuration of a main part of main arithmetic circuit 20 included in each of basic arithmetic blocks FB1-FBh shown in FIG. In FIG. 2, in memory cell mat 30, memory cells MC are arranged in a matrix. Memory cell MC is divided into m entries ERY. The entry ERY has a bit width of n bits. Basically, one entry ERY is composed of memory cells MC aligned in one column. Therefore, in this case, the number of entries ERY is determined by the number of rows of memory cell mats 30, that is, the number of bit lines.

  In the arithmetic processing unit group 35, an ALU 31 is provided for each entry ERY. The ALU 31 can execute operations such as addition, logical product, coincidence detection (EXOR), and inversion (NOT).

  Data load (transfer of data from the memory cell mat 30 to the arithmetic processing unit group 35) and store (data transfer storage from the arithmetic processing unit group 35 to the memory cell mat 30) between the entry ERY and the corresponding ALU 31 To perform arithmetic processing. Each bit of multi-bit data is stored in the entry ERY, and the ALU 31 executes arithmetic processing in a bit-serial manner (a manner in which a multi-bit data word is processed in units of bits). In the arithmetic processing unit group 35, data arithmetic processing is executed in a bit serial manner for data words and in an entry parallel manner in which a plurality of entries ERY are processed in parallel.

  By changing the bit width of the entry ERY, data processing can be executed only by changing the number of operation cycles (range of address pointer) even when the word structure of the data word is different. Further, by increasing the number of entries m, a large amount of data can be collectively processed.

  FIG. 3 is a diagram showing an example of the configuration of the memory cell MC shown in FIG. In FIG. 3, a memory cell MC includes a P-channel MOS transistor (insulated gate field effect transistor) PQ1 connected between a power supply node and a storage node SN1 and having a gate connected to the storage node SN2, a power supply node, and a storage node. P-channel MOS transistor PQ2 connected between SN2 and its gate connected to storage node SN1, and N-channel MOS transistor connected between storage node SN1 and ground node and connected to storage node SN2 NQ1, N-channel MOS transistor NQ2 connected between storage node SN2 and ground node and having its gate connected to storage node SN1, and storage nodes SN1 and SN1 in response to the potential on word line WL The SN2, respectively, and an N-channel MOS transistors NQ3 and NQ4 connected to the bit lines BL and / BL.

  Memory cell MC shown in FIG. 3 is an SRAM cell having a full CMOS (complementary MOS) structure, and data can be written / read at high speed. By using this SRAM cell, it is not necessary to refresh stored data in the memory cell mat 30, operation control is facilitated, and arithmetic processing can be executed at high speed.

  When performing calculations in the main arithmetic circuit 20, first, data to be calculated is stored in each entry ERY. Next, a certain digit of the stored data is read in parallel for all entries ERY and transferred (loaded) to the corresponding ALU 31. In the case of a binary operation, a similar transfer operation is performed for bits of another data word in each entry ERY, and then a two-input operation is performed in each ALU 31. The calculation processing result is rewritten (stored) from the ALU 31 to a predetermined area in the corresponding entry ERY.

  FIG. 4 is a diagram schematically showing an arithmetic operation in the main arithmetic circuit 20 shown in FIG. In FIG. 4, data words a and b having a 2-bit width are added to generate data word c. The entry ERY stores both data words a and b that form a set to be calculated.

  In FIG. 4, 10B + 01B is added in ALU 31 for entry ERY in the first row, and 00B + 11B is calculated in ALU 31 for entry ERY in the second row. Here, “B” at the end indicates a binary number. In the ALU 31 for the entry ERY in the third row, the calculation of 11B + 10B is performed. Similarly, addition of data words a and b stored in each entry ERY is executed.

  The calculation is performed in a bit serial manner in order from the lower bit. First, the lower bit a [0] of the data word a is transferred to the corresponding ALU 31 in the entry ERY. Next, the lower bit b [0] of the data word b is transferred to the corresponding ALU 31. The ALU 31 performs an addition operation using these given 2-bit data. This addition operation result a [0] + b [0] is written (stored) at the position of the lower bit c [0] of the data word c. That is, in the entry ERY in the first row, “1” is written at the position of bit c [0].

  This addition process is also performed for the upper bits a [1] and b [1], and the operation result a [1] + b [1] is written at the position of the bit c [1].

  In the addition operation, a carry may occur, and the carry value is written at the bit c [2] position. Thereby, the addition of the data words a and b is completed in all the entries ERY, and the result is stored as data c in each entry ERY. For example, when 1024 entries are prepared as entries, 1024 sets of data can be added in parallel.

  FIG. 5 is a diagram schematically showing the internal timing during this addition operation processing. Hereinafter, the internal timing of the addition operation will be described with reference to FIG. In this addition calculation process, a 2-bit adder (ADD) included in the ALU 31 is used.

  In FIG. 5, “Read” indicates an operation (load) or operation instruction for reading the data bit to be calculated from the memory cell mat 30 and transferring it to the corresponding ALU 31, and “Write” corresponds to the operation result data of the ALU 31. Indicates an operation (store) or operation instruction to be written in the corresponding bit position of the entry ERY.

  In the machine cycle k, the data bit a [i] is read from the memory cell mat 30, and in the next machine cycle (k + 2), the next data bit b [i] to be calculated is read (Read), and the ALU 31 is added. Is provided to each device (ADD).

  In the machine cycle (k + 2), addition processing of the data bits a [i] and b [i] given in the adder (ADD) of the ALU 31 is performed. In the machine cycle (k + 3), the addition result c [i] Written in the corresponding bit position of the corresponding entry.

  In the next machine cycles (k + 4) and (k + 5), the data bits a [i + 1] and b [i + 1] to be calculated next are read and transferred to the adder (ADD) of the ALU 31 and in the machine cycle (k + 6). Addition processing is performed by the ALU 31, and the addition result is stored in the bit position c [i + 1] in the machine cycle (k + 7).

  One machine cycle is required for the transfer of data bits between the memory cell mat 30 and the ALU 31, and one machine cycle is required in the ALU 31. Therefore, 4 machine cycles are required to add 1-bit data and store the addition result. The memory cell mat 30 is divided into a plurality of entries ERY, a set of operation target data is stored in each entry, and the operation processing is performed in a bit serial manner in the corresponding ALU 31. If a relatively large number of machine cycles are required, but the amount of data to be processed is very large, high-speed data processing can be realized by increasing the degree of parallelism of operations. .

  For example, when the bit width of the data word to be calculated is N, 4 · N machine cycles are required for the calculation of each entry. The bit width of the data word to be calculated is about 8 to 64 bits. When the number of entries m is increased to, for example, 1024, for example, in the case of 8-bit data, 1024 operation results can be obtained in 32 machine cycles, and 1024 sets of data are processed sequentially. The processing time can be greatly shortened compared to.

  In addition, since the arithmetic processing is performed in the bit serial form and the bit width of the processed data is not fixed, it can be easily adapted to various applications having various data configurations.

  FIG. 6 is a diagram showing a configuration of the controller 22 in the basic calculation block FBi. In this basic arithmetic block FBi, the main arithmetic circuit 20 is provided with a memory cell mat 30, an arithmetic processing unit group 35, and an ALU interconnection switch circuit 32 as in the configuration shown in FIG. In FIG. 6, a write / read circuit 38 provided between the memory cell mat 30 and the arithmetic processing unit group 35 is also shown. Write / read circuit 38 includes a sense amplifier and a write driver SAW provided corresponding to each entry ERY. In memory cell mat 30, word lines are provided in common in entries ERY extending in the column direction, and bit lines are arranged in pairs in each entry. In FIG. 6, a circuit for selecting a column (word line) and a row (bit line) of memory cell mat 30 is not shown.

  The controller 22 decodes the data fetched from the microinstruction memory 21, generates an instruction decoder 40 for generating various control signals, a program counter 41 for generating an address to the microinstruction memory 21, and the count value of the program counter 41. A PC (program count) calculation unit 42 to be updated, a general-purpose register group 43 including a plurality of general-purpose registers Rx, and an arithmetic circuit (ALU) that performs operations such as condition judgment on the contents of the general-purpose registers in the general-purpose register group 43 44 and a control register group 45 for storing various control information of the basic operation block FBi. The control register group 45 includes a control register (status register) 45s for storing the execution result of the arithmetic unit (ALU) 44, an output port register 45o and an input port register 45i for communicating with the interrupt controller 44 and the DMA controller 13. .

  The controller 22 further includes an address calculation unit 46 that calculates an address for the memory cell mat 30, and an address register group 47 that stores the address calculated by the address calculation unit 46 and supplies the address to the main arithmetic circuit 20. The address register group 47 includes an address register Ax that generates an address for each data in the entry.

  The microinstruction memory 21 stores a microprogram in which necessary sequence processing is encoded. The instruction decoder 40 decodes the microinstruction fetched from the microinstruction memory 21, generates a control signal for each module in the controller 22, and generates a control signal for the main arithmetic circuit 20. The so-called firmware can execute the required processing at high speed. In FIG. 6, the instruction decoder 40 should execute the read / write control signal (RW control) for the sense amplifier / write driver SAW included in the write / read circuit 38 and the ALU 31 included in the arithmetic processing unit group 35. An ALU control signal for instructing calculation contents and a switch control signal for controlling connection in the ALU interconnection switch circuit 32 are shown representatively.

  The controller 22 is also provided with a memory interface (I / F) 48 for loading / storing data between the general-purpose register group 43 and the work data memory 23.

  The host CPU (8) shown in FIG. 1 monitors the execution state of the controller 22 based on the data stored in the status register 45s included in the control register group 45, and confirms the operation status of the basic operation block FBi. The controller 22 is handed a control right from the host CPU (8) via the system bus interface 24, and controls the processing operation in the basic arithmetic block FBi.

  FIG. 7 is a diagram showing an example of a microprogram described by microinstructions corresponding to the addition operation processing shown in FIG. In FIG. 7, the microinstruction to be executed is shown next to the line number of the microprogram. “//” in the program instruction sequence is a header that defines the processing content for the next instruction sequence. Corresponding to each instruction line, a comment indicating the processing content of the corresponding instruction is added after “//” on the right side. In FIG. 7, the instruction shown next to the line number is executed as a microinstruction.

  The “LD Ax, #imm” instruction is an instruction for setting a constant value #imm in the address register Ax included in the address register group 47.

  The “LD Rx, #imm” instruction is an instruction for setting a constant value #imm in the general purpose register Rx included in the general purpose register group 43.

  The “LD Output, #imm” command is a command for setting a constant value #imm in the output port register 45 o included in the control register group 45.

  “Set Idle” is an instruction to set an idle bit indicating an empty state in the status register (control register) 45 s of the control register group 45.

The “Inc Ax” instruction is an instruction for adding 1 to the address register Ax.
The “BNE Rx, Label” instruction is a branch instruction indicating branching to the instruction indicated by “Label” when the register value of the general-purpose register Rx is other than 0.

  The “Add Rx, #imm” instruction is an instruction for adding a constant value #imm to the stored value of the general-purpose register Rx. This addition is performed with a sign, and a negative number can be designated as the constant value #imm.

  The “MemLd Ax” instruction is a control instruction for the main arithmetic circuit 20 and is an instruction for loading data to the arithmetic processing unit group 35 from the address of the memory cell mat 30 indicated by the address stored in the address register Ax. The loaded data is held by a flip-flop (or register) included in the ALU 31.

  The “MemLdAdd Ax” instruction is an instruction that loads data from the address of the memory cell mat 30 indicated by the stored value of the address register Ax to the ALU 31 and adds the value held in the ALU 31 and the loaded data. is there. The addition result, that is, sum (Sum) and carry information, is held in a flip-flop (register) in the ALU 31.

  The “MemStSum Ax” instruction is an instruction for writing the contents of the flip-flop (register circuit) holding the sum (Sum) information in the ALU 31 to the address position indicated by the address register Ax in the memory cell mat 30.

  The “MemStCarry Ax” instruction is an instruction for writing the contents of the flip-flop (register circuit) holding the carry information in the ALU 31 to the address position indicated by the stored value of the address register Ax in the memory cell mat 30. .

  Execution of each instruction requires one instruction cycle. However, an instruction written together in one line across “||” in an instruction line indicates an instruction executed in parallel in the same instruction cycle. The processing contents of the program shown in FIG. 7 will be described below.

  In line number 0, an initial comment is simply added, and the process is not executed. At line number 1, the output bit register 45o is loaded with a start bit #Start for executing addition operation processing. As a result, the output port register 45o is initialized.

  In line numbers 2 to 4, address registers A0, A1, and A2 of address register group 47 have pointers #Apos, #Bpos, and #Cpos indicating the address positions of data a and b and addition result c, respectively. Each is set.

  At line number 5, a constant value 2 is stored in the general-purpose register R0 of the general-purpose register group 43, and the number of loops when loop processing is performed is set. Since this loop processing is performed in bit serial, it indicates that each addition operation is repeated.

  At row number 8, the bit at the position of address register A0 is selected in the memory cell mat and loaded into ALU 31. In the same cycle as this load operation, the pointer of the address register A0 is incremented by one.

  At row number 9, bit b [i] indicated by the pointer of address register A1 is selected in the memory cell mat and loaded into ALU 31, and addition of bits a [i] and b [i] is executed. Also in this cycle, the pointer value of the address register A1 is incremented by one.

  In row number 10, the addition result Sum is stored in bit position c [i] indicated by address pointer A2 of the memory cell mat. At this time, the pointer value of the address register A2 is also incremented by one.

  In line number 11, (-1) is added to the stored value of the general-purpose register R0, that is, the stored value of the general-purpose register R0 is decremented by 1, indicating that the addition process has been performed once.

  If the stored value of the general-purpose register R0 is different from 0 at the line number 12, the process returns to the loop label AddLoop at the line number 7 again. When the stored value of the general-purpose register R0 is 0, since the 2-bit addition process is completed, the process proceeds to the instruction of the next line number 13. Line number 13 is simply a comment statement indicating the contents of subsequent processing, and the processing is not executed.

  In the row number 14, the bit held by the flip-flop (register) that stores the carry of the ALU 31 is stored in the position indicated by the pointer value c [2] of the address register A2 of the memory cell mat.

  In line number 15, a comment sentence indicating the following processing content is added again, indicating that an instruction to transition to the standby state is performed.

  Since the process is completed at line number 16, an integer value Finish indicating that the process is completed is set in the output port register 45o, and an idle bit is set in the status register 45s at line number 17. Through the processing of line numbers 16 and 17, the basic operation block FBi notifies the external host CPU 8 and the like that the addition operation processing has been completed.

  FIG. 8 is a timing chart showing the update of the address values at the line numbers 8 to 10 shown in FIG. First, an initial address POS0 is set in the address calculation unit 46 by an initial setting instruction sequence. When the addition processing loop is executed, the address pointer POS0 stored in the address calculation unit 46 is set and stored in the address register Ax, and data transfer is executed (load / store). At this time, the address calculation unit 46 updates the address pointer to designate the next address POS1. In the next cycle, the pointer POS1 updated by the address calculation unit 46 is transferred to the address register Ax. Thereafter, the storage pointers of the address calculation unit 46 and the address register Ax are updated in parallel with the data transfer according to the loop of the addition processing loop AddLoop until necessary arithmetic processing is completed.

  An address register group 4 is provided, and address pointers Apos, Bpos, and Cpos for each operation target data are generated and stored in corresponding address registers, so that the address update cycle and the data transfer cycle are set to the same cycle. And the number of cycles required for instruction execution can be reduced.

  FIG. 9 is a diagram illustrating an example of the configuration of the ALU 31. In FIG. 9, an ALU 31 includes an arithmetic operation logic circuit 50 that performs a specified operation process, an A flip-flop (register circuit) 52 that temporarily stores data read from a corresponding entry, and a read from the corresponding entry. X flip-flop (register circuit) 54 for temporarily storing the processed data or the arithmetic processing result data of the arithmetic logic circuit 50 or the data to be transferred to the write driver, and the C flip-flop for storing the carry or borrow at the time of the addition / subtraction processing (Register circuit) 56 and an M flip-flop (register circuit) 58 for storing mask data designating prohibition of arithmetic processing of the arithmetic logic circuit 50.

  The sense amplifier and write driver SAW shown in FIG. 6 includes a write driver 60 and a sense amplifier 62 provided corresponding to the bit line pair BLP. The write driver 60 buffers the data stored in the X flip-flop 54 and writes it into the memory cell of the corresponding entry via the corresponding bit line pair BLP. Sense amplifier 62 amplifies the data read from the memory cell of the corresponding entry and transfers the amplified data to A flip-flop 52 or X flip-flop 54 via internal data transfer line 63. X flip-flop 54 is coupled to arithmetic logic circuit 50 and write driver 60 via internal data transfer line 64.

  The inter-ALU connection switch circuit 32 includes an inter-ALU connection circuit 65 provided for the ALU 31. The inter-ALU connection circuit 65 is constituted by a switch matrix, for example.

  The arithmetic operation logic circuit 50 can execute operations such as addition (ADD), logical product (AND), logical sum (OR), exclusive logical sum (EXOR: coincidence detection), inversion (NOT), etc. The calculation content is set by a control signal (ALU control in FIG. 6) from the controller 22 based on the microinstruction. When the mask data stored in the M flip-flop 58 is “0”, the arithmetic processing operation of the ALU 31 is stopped, and when the mask data is “1”, the arithmetic processing operation of the ALU 31 is enabled. By using this operation mask function, even if not all entries are used, it is possible to execute operations only on valid entries, perform accurate processing, and perform unnecessary operations. By stopping, current consumption can be reduced.

  In the arithmetic operation logic circuit 50, when the previous binary addition is performed, the addition is performed using a full adder, and finally the carry stored in the C flip-flop 56 is stored in the microinstruction of the line number 14 shown in FIG. To write the memory cell mat into the corresponding bit position c [2]. The addition result Sum is stored in the X flip-flop 54.

  As described above, according to the first embodiment of the present invention, a microinstruction memory is provided in each basic arithmetic block, and data transfer (load / store) and arithmetic processing are performed according to the microinstruction stored in the microinstruction memory. The contents of the operation can be freely switched only by changing the microinstruction.

  In addition, by providing an address register and an address calculation unit, address updating can be performed in parallel with the data transfer operation, the number of instruction cycles required for computation can be reduced, and high-speed processing can be realized. .

[Embodiment 2]
FIG. 10 schematically shows a structure of basic operation block FBi according to the second embodiment of the present invention. In basic operation block FBi shown in FIG. 10, the following configuration of controller 22 is different from the configuration of controller 22 according to the first embodiment shown in FIG. That is, the controller 22 is provided with a start address register 70 for storing the start address of the loop at the time of execution of the loop instruction and an end address register 72 for storing the end address of the loop. The stored values of the start address register 70 and the end address register 72 are given to the PC value calculation unit 42. The other configuration of the controller 22 shown in FIG. 10 is the same as the configuration of the controller 22 shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the second embodiment, a loop instruction LOOP is added which performs the subtraction process and branch process of the loop counter indicated by line numbers 11 and 12 of the microprogram shown in FIG. 7 with one instruction.

  The instruction “LOOP Rx, Label” is an instruction that repeats the number of times indicated by the stored value of the general-purpose register Rx between the next instruction and the instruction indicated by the label Label. When the loop instruction LOOP is executed, the start address and end address of the loop instruction are stored in the start address register 70 and the end address register 72, respectively.

  The PC value calculation unit 42 compares the count value of the program counter 41 with the address value stored in the end address register 72. When the count value of the program counter 41 matches the end address, the stored value of the general-purpose register Rx designated as the loop counter is decremented by one. If the subtraction result is not 0, the start address stored in the start address register 70 is set as the next program count value. When the stored value of the general-purpose register Rx is 0, the count value of the program counter 41 is incremented by 1 and the instruction at the next address is executed, as in normal processing.

  FIG. 11 shows an example of a microprogram using loop instruction LOOP according to the second embodiment of the present invention. The microprogram shown in FIG. 11 executes the same processing as the microprogram shown in FIG.

  As shown in FIG. 11, the instruction of line number 5 stores constant 2 in general-purpose register R0 and designates the number of loops. At line number 7, the loop instruction “LOOP R0, AddLoopLast” is executed. In this case, it is specified that the instruction indicated by the label “AddLoopLast:”, that is, the instruction sequence up to the instruction MemStSum on the eleventh row is repeated the number of times indicated by the value (2) stored in the general-purpose register R0. The instruction sequence from line number 7 to line number 10 is different from the instruction sequence of the microprogram shown in FIG.

  FIG. 12 shows the processing contents of the loop instruction LOOP. Hereinafter, the operation content of the loop instruction will be described with reference to FIG. In the following description, reference is made to the program line numbers shown in FIG.

  In the instruction group of line numbers 0 to 5, processing similar to that shown in FIG. 7 is performed, and initialization of output port register 45o and initialization of address registers A0-A2 and general-purpose register R0 are performed. The loop count 2 is set in the general-purpose register Rx (R0) (step S1).

  Next, when the loop instruction is executed at line number 7 (step S2), the start address of the loop (address of the instruction MemLd of line number 8) and the end address of the loop (address of the instruction MemStSum of line number 11) are obtained. They are stored in the start address register 70 and the end address register 72, respectively (step S3). Until this loop instruction is reached, it waits for execution of the loop instruction in decision block S2.

  After the loop start and end addresses are stored, the pointer PC of the program counter is incremented (step S4), and the next line number 8 instruction is executed (step S6). As a result, the memory cell data corresponding to the address stored in the address register A0 is loaded into the ALU, and the pointer of the address register A0 is incremented by one.

  In parallel with the instruction execution in step S6, branch determination is executed in step S5 and subsequent steps. Since the counter value of the PC value calculation unit 42 is not equal to the end address (step S5), the count value PC of the program counter 41 is incremented by 1 (step S4), and the instruction MemLdAdd of the next line number 9 is executed. (Step S6). Since the instruction address of the line number 9 (count value of the program counter 41) is not equal to the loop end address, the count value of the program counter 41 is incremented by 1, and the line number 11 specified by the label of the next line number 10 is designated. Are executed (steps S4 and S6).

  Since the address of the instruction of line number 11 (the count value of the program counter 41) is equal to the end address stored in the end address register 72, the register value stored in the general-purpose register R0 is 1 according to the determination result in step S5. It is decremented (step S7).

  Next, a determination is made as to whether or not the register stored value Rx is equal to 0 (step S8). Since it is still the first time, the PC value calculation unit 42 sets the count value PC of the program counter 41 to the start address register 70. (Step S9), and the process returns to step S6. Thereafter, the operations from step S4 to step S7 are repeated.

  In step S8, when the register value of the general-purpose register Rx (R0) becomes 0 after the instruction of the line number 11 is completed, it is determined that the loop processing is completed, and the PC value calculation unit 42 increments the count value of the program counter 11 by 1. (Step S10). As a result, the loop processing is completed, the next line number 13 instruction is performed, and the carry is written into bit position c [2].

  Therefore, in this loop instruction LOOP, the loop instruction itself is executed only once, that is, a loop-like branch is performed only once, and three instructions from the eighth line to the eleventh line are executed as loop processing.

  As the storage of the end address, the address of the next instruction may be stored in the end address register 72 when the label AddLoopLast of the line number 10 is reached. Even when the end address is stored when the label arrives, the comparison step S5 is executed with the label of the line number 10, and the branch to the line number 11 or the line number 7 is determined according to the execution result. Can be done.

  By adding this loop instruction LOOP, it is possible to eliminate the cycle in which the main arithmetic circuit is in an operation standby state for loop branch determination (line numbers 11 and 12 in the microprogram shown in FIG. 7). 9 is executed in parallel with the execution of the instruction 9), the loop process can be executed with the minimum number of cycles (in the flowchart shown in FIG. 12, steps S5 to S8 are executed from the instruction execution step S6). Executed in parallel).

  As described above, according to the second embodiment of the present invention, since the loop operation instruction is prepared, the period during which the main operation circuit is in the non-operating state can be reduced, and high-speed processing is realized.

[Embodiment 3]
FIG. 13 schematically shows a structure of basic operation block FBi according to the third embodiment of the present invention. In FIG. 13, the main arithmetic circuit 20 is provided with two memory cell mats 30A and 30B. Read / write circuits 38A and 38B are provided for memory cell mats 30A and 30B, respectively. Memory cell mats 30A and 30B have the same configuration and are each divided into a plurality of entries ERY. In read / write circuits 38A and 38B, a sense amplifier and a write driver SAW are provided corresponding to each entry ERY.

  These memory cell mats 30A and 30B are coupled to corresponding ALUs 31 included in the arithmetic processing unit 35 through bit line pairs separated from each other. Therefore, these memory cell mats 30A and 30B can be individually accessed. The main arithmetic circuit 20 is also provided with an inter-ALU interconnection switch circuit 32 for switching the connection path between the ALUs 31 of the arithmetic processing unit 35 as in the first and second embodiments.

  In order to control the operation of memory cell mats 30A and 30B, address calculation units 46A and 46B and address register groups 47A and 47B are provided. An address for memory cell mat 30A is generated by address calculation unit 46A and address register group 47A, and an address for memory cell mat 30B is generated by address calculation unit 46B and address register group 47B. As will be described later, the memory cells included in memory cell mats 30A and 30B are dual-port SRAM memory cells, and have a write port and a read port. These address register groups 47A and 47B are respectively Write address and read address are generated separately.

  The instruction decoder 40 generates an ALU control signal that defines the contents of arithmetic processing in the arithmetic processing unit 35 and generates a switch control signal that sets a connection path of the inter-ALU interconnection switch circuit 32. Instruction decoder 40 generates a write control signal (write control) for read / write circuits 38A and 38B. The memory cell is an SRAM cell. In the read / write circuit, the sense amplifier in the access is always activated by the sense amplifier and the sense amplifier included in the write driver SAW, and only the activation / inactivation of the write driver is determined by the instruction decoder. This is performed in accordance with a write control signal from 40.

  The other configuration of the controller 22 shown in FIG. 13 is the same as the configuration of the controller 22 shown in FIG. 10 in the second embodiment, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted. To do.

  FIG. 14 shows an example of the configuration of memory cells MC included in memory cell mats 30A and 30B shown in FIG. In FIG. 14, memory cell MC has a dual port memory cell structure in which a write port and a read port are provided separately. For memory cell MC, read word line RWL and write word line WWL are provided, and read bit lines RBL and / RBL and write bit lines WBL and / WBL are provided. Read port includes N channel MOS transistors NQ5 and NQ6 connecting storage nodes SN1 and SN2 to read bit lines RBL and / RBL, respectively, in response to the signal potential of read word line RWL. Write port includes N channel MOS transistors NQ7 and NQ8 connecting storage nodes SN1 and SN2 to write bit lines WBL and / WBL, respectively, in response to a signal potential on write word line WWL.

  Data storage portion of memory cell MC includes load P-channel MOS transistors PQ1 and PQ2 and drive N-channel MOS transistors NQ1 and NQ2, similarly to those shown in the first embodiment.

  By using the dual port memory cell structure shown in FIG. 14, when performing data processing in a bit serial manner, writing and reading, that is, storing and loading can be performed simultaneously. The area where the operation result is written is provided separately from the area where the operation target data is stored, and there is no problem of collision between the write data and the read data in the selected memory cell. There is no address arbitration problem.

  FIG. 15 schematically shows configurations of sense amplifiers and write drivers SAW and ALU 31 of memory cell mats 30A and 30B shown in FIG. 15, in read / write circuit 38A, sense amplifier and write driver SAW includes a write driver 60A coupled to write bit line pair WBLPA and a sense amplifier 62A coupled to read bit line pair RBLPA. . In read / write circuit 38B, sense amplifier and write driver SAW includes a write driver 60B coupled to write bit line pair WBLPB and a sense amplifier 62B coupled to read bit line pair RBLPB.

  As shown in FIG. 15, memory cell mats 30A and 30B are arranged symmetrically with respect to arithmetic processing unit 35 (ALU 31). The wiring layout of the bit line pairs in the memory cell mats 30A and 30B is facilitated.

  Unlike the configuration of ALU 31 shown in FIG. 9, ALU 31 includes an A flip-flop 52A that stores output data of sense amplifier 62A and an A flip-flop 52B that stores output data of sense amplifier 62B. X flip-flop 54 is commonly coupled to write drivers 60A and 60B. The arithmetic operation logic circuit 50 is supplied with the data stored in the A flip-flops 52A and 52B as operation target data, and the operation result is stored in the X flip-flop 54.

  The ALU 31 is further provided with a C flip-flop 56 for storing carry or borrow and an M flip-flop 58 for storing mask data indicating activation / inactivation of the ALU 31.

  When the ALU 31 shown in FIG. 15 is used, operation result data can be written from the X flip-flop 54 via the write driver 60A or 60B in parallel with the latching of data from the sense amplifiers 62A and 62B.

  FIG. 16 schematically shows a specific arrangement of memory cell mats 30A and 30B included in main operation circuit 20. In FIG. In the main arithmetic circuit 20 shown in FIG. 16, memory cell mats 30 </ b> A and 30 </ b> B are arranged on both sides of the arithmetic processing unit 35. These memory cell mats 30A and 30B have the same configuration, and m entries ERY each having a data bit width of n bits are arranged.

  ALU 31 performs the specified arithmetic processing on the data of the corresponding entries in memory cell mats 30A and 30B. When the ALU 31 performs the two-term operation, the calculation target data of each term is stored in the memory cell mats 30A and 30B, and the calculation processing result is stored in one of the memory cell mats 30A and 30B.

  The memory cell MC is a dual port memory cell, and the transfer (load) of operation target data to the ALU 31 and the transfer (store) of operation result data can be performed in parallel.

  FIG. 17 shows an example of a microinstruction program for executing a binary addition operation according to the third embodiment of the present invention. Hereinafter, with reference to FIG. 17, the processing of the basic operation block according to the third embodiment of the present invention will be described.

  In the microinstruction program shown in FIG. 17, the same processing as that in the second embodiment is executed at line numbers 0 to 5. That is, the instruction “LD Ax, #imm” from line number 2 to line number 4 sets the start address of the data to be accessed (address of the least significant bit of the data) in the address pointers A0 to A2. As an example, an address for the memory cell mat 30A is set in the address register A0, and an address for the memory cell mat 30B is set in the address register A1. One address of the memory cell mat 30A or 30B is set in the address register A2 that stores an address for the data c after the calculation.

  By the instruction “LD R0, # 2” of the line number 5, the loop count (twice) is set in the control register R0.

  Next, at line number 7, a loop instruction is executed, and the address corresponding to the start address of the loop instruction (the address of the instruction at line number 8) and the address for the instruction at line number 9 are stored as the start address and end address, respectively. The In this case, when the labels and instructions of line numbers 8 and 9 are stored at the same address in the microinstruction memory, the start address and the end address are the same address.

  In the instruction group of line number 9, addition, storage of the addition result, and address increment are executed in parallel. That is, according to the instruction of row number 9, the memory cell at the address stored in address register A0 is read out and transferred to the corresponding ALU, and in parallel, the memory cell at the address stored in address register A1 Are read from the corresponding memory cell mat and transferred to the corresponding ALU. In this transfer operation, read word line RWL of the memory cell is driven to a selected state, and data is transferred to A flip-flops 52A and 52B of the corresponding ALU via read bit lines RBL and / RBL.

  After this transfer operation and addition, the addition result is stored in the address position indicated by the address register A2 in the same cycle. In writing, write word line WWL is driven to a selected state, and data is transferred via write bit lines WBL and / WBL. The load, addition, and store may be performed in the first half cycle within one machine cycle, and the addition result (Sum) may be transferred in the second half cycle. Alternatively, the addition result may be stored in the next cycle of loading the operation target data. In this case, the next calculation target data is loaded and stored in parallel.

  In parallel with the execution of the load, addition, and store operations, the pointer values of the address registers A0, A1, and A2 are incremented by one.

  The loop instruction LOOP is executed, the same processing as in the flow shown in FIG. 12 is performed, the instruction of line number 9 is the end address of the loop instruction, and the stored value of the register R0 is decremented by 1. A determination is made as to whether the stored value of the register is equal to zero. At the time of the first calculation process, the stored value of the control register R0 is 1. Again, the processing returns to the line number 8 and the instruction starting with the label AddLoopLast is executed.

  When the second load, addition, and store operations are completed, the stored value of the general-purpose register R0 is decremented again to determine whether the register value is not 0. The stored value of the general-purpose register R0 is 0 at this time, the execution sequence of the loop instruction is completed, the count value of the program counter is incremented by 1, the instruction of line number 11 is executed, and the carry is designated by the address register A2. Stored in memory cell location.

  Thereafter, in line numbers 12 to 14, the same processing as in the first and second embodiments is performed, and the completion of the addition operation is notified to an external host CPU or the like by storing the control bit in the control register.

  By separately providing address register groups 47A and 47B for memory cell mats 30A and 30B, the load instructions indicated by line numbers 2 to 4 can be executed in parallel in one cycle ( In the program sequence shown in FIG. 17, it is shown that these are stored sequentially). Therefore, the number of operation cycles required for setting the address pointer can be reduced, and the number of processing cycles can be reduced. When setting pointers in these address registers A0-A2, address registers A0, A1 and A2 are designated as destination addresses as microinstructions, and pointer values stored in the address registers are stored in the control field and operated. This is easily realized by storing the power execution instruction “LD” in the source operand field.

  By using this dual port memory cell, in a loop instruction, load, addition, and store can be executed in one cycle. Compared to the process using the loop instruction in the second embodiment, The number of arithmetic processing cycles is reduced, and a loop process with three times the performance can be realized as the processing performance.

  When this dual port memory cell is used, when only memory cell mat 30A or 30B is used, a read address register and a write address register and respective address calculation units are provided. Load and store can be executed in parallel for one memory cell mat.

  As described above, according to the third embodiment of the present invention, the memory cell mat is divided into a plurality of mats, and each divided mat is also provided with dual port memory cells, and each memory cell mat has an address. A calculation unit and an address register group are provided, and load, calculation, and store operations can be executed in the same cycle, and high-speed processing can be realized.

  When data loading, calculation, and store are executed in the same cycle, for example, a configuration is used in which all flip-flops in the ALU are set to the through state and all given data is transferred via the output unit. . By performing the arithmetic processing statically, it is possible to statically perform the arithmetic processing on the transfer data (load data) and transfer and write the data after the arithmetic processing to the target memory cell via the write driver. .

[Embodiment 4]
FIG. 18 is a diagram schematically showing the contents of the arithmetic processing executed as an example in the fourth embodiment of the present invention. In the fourth embodiment of the present invention, filter processing is performed on the image data P. That is, as shown in FIG. 18, with respect to the target pixel P (i, j), adjacent pixels P (i−1, j), P (i + 1, j), P (i, j−1), The filter matrix shown in FIG. 18 is applied using P (i, j + 1) to generate a filtered pixel B (i, j). That is, the edge-enhanced image is obtained by performing the filter processing represented by the following equation.

B (i, j)
= 5 · P (i, j) −P (i−1, j) −P (i + 1, j)
-P (i, j-1) -P (i, j + 1)
0 ≦ i <N−1,
0 ≦ j <M−1
Here, N and M indicate the number of pixel rows and pixel columns of image data of one frame. Therefore, in this edge emphasis filter process, data for four adjacent pixels is required in addition to the target pixel data as a process for the target pixel P (i, j).

  FIG. 19 is a diagram schematically showing a configuration of a portion related to image data filter processing of the signal processing system according to Embodiment 4 of the present invention. In FIG. 19, in the system LSI 2, two basic operation blocks FBA and FBB are used. These basic operation blocks FBA and FBB output a DMA transfer request DMARQ to the DMA controller 13. When a DMA transfer request is generated, the DMA controller 13 reads data of a large capacity memory (SDRAM) 4 coupled to the external system bus 3 via the external bus controller 14 and reads the basic operation block FBA via the internal system bus 7. Alternatively, necessary data is transferred to the FBB.

  In the SDRAM 4, image data to be processed is stored. As an example, a VGA size (video graphics array) is considered as the size of image data of one frame. In this VGA, one frame is composed of 640 · 480 pixels (M = 640, N = 480). Assume that each of the arithmetic blocks FBA and FBB can process data of three rows (lines) of pixels (640 × 3 = 1920 pixels). This image data is stored in the SDRAM 4, the basic operation blocks FBA and FBB are operated in a pipeline manner, and filter operation processing is executed with high throughput.

  A basic instruction block for the filter operation processing and a microinstruction sequence for data transfer between the SDRAM 4 are executed by the host CPU 8. The microprogram for filter processing is stored in the microinstruction memory of each basic operation block FBA and FBB, and edge emphasis filter operation processing is executed under the control of the corresponding controller (21).

  FIG. 20 is a flowchart showing a processing sequence of the host CPU of the signal processing system according to the fourth embodiment of the present invention. The operation of the signal processing system shown in FIG. 19 will be described below with reference to FIG.

Step ST1:
A microprogram for performing a filter operation on the three rows of pixels for the basic operation block FBA is set in the corresponding microinstruction memory (21). After setting the microprogram, the pixel data of the 0th to 2nd rows of the frame are transferred from the SDRAM 4 to the memory cell mat of the basic operation block FBA via the external bus controller 14 and the internal system bus 7. When this transfer operation is completed, the operation of the basic operation block FBA is started, and the filter operation processing is started in the operation block FBA according to the microprogram stored in the microinstruction memory. The completion of the transfer and storage of the memory cell mat of data is referred to by monitoring the bit value stored in the status register included in the control register group 45, for example. For example, a bit at the time of data transfer may be set in the input port register 45i shown in FIG. 6, and the waiting for the calculation in the basic calculation block FBA may be designated.

Step ST2:
In the basic operation block FBA, filter operation processing is executed in accordance with the microprogram stored in the microinstruction memory. In parallel with the execution of the filter calculation processing for the pixels in the first row in the basic calculation block FBA, the host CPU 8 similarly performs the microprogram for the filter calculation for the pixels in the three rows for the basic calculation block FBB. Are stored in the microinstruction memory, and the pixel data in the 239th to 241st rows are transferred from the SDRAM 4 to the basic operation block FBB and stored in the corresponding memory cell mat.

  In the basic operation block FBA, when the filter operation processing for the pixels in the first row is completed, a DMA transfer request DMARQ is issued to the DMA controller 13. The DMA transfer request DMARQ is issued, for example, by setting a bit in an output port register included in the control register group.

Step ST3:
When the DMA controller 13 receives the DMA transfer request from the basic operation block FBA, the DMA controller 13 transfers the operation result data from the basic operation block FBA to the SDRAM 4, and after this transfer is completed, the pixel data of the third row is transferred to the basic operation block. Transfer to FBA. In the basic operation block FBA, the newly transferred pixel data of the third row is sequentially stored in the pixel data storage area of the zeroth row. Thereby, the pixel data of the 0th row that has been processed is replaced with the new pixel data of the third row.

  In parallel with the data transfer in the DMA mode between the basic operation block FBA and the SDRAM 4, a filter operation is performed on the pixel data in the 240th row in the basic operation block FBB. After completion of this filter operation processing, the basic operation block FBB issues a DMA transfer request DMARQ via its output port register.

Step ST4:
The basic operation block FBA performs a filter operation on the pixels in the second row after the transfer of the pixel data in the third row is completed. On the other hand, in the basic operation block FBB, in accordance with the DMA transfer request issuance, the filter operation result for the pixels in the 240th row is transferred to the SDRAM 4 in the DMA mode, and after the transfer is completed, the pixel data of the next 242nd row is transferred from the SDRAM 4. Receive. The pixel data of the 242nd row is replaced with the previously stored pixel data of the 239th row.

Step ST5:
After completion of the filter calculation processing for the pixel data of the second row in the basic operation block FBA, a DMA transfer request is issued, and the second row is transferred from the basic operation block FBA to the SDRAM 4 in the DMA mode under the control of the DMA controller. The filter calculation result data of the pixels is transferred. After this transfer is completed, the SDRAM 4 transfers the pixel data of the fourth row to the basic operation block FBA. The newly transferred pixel data of the fourth row is stored in the pixel data storage area of the first row of the memory cell mat of the basic arithmetic block FBA.

  On the other hand, in the basic calculation block FBB, filter calculation processing is performed on the pixels in the 241st row using the transferred pixel data. After the completion of the filter calculation process, a DMA transfer request DMARQ is issued.

Thereafter, similar processing is repeatedly performed alternately after step ST6.
That is, in step ST5 to step ST481, the processes in steps ST3 and ST4 are repeated 239 times while incrementing the target pixel line by one. When the process of step ST481 is completed, the filter calculation process for the pixels of one screen is completed.

  As described above, by executing the DMA transfer and the arithmetic processing alternately in the basic arithmetic blocks FBA and FBB, the arithmetic processing can be efficiently executed as the entire system.

  FIG. 21 schematically shows a signal processing sequence of the signal processing system according to the fourth embodiment of the present invention. In FIG. 21, in the basic operation blocks FBA and FBB, microinstructions for performing edge emphasis filtering on pixels of three lines are stored in the microinstruction memory 21. The controller 22 executes arithmetic processing according to the microprogram stored in the microinstruction memory 21.

  In the SDRAM 4, first, three lines of pixel data are stored in the memory cell mats 30 of the basic operation blocks FBA and FBB, respectively, under the control of the host CPU. Next, the basic arithmetic blocks FBA and FBB each perform arithmetic processing under the control of the corresponding controller 22 using the arithmetic processing unit 35 and the inter-ALU connection switch circuit (ALU switch) 20.

  The basic operation blocks FBA and FBB transfer the pixel data after the filter operation processing for one line to the SDRAM 4 according to the DMA transfer modes DMA3 and DMA4 when the edge emphasis filter processing for three lines is completed for one row of pixels. On the other hand, at this time, one line of pixel data before the next processing is transferred from the SDRAM 4 to the basic operation blocks FBA and FBB according to the DMA transfer modes DMA1 and DMA2, respectively. Done. Therefore, the pixel data of 3 lines (rows) is stored in the memory cell mat 30 and the filter calculation process is executed.

  FIG. 22 is a diagram showing changes in the address pointer of the memory cell mat during the DMA transfer. Memory cell mat 30 is divided into four areas MA-MD as an example. The divided area MD is a work area and is used as an area for storing intermediate values. Pixel data of different rows are stored in the divided areas MA-MC. As shown in FIG. 22A, in the initial state, the initial address pointers of the divided areas MA, MB, and MC are set to RP0, RP1, and RP2, respectively. In the divided areas MA, MB, and MC, pixel data of the 0th row, the 1st row, and the 2nd row are stored, respectively. The address pointer RP1 designates an area of pixel data to be subjected to filter calculation processing, the address pointer RP0 represents an area of pixels on the row above the pixel to be filtered, and the pointer RP2 represents a pixel line to be subjected to filter calculation processing. The pixel area of the lower line is shown. Accordingly, in FIG. 22A, the filter calculation process is executed on the pixel data stored in the divided area MB designated by the pointer RP1.

  In the DMA transfer mode, the write pointer WP designates the divided area MA, and the transfer pointer TP designates the divided area MB. Data after the filter calculation processing is stored in the divided area MB, and the pixel data after the filter calculation of the divided area MB is transferred according to the transfer pointer TP. On the other hand, the pixel data of the next third row is stored in the area MA designated by the write pointer WP. Therefore, at the completion of this transfer, as shown in FIG. 22B, the pointer RP1 that designates the pixel to be processed indicates the divided area MC, the upper line pixel designation pointer RP0 indicates the divided area MB, and the lower line The pixel area designation pointer RP2 indicates the divided area MA. Thereby, the filter calculation process is performed on the pixel data of the second row stored in the divided region MC.

  After completion of the filter operation processing of the pixel data of the second row, the transfer pointer TP indicates the divided area MC, and the write pointer WP indicates the divided area MB. Therefore, in this case, the pixel data of the second row (after the filter calculation process) stored in the divided region MC is transferred, and the pixel data of the fourth row of the next row is stored in the divided region MB. After this storage, the pointers are shifted as shown in FIG. 22 (c), the processing area pointer RP1 indicates the divided area MA, the upper line pixel area designation pointer RP0 indicates the divided area MC, and the lower line pixels. The area designation pointer RP2 indicates the divided area MB. The transfer pointer TP also indicates the divided area MA, and the write pointer MB indicates the divided area MB. Therefore, in this state, the filter calculation is performed on the pixels in the third row of the divided area MA indicated by the pointer RP1, and the data after the completion of the filter calculation process is stored in the divided area MA. After completion of the arithmetic processing, the pixel data after the filter operation of the third row of the divided area MA is transferred according to the transfer pointer TP and stored in the SDRAM. On the other hand, in the divided area MB indicated by the write pointer WP, The pixel data of the fourth line is stored.

  After this transfer is completed, the pointers RP0-RP2, TP, and WP are shifted again, the processing target area designation pointer RP1 indicates the divided area MB, the upper line pixel area designation pointer RBP0 indicates the divided area MA, and the lower line pixels The area designation pointer RP2 indicates the divided area MC. The transfer pointer TP indicates the divided area MB, and the write pointer WP indicates the divided area MC. Therefore, the position of the pointer shown in FIG. 22D is the same as the position of the pointer shown in FIG. Therefore, by sequentially shifting these pointers RP0 to RP2, TP, and WP by the size of the divided area for each process, data can be easily written, transferred, and the process result can be stored.

  This setting of the address pointer is realized by, for example, an instruction that uses a general-purpose register and sequentially shifts the contents of each register when one 3-line edge emphasis filter process of the microprogram instruction is completed.

  In the pointer shift configuration shown in FIGS. 22A to 22D, the transfer pointer TP always designates a fixed divided area MD, and this divided area always represents the pixel data after the filter calculation process. It may be used as a storage area. Control of the transfer pointer TP is simplified.

  Next, various processing flows can be considered as the procedure of the edge enhancement filter calculation process. For example, the following processing flow can be considered. In the arithmetic processing for multiplying the pixel data P (i, j) to be processed by 5 times, all the bits of the pixel data P (i, j) are shifted in the upper 2 bits and stored in the divided region MD shown in FIG. As a result, 4 · P (i, j) is calculated. Subsequently, the pixel data P (i, j) and 4 · P (i, j) stored in the area designated by the pointer RP1 are added, and the addition result is stored in the pixel data P (i, j) storage area. Store. As a result, multiplication processing of 5 · P (i, j) is realized.

  Next, the pixels P (i−1, j) and P (i + 1, j) in the same column are added, and data P (i−1, j) + P (i + 1, j) is stored in the divided region MD. Next, the data stored in the divided area MD is subtracted from this 5 · P (i, j). In the case of the subtraction process, in order to perform a 2's complement operation, all the bit values of the data stored in the divided area MD are first inverted, and then 1 is added. -{P (i-1, j) + P (i + 1, j)} = A (i, j) is generated. Next, 5 · P (i, j) −A (i, j) is generated by adding these.

  Next, when subtracting the pixel data of the adjacent column, first, the ALU path is switched by the inter-ALU connection switch circuit 20 so as to transfer the data of the adjacent column. As a result, the right or left pixel is subtracted, and then the connection path of the ALU switch circuit 20 is switched again to perform subtraction with another adjacent column of pixels. Through a series of these processes, the pixel data after the filter calculation process can be obtained by performing the filter calculation process described above. By these series of processes, a complicated filter calculation process can be executed in a bit serial manner.

  The switching of the connection path and each operation sequence are all defined by a microprogram stored in the microinstruction memory.

  As described above, according to the fourth embodiment of the present invention, data transfer is performed in a DMA mode between a plurality of basic blocks and an external large-capacity memory, and data transfer and arithmetic processing are performed in a pipeline manner. It is running and can process large amounts of data at high speed.

[Embodiment 5]
FIG. 23 shows an example of a specific configuration of main arithmetic circuit 20 according to the fifth embodiment of the present invention. In the main arithmetic circuit 20, the memory cells MC arranged in the memory cell mat 30 are single port SRAM cells. A word line WL is arranged corresponding to each memory cell row, and a bit line pair BLP is arranged corresponding to each memory cell column. Memory cell MC is arranged corresponding to the intersection of bit line pair BLP and word line WL. A memory cell MC in a corresponding row is connected to the word line WL, and a memory cell MC in a corresponding column is connected to the bit line pair BLP.

  Entry ERY is provided corresponding to each bit line pair BLP. In memory cell mat 30 shown in FIG. 23, entries ERY0-ERY (m--) correspond to bit line pairs BLP0 to BLP (m-1), respectively. 1) is arranged. The bit line pair BLP is used as a data transfer line between the corresponding entry ERY and the corresponding ALU 31.

  A word line WL to which an operation target data bit is connected is selected in accordance with an address signal from the controller 22 or an address signal (and control signal) from the system bus I / F 24 with respect to the word line WL of the memory cell mat 30 A row decoder 74 is provided for driving to. Memory cells at the same position in entries ERY0 to ERY (m−1) are connected to word line WL, and row decoder 74 selects data bits at the same position in entries ERY0 to ERY (m−1). .

  In the arithmetic processing unit 35, the ALU 31 is arranged corresponding to the bit line pair BLP0-BLP (m-1).

  A read / write circuit 38 for loading / storing data is provided between the arithmetic processing unit group 35 and the memory cell mat 30. Read / write circuit 38 includes a sense amplifier group 70 and a write driver group 72 each including a sense amplifier and a write driver provided for each of bit line pairs BLP0 to BLP (m−1).

  An input / output circuit 76 for exchanging data with the outside via the system bus I / F 24 is provided for the read / write circuit 38. By this input / output circuit 76, data transfer is performed between the memory cell mat 30 and the internal data bus. The data input / output bit width of the memory cell circuit 76 is set according to the data bit width of the system bus I / F 24.

  A column decoder 78 is provided to adjust the data bit width in the input / output circuit 76 and the bit width (m) of an entry connected to one word line WL. A bit line pair (sense amplifier or write driver) corresponding to the bus width of the system bus I / F 24 is selected by the column selection line CL from the column decoder 78. The column decoder 78 is supplied with the lower bits of the address signal supplied from the system bus I / F 24. The number of lower bits is appropriately determined according to the bus width of the system bus I / F 24.

  The entry selected by the column selection line CL is connected to the input / output circuit 76, and data is exchanged with the system bus I / F 24. Thereby, data access to memory cell mat 30 can be performed via system bus I / F 24.

  FIG. 24 shows an example of CPU address assignment of the main arithmetic circuit according to the fifth embodiment of the present invention. In the configuration shown in FIG. 24, as an example, memory cell mat 30 is divided into 64 entries ERY0 to ERY63. The number of bits of the upper address supplied to the row decoder 74 is determined according to the number of word lines (bit width of the entry) included in the memory cell mat 30.

  In the region of read / write circuit 38, internal data lines IO0-IO3 coupled to input / output circuit 76 are arranged. The input / output circuit 76 transfers 4-bit data. In this case, a 4-bit lower address is given to the column decoder 78. A column address “0” is assigned to the entries ERY0 to ERY3, and a column address “1” is assigned to the entries ERY4 to ERY7. Thereafter, the column address “f” (hexadecimal) is assigned from the entry ERY60 (not shown) to the entry ERY63 in the same manner.

  Therefore, the column decoder 78 performs 1/16 selection. When the column selection line CL0 is selected, the entries ERY0 to ERY3 are selected, and when the column selection line CL1 is selected, the entries ERY4 to ERY7 are selected. Similarly, when the column selection line CL15 is selected, entries ERY60 to ERY63 are selected.

  A word line is selected by row decoder 74 in accordance with an upper address (for example, “0xx”).

  By using the column decoder 78 to make the number of data transfer bits input / output by the input / output circuit 76 the same as the bit width of the system bus I / F 24, an external host CPU or DMA controller can store the data in the memory cell mat 30. Data can be accessed.

  In this case, data accessible from the outside is data at the same bit position across a plurality of entries. When the arithmetic processing is executed in the bit serial mode, therefore, the data string is rearranged so that each bit of one data is stored in the same entry.

  As described above, according to the fifth embodiment of the present invention, the number of selected columns of the column decoder 78 is set so that the bit width of the input / output circuit is the same as the bit width of the system bus I / F. The data in the memory cell mat 30 can be accessed by an external host CPU or DMA controller.

[Embodiment 6]
FIG. 25 schematically shows a structure of a system LSI according to the sixth embodiment of the present invention. FIG. 25 specifically shows only the configuration of basic operation block FB1, but in each of basic operation blocks FB1-FBh, a switching circuit (MUX) for transferring work data from controller 22 to memory cell mat 30. 80 is provided. The switching circuit (MUX) 80 couples one of the system bus I / F 24 and the controller 22 to the memory cell mat 30 included in the main arithmetic circuit 20. Specifically, switching circuit 80 is coupled to input / output circuit 76 in the main arithmetic circuit shown in FIG.

  The other configuration of the system LSI shown in FIG. 25 is the same as that of the system LSI shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 25, the memory cell mat 30 is used as a calculation target data storage area and is also used as a work data storage area of the controller 22. Therefore, the work data memory (23) shown in FIG. 1 or the like is not necessary, and the chip area can be reduced.

  FIG. 26 schematically shows a structure of a data storage region in memory cell mat 30 in the sixth embodiment of the present invention. 26, memory cell mat 30 includes a calculation data area 30p for storing calculation data and a work area 30w for storing work data from controller 22. In the calculation data area 30p, each bit of the calculation target data DTo is stored in the entry ERY (ERYa, ERYb). On the other hand, in work area 30w, each bit of work data DTw is stored in the same column over a plurality of entries (ERYa... ERYb). Therefore, in operation data area 30p, the data in which the bit positions of the external data words are rearranged is stored, while in work area 30w, the work data from the controller is not subjected to the rearrangement process. A word is stored at one address location.

  In memory cell mat 30, work area 30w is uniformly assigned to the entries of memory cell mat 30, and work data is stored. Therefore, the calculation data storage part and the work data storage part are equally allocated to each entry, and the entire area of a specific entry is not used for work data storage. Will not be damaged.

  In the work area 30w, there is no need to rearrange data, and the controller 22 can access the work data DTw by the same operation as the work memory access for storing normal work data.

  As described above, according to the sixth embodiment of the present invention, the memory cell mat is configured such that the controller can access the memory cell mat via the switching circuit, and the memory cell mat is stored in the operation data and work data. It can be used as a region, a work data memory becomes unnecessary, and the chip area can be reduced.

[Embodiment 7]
FIG. 27 schematically shows a structure of a system LSI according to the seventh embodiment of the present invention. In the system LSI 2 shown in FIG. 27, in each of the basic arithmetic blocks FB1 to FBh, a transposition circuit 85 that rearranges the rows and columns of given data between the system bus I / F 24 and the main arithmetic circuit 20, A switching circuit (MUX) 87 for setting a connection between one of system bus I / F 24 and transposition circuit 85 and main arithmetic circuit 20 is provided. Also in FIG. 27, the basic operation blocks FB1 to FBh have the same configuration, and therefore the configuration of the basic operation block FB1 is representatively shown. The other configuration of the semiconductor signal processing device 1 shown in FIG. 27 is the same as that of the semiconductor signal processing device shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Transposition circuit 85 transfers data transferred from system bus I / F 24 in a bit-parallel and word-serial manner in a word-parallel and bit-serial manner, and stores different data words in each entry of memory cell mat 30. Write bits in the same position in parallel. The transposition circuit 85 transposes the data string transferred in word parallel and bit serial from the memory cell mat 30 of the main arithmetic circuit 20 and transfers it in a bit parallel and word serial manner. Thereby, consistency of data transfer between the system bus I / F 24 and the memory cell mat 30 is ensured.

  In the configuration shown in FIG. 27, the switching circuit 87 may be configured to select work data from the controller 22 and transfer it to the main arithmetic circuit 20. In this case, the work data memory 23 becomes unnecessary. When it is not necessary to transpose the operation target data, the switching circuit 87 selects the system bus I / F 24 and connects it to the main operation circuit 20.

  FIG. 28 schematically shows a structure of transposition circuit 85 shown in FIG. 28, a transposition circuit 85 includes a transposition memory 90 having storage elements arranged in L rows and L columns, and a system bus transposition memory I / F (interface) that serves as an interface between the transposition memory 90 and the system bus I / F 24. ) 91, a memory cell mat transposed memory I / F 92 coupled to the input / output circuit 76 via the transposed memory 90 and the internal memory bus and serving as an interface for data transfer with the memory cell mat (30), and the transposed circuit 85, a control register group 94 for storing information necessary for internal operation, an internal register group 93 for storing address information at the time of data transfer, and an access target for the memory cell mat based on the information contained in the internal register group 93 A memory cell mat address calculation unit 95 that calculates No.

  Data transfer is performed between the memory cell mat and the transposition circuit 85 in units of L bits, and data transfer is performed between the transposition circuit 85 and the system bus I / F 24 in units of L bits. The bit widths of the memory internal bus (IO line shown in FIG. 24) and the internal system bus 7 are L bits.

  The internal register group 93 includes a system bus access number counter 93a that stores count information of the number of accesses to the internal system bus 7, and a memory cell mat access number counter 93b that stores count information of the number of accesses to the memory cell mat. .

  The control register group 94 includes an entry position register 94a for storing entry position information, a bit position register 94b for storing bit position information, and an enable register 94c for storing control bits for determining the activation / inactivation of the transposition circuit 85. And a read / write direction register 94d for storing information for setting the data write / read direction of transposition circuit 85. The entry position register 94a and the bit position register 94b specify entry position and bit position information in the memory cell mat. The transposition memo 90 holds the contents in the memory cell mat of the designated area, and the transposition circuit 85 functions as a read / write buffer circuit having a function of rearranging data.

  The storage status of data in transposition memory 90 is indicated by the count values of counter registers 93a and 93b in internal register group 93.

  The system bus transposition memory I / F 91 has a function of controlling data transfer between the transposition circuit 85 and the internal system bus 7, and at the time of data transfer from the transposition circuit 85 to the memory cell mat (memory internal bus) Wait control of a bus request for requesting data transfer between the system bus 7 and the transposition memory 90 is performed.

  The memory cell mat address calculation unit 95 calculates the address of the memory cell mat to be transferred based on the information stored in the entry position register 94a and the bit position register 94b during data transfer to the memory cell mat. Transfer to the main arithmetic circuit (transfer to the row decoder 70 and the column decoder 4 shown in FIG. 24).

  Transposition memory 90 performs data transfer with system bus transposition memory I / F 91 in units of data DTE composed of bits aligned in the Y direction (data DTE is sequentially stored in the X direction). Since the data word is stored in the same entry, the system bus I / F 91 transfers data in entry units. On the other hand, transposition memory 90 performs data transfer using data bits aligned in the X direction when transferring data to / from memory cell mat transposition memory I / F 92. That is, in transposition memory 90, data DTE aligned in the Y direction is data in units of external addresses, and in the memory cell mat, data is in units of entries stored in the same entry, and is in word serial bit parallel units. Stores the data to be transferred. On the other hand, the data DTA in the X direction is data over a plurality of entries in the memory cell mat, is data stored at the same address in the memory cell mat, is transferred in word parallel and bit serial, and is stored at the same position in each entry. This is data in the address unit of the memory cell mat composed of bits.

  In transposition memory 90, by separately providing a port for transferring data to and from the system bus and a port for transferring data to and from the memory internal bus, data transfer is performed by rearranging X-direction data and Y-direction data. Can do. Next, an operation of transposition circuit 85 when data is written from internal system bus 7 to memory cell mat via input / output circuit 76 will be described with reference to the operation flow of FIG. 29 as an example.

Phase 1:
First, the first bit position (word line address) and entry position (bit line address) to be written in the memory cell mat of the main arithmetic circuit are set in the bit position register 94b and the entry position register 93a, respectively. Next, a bit indicating writing is set in the read / write direction register 90d.

  Thereafter, an enable bit is set in the enable register 94c to enable the transposition circuit 85. By asserting the enable bit of the enable register 94c, the count values of the counter registers 93a and 93b included in the internal register group 93 are initialized to 0 (step SP1).

Phase 2:
Transfer data is written from the system bus I / F 24 to the transposition memory 90 via the system bus transposition memory I / F 91. The write data to the transposition memory 90 is stored in order from the first row in the X direction of the transposition memory 90 as multi-bit data DTE aligned in the Y direction. Each time data is written to the transposition memory 90, the count value of the system bus access number counter register 93a is incremented (step SP2).

Phase 3:
Data through the system bus transposition memory I / F 91 until the storage contents of the transposition memory 90 become full, that is, until the count value of the system bus access count counter register 93a reaches the bus width L of the memory internal bus. Writing is performed (step SP3).

Phase 4:
When data is written L times into transposition memory 90 from internal system bus 7 via system bus I / F 24 and system bus transposition memory I / F 91, data is transferred from transposition memory 90 to the memory cell mat. Therefore, the system bus transposition memory I / F 91 asserts a wait control signal for the internal system bus 7 and sets the system bus I / F 24 in a state of waiting for subsequent data writing (step SP4). Whether or not the storage state of the transposition memory 90 is full is determined by monitoring the count value of the system bus access number counter register 93a.

  In parallel with this operation, memory cell mat transposition memory I / F 92 is activated, data DTA aligned in the X direction of transposition memory 90 is read, and data is transferred to input / output circuit 76 (step SP5).

  The memory cell mat address calculation unit 95 calculates the address of the memory cell mat to be transferred based on the stored values of the entry position register 94a and the bit position register 94b and the memory cell mat access frequency counter register 93b, and transmits this data. Output together. Further, in accordance with the data transmission to the memory cell mat, the memory cell mat transposition memory I / F 92 increments the count value of the memory cell mat access number counter 93b.

Phase 5:
Until the stored contents of the transposition memory 90 become empty, until the stored value of the memory cell mat access count counter register 93b becomes L, data in L bit units from the transposition memory 90 via the memory cell mat transposition memory I / F 92 The transfer continues (steps SP5 and SP6).

Phase 6:
If it is determined in the determination step SP6 of the flowchart shown in FIG. 29 that the storage contents of the transposition memory 90 are empty, it is determined whether all transfer data has been transferred (step SP7). If transfer data remains, the count values of the access count register counters 93a and 93b are initialized again, and then the process returns to step SP2 shown in FIG. At this time, L is added to the stored value of the entry position register 94a. When the stored value of the entry position register 94a exceeds the number of entries in the memory cell mat, the value of the entry position register 94a is set to 0, and the next word line is selected in the memory cell mat, so that the bit position register 94b is selected. Is incremented by 1 (step SP8). The system bus transposition memory I / F 91 releases the wait to the internal system bus I / F 7 and resumes writing data from the internal system bus 7 to the transposition memory 90.

  Next, the above-described phase 2 to phase 6 (that is, the operations of steps SP2 to SP8 shown in FIG. 29) are repeatedly executed.

  In step SP7 shown in FIG. 29, when it is determined that all the data transfer has been completed (determined by the deassertion of the transfer request from the system bus I / F 24), the data transfer ends. Through a series of these processes, data transferred from the outside in word serial can be converted into bit serial and word parallel data and transferred to the memory cell mat.

  FIG. 30 schematically shows data transfer from SDRAM 4 to memory cell mat 30 shown in FIG. In FIG. 30, data transfer when the bit width of the internal system bus 7 is 4 bits is shown as an example.

  In FIG. 30, 4-bit data A (bits A3-A0) to I (bits I3-I0) are stored in the SDRAM 4. 4-bit data DTE (data I; bits I3-I0) is transferred from SDRAM 4 to internal memory 90 via internal system bus 7 and stored. The data DTE from the SDRAM 4 is entry unit data stored in the same entry. In the transposition memory 90, data bits are stored in the Y direction.

  At the time of data transfer from transposition memory 90 to memory cell mat 30, each bit of data DTA aligned in the X direction of transposition memory 90 is read in parallel. Address unit data DTA including data bits E1, F1, G1, and H1 is stored in the positions indicated by the entry position information and the write bit position information of the memory cell mat 30. The bit position information stored in the bit position register is used as the word line address of the memory cell mat 30, and the entry position information is used as the bit line address of the memory cell mat 30. The bit position information and the entry position information are stored in the entry position register 94a and the bit position register 94b in the previous control register group 94. The write bit position information indicating the actual data write position is stored in memory based on the count value of the memory cell mat access count counter 93b, the information in the entry position register 94a, and the bit position information stored in the bit position information 94b. It is generated by the cell mat address calculation unit 95.

  By using this transposition memory 90, data bits are stored simultaneously in the Y direction, and then read out the data bits aligned in the X direction. The data DTA can be converted into word parallel and bit serial address unit data DTA and stored in the memory cell mat 30.

  When data is read from the memory cell mat 30 and transferred to the internal system bus 7, the data transfer direction is reversed, but the same as when data is written to the operation memory cell mat of the transposition memory 90. Information to be accessed in the memory cell mat 30 at the time of data reading is stored in each register of the control register 94, and a bit indicating data reading is set in the read / write direction register 94d. Data in units of addresses of the memory cell mat 30 is read from the memory cell mat 30 and stored sequentially in the transposition memory 90 from the start position in the Y direction. Next, the data read from the memory cell mat 30 in the word parallel and bit serial form is converted to word serial and bit parallel data by sequentially reading the data from the transposition memory 90 from the head position in the X direction. can do.

  FIG. 31 is a diagram illustrating an example of a configuration of a memory cell included in the transposition memory 90. The memory cell included in transposition memory 90 is a dual port SRAM cell. In FIG. 31, transposed memory cells include load P-channel MOS transistors PQ1 and PQ2 that are cross-coupled and drive N-channel MOS transistors NQ1 and NQ2 for data storage that are cross-coupled. This transposed memory cell is provided with an inverter latch (flip-flop element) as a data storage element similarly to a normal SRAM cell, and the flip-flop element stores complementary data in storage nodes SN1 and SN2.

  Transposed memory cell further includes N channel MOS transistors NQA1 and NQ2 coupling storage nodes SN1 and SN2 to bit lines BLA and / BLA, respectively, in response to a signal potential on word line WLA, and a signal potential on word line WLB. In response, N channel MOS transistors NQB1 and NQB2 coupling storage nodes SN1 and SN2 to bit lines BLB and / BLB are included. Word lines WLA and WLB are arranged orthogonally, and bit lines BLA and / BLA are arranged orthogonally to bit lines BLB and BLB.

  A first port (transistors NQA1, NQA2) constituted by the word line WLA and the bit lines BLA and / BLA and a second port constituted by the word line WLB and the bit lines BLB and / BLB (transistors NQB1, NQB2) Are respectively coupled to separate transposition memory I / Fs. That is, for example, the first port (word line WLA, bit line BLA, / BLA) is used as an interface port with the internal system bus, and the second port (word line WLB and bit line BLB, / BLB). Are used as ports for accessing the memory data bus. As a result, data can be accessed by performing row and column conversion in the transposed memory.

  As described above, according to the seventh embodiment of the present invention, a transposition circuit for exchanging rows and columns of transfer data is used between the system bus and the memory data bus, and the internal system bus and the memory cell are used. Multi-bit width data can be transposed at the time of data transfer between mats, and the number of accesses to the memory cell mat required at the time of data transfer to the memory cell mat can be reduced. Time can be shortened and high-speed processing is realized.

  The semiconductor signal processing apparatus according to the present invention can be applied not only to general image or sound data processing but also to a semiconductor signal processing apparatus that performs a large amount of data processing. In the field of digital signal processing, the semiconductor signal processing apparatus according to the present invention is applicable. The device can be widely applied.

  1 Semiconductor signal processing system, 2 system LSI, 3 external system bus, 4 SDRAM, 7 internal system bus, 8 host CPU, 11 interrupt controller, 13 DMA controller, 14 external bus controller, FB1-FBh basic operation block, 20 main Arithmetic circuit, 21 Microinstruction memory, 22 Controller, 23 Work data memory, 24 System bus I / F, 30 Memory cell mat, 31 ALU, 32 ALU interconnection switch circuit, 30A, 30B Memory cell mat, 35 Arithmetic processing Unit, 38, 38A, 38B read / write circuit, 40 instruction decoder, 41 program counter, 42 PC value calculation unit, 43 general purpose register group, 45 control register group, 46, 46A, 46B address calculation unit 47, 47A, 47B address register group, 70 start address register, 72 end address register, SAW sense amplifier and write driver, 74 row decoder, 76 input / output circuit, 78 column decoder, 80 switching circuit (MUX), 85 transposition circuit, 90 transposition memory, 91 system bus transposition memory I / F, 92 memory cell mat transposition memory I / F, 93 internal register group, 94 control register group, 95 memory cell mat address calculation unit.

Claims (8)

A memory array having a plurality of memory cells arranged in a matrix by a plurality of word lines and a plurality of bit lines and divided into a plurality of entries having a plurality of memory cells in each bit line direction, and the memory array A main arithmetic circuit including a plurality of arithmetic circuits arranged one by one corresponding to each entry of
A microinstruction memory that stores microinstructions, and an arithmetic processing unit that includes a control circuit that performs operation control on the memory array and the plurality of arithmetic circuits according to microinstructions from the microinstruction memory;
A processing device that issues a calculation instruction to the calculation processing unit;
The processor performs control to store the microinstruction in the microinstruction memory prior to issuing the operation instruction to the arithmetic processing unit,
Each of the plurality of arithmetic circuits performs arithmetic processing using data stored in a predetermined memory cell of a corresponding entry in accordance with a microinstruction stored in the microinstruction memory, and executes the arithmetic processing. A semiconductor signal processing device having a register for storing information indicating whether or not to perform.   The micro-instruction includes a load / store instruction for instructing data transfer between the memory array and the plurality of arithmetic circuits, and an arithmetic instruction for instructing arithmetic contents to be executed by the plurality of arithmetic circuits. Item 14. A semiconductor signal processing device according to Item 1. A register circuit for storing a start address and an end address of a series of operation instructions of the microinstruction memory;
The semiconductor signal processing apparatus according to claim 1, wherein the microinstruction includes a loop instruction that repeatedly executes an instruction between the start address and the end address. The memory array is a multi-port memory cell divided into a plurality of mats, and each of the memory cells has a write port and a read port;
The semiconductor signal processing device according to claim 1, wherein the control circuit controls writing and reading in parallel with respect to each of the memory mats. A plurality of the main arithmetic circuits are provided in parallel,
The control circuit is arranged corresponding to each main arithmetic circuit,
The semiconductor signal processing device further includes:
Further provided with a transfer control circuit arranged corresponding to each main arithmetic circuit, for transferring data between the external memory and the corresponding main arithmetic circuit,
The transfer control circuit executes an operation and data transfer between the external memory in a pipeline manner so that the data transfer with the external memory is performed in another main arithmetic circuit when the operation is performed in one main arithmetic circuit. 2. The semiconductor signal processing apparatus according to claim 1, wherein the operation of the corresponding main arithmetic circuit is controlled as described above. The main arithmetic circuit further includes:
An internal data bus having a bit width smaller than the plurality of bit widths;
An entry selection circuit for simultaneously selecting bits at the same position of the plurality of entries according to a first address signal;
And a bit selection circuit configured to simultaneously select and connect the same number of bits as the bus width of the internal bus among the simultaneously selected bits of the plurality of entries according to a second address signal. Item 14. A semiconductor signal processing device according to Item 1. A system bus for exchanging data with the outside of the main arithmetic circuit;
The semiconductor signal processing apparatus according to claim 1, further comprising a switching circuit that selects one of data from the system bus and data from the control circuit and transfers the data to the memory array. The semiconductor signal processing device further includes:
A system bus for transferring data with the outside of the main arithmetic circuit;
The transposition circuit is further disposed between the system bus and the main arithmetic circuit and rearranges the given multi-bit data, and the transposition circuit stores bits of the same data in the same entry of the entry. The semiconductor signal processing apparatus according to claim 1, wherein multi-bit data is transposed from the system bus.

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