JP2004021645A - Image processing device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up image processing in an image processing device using a SIMD (Single Instruction Multiple Datastream) type processor. <P>SOLUTION: This control method comprises supplying each of a plurality of pixel data to be processed in parallel to each corresponding element processor PE (S11 and S12); judging whether a specified operation is to be executed or not based on the pixel data supplied to each PE (S13); and performing a control so as to execute the operation only when the specified operation is judged to be executed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus that outputs an image formed based on image data represented by a digital signal, and a control method therefor.
[0002]
[Prior art]
Currently, there is an image processing apparatus called a so-called MFP (Multi Function Printer) configured as a complex machine of image processing apparatuses such as a copier, a facsimile machine, a printer, and a scanner. For example, Japanese Patent Application Laid-Open No. 8-315126 discloses a technique for processing an image at high speed by using a SIMD (Single Instruction Stream Multiple Data Stream) type processor in the image processing unit of the MFP. ing.
[0003]
By the way, image processing used in the MFP increases the compression ratio by correcting binarized pixel data to black (or white) by correcting isolated white (or black) pixels with reference to a plurality of surrounding pixels. It includes adaptive processing represented by so-called isolated point removal processing that reproduces an image as an easy-to-view image.
[0004]
[Problems to be solved by the invention]
However, when the image processing as described above is performed on all pixels over the entire image, this is realized by parallel processing by a single software using a SIMD type arithmetic processing unit. There is a problem that the processing speed is inferior to that realized.
[0005]
Accordingly, an object of the present invention is to increase the speed of image processing in an image processing apparatus using a SIMD type processor.
[0006]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object, for example, an image processing apparatus of the present invention comprises the following arrangement. That is, an image processing apparatus that includes a parallel processing unit that causes each of a plurality of element processors to execute the same instruction in parallel, and performs predetermined image processing using the parallel processing unit, and a plurality of pixel data to be processed in parallel Are supplied to the corresponding element processor, based on pixel data supplied to each element processor, determination means for determining whether or not to perform a specific operation in the image processing, and the operation And a control means for controlling to execute the calculation only when it is determined that the process is to be executed.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0008]
(Functional configuration of image processing apparatus)
FIG. 1 is a block diagram functionally showing the configuration of the image processing apparatus according to the embodiment.
[0009]
In FIG. 1, an image processing apparatus 1 is configured to include the following five units. That is, the five units are an image data control unit 100, an image data input unit 101 for inputting image data, an image memory control unit 102 for controlling image memory for storing images and writing / reading image data, and an image An image processing unit 103 that performs image processing such as processing and editing on the data, and an image writing unit 104 that writes the image data on transfer paper or the like.
[0010]
Each of the above units is configured around the image data control unit 100. That is, the image data input unit 101, the image memory control unit 102, the image processing unit 103, and the image writing unit 104 are all connected to the image data control unit 100 and are subjected to overall control by the image data control unit 100. Hereinafter, functions of these units will be described.
[0011]
The processing performed by the image data control unit 100 is, for example, as follows.
[0012]
Interface processing with control data bus (described later), overall system control, local bus control processing (ROM, RAM, access control processing for starting system controller described later), interface processing with image data input unit 101, image Interface processing with the memory control unit 102, interface processing with the image processing unit 103, interface processing with the image writing unit 104, network control processing, and the like.
[0013]
The processing performed by the image data input unit 101 is as follows, for example.
[0014]
Interface control processing with system controller (described later), reading processing of original reflected light by optical system, conversion processing to electric signal using CCD (Charge Coupled Device), A / D converter Digitization processing, shading correction processing (processing for correcting illuminance distribution unevenness of the light source), processing for correcting density characteristics of a reading system, rasterization processing of PDL image data input via a network, and the like.
[0015]
The processing performed by the image memory control unit 102 is as follows, for example.
[0016]
Interface control processing with a system controller (described later), writing / reading processing to / from a memory unit, access control processing to a memory module (arbitration processing of memory access requests from a plurality of units), etc.
[0017]
The processing performed by the image processing unit 103 is as follows, for example.
[0018]
Color conversion processing, color correction processing, MTF correction processing, smoothing processing, arbitrary scaling processing in the main scanning direction, density conversion (γ conversion processing: corresponding to density adjustment key), simple binarization processing, various pseudo halftone processing , Dot placement phase control processing (jaggy correction), isolated point removal processing, image area separation processing (color determination, attribute determination, adaptive processing), density conversion processing, and the like.
[0019]
The processing performed by the image writing unit 104 is as follows, for example.
[0020]
Image signal pulse control processing, parallel data and serial data format conversion processing, etc.
[0021]
(Hardware configuration of image processing device)
Next, a hardware configuration of the image processing apparatus according to the present embodiment will be described. This image processing apparatus constitutes an MFP (digital multifunction peripheral).
[0022]
FIG. 2 is a block diagram illustrating an example of a hardware configuration of the image processing apparatus according to the embodiment.
[0023]
In the block diagram of FIG. 2, the image processing apparatus 1 includes a reading unit 201 that reads an image original, a PDL processing unit 202, an image data control unit 203, an image processing processor 204, an image forming unit (engine) 205, and a memory control unit. 206, a memory module 207 that stores image data and the like, a network control unit 214, and a working memory 216. In addition to this, the image processing apparatus 1 includes a system controller 209, a ROM 210, a RAM 211, and an operation panel 212 via a control data bus 208. The image processing apparatus 1 is also connected to a personal computer 215 via a network 213.
[0024]
Of the above-described configurations, the image processor 204 processes the digital image data created based on the image so that it can be visualized and output, and can implement a plurality of image forming operations in a programmable manner. The configuration of the image processor 204 will be described in detail later.
[0025]
The image data control unit 203 collectively manages image data transmission between a data bus for transmitting image data and a processing unit used for image processing by the image processor 204. Specifically, data transmission management is performed among the reading unit 201, the PDL processing unit 202, the image processing processor 204, the memory control unit 206, the image forming unit 205, and the network control unit 214.
[0026]
Here, the relationship between each component described above and each unit 100 to 104 shown in FIG. 1 will be described.
[0027]
The reading unit 201 and the PDL processing unit 202 implement the function of the image data input unit 101 in FIG. The image data control unit 203, the system controller 209, the ROM 210, the RAM 211, the operation panel 212, and the network control unit 214 implement the functions of the image data control unit 100. Further, the image processing processor 204 and the working memory 216 realize the function of the image processing unit 103. The image forming unit 205 realizes the function of the image writing unit 104, and the memory control unit 206 and the memory module 207 realize the function of the image memory control unit 102.
[0028]
The system controller 209 operates based on a control program stored in the ROM 210 connected via the control data bus 208, and uses the RAM 211 as a work memory. Further, the reading unit 201, the PDL processing unit 202, the image data control unit 203, the image processing processor 204, the image forming unit 205, the memory control unit 206, the network control unit 214, and the operation panel 212 are respectively connected via a control data bus 208. The operation is controlled by the system controller 209.
[0029]
Next, the operation content of each component will be described.
[0030]
A reading unit 201 that optically reads an original is composed of a lamp, a mirror, a lens, and a light receiving element, and condenses reflected light of lamp irradiation on the original on the light receiving element (for example, CCD) by the mirror and the lens. Image data converted into an electrical signal in the light receiving element is converted into a digital signal and then output (transmitted) from the reading unit 201.
[0031]
The PDL processing unit 202 rasterizes the PDL image data output from the personal computer 215 connected to the network 213 into a bitmap image. When the PDL image data input via the network 213 is input to the PDL processing unit 202 via the network control unit 214, the PDL processing unit 202 performs rasterization based on the input PDL image data and generates a bitmap. Output (send) image data. As described above, the image data output (transmitted) from the reading unit 201 and the PDL processing unit 202 is input (received) to the image data control unit 203.
[0032]
The image data control unit 203 outputs the image data received from the reading unit 201 and the PDL processing unit 202 to the image processing processor 204 or the memory control unit 206.
[0033]
The operation when the image data is output to the image processor 204 by the image data control unit 203 is as follows.
[0034]
The image processor 204 performs predetermined image processing on the input image data using the working memory 216, and outputs the data after the image processing to the image data control unit 203 again. The image data input to the image data control unit 203 is output to the memory control unit 206 and stored in the memory module 207 via the memory control unit 206.
[0035]
After the processing of the image data for one screen by the image processor 204 is completed and the processed data for one screen is stored in the memory module 207, the memory control unit 206 reads the image data from the memory module 207, The read image data is output to the image forming unit 205 via the image data control unit 203, whereby a print output is obtained. The image data read from the memory module 207 can be output to the network control unit 214 via the image data control unit 203 and can be output to the personal computer 215 via the network 213.
[0036]
The operation when the image data is output to the memory control unit 206 by the image data control unit 203 is as follows.
[0037]
Image data input from the image data control unit 203 to the memory control unit 206 is stored in the memory module 207. Next, the memory control unit 206 reads out the stored image data from the memory module 207 and outputs it to the image processing processor 204 via the image data control unit 203. The image processor 204 processes the input image data, and the processed image data is stored again in the memory module 207 via the image data control unit 203 and the memory control unit 206. After the processing of the image data for one screen by the image processor 204 is finished and the processed data for one screen is stored in the memory module 207, the memory control unit 206 reads the image data for the memory module 207, The read image data is output to the image forming unit 205 via the image data control unit 203, whereby a print output is obtained. Alternatively, the image data read from the memory module 207 can be output to the network control unit 214 via the image data control unit 203 and output to the personal computer 215 via the network 213.
[0038]
In the above operation example, the image processor 204 performs processing on the image data output from the reading unit 201 and the PDL processing unit 202, and the processed image data for one screen is stored in the memory module 207. Thus, the processed image data is read out and output to the image forming unit 205 or the network control unit 214. However, the processed image data is stored before the storage of the processed image data for one screen is completed. You may control to read from the memory module 207 and to start a process.
[0039]
Next, another operation example will be described. This is performed without storing image data in the memory module 207.
[0040]
Image data received by the image data control unit 203 from the reading unit 201 and the PDL processing unit 202 is output from the image data control unit 203 to the image processing processor 204. The image processor 204 performs predetermined processing on the input image data and outputs it to the image data control unit 203. The image data input from the image processor 204 to the image data control unit 203 is output to the image forming unit 205 and the network control unit 214 via the image data control unit 203.
[0041]
As an example of the operation when storing one screen of processed image data in the memory module 207, when a plurality of copies of one original are copied, the reading unit 201 is operated only once and is read by the reading unit 201. There is a method in which the stored image data is stored in the memory module 207 and the stored image data is read out a plurality of times. As an operation example in which the image data is not stored in the memory module 207, there is a case where only one original is copied. Since the processed data for the read image data may be directly output to the image forming unit 205, it is not necessary to access the memory module 207.
[0042]
Note that the overall operation of the present apparatus is controlled by the system controller 209 based on processing to be performed by the image processing apparatus input from the operation panel 212. From the operation panel 212, the type of processing (copying, transmission, image reading, printing, etc.), the number of processings, and the like can be input.
[0043]
FIG. 3 is a diagram showing a configuration of the image processor 204 shown in FIG.
[0044]
As shown in FIG. 3, the image processing processor 204 includes FIFO memories 301 and 307 and an arithmetic processing unit 300. The arithmetic processing unit 300 includes a control processing unit 305, an external memory interface 306, and the SIMD processor 308 shown in FIG. As shown in the figure, the SIMD processor 308 includes an input register 302, an output register 304, and a SIMD type data operation processing unit 303. SIMD is to execute a single instruction in parallel for a plurality of data. In this embodiment, the data operation processing unit 303 is configured by 128 element processors (PEs). This configuration will be described in detail later.
[0045]
The FIFO memory 301 is a first-in / first-out memory having a capacity of one raster (7168 pixels) of image data input from the reading unit 201 or the PDL processing unit 202, and writing and reading are controlled independently. . Image data input via the data bus A (see FIG. 2) of the image data control unit 203 is input to the FIFO memory 301 and has the same number of registers as the number of PEs (128) of the data arithmetic processing unit 303. The image data is divided into 56 pieces and inputted to the configured input register 302 as 128 pieces of image data.
[0046]
The image data input from the FIFO memory 301 to the input register 302 is output to the data arithmetic processing unit 303 and the external memory interface 306. The image data input to the data operation processing unit 303 is subjected to predetermined processing by the data operation processing unit 303, and the processed image data is output to the output register 304 and the external memory interface 306. The external memory interface 306 can output intermediate data processed by the data arithmetic processing unit 303.
[0047]
Similar to the input register 302, the output register 304 is configured with the number of registers equal to the number of PEs included in the data operation processing unit 303. The output image data of the output register 304 is input to a FIFO memory 307 having a capacity for one raster of image data. The FIFO memory 307 is a first-in / first-out memory in which writing and reading are controlled independently of each other. The image data signal output from the FIFO memory 307 is output to the image data control unit 203 via the data bus B (see FIG. 2).
[0048]
Further, the SIMD processor 308 and the external memory interface 306 are connected to the control processing unit 305 connected to the control data bus 208 shown in FIG. The control processing unit 305 supplies instructions to the PEs of the data operation processing unit 303, determines the status of each PE, controls the memory connected to each PE, input / output of data to / from the registers, and controls the external memory interface 306. Data control between the internal memory or register of the SIMD processor 308 and the working memory 216 is performed. Note that the control processing unit 305 and the SIMD processor 308 can independently execute different processes.
[0049]
Next, the configuration of the control processing unit 305 and the arithmetic processing unit 300 will be described in detail with reference to FIG.
[0050]
As shown in FIG. 4, the control processing unit 305 includes a control processor 401, a program memory 402 in which a program for controlling operations of the control processor 401 and the SIMD processor 308 is stored, and a data memory 403.
[0051]
On the other hand, the SIMD processor 308 is composed of, for example, 128 PEs (PE0 to PE127) 404 as described above. As shown in FIG. 4, each PE of PE0 to PE127 determines whether or not to perform an arithmetic operation of an 8-bit arithmetic unit (ALU) 405, a general-purpose register 406 composed of 16 8-bit registers, and an ALU. A mask register 407 for controlling the data, a PE register 408 for storing data during the operation, an output register 409, an input register 410, and a memory 411 having a capacity of 2 Kbytes.
[0052]
Each of the ALU 405 and the PE register 408 is mutually connected to the same component in the adjacent PE, and is configured to be able to input and output data. The output register 409 and the input register 410 are also connected to the same constituent element of the adjacent PE, and operate as a 128-stage shift register. The connection configuration of the input register 410 in all the PEs operating as the 128-stage shift register corresponds to the input register 302 in FIG. Similarly, the connection configuration of the output registers 409 in all the PEs operating as the 128-stage shift register corresponds to the output register 304 in FIG.
[0053]
The memory 411 in each PE is connected to the working memory 216 via the external memory interface 306 and the data bus C (see FIG. 2).
[0054]
Note that the external memory interface 306 and the ALU 405, general-purpose register 406, mask register 407, PE register 408, output register 409, input register 410, and memory 413 constituting the PE are each set of data between arbitrary blocks in the PE. It has a configuration that allows input and output. For example, data input / output between the memory 411 and the PE register 408 and data input / output between the PE register 408 and the external memory interface 306 are possible.
[0055]
The supply of instructions to each PE is given to each PE with the same content from the control processor 401 via the instruction supply bus 413, and all PEs are controlled to perform operations according to the same instruction. By making the processing target data given to the PEs different, each PE is controlled to perform arithmetic processing on the different processing target data in parallel. For example, if the contents of 128 pixels in one raster of image data are arranged in the PE register 408 for each pixel and the arithmetic processing for the PE register 408 is performed with the same instruction code, the processing time is shorter than sequential processing for each pixel. Thus, the processing result for 128 pixels can be obtained.
[0056]
As described above, since the configuration is such that input / output can be performed between adjacent PEs, the calculation result of each PE in the ALU 405 and the content of the PE register 408 are the same as the calculation result of the adjacent PE and of the ALU 405 and the content of the PE register 408. It can be obtained by the referred arithmetic processing. Furthermore, the memory 411 of each PE, the input register 410, the output register 409, the PE register 408, the mask register 407, and the general-purpose register 406 are connected to the control processor 401 via the memory / register access bus 414, and the memory and Input / output of each register data is controlled by the control processor 401.
[0057]
The control processor 401 can input / output control data to / from the system controller 209 shown in FIG. 2 via the control data bus 208. Further, the program memory 402 and the data memory 403 that control the operation of the control processor 401 can be accessed from the system controller 209 via the control data bus 208, and processing performed by the image processing unit 300 by the system controller 209. The program memory 402 that controls the operation of the control processor 401 can be rewritten according to the contents.
[0058]
(Image processing overview)
FIG. 5 is a flowchart illustrating an overview of image processing executed by the image processing apparatus according to the embodiment. A program corresponding to this flowchart is stored in the program memory 402 in the control processing unit 305, and is executed by the control processor 401 and the SIMD processor 308.
[0059]
The image signal of 1 raster 7168 pixels subjected to shading correction by the reading unit 201 is divided into 128 pixels equal to the number of PEs of the SIMD processor 308 and processed.
[0060]
Therefore, first, the control processor 401 inputs the image signal read by the CCD by the reading unit 201 in FIG. 2 as an 8-bit image signal to the FIFO memory 301 of the image processor 204 through the image data control unit 203. And stored in the working memory 216 via the input register 302 and the external memory interface 306 (step S1).
[0061]
Next, logarithmic conversion from the luminance signal to the density signal is performed (step S2). Next, density conversion processing for density adjustment is performed on the logarithmically converted density data in accordance with an input from the operation panel 212 (step S3). Similarly, spatial filter processing is performed on the image signal in accordance with the designation of the image mode or the like set based on the input of the operation panel 212 (step S4).
[0062]
Subsequently, in step S5 where pseudo halftone processing is performed, error diffusion processing, tissue dither processing, simple binarization processing, and the like are selectively performed. Step S6 is a step for performing isolated point removal processing, and processing for the binarization result when the simple binarization processing is selected in the previous pseudo halftone processing.
[0063]
Further, other processing is executed as necessary. In step S7, the image signal for one raster binarized as a signal for compressing a binary signal such as a recording signal or JBIG is stored in the external working memory 216. Then, the process for one raster 7168 pixels is completed. If the above raster processing is repeated for 4960 rasters (step S8), the A4 size 1 page processing is completed.
[0064]
(Contents of isolated point removal processing)
Next, the isolated point removal process in step S6 described above will be described with reference to FIGS.
[0065]
First, the image signal of 1 raster 7168 pixels binarized by the pseudo halftone process in step S5 is stored in the working memory 216 via the external memory interface 306 as a 1-bit image signal. The external working memory 216 always stores image signals for five rasters, and new raster signals are sequentially updated as the processing ends.
[0066]
FIG. 6 is a diagram schematically illustrating image data to be processed. In the figure, reference numeral 503 denotes a raster image signal C to be processed, 502 is data B before one raster, 504 is data D after one raster, 501 is data A before two rasters, and 505 is two rasters. The subsequent data E is shown. The image signal of each raster of 7168 pixels is shown in the form of being divided into 56 bands for every 128 pixels corresponding to the number of PEs.
[0067]
That is, the band C-1 indicates 128 pixels (0th to 127th pixels) from the head of the raster to be processed now, and the band C-2 is the 128th to 255th pixels as the second band of the raster to be processed now. Represents the data. Now, if each pixel data of these 128 pixels in 1 band is processed by each of 128 sets of PEs for each pixel, PE0 is in charge of the 128th pixel belonging to band 2 as shown in FIG. The 129th pixel is assigned to PE1, the 130th pixel is assigned to PE2,.
[0068]
An example of the reference pixel position with respect to the target pixel position * for the isolated point removal process performed in step S6 is shown in FIG. Each PE is a process of referring to a total of 25 pixels including the two pixels before and after the PE arrangement direction and the two rasters before and after the raster direction, with the pixel of interest * at the center.
[0069]
Referring to band 2 shown in FIG. 7 as an example, when the 130th pixel in charge of PE2 is the target pixel, the 128th pixel to the 132nd pixel are referred to centering on this 130th pixel. In this case, since all the pixels to be referred to belong to the same band 2, there is no particular difficulty in referring to the data.
[0070]
Next, consider a case where the 129th pixel handled by PE1 is the target pixel. In this case, the 127th to 131st pixels are referred to centering on the 129th pixel. However, among these pixels, the 127th pixel belongs not to band 2 but to band 1, so that the pixel data cannot be directly referred to. This problem also occurs when the pixel assigned to PE0, PE126, and PE127 is the target pixel. Therefore, when the pixel in charge of PE0, PE1, PE126, and PE127 located at the end is the target pixel, it is necessary to perform processing by a program that is partially different from the processing for other PEs.
[0071]
FIG. 9 is a diagram schematically showing a part of the memory 411 of each PE in the isolated point removal processing.
[0072]
In the figure, A _n (1) indicates that pixel data handled by PEn in band 1 (ie, A-1) is stored in the internal memory 411 in the nth PE (PEn). A _n (2) indicates that pixel data handled by PEn in band 2 (ie, A-2) is stored in the internal memory 411 in the nth PE (PEn). Here, for example, when n is 2, A _n (2) represents the pixel of band 2 of the raster data A that PE2 is in charge of, that is, the data of the 130th pixel in 7168 pixels. Here, as described with reference to FIG. 7, since one raster is divided into 56 bands and processed, image data for 5 rasters is stored in an area of 56 * 5 (= 280) bytes in the internal memory 411 of each PE. Will be stored.
[0073]
FIG. 10 is a flowchart showing the isolated point removal process for one raster image signal in step S6.
[0074]
First, a variable (band counter) m indicating a band being processed is initialized to 1, and pixel data of band m (that is, band 1) of raster data E handled by PEn is E. _n (M), ie E _n (1) is input from the external working memory 216 to the input register 410 assigned to the corresponding PEn (step S11). Here, it is assumed that the raster image data A, B, C, and D in FIG. 7 has already been input when the preceding four rasters are processed.
[0075]
Next, in step S12, the E-th raster data E of the band (m + 1) next to the band m to be processed from now on. _n (M + 1) is input to the internal memory 411. That is, the image data required for processing by the PE 126 and PE 127 at the rear end of the band C currently processed is input here. Only when m = 56, there is no image data required for processing by the rear end PE, but up to band 55, the band data after that for the band to be processed is stored in the internal memory 411 of each PE for five rasters. Will be stored. Since these data are sequentially stored for one raster for each band, all the image data of one band before the PE0 and PE1 at the front end except for the band of m = 1 are also required for each PE. It is held in the internal memory.
[0076]
In step S13, the data C of all 128 pixels to be processed by each PE _n For (m), it is checked whether all 128 pixels have the lowest value (ie, 0) or all 128 pixels have the highest value (ie, 1). The isolated point removal process is a process of inverting the binary data at the target pixel position when the binary data at the target pixel position is different from the binary data of all the 24 surrounding pixels. If 128 consecutive binary data on the same raster to be processed are all 0's or all 1's, it is assumed that there will be no isolated points in these 128 data regardless of the state of other adjacent pixels. Is done.
[0077]
Therefore, in such a case, it is determined that the current pixel of interest is not a pixel subject to isolated point removal, and steps S14 to S14 are operations that depend on a predetermined number of surrounding pixels with respect to the pixel of interest as described below. The process of S22 is skipped, and the target pixel value C in step S23 _n (M) is directly output to the external working memory 216 as a processing result.
[0078]
If there is a pixel to be processed in step S13, the process proceeds to step S14.
[0079]
In step S14, the data P13, P23, P43, P53 stored in the internal memory 411 of the responsible PE among the reference pixel positions shown in FIG. _n (M), B _n (M), D _n (M), E _n The binary data of (m) is added and stored in the PE register PER.
[0080]
Step S15 is a determination step for executing different processing depending on the number of each PE, and the SIMD processor 308 can perform comparison with each PE number on a single program. Can be executed.
[0081]
As described above, for PEs other than PE0, PE1, PE126, and PE127 located at the end, the process proceeds from step S15 to step S16, and other peripheral pixel data are sequentially added.
[0082]
That is, the pixel data A for which the previous pixel is in charge of the nth PE. _n-1 (M), B _n-1 (M), C _n-1 (M), D _n-1 (M), E _n-1 (M) is added to PER. Similarly, pixel data A for which the previous pixel is in charge of the nth PE _n-2 (M), B _n-2 (M), C _n-2 (M), D _n-2 (M), E _n-2 (M) is added to PER. Similarly, the pixel data A assigned to the PE after one pixel for the nth PE _{n + 1} (M), B _{n + 1} (M), C _{n + 1} (M), D _{n + 1} (M), E _{n + 1} (M) is added to PER. Further, similarly, the pixel data A assigned to the PE after 2 pixels for the nth PE. _{n + 2} (M), B _{n + 2} (M), C _{n + 2} (M), D _{n + 2} (M), E _{n + 2} (M) is added to PER.
[0083]
Since the SIMD processor 308 can access the registers and the like that are handled by three pairs of PEs separated from each other on the left and right, all 124 pairs of PEs PE2 to PE126 can execute the same step S16.
[0084]
Next, processing step S17 of PE0 branched at step S15 will be described. FIG. 11 is a flowchart showing the process performed in step S17.
[0085]
The PE of n-1 with respect to PE0 is PE127. If the image data of the previous pixel is processed in step S16, the PE127 in the same band is in charge, not the pixel data in charge of the PE127 in the previous band. The pixel will be referred to. Therefore, PE0 is the pixel data of the previous band handled by the PE of the previous pixel in step S17a, that is, A _n-1 (M-1), B _n-1 (M-1), C _n-1 (M-1), D _n-1 (M-1), E _n-1 (M-1) is added to PER. Similarly, pixel data of the previous band handled by the PE of the previous two pixels, that is, A _n-2 (M-1), B _n-2 (M-1), C _n-2 (M-1), D _n-2 (M-1), E _n-2 (M-1) is added to PER. The subsequent step S17b is an operation for the pixel after the first pixel and the pixel after the second pixel, and performs the same processing as in step S16 described above.
[0086]
Next, processing step S18 of PE1 branched in step S15 will be described. FIG. 12 is a flowchart showing the process performed in step S18.
[0087]
The PE of n-2 with respect to PE1 is PE127, and if the image data two pixels before is processed in step S16, the pixel in charge of PE127 in the same band will be referred to. In step S18a, PE1 is the pixel data of the previous band, A _n-2 (M-1), B _n-2 (M-1), C _n-2 (M-1), D _n-2 (M-1), E _n-2 (M-1) is added to PER. In the subsequent step S18b, calculation is performed on the pixel data one pixel before, one pixel after, and two pixels after, similarly to step S16 described above.
[0088]
Next, processing step S19 of PE 126 branched in step S15 will be described. FIG. 13 is a flowchart showing the process performed in step S19.
[0089]
The PE of n + 2 with respect to PE126 is PE0, and if the image data after two pixels is processed in step S16, the pixel data handled by PE0 in the same band will be referred to. Therefore, in step S19a, the PE 126 is pixel data after one band, which is handled by the PE after two pixels, that is, A _{n + 2} (M + 1), B _{n + 2} (M + 1), C _{n + 2} (M + 1), D _{n + 2} (M + 1), E _{n + 2} Add (m + 1) to the PER. In the subsequent step S19b, the calculation for the pixel data after one pixel, one pixel before, and two pixels before is performed in the same manner as in step S16 described above.
[0090]
Next, processing step S20 of PE127 branched in step S15 will be described. FIG. 14 is a flowchart showing the process performed in step S20.
[0091]
The PE of n + 1 with respect to PE127 is PE0, and if the image data after two pixels is processed in step S16, the pixel data handled by PE0 in the same band will be referred to. Therefore, in step S20a, the PE 127 is pixel data after one band, which is handled by the PE after two pixels, that is, A _{n + 2} (M + 1), B _{n + 2} (M + 1), C _{n + 2} (M + 1), D _{n + 2} (M + 1), E _{n + 2} Add (m + 1) to the PER. Similarly, pixel data after one band for which PE after one pixel is in charge, that is, A _{n + 1} (M + 1), B _{n + 1} (M + 1), C _{n + 1} (M + 1), D _{n + 1} (M + 1), E _{n + 1} Add (m + 1) to the PER. In the subsequent step S20b, the calculation for the pixel one pixel after, one pixel before, and two pixels before is executed in the same manner as in step S16 described above.
[0092]
After the processing according to each PE number is finished, each PE register holds a value obtained by adding binary data of 24 pixels around the pixel of interest. Therefore, in step S21, each target pixel data C _n Whether (m) is isolated from the surrounding pixel data, that is, the target pixel C _n When only (m) is 1 and all the surrounding 24 pixels are 0 (PER = 0), or the target pixel C _n If only (m) is 0 and the surrounding 24 pixels are all 1 (PER = 24), it is determined whether or not it is true.
[0093]
When an isolated point is detected in step S21, the process proceeds to step S22, and the target pixel data C _n Invert (m) from 0 to 1 or from 1 to 0. Next, in step S23, the target pixel data C _n (M) is output. Here, the target pixel data C stored in the internal memory 411 is displayed. _n Even if (m) is an isolated point, this value is not rewritten, and only the processing result is inverted and output.
[0094]
A series of processing in steps S12 to S23 is repeated until the number of bands is reached (step S24), and one raster processing is completed.
[0095]
In step S25, every time processing for one raster is completed, the oldest raster data stored in the internal memory 411 assigned to each PE, that is, the A data is updated with the B data. Is updated with C data, C data is updated with D data, and D data is updated with E data. Thus, when the next raster is processed, new E raster data is sequentially input for each band in steps S11 and S12.
[0096]
According to the above processing, in step S13, it is determined whether or not there is a pixel to be subjected to isolated point removal in the 128 pixel data to be processed in parallel. The isolated point removal process for the pixel is omitted. Therefore, the processing speed can be increased.
[0097]
(Contents of logarithmic conversion process)
FIG. 15 is a flowchart showing the logarithmic conversion process in step S2. Similarly to the isolated point removal process described above, the logarithmic conversion process also divides 7168 pixels per raster into 56 bands for each 128 pixels, and 128 band data is processed in parallel.
[0098]
First, the band counter m is set to 1 (step S31), and the luminance signal A _n (M) is input from the external working memory 216 to an arbitrary register in charge of each PE (step S32).
[0099]
Luminance signal A _n (M) can take an 8-bit value from the brightest value 255 to the darkest value 0, but generally in logarithmic conversion processing, the brightest value 255 is converted to 0 and the darkest value 0 is converted to 255 uniquely. To do. In the present embodiment, a luminance signal converted into raster data as PDL image data is input from the PDL unit 202 to the SIMD processor 308. In general, however, the white portion of the background in the PDL image and the black solid in the figure. An image or the like has a luminance value of 255 or 0 in a wide range.
[0100]
Therefore, 128 image signals A to be processed by all PEs in step S33 for such image signals. _n When it is detected that (m) is all 0 or 255, the process proceeds to step S35 and the luminance signal A is uniquely determined. _n The value obtained by inverting the bit of (m) is the density value D. _n As (m), the process proceeds to step S36. If there is a pixel having an 8-bit intermediate value in step S33, the process proceeds to step S34, and a logarithmic conversion process is performed as usual. As a normal logarithmic conversion method, for example, a luminance value A _n Method of performing polynomial approximation calculation using (m) as a variable, luminance value A _n There are known a conversion method based on a broken line approximation of several points by comparing (m) with a threshold, an LUT conversion method using an internal memory, and the like. In step S34, any method may be used.
[0101]
In step S36, the density value D _n (M) is output to the external working memory 216 as a processing result. The above process is repeated 56 times (step S37), and the logarithmic conversion process for one raster of 7168 pixels is completed.
[0102]
According to such a process, in particular, for a PDL image signal, since it is a simple process in step S35 in most cases, the logarithmic conversion process can be processed at a very high speed.
[0103]
(Contents of pseudo intermediate processing)
FIG. 16 is a flowchart showing the pseudo halftone process in step S5.
[0104]
In this pseudo halftone process, as in the above-described isolated point removal process and logarithmic conversion process, one raster of 7168 pixels is divided into 56 bands for every 128 pixels, and band data of 128 pixels is processed in parallel.
[0105]
First, the band counter m is set to 1 (step S41), and the density signal A _n (M) is input from the external working memory 216 to an arbitrary register in charge of each PE (step S42). Density signal A _n (M) can take an 8-bit value from the brightest value 0 to the darkest value 255, but generally in the pseudo halftone process, the brightest value 0 is set to 0 and the darkest value 255 is set to 1, so that it is uniquely binarized. Is done. In this embodiment, an image signal converted into raster data as PDL image data is input from the PDL unit 202 to the SIMD processor 308. In general, a white portion of the background in the PDL image, a black solid image in the figure, etc. And has a density value of 255 or 0 in a wide range.
[0106]
Therefore, 128 image signals A to be processed by all the PEs in step S43 for such image signals. _n If it is detected that (m) is all 0 or 255, the process proceeds to step S45, where the 8-bit density signal A is uniquely determined. _n The MSB of (m) is converted into 1-bit binary data D _n (M), and the process proceeds to step S46. If there is a pixel having an 8-bit intermediate value in step S43, the process proceeds to step S44, and the normal pseudo halftone process is executed. As a method of this pseudo halftone processing, for example, a systematic dither method, a random number dither method, an error diffusion method and the like are known. In step S44, any method may be used.
[0107]
In step S46, the binarized data D _n (M) is output to the external working memory 216 as a processing result. The above process is repeated 56 times (step S47), and the logarithmic conversion process for one raster of 7168 pixels ends.
[0108]
According to such a process, since it is a simple process in step S45 in most cases especially for a PDL image signal, the pseudo halftone process can be processed extremely quickly over one page. .
[0109]
Here, an example in the case of binarized data of the density signal is shown, but it is of course applicable to other multilevel data, for example, 2-bit 4-level or 3-bit 8-level multilevel processing. In this case, it goes without saying that the upper 2 bits or 3 bits of the input signal can be obtained as the multilevel signal for the input signal 255, respectively.
[0110]
(Other embodiments)
The present invention can also be applied to a smoothing process similar to the isolated point removal process described above.
[0111]
In addition, in the smoothing process or the like, when the correction process is performed on the target pixel with reference to the surrounding pixels of the target pixel, the value is evaluated only for the 128 pixels to be processed in the above-described embodiment, and thereafter It is determined whether or not to execute the specific calculation. However, according to the purpose of the processing, for example, the above determination may be performed in consideration of the state of 128 pixels before one adjacent raster. .
[0112]
In addition, the present invention can be applied to, for example, spatial filter processing that is processing for a multilevel image signal.
[0113]
For example, in the case of a 3 × 3 spatial filter, when at least all the three raster image signals to be referenced are 0 or all 255, the processing result of every spatial filter is uniquely 0 or 255. Also, for example, in the case of a Laplacian filter, Laplacian is calculated, and when the value is 0 for all PEs, it is determined that the target image signal has no change and is a uniform image region, and calculation from that point is stopped. By doing so, it is possible to omit unnecessary processing thereafter. Therefore, in this case as well, for PDL images, the processing speed can be increased as in the above-described embodiment.
[0114]
The present invention can also be applied to black character processing in color image processing.
[0115]
Black character processing refers to processing for determining whether a pixel is black and whether it constitutes a part of a character and configuring a recording signal with, for example, a single black color according to the determination result. In this process, whether or not each pixel signal is black is determined in advance. If all the pixels handled by the PEs of SIMD operating in parallel are not black, the subsequent character determination process is performed. Is unnecessary. In general, the area of black characters constituting one page is 10% or less at most, so in this case as well, by applying the present invention, all the pixels in charge of each PE operating in parallel are all black. Only when the determination is made, the subsequent character determination process needs to be performed, so that the black character process can be performed at a very high speed.
[0116]
Further, in the above-described embodiment, it is determined whether or not to perform a specific calculation related to the image processing inside each image processing to be applied. In addition, it may be determined whether or not to execute specific, and each image processing may be operated based on the determination result. In this case, it is not necessary to bother to perform a process for determining whether or not to execute a specific calculation in each image process, and further, it is possible to speed up the entire image process.
[0117]
Although the embodiments of the present invention have been described in detail above, the present invention comprises a single device even when applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.). You may apply to an apparatus (for example, a copying machine, a facsimile machine, etc.).
[0118]
In the present invention, a software program (a program corresponding to at least one flowchart of FIG. 10 (including FIGS. 11 to 14), FIG. 15 and FIG. 16) that realizes the functions of the above-described embodiments. This includes a case where the object is also achieved by supplying the system or apparatus directly or remotely, and reading and executing the supplied program by the computer of the system or apparatus.
[0119]
Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. That is, the scope of the claims of the present invention includes the computer program itself for realizing the functional processing of the present invention.
[0120]
In this case, the program may be in any form as long as it has a program function, such as an object code, a program executed by an interpreter, or script data supplied to the OS.
[0121]
Examples of the storage medium for supplying the program include a flexible disk, an optical disk (CD-ROM, CD-R, CD-RW, DVD, etc.), a magneto-optical disk, a magnetic tape, and a memory card.
[0122]
In addition, the program supply method includes a mode in which the program of the present invention is acquired by file transfer via the Internet.
[0123]
In addition, the program of the present invention is encrypted, stored in a storage medium such as a CD-ROM, distributed to users, and a user who clears predetermined conditions is allowed to acquire key information for decryption via the Internet, By using the key information, an encrypted program can be executed and installed in a computer.
[0124]
In addition to the functions of the above-described embodiments being realized by the computer executing the read program, the OS or the like running on the computer based on an instruction of the program may be a part of the actual processing or All the functions are performed, and the functions of the above-described embodiments can be realized by the processing.
[0125]
Furthermore, after the program read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion board or The CPU or the like provided in the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.
[0126]
【The invention's effect】
According to the present invention, it is possible to increase the speed of image processing in an image processing apparatus using a SIMD type processor.
[Brief description of the drawings]
FIG. 1 is a block diagram functionally showing a configuration of an image processing apparatus according to an embodiment.
FIG. 2 is a block diagram illustrating an example of a hardware configuration of the image processing apparatus according to the embodiment.
FIG. 3 is a diagram illustrating a configuration of an image processor in the embodiment.
FIG. 4 is a diagram illustrating a configuration of a control processing unit and an arithmetic processing unit in the embodiment.
FIG. 5 is a flowchart illustrating an outline of image processing executed by the image processing apparatus according to the embodiment.
FIG. 6 is a diagram schematically illustrating image data to be processed.
FIG. 7 is a diagram for explaining handling of band data in the SIMD processor in the embodiment.
FIG. 8 is a diagram for explaining pixels referred to in isolated point removal processing;
FIG. 9 is a diagram schematically showing a part of the memory of each PE in isolated point removal processing.
FIG. 10 is a flowchart showing isolated point removal processing in the embodiment.
FIG. 11 is a flowchart illustrating a procedure for adding peripheral pixel data according to the embodiment.
FIG. 12 is a flowchart illustrating a procedure for adding peripheral pixel data according to the embodiment.
FIG. 13 is a flowchart illustrating a procedure for adding peripheral pixel data according to the embodiment.
FIG. 14 is a flowchart illustrating a procedure for adding peripheral pixel data according to the embodiment.
FIG. 15 is a flowchart illustrating logarithmic conversion processing according to the embodiment.
FIG. 16 is a flowchart illustrating pseudo halftone processing according to the embodiment.

Claims (6)

An image processing apparatus comprising parallel processing means for causing a plurality of element processors to execute the same instruction in parallel, and performing predetermined image processing using the parallel processing means,
Supply means for supplying each of the plurality of pixel data to be processed in parallel to the corresponding element processor;
Determination means for determining whether or not to perform a specific operation in the image processing based on pixel data supplied to each element processor;
Control means for performing control only when it is determined that the calculation should be performed;
An image processing apparatus comprising: 2. The determination unit according to claim 1, wherein when the pixel data supplied to each element processor is the highest value or the lowest value, the calculation is not to be executed. The image processing apparatus according to 1. The image processing according to claim 1, wherein the predetermined image processing includes at least one of isolated point removal processing, logarithmic conversion processing, pseudo intermediate processing, smoothing processing, spatial filtering processing, and black character processing. apparatus. The image processing apparatus according to claim 1, wherein the specific calculation is a calculation depending on a predetermined number of surrounding pixels with respect to the target pixel. A control method of an image processing apparatus comprising parallel processing means for causing each of a plurality of element processors to execute the same instruction in parallel, and performing predetermined image processing using the parallel processing means,
Supplying each of a plurality of pixel data to be processed in parallel to the corresponding element processor;
A determination step of determining whether or not to perform a specific operation in the image processing based on pixel data supplied to each element processor;
A control step for controlling to execute the calculation only when it is determined that the calculation should be performed;
A control method for an image processing apparatus, comprising: A program for controlling an image processing apparatus that includes a parallel processing unit that causes each of a plurality of element processors to execute the same instruction in parallel, and that performs predetermined image processing using the parallel processing unit,
Supplying each of a plurality of pixel data to be processed in parallel to the corresponding element processor;
A determination step of determining whether or not to perform a specific operation in the image processing based on pixel data supplied to each element processor;
A control step for controlling to execute the calculation only when it is determined that the calculation should be performed;
A program that executes

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