JP4989899B2 - Semiconductor processing unit - Google Patents

Description

  The present invention relates to a semiconductor arithmetic processing apparatus, and more particularly to a semiconductor arithmetic processing apparatus having a semiconductor memory divided into a plurality of entries and an arithmetic unit provided corresponding to each entry. More specifically, the present invention relates to a configuration for performing high-speed data transfer between arithmetic units in a semiconductor arithmetic processing apparatus with a small occupation area.

  With the recent widespread use of portable terminal devices, the importance of digital signal processing for processing a large amount of data such as sound and images at a high speed has increased. In this digital signal processing, a DSP (digital signal processor) is often used as a dedicated semiconductor device in general. In data processing such as filter calculation, there are many calculation processes that repeat product-sum calculation. Therefore, in general, in the configuration of the DSP, a multiplication circuit, an addition circuit, and an accumulation register are provided. If such a dedicated DSP is used, the product-sum operation can be executed in one machine cycle, and high-speed operation processing is possible.

  In addition, a SIMD (Single Instruction Stream Multiple Data Stream) type processor may be used in such applications as image processing for performing the same operation on a large amount of data. Many. In this SIMD type processor, a plurality of processor elements are provided, and the same arithmetic processing is executed for different data in each of the plurality of processor elements. Therefore, since a plurality of processor elements execute arithmetic processing in parallel, a large amount of data can be processed at high speed.

  In such a SIMD type processor, a configuration for storing different data at high speed for each processor element is disclosed in Japanese Patent Laid-Open No. 2002-207707. Allocates a plurality of data buses from the global processor to each processor element, and each processor element forms a signal for selecting one of the plurality of data buses according to the processor element number. Then, the data on the corresponding data bus is selected and stored in the A register in the processor element.In Patent Document 1, in the dither processing in the image processing, the threshold value corresponding to each pixel column is set for each column. Stored in the processor element and ratio to threshold in dither processing It aims to speed up the operation.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2001-84229) discloses a SIMD type processor for executing data processing in a flexible manner corresponding to different data bit widths. In the configuration disclosed in Patent Document 2, the processor element can be addressed, and data is transferred between the internal register of the addressed processor element and the data transfer bus. The processor element has a register of the register file and an arithmetic unit of the arithmetic unit array. By adjusting the number of registers in the register file according to the processing data bit width, Try to accommodate width changes.

Patent Document 3 (Japanese Patent Application Laid-Open No. 2002-207706) discloses a SIMD type processor aiming to perform summation calculation and peak detection with a small circuit scale. In the configuration shown in Patent Document 3, a multiplexer is provided corresponding to each of the processor elements of the processor element, and the multiplexer selects either the corresponding register of the register file or the seven adjacent columns of the corresponding register. . The multiplexer and the operation result data are transferred between the processor elements by this multiplexer.

  In this Patent Document 3, an arithmetic unit and a common data bus are provided, the common data bus is divided by a predetermined number unit, and the processor elements in each divided group are connected via the divided common data bus. Thus, the data is transferred, and calculations such as the sum value calculation and peak value calculation are executed at high speed.

  Japanese Patent Application Laid-Open No. 2001-202351 discloses a configuration for performing image data processing at high speed. In the configuration disclosed in Patent Document 4, a processor element can be addressed, the processor element is addressed in accordance with an address signal from a global processor, and data is stored in an arithmetic register in the processor element. Data transfer time is shortened by transferring data only to necessary processor elements.

Patent Document 5 (Japanese Patent Laid-Open No. 2003-186854) discloses a SIMD type processor for the purpose of monitoring internal data of a processor element from the outside. In the configuration disclosed in Patent Document 5, a mirror register for copying and storing the contents of the operation register is provided in each processor element, and the mirror register can be accessed from the outside by addressing the processor element. .
JP 2002-207707 A JP 2001-84229 A JP 2002-207706 A JP 2001-202351 A JP 2003-186854 A

  When the amount of data to be processed is very large, it is difficult to dramatically improve the performance even if a dedicated DSP is used. For example, if there are 10,000 sets of calculation target data, even if the calculation for each data set can be executed in one machine cycle, at least 10,000 machine cycles are required. Further, when using a DSP, the processing performance largely depends on the operating frequency, and therefore power consumption increases when priority is given to high-speed processing.

  In the SIMD type processor shown in Patent Document 1, a plurality of data buses extending from the global processor are provided, and in each processor element, the data bus is selected according to the processor element number, and the data of the selected data bus is registered. To store. As a result, threshold data corresponding to the pixel position of the pixel array is stored in the corresponding processor element, and filter processing is performed on a pixel matrix of a predetermined size. Data from the global processor is transferred and stored in parallel to the processor element to reduce the number of data transfer cycles.

In this Patent Document 1, in addition, when the arithmetic data of a processor element is transferred between different processor elements at the time of arithmetic processing, a multiplexer is used between processor elements (± 3 adjacent processor elements) in a predetermined range. A configuration for performing data transfer is shown. With this multiplexer, in each processor element, the data of the registers of the processor elements in different columns is selected to perform arithmetic processing. In order to make the selection path the same in each multiplexer during data transfer, the common data bus line to which the output line of the register of the register file of each processor element is coupled is different (one column register is selected by seven adjacent arithmetic units). For single use, adjacent column registers are connected to different bus lines). The connection between each multiplexer and the bus line of the common data bus is changed according to the connection between the output signal line of the register file and the common data bus. For this reason, the wiring for the multiplexer is complicated in each processor element, and the wiring is complicated. Further, the range in which the data of the register in a certain column can be transferred is fixed, and a configuration for transferring data between arbitrary processor elements is not shown.

  In Patent Document 2, in order to perform data transfer at high speed, a selection signal is given to each processor element, and data is written / read to / from the selected processor element. Also in this Patent Document 2, in addition to the configuration for writing / reading data to / from the register in the register file, a multiplexer is used in the same manner as in Patent Document 1 at the time of data transfer between processor elements in different columns. Therefore, there arises a problem that internal wiring is complicated, and it is difficult to transfer data between arbitrary processor elements.

  In the configuration disclosed in Patent Document 3, a data bus provided in common to processor elements is divided into a plurality of segments, and data is transferred between arithmetic units via each divided data bus. However, in this case, data transfer from one processor element to another processor element is executed in each divided data bus and processing such as sequential addition is performed, and each processor element performs effective arithmetic processing. It is not done in the cycle. Therefore, although it can be applied to processing such as total value calculation or peak value calculation, it is difficult to apply to a configuration in which calculation processing is performed by performing data transfer such as a normal copy operation. Also in Patent Document 3, the selection of the data line of the divided data bus is performed by using a multiplexer, and similarly to Patent Documents 1 and 2, there is a problem that internal wiring is complicated.

  In the configuration disclosed in Patent Document 4, the processor element is addressed, and the data of the global processor register is transferred to the register in the selected processor element. However, also in this Patent Document 4, data transfer between processor elements is performed using a multiplexer, the internal wiring is complicated as in Patent Documents 1 to 3, and the data transfer range is limited.

  In the configuration disclosed in Patent Document 5, a mirror register is simply provided in a register file, and data in the mirror register is monitored from the outside even during arithmetic processing. The data transfer between the processor elements is executed only by using a multiplexer as in the above-described Patent Documents 1 to 4, and the internal wiring is complicated, and the data transfer range is limited.

  In general, in a parallel arithmetic unit provided with a plurality of arithmetic units, when transferring data between arbitrary arithmetic units, it is necessary to arrange a plurality of data transfer wirings in the arithmetic units of each processor element according to the transfer distance. Yes, the wiring area increases. As a result, as shown in Patent Documents 1 to 5 described above, there are problems that the wiring occupation area between the register file and the arithmetic unit array becomes large and the wiring layout is complicated.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor arithmetic processing apparatus including a transfer circuit having a small occupation area that can transfer data between arbitrary arithmetic units at high speed.

  A specific object of the present invention is to provide a wiring area for transferring data between arithmetic units or between entries in a semiconductor processing unit in which a memory array is divided into a plurality of entries and an arithmetic unit is provided for each entry. It is to realize a transfer circuit that can be performed at a high speed without increasing the number of.

  A semiconductor arithmetic processing apparatus according to the present invention includes a memory array that is divided into a plurality of entries each having a plurality of memory cells, and arranged corresponding to these entries, each of which performs arithmetic processing on given data. And a transfer circuit for transferring data between a plurality of entries. The transfer circuit includes a plurality of transfer wiring paths that are arranged corresponding to the entries and each transfer data of the corresponding entry to one of a plurality of different different entries. Each transfer wiring path includes a data output unit that receives and outputs data of a corresponding entry, and a plurality of data transmission units coupled to different different entries. The transfer data is transferred from the data output unit toward the data transmission unit in each transfer wiring path.

  A transfer path is used for data transfer between entries. Each of the transfer paths includes data of a corresponding entry and a data transmission unit that transfers data to a plurality of different entries. Therefore, by selecting the data transmission unit in each transfer path, data transfer can be performed in parallel between a plurality of entries, and high-speed data transfer can be realized.

  In addition, by providing the data output unit and the data transmission unit separately in each transfer path, the wiring layout is simplified compared to a configuration in which the data transfer path is set using a multiplexer.

  Also, by sequentially transferring data between entries via this transfer path, data transfer between entries separated by an arbitrary distance can be realized.

[Overall configuration]
FIG. 1 is a diagram schematically showing an overall configuration of a processing system to which a semiconductor processing device according to the present invention is applied. In FIG. 1, the signal processing system 1 includes a system LSI 2 that realizes an arithmetic function for executing various processes, and an external memory connected to the system LSI 2 via an external system bus 3. The external memory includes a large-capacity memory 4, a high-speed memory 5, and a read-only memory (read-only memory: ROM) 6 that stores fixed information such as instructions at the time of system startup. The large-capacity memory 4 is composed of, for example, a clock synchronous dynamic random access memory (SDRAM), and the high-speed memory 5 is composed of, for example, a static random access memory (SRAM).

  The system LSI 2 includes basic operation blocks FB1 to FBh coupled in parallel to the internal system bus 7, a host CPU 8 that controls processing operations of these basic operation blocks FB1 to FBh, and input signals from the outside of the signal processing system 1. It includes an input port 9 that converts IN to internal processing data, and an output port 10 that receives internal output data given from the internal system bus 7 and generates output data OUT to the outside of the system. These input port 9 and output port 10 are constituted by, for example, library IP (intellectual property) blocks, and realize functions necessary for data / signal input / output.

  The system LSI 2 further receives an interrupt request from the basic operation blocks FB1 to FBh, notifies the host CPU 8 of the interrupt, and a CPU peripheral that performs a control operation necessary for each processing of the host CPU 8. 12, a DMA (direct memory access) controller 13 for transferring data to an external memory in accordance with a transfer request from the basic operation blocks FB1 to FBh, and an external system bus 3 in accordance with an instruction from the host CPU 8 or the DMA controller 13 The external bus controller 14 that performs access control to the memory 4-6 and the dedicated logic 15 that assists the data processing of the host CPU 8 are included.

  The CPU peripheral 12 has functions necessary for program and debugging purposes in the host CPU 8 such as a timer and serial IO (input / output). The dedicated logic 15 is configured by, for example, an IP block, and implements a necessary processing function using an existing function block. These functional blocks 9-15 are connected to the internal system bus 7. The DMA controller 13 is given a DMA request signal from the basic operation blocks FB1-FBh.

  Since basic operation blocks FB1-FBh have the same configuration, FIG. 1 representatively shows the configuration of basic operation block FB1.

  The basic arithmetic block FB1 includes a main arithmetic circuit 20 that performs arithmetic processing on actual data, a microinstruction memory 21 that stores microinstructions that specify arithmetic processing in the main arithmetic circuit 20, and a microinstruction from the microinstruction memory 21. Controller 22 for controlling the arithmetic processing of the main arithmetic circuit 20, the work data memory 23 for storing intermediate processing data or work data of the controller 22, and the data / data between the basic arithmetic block FB1 and the internal system bus 7. And a system bus interface (I / F) 24 for transferring signals.

  The main arithmetic circuit 20 is arranged corresponding to the memory cell mat 30 in which a plurality of memory cells are arranged in a matrix and divided into a plurality of entries, and the entry of the memory cell mat 30 is performed. An arithmetic unit (ALU) 31 and an ALU interconnection switch circuit 32 for setting a data transfer path between the arithmetic units 31 are included.

  Basically, each bit of multi-bit data is stored in one entry. The arithmetic unit (ALU) 31 receives the data bits from the corresponding entry in serial and performs arithmetic processing, and stores the processing result serially in a designated entry (for example, corresponding entry) of the memory cell mat 30.

  The inter-ALU interconnection switch circuit 32 switches the connection path of the arithmetic unit 31 and enables calculation of data of different entries. By storing different data in each entry and performing parallel arithmetic processing by the arithmetic unit 31, data processing can be performed at high speed.

  The controller 22 performs an operation according to the microprogram method in accordance with the microinstruction stored in the microinstruction memory 21. Work data necessary for this microprogram operation is stored in the work data memory 23.

  The system bus I / F 24 enables the host CPU 8 or the DMA controller 13 to access the memory cell mat 30, the control register in the controller 22, the microinstruction memory 21, and the work data memory 23.

Different address areas (CPU address areas) are allocated to the basic operation blocks FB1 to FBh. Similarly, different addresses (CPU addresses) are assigned to the memory cell mat 30 in the basic operation blocks FB1 to FBh, the control register in the controller 22, the microinstruction memory 21, and the work data memory 23, respectively. Therefore, different arithmetic processes can be executed in parallel by storing microinstructions having different contents in each of these basic arithmetic blocks FB1-FBh. In the basic operation blocks FB1 to FBh, microinstructions having the same operation content may be stored in the microinstruction memory 21 so that the same operation processing is performed on data in different address areas. The microinstruction memory 21 may store microinstructions but may store macroinstructions.

  According to each assigned address, the host CPU 8 and the DMA controller 13 identify the basic arithmetic block FBi to be accessed (any one of FB1 to FBh) and execute access to the basic arithmetic block to be accessed.

  FIG. 2 schematically shows a configuration of a main part of main arithmetic circuit 20 included in each of basic arithmetic blocks FB1-FBh shown in FIG. In FIG. 2, in the memory cell mat 30, memory cells MC are arranged in a matrix. This memory cell mat is divided into m entries ERY. The entry ERY has a bit width of n bits. In this memory cell mat 30, a word line is provided in common for m entries ERY, and a bit line is provided for each entry. Basically, one entry ERY is composed of memory cells MC aligned in this one column (bit line extending direction). Therefore, the number of entries ERY is determined by the number of bit lines of the memory cell mat.

  Corresponding to each entry ERY, an arithmetic unit (ALU) 31 is arranged in the arithmetic processing unit 35. The computing unit 31 can perform operations such as addition, logical product, coincidence detection (EXOR), and inversion (NOT).

  Data load (transfer of data from the memory cell mat 30 to the arithmetic processing unit 35) and store (data transfer from the arithmetic processing unit 35 to the memory cell mat 30) and between the entry ERY and the corresponding arithmetic unit 31 Store) to execute the arithmetic processing. Each bit of the multi-bit data is stored in the entry ERY.

  An ALU interconnection switch circuit 32 is arranged for the arithmetic unit 35. This ALU interconnection switch circuit 32 realizes data transfer between the arithmetic units 31.

  The arithmetic unit 31 performs arithmetic processing in a bit serial mode (a mode in which multi-bit data words are sequentially processed in units of bits). In the arithmetic processing unit 35, the data arithmetic processing is executed in a bit serial manner with respect to the data word and in an entry parallel manner in which the data of the plurality of entries ERY are processed in parallel.

  By changing the bit width of this entry ERY, data processing can be executed only by changing the number of operation cycles (range of address pointer) even when the word structure of the data word is different. Further, by increasing the number of entries m, a large amount of data can be collectively processed.

  Memory cell MC is formed of, for example, an SRAM cell having a CMOS (complementary metal-insulating film-semiconductor) structure, and performs data writing / reading at high speed. Further, by using an SRAM cell as the memory cell MC, it is not necessary to refresh the stored data in the memory cell mat 30, operation control is facilitated, and arithmetic processing can be executed at high speed.

  When the main arithmetic circuit 20 performs an operation, basically, data to be calculated is first stored in each entry ERY. Next, a certain digit of the stored data is read in parallel for all the entries ERY and transferred (loaded) to the corresponding arithmetic unit 31. In the case of binary operation, the same transfer is performed for bits of another data word in each entry ERY, and then 2-input operation is performed in each calculator 31. The calculation processing result is rewritten (stored) from the calculator 31 in a predetermined area in the corresponding entry ERY.

  FIG. 3 is a diagram schematically showing an example of the arithmetic operation in the main arithmetic circuit 20 shown in FIG. In FIG. 3, data words a and b having a 2-bit width are added to generate data word c. The entry ERY stores both data words a and b that form a set to be calculated.

  In FIG. 3, the calculator 31 for the entry ERY in the first row adds 10B + 01B, and the calculator 31 for the entry ERY in the second row calculates 00B + 11B. Here, “B” at the end indicates a binary number. In the calculator 31 for the entry ERY in the third row, the calculation of 11B + 10B is performed. Similarly, addition of data words a and b stored in each entry ERY is executed.

  The calculation is performed in a bit serial manner in order from the lower bit. In addition, the lower bit a [0] of the data word a is transferred to the corresponding arithmetic unit 31 in the entry ERY. Next, the lower bit b [0] of the data word b is transferred to the corresponding computing unit 31. The arithmetic unit 31 performs an addition operation using these given 2-bit data. This addition operation result a [0] + b [0] is written (stored) at the position of the lower bit c [0] of the data word c. That is, “1” is written at the position of bit c [0] in entry ERY in the first row.

  This addition processing is then performed for the upper bits a [1] and b [1], and the operation result a [1] + b [1] is written at the position of bit c [1].

  A carry may occur in the addition operation. This carry value is written at the position of bit c [2]. Thereby, the addition of the data words a and b is completed in all the entries ERY, and the result is stored as data c in each entry ERY. For example, when 1024 entries are prepared as entries, 1024 sets of data can be added in parallel.

  FIG. 4 is a diagram schematically showing the internal timing during the addition calculation process. Hereinafter, the internal timing of the addition operation will be described with reference to FIG. In this addition calculation process, a 2-bit adder (ADD) included in the calculator 31 is used.

  In FIG. 4, “Read” indicates an operation (load) or operation instruction for reading the data bit to be calculated from the memory cell mat 30 and transferring it to a corresponding arithmetic unit, and “Write” indicates an operation result of the arithmetic unit 31. Indicates an operation (store) or operation instruction for writing data to a corresponding bit position of a corresponding entry ERY.

  In the machine cycle k, the data bit a [i] is read from the memory cell mat 30, and in the next machine cycle (k + 1), the next operation target data bit b [i] is read (Read). To the adder (ADD).

  In the machine cycle (k + 2), the adder (ADD) of the arithmetic unit 31 performs addition processing of the read data bits a [i] and b [i]. In the machine cycle (k + 3), this addition result c [i] is written in the corresponding bit position of the corresponding entry.

  In the next machine cycles (k + 4) and (k + 5), the next operation target data bits a [i + 1] and b [i + 1] are read and transferred to the adder (ADD) of the arithmetic unit 31. In the machine cycle (k + 6), addition processing is performed by the arithmetic unit 31, and the addition result is stored in the bit position c [i + 1] in the machine cycle (k + 7).

  Transfer of data bits between the memory cell mat 30 and the arithmetic unit 31 requires one machine cycle, and the arithmetic unit 31 requires one machine cycle. Therefore, 4 machine cycles are required to add 1-bit data and store the addition result. The memory cell mat 30 is divided into a plurality of entries ERY, a set of data to be calculated is stored in each entry, and a calculation process is performed in a bit serial manner in the corresponding calculator 31. Although data operations require a relatively large number of machine cycles, if the amount of data to be processed is very large, high-speed data processing can be realized by increasing the parallelism of the operations. That is.

  For example, when the bit width of the data word to be operated is N, 4 · N machine cycles are required for the operation of each entry. The bit width of the data word to be calculated is about 8 to 64 bits. When the number of entries m is increased to, for example, 1024, for example, in the case of 8-bit data, 1024 operation results can be obtained in 32 machine cycles, and 1024 sets of data are processed sequentially. The processing time can be greatly shortened compared to.

  In addition, since the arithmetic processing is performed in the bit serial form and the bit width of the processed data is not fixed, it can be easily applied to various applications having various data configurations.

  FIG. 5 is a diagram schematically showing a control mode of the controller 22 shown in FIG. Corresponding to the controller 22, a register group 40 is provided. In this register group 40, pointer registers r0-r3 are provided. The addresses in the memory cell mat 30 of the data to be calculated are stored in these pointer registers r0-r3. The controller 22 generates an address for designating an entry in the main arithmetic circuit or an in-entry position according to the pointer stored in the pointer registers r0 to r3, and between the memory cell mat (30) and the arithmetic processing unit (35). Control data transfer (load / store). The controller 22 sets connection designation information between the arithmetic units (ALU) 31 in the arithmetic processing unit (35) when a transfer instruction is given from the microinstruction memory 21 according to the pointers of the pointer registers r0 to r3. To do.

[Configuration 1 of the computing unit]
FIG. 6 is a diagram schematically showing a configuration of the computing unit (31) shown in FIG. 1 and a configuration of a portion related to one computing unit. In FIG. 6, an arithmetic unit (ALU) 31 performs an arithmetic operation logic circuit 50 that performs a specified operation process, and data read from a corresponding entry or operation process result data of the arithmetic operation logic circuit 50 or a corresponding entry. An X register 54 for temporarily storing data to be transferred, a C register 56 for storing a carry or a borrow at the time of addition operation processing, and an M for storing mask data for designating prohibition of the arithmetic processing of the arithmetic operation logic circuit 50 Register 58 is included.

  A sense amplifier 62 and a write driver 60 are provided between the entry and the arithmetic unit. Sense amplifier 62 and write driver 60 are coupled to bit line pair BLP of the corresponding entry. Sense amplifier 62 amplifies data read from the memory cell of the corresponding entry, and transfers the amplified data to X register 54 via internal data transfer line 200. The write driver 60 buffers the data stored in the X register 54 and writes the data to the memory cell of the corresponding entry via the corresponding bit line pair BLP.

This arithmetic operation logic circuit 50 can execute operations such as addition (ADD), logical product (AND), logical sum (OR), exclusive logical sum (EXOR), inversion (NOT), etc. Is set by a control signal (ALU control) from the controller 22 shown in FIG. Based on the mask data stored in the M register 58, the arithmetic processing operation in the arithmetic unit 31 is selectively enabled / disabled. By using this calculation mask function, even when not all entries are used, it is possible to execute an operation only on valid entries and perform accurate processing. In addition, current consumption can be reduced by stopping unnecessary computations.

  The X register 50 is also connected to another arithmetic unit (ALU) via an inter-ALU connection circuit 65 included in the inter-ALU interconnection switch circuit 32. The configuration of the inter-ALU connection circuit 65 will be described in detail later. By the transfer function of the inter-ALU connection circuit 65, it is possible to realize an operation on data stored at various physical positions in the memory mat, and to increase the degree of freedom of the operation.

  FIG. 7 is a diagram showing a list of instructions for moving data between entries among ALU instructions.

  The instruction “ecm.mv.n # n” defines the movement amount in the data movement instruction (Move) with a numerical value #n. Therefore, with this instruction, in the data transfer between the X registers, the stored value of the X register of entry j + n is stored in the X register of entry j. As an example, the entry movement amount n takes an integer value ranging from 0 to 128, and data movement can be performed between entries at positions separated by a maximum of 128 bits.

  The instruction “ecm.mv.r rx” is an instruction for moving data between entries by the value stored in the pointer register rx. When this instruction is executed, the stored value of the X register of entry j + rx is transferred to the X register of entry j.

  In accordance with the ALU instruction, a connection path in the inter-ALU connection circuit 65 is set, and the arithmetic unit provided for each entry executes data transfer in parallel using the X register.

[Calculation configuration 2]
FIG. 8 is a diagram schematically showing another configuration of the arithmetic unit 31 used in the present invention. For the configuration of the arithmetic unit 31 shown in FIG. 8, one entry ERY in the memory cell mat has an even entry ERYe for storing even-address data bits A [2i] and an odd-address data T bit A [ 2i + 1] and an odd entry ERyo. By executing arithmetic processing in parallel on the data bits at the same address in the even-numbered entry ERYe and the odd-numbered entry ERYo, the processing speed is increased.

  In the arithmetic unit (ALU) 31, cascaded full adders 210 and 211 for performing arithmetic processing are provided as arithmetic processing units. Full adders 210 and 211 add the data bits applied to inputs A and B, respectively, and output the operation result to sum output S and carry output Co. Full adder 210 receives the data stored in C register 56 at carry input CIn. At the time of 1-bit operation, the carry of the C register 56 or the carry input Cin of the full adder 211 is given. In a 2-bit operation in which 2-bit processing is performed in parallel, the carry output Co of the full adder 210 is transmitted to the carry input Cin of the full adder 211. By switching the connections of the full adders 210 and 211, 2-bit parallel operation and 1-bit sequential processing can be executed.

The computing unit 31 is provided with an X register 54 for temporarily storing load data from the memory cell of the corresponding entry and temporarily storing a result in the middle of the operation. At the time of binary operation processing, when the first operation data bit is stored in the X register 54, the next (other) operation data bit is given from the entry of the memory cell mat directly corresponding to the operation unit 31. And the arithmetic processing is executed. The X register 50 is connected to another arithmetic unit (ALU) via an inter-ALU connection switch circuit, and can transfer data between different arithmetic units.

  The arithmetic unit (ALU) 31 further includes one of the data sets of the registers 54, 220, and 221 in accordance with the stored values of the XH register 220 and XL register 221 and the D register 222 for storing 2-bit data in parallel. A selector (SEL) 227 that selects 2 bits, a selection inversion circuit 217 that performs inversion / non-inversion operation on the 2 bits selected by the selector 227 in accordance with the storage bits of the F register 205, and data stored in the N register 207 and the V register 208 , Gates 223 and 224 for selectively outputting data bits from outputs S of full adders 210 and 211 are included.

  The 2-bit output of selective inversion circuit 217 is applied to inputs A of full adders 210 and 211, respectively. XH register 220 and XL register 221 transfer odd address bits of odd entry ERYo and even address bits of even entry ERYe via internal data lines 226 and 228, respectively. X register 54 is selectively connected to one of internal data lines 226 and 228 by switch circuits SWa and SWb according to a 2-bit / 1-bit operation.

  The N register 207 stores a constant value. The V register 208 stores a mask bit for controlling the interruption / connection of the transfer path of the gates 223 and 224.

  The input B of full adder 210 is coupled to internal data line 226, and the output of gate 223 receiving sum output S of full adder 210 is also connected to internal data line 226. Input B of full adder 211 is selectively connected to one of internal data lines 226 and 228 by switch circuits SWc and SWd. The data is added to the data bit gate 224 from the sum output S of the full adder 211. The output of gate 224 is selectively connected to one of internal data lines 226 and 228 in accordance with switch circuits SWe and SWf. These switch circuits SWa-SWf execute bit serial processing in units of 1 bit when performing 2-bit parallel division processing.

  Gates 223 and 224 execute designated arithmetic processing (perform data transfer operation) when the stored values of V register 208 and N register 207 are both “1”, and otherwise output high impedance. (Output high impedance state).

  A switch 225 provided for the carry input Cin of the full adder 211 and the carry output Co of the full adder 210 disconnects the carry output Co of the full adder 210 when performing arithmetic processing in units of one bit. The carry input Cin of the adder 211 is connected to the C register 56.

  In this computing unit 31, the X register 54, the XH register 220, and the XL register 221 have a function of performing data transfer with the corresponding registers of other entries.

  When the configuration of the second modification is used, one arithmetic unit is arranged corresponding to two entries. Therefore, in addition to 1-bit sequential processing, 2-bit parallel computation can be performed to execute high-speed processing, and the computing units 31 can be arranged with a margin in the computation processing unit.

  FIG. 9 is a diagram schematically showing internal connections of the ALU 31 at the time of 2-bit computation of the computing unit (31) shown in FIG. At the time of this 2-bit operation, particularly when multiplication is performed according to the secondary Booth algorithm, the X register 54 is coupled to the internal data line 226 via the switch circuit SWa. Switch circuit SWb is set to a state in which XL register 54 and internal data line 228 are disconnected.

  Switch circuit SWb disconnects input B of full adder 211 from internal data line 226. The switch 225 separates the carry output Co of the full adder 210 and the carry input Cin of the full adder 210. C register 56 is coupled to carry input Cin of full adder 210 via switch 225. The output of gate circuit 224 is coupled to internal data line 228 by switch circuit SWf.

  At the time of 2-bit operation, full adders 210 and 211 operate in parallel to add the data bits supplied from selective inversion circuit 217 to the data bits transferred from internal transfer lines 226 and 228, respectively, and the respective addition results Are output to internal data lines 226 and 228 via gates 223 and 224, respectively. Therefore, the addition result is calculated in parallel for the bits Aj [px] and Aj [px + 1]. Here, px and px + 1 are pointer values of the pointer register, and are the same word line address bits in the memory cell mat during 2-bit parallel operation.

  In the memory cell mat, data bits of even address A [2i] and odd address A [2i + 1] are stored in even entry ERYe and odd entry ERYo, respectively. A memory cell at the same bit position of the even-numbered entry ERYe and the odd-numbered entry ERYo is designated by the pointer of the pointer register rx. Accordingly, when the count value of the pointer register rx is incremented by 2 at the time of program execution, the bit position of the odd entry ERYo and the even entry ERYe is shifted upward by one bit. When an address for selecting the word line of the memory cell mat is generated based on the pointer of the pointer register rx, a configuration in which the pointer of the pointer register rx is incremented by 2 is realized by switching the word line.

  By providing two full adders 210 and 211 in the computing unit 31 and performing 2-bit addition, for example, in a multiplication operation according to the Booth algorithm, partial product generation in units of 2 bits and addition with the previous partial product are performed. Can do. Also, addition and subtraction can be executed in units of 2 bits, and operations can be executed in units of 1 bit. In division, the bit position of the dividend needs to be shifted right by one and subtraction is performed, and the calculation is performed in units of one bit. In order to realize this 1-bit operation, a switch 225 is provided.

  FIG. 10 is a diagram schematically showing an example of internal connections of the arithmetic unit 31 during a 1-bit arithmetic operation. When 1-bit operation is connected, X register 54 is connected to internal data lines 226 and 228 via switch circuits SWa and SWb, respectively. The output of the X register 54 is selected by the selector 227 according to the data stored in the D register 220. The connection between the switch circuits SWa and SWb is determined by a pointer px (pointer of the pointer register rx).

Addition / subtraction is realized by the selective inversion circuit 217 according to the stored bit value of the F register 205. The output of the selective inverter 217 is given to the input A of the full adder 211. The input B of the full adder 210 is connected to the internal data line 226. The carry output Co of the full adder 210 is separated from the carry input Cin of the full adder 210 by the switch circuit 225. Sum output S of full adder 210 is coupled to internal data line 226 via gate 223. The full adder 210 is not used for the addition operation. Carry input C of full adder 211
in is coupled to C register 56 via switch circuit 225. The input B of the full adder is selectively coupled to the internal data line 226 or 228 via the switch circuits SWc and SWd by the pointer px. The sum output S of the full adder 211 is selectively connected to the internal data lines 226 and 228 via the gate 224 and the switch circuits SWe and SWf.

  When the subtraction operation is performed by the two's complement addition operation, “1” is stored in the C register 56 as an initial value, and the bit value from the X register 54 is inverted by the selective inversion circuit 217. When the addition operation is performed, the C register 56 is cleared to “0” as an initial state.

  In the entry in the memory cell mat, data bits A [2i] and A [2i + 1] of continuous addresses are stored in the area connected to internal data lines 226 and 227, and X is transmitted via internal data lines 226 and 228. 2-bit data is transferred to the register 54 in parallel. By sequentially switching the value of the pointer px [0], it is possible to perform addition in a bit serial manner on the data bits of the entry of the address A [2i] and the entry of the address A [2i + 1].

  FIG. 11 is a diagram showing a list of instructions for performing data movement (move) between entries during 1-bit operation. The pointer register rn is used when data is moved between entries (between ALUs). The aforementioned pointer registers r0 to r3 are provided as candidate registers for the inter-entry data movement pointer register rn.

  The instruction “ecm.mv.n # n” is an instruction indicating that the value stored in the X register of entry a + n separated by a constant n is transferred to the X register of entry j.

  The instruction “ecm.mv.r rn” is an instruction indicating an operation in which the value of the X register of the entry j + rn separated from the stored value of the register rn is transferred to the X register of the entry j.

  The instruction “ecm.swp” is an instruction for instructing an operation for exchanging the stored values of the X registers of the adjacent entries j + 1 and j.

  FIG. 12 is a diagram showing a list of commands for instructing an operation of data movement between entries (move) in an arithmetic unit during a 2-bit operation. In the 2-bit operation, the instruction descriptor “ecm2” is used in place of the instruction descriptor “ecm”. When this instruction descriptor “ecm2” is designated, arithmetic processing in units of 2 bits is designated, and parallel data transfer is performed between the XH register and the XL register. To specify the transfer contents between the registers, the same instruction descriptors “mv.n # n”, “mv.r rn”, and “swp” as in the previous one-bit operation are used.

[Embodiment 1]
FIG. 13 schematically shows a wiring layout of the inter-ALU interconnection switch circuit according to the first embodiment of the present invention. FIG. 13 shows a wiring layout of inter-entry communication wirings having a set of movement amounts of ± 1, ± 2, and ± 4 as data movement amounts.

In FIG. 13, entries n + 13 to n-13 are shown. The data transfer wiring 300 includes an output unit 305 that receives and outputs data from corresponding entries, and data sending units XP1, XP2, and XP4, XN1, XN2, and XN4 to the transfer destination entries. The sending sections XP1, XP2, and XP4 are sending sections that transfer data for entries that are separated by +1, +2, and +4, respectively. The sending sections XN1, XN2, and XN4 are entries that are separated by -1, -2 and -4, respectively. It is a sending part which transfers data to. Accordingly, one data transfer wiring 300 is arranged extending over nine entries.

  The data transfer wiring 300 is arranged in a line in the direction intersecting the entry (second direction), and the data output unit 305 has one entry in the extending direction of the entry (first direction). They are arranged in an array so as to be displaced. In this data transfer wiring 300, the farthest data transmission unit corresponds to an entry that is separated by ± 4 entries, and the data transfer wiring 300 is aligned in the second direction every nine entries including itself. Arranged.

  By separately providing a data output unit that receives and outputs data from each entry and a data transmission unit that provides data to a transfer destination entry, by providing a plurality of data transmission units in one data transfer wiring 300, Other communication can be realized between a plurality of types of entries with one wiring. Further, the data transfer path can be efficiently wired by shifting the output part of the data from each entry by one transfer wiring 300 in the first direction. That is, as shown in FIG. 13, by arranging the parallelograms 320 in the rhombus shape having opposite sides having inclinations over nine entries in order in the second direction, the wiring layout is reduced and the inter-entry can be efficiently performed. Communication wiring can be arranged and wired.

  As described above, instead of individually arranging the wiring according to the data transfer amount, a single data transfer wiring 300 realizes a plurality of sets of data movement amounts, and the arithmetic unit corresponding to each entry selects By taking in the signal from the sending unit, data can be transferred in parallel in each entry, and the wiring layout area can be reduced. Further, by providing a plurality of sets of inter-entry data movement amounts, any inter-entry movement can be realized with a relatively small number of cycles.

  For example, when data is moved between ± 4 entries in one cycle, the sending sections XP4 and XN4 are selectively used. In this case, cyclic data movement as shown in FIG. 14 is realized. However, in FIG. 14, 2048 entries are provided in the memory cell mat.

  For example, when the entry 0 data is moved by +4 entries, the entry 044 is transferred to the X register that is used for the entry 2044. Here, + movement is set in a direction in which data is transferred to an entry with a small entry number. When the data of entry 2047 is moved by -4 entries, it is transferred to the X register of entry 3.

  Therefore, similarly to the data transfer between one adjacent entry, the data transfer to an entry separated by four entries can be realized in one machine cycle using the data transfer wiring 300. Therefore, for example, when transferring data to a position separated by three entries, two-entry movement and one-entry movement are performed in the same manner as in the case of sequentially transferring data using a shift register. Can be realized. Further, when transferring data to an entry that is 8 entries apart, the transfer between 8 entries is realized by repeating the 4-entry movement twice. By repeating this data transfer in the shift register mode, data communication between entries separated by an arbitrary distance (number of entries) is realized.

  By providing a larger number of sets of data movement amounts realized by one data transfer wiring 300 in accordance with the margin of the wiring layout area, data movement between any entry can be realized with a relatively small number of cycles.

FIG. 15 schematically shows a wiring layout of data transfer wiring 300 for entries 0-5 and 2044-2047 at the ends of the memory cell mat. This entry 0-
3, when data shift transfer of +1, +2, and +4 is performed from the data output end 305, it is necessary to shift data in the direction of entries 2045-2047. Therefore, in this case, the transfer path of each data transfer wiring 300 is wired from the entry end to the other end using the plus shift wiring 330p. As a result, plus-direction shift sending sections XP1, XP2 and XP4 can be arranged for the data output sections 305 of entries 0 to 3, respectively.

  On the other hand, in the data transfer wiring 300 provided for the entries 2045 to 2047 at the other end of the memory cell mat, it is necessary to return to the first entry 0 and transfer data when transferring data in the minus direction. For this reason, a minus shift wiring 330n is provided from the other end of the memory cell mat to one end, thereby realizing a data shift in the minus direction of each data transfer wiring 300. As a result, the transmission outputs XN1, XN2, and XN4 in the minus direction can be respectively arranged for the data output unit 305 provided for the entries 2045-2047. In each data transfer wiring 300, ± 1, Data transfer shifts of ± 2 and ± 4 can be realized.

  The data shift wirings 330p and 330n may be formed of wirings in a wiring layer different from the wirings constituting the transfer path 300. The sending sections XP1, XP2, and XP4 and XN1, XN2, and XN4 connected by the shift wirings 330n and 330p are respectively empty areas (triangular areas) at the bottom of the parallelogram area of the data transfer wiring 300. ).

  In any case, in the entries 0 to 2047, data can be moved in a ring shape, and data movement between any data entries can be realized in any direction.

  FIG. 16 schematically shows a configuration of inter-ALU connection circuit 65 shown in FIG. In the inter-ALU connection circuit 65, the X register 54, the XH register 220, and the XL register 221 of the arithmetic unit 31 are respectively coupled to transfer wiring bundles 340a, 340h, and 340l having an n-bit width. The n-bit width transfer wiring bundles 340a, 340h and 340l are bundles of data transfer wirings 300 from other entries, respectively. These transfer wiring bundles 340a, 340h and 340l are coupled to X register 54, XH register 220 and XL register 221 via connection portions 350a, 350h and 350l, respectively.

  On the other hand, X register 54, XH register 220 and XL register 221 are coupled to data transfer lines 300a, 300h and 300l through output nodes 305a, 305h and 305l, respectively. Each of these transfer wirings 300a, 300h, and 300l extends to the entry portion of the maximum data movement amount, and transfers data to other entries along the route. In the other entry, the data movement amount wiring is selected by the connection portions 350a, 350h and 350l.

  The configuration of the computing unit 31 is the same as the configuration of the computing unit shown in FIG. 8, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In these connection portions 350a, 350h, and 350l, it is necessary to select a corresponding entry according to the amount of data movement. In order to select another entry corresponding to this, a switching circuit is provided in each of the connection portions 350a, 350h, and 350l.

FIG. 17 is a diagram showing an example of the configuration of the switch circuit and related portions in the inter-ALU connection circuit 65. When transferring 1-bit data, the X register 54 is used. The XH register and the XL register are used during 2-bit data transfer. The configuration shown in FIG. 17 is provided for each of the X register, XH register, and XL register of the arithmetic units of other entries. However, in FIG. 17, only the configuration of the portion corresponding to the X register 54 is representatively shown to simplify the drawing.

  In FIG. 17, the inter-ALU connection circuit 65 generates a signal according to the signal on the corresponding data output wiring ECM_IN_k according to the selection signal ECM_EM_k (k = 1,... 256) of another entry, and the transfer. A selector 362 that selects one of the data transferred from the entry corresponding to the output signal of the switch circuit 360 according to the enable signal ECM_EN, and a trie that generates the output data ECM_OUT according to the data held in the X register 54 according to the transfer enable signal ECM_EN. A state buffer 364 is included. The tristate buffer 364 drives the output stage 305 (305a, 305h, 305l) of the data transfer wiring.

  Switch circuit 360 includes select switch gates PSQ256... PSQ1, NSQ1,... NSQ256 provided corresponding to each of the other entries. These selection switch gates PSQ256-PSQ1, NSQ1-NSQ256 select output signal ECM_IN_k on the corresponding data transfer wiring in accordance with entry selection signal ECM_EN_k, respectively, and internal node ND in accordance with the input signal on the corresponding data transfer wiring. Drive.

  These selective switching gates PSQ256-PSQ1, NSQ1-NSQ256 include N channel MOS transistors (insulated gate field effect transistors) NQ1 and NQ2 connected in series between internal node ND and the ground node, respectively. The gate of MOS transistor NQ1 receives transfer input signal ECM_IN_k from another corresponding entry, and the gate of MOS transistor NQ2 receives entry selection signal ECM_EN_k.

  Therefore, in the configuration of switch circuit 360 shown in FIG. 17, the data transfer wiring transfers data between entries at positions separated by a maximum of ± 256 entries. The intermediate transfer amount (data movement amount) provided in the middle of the data transfer wiring may be sequentially set as a power of 2.

  Switch circuit 360 further includes a P channel MOS transistor PQ1 for precharging internal node ND to the power supply voltage level in accordance with precharge instruction signal / ECM_PRC, an inverter IV1 for inverting a signal on internal node ND, and an output signal of inverter IV1 And a P channel MOS transistor PQ2 for driving internal node ND to the power supply voltage level, and an inverter IV2 for inverting the output signal of inverter IV1 and generating an output signal of switch circuit 360.

  MOS transistor PQ2 and inverter IV1 form a so-called “half latch”. Internal node ND is precharged to the power supply voltage level during precharging. Select switch gate PSQk or NSQk (k = 1-256) drives internal node ND to the ground voltage level when selected. Internal node ND is driven by a so-called open drain method using selection switch gates PSQ256-PSQ1 and NSQ1-NSQ256. Internal node ND is merely driven from the precharge voltage level to the ground voltage level, and data transfer can be performed at a high speed during data transfer. Each selection switch gate is composed of two transistors, and the layout area of the circuit can be reduced.

  The X register 54 is in a latch state in response to the rise of the clock signal CLKX (clock that determines the internal arithmetic processing cycle). Here, in FIG. 18, the waveform at the time of +1 shift operation is shown. That is, the entry number (i + 1) entry data is transferred to the entry number i entry, and data transfer is performed between adjacent entries.

  FIG. 18 is a timing chart showing the operation of the inter-ALU connection circuit shown in FIG. The operation of the inter-ALU connection circuit 65 shown in FIG. 17 will be described below with reference to FIG.

  In clock cycle # 1, no transfer operation is performed, and transfer enable signal ECM_EN is at the L level. In this state, selector 362 is set to select data from the corresponding entry, and tristate buffer 364 is in an output high impedance state. The X register 54 stores data D [i].

  In clock cycle # 2, transfer enable signal ECM_EN is set to an active H level. In response, selector 362 is set to a state for selecting the output signal of switch circuit 360, and tristate buffer 364 is activated. Thereby, the transfer output signal ECM_OUT is set to a state corresponding to the data D [i] according to the data D [i] held in the X register 54.

  When the transfer output signal ECM_OUT is determined, data is transferred from the output unit in the corresponding data transfer wiring, and accordingly, the data ECM_IN_i of each transfer data transmission unit is determined in each entry.

  At the time of transmission of this transfer output signal, precharge instruction signal / ECM_PRC is at L level, and switch circuit 360 is in a precharge state (entry selection signal ECM_EN_ + 1 is in an inactive state).

  In clock cycle # 2, in accordance with the fall of clock signal CLKX, precharge instruction signal / ECM_PRC becomes inactive at the H level, and in parallel with this, entry selection signal ECM_EN_ + 1 is activated. When the entry selection signal ECM_EN_ + 1 is activated, the output data ECM_IN_ + 1 transferred from the adjacent entry (i + 1) to the data transfer wiring via the tristate buffer 364 is already in a definite state. Therefore, the output data from the switch circuit 360 is in a state corresponding to the transfer data ECM_IN_ + 1.

  That is, when transfer data ECM_IN_ + 1 from adjacent entry (i + 1) is at the H level, MOS transistors NQ1 and NQ2 are both rendered conductive in selection switch gate PSQ1, and node ND is driven to the ground voltage level. In this state, the output signal of inverter IV1 is at the H level, MOS transistor PQ2 is in the off state, and node ND is maintained at the L level. On the other hand, when transfer data ECM_IN_ + 1 from the adjacent entry (i + 1) is at the L level, the selection switch gate PSQ1 is in a non-conductive state, and the node ND maintains the precharged voltage level. When node ND is at H level, the output signal of inverter IV1 is at L level, and accordingly MOS transistor PQ2 is turned on, and node ND is maintained at the power supply voltage level.

  Therefore, in the latter half cycle when clock signal CLKX of clock cycle # 2 falls, switch circuit 360 generates data corresponding to data D [i + 1] transferred from adjacent entry (i + 1) through data transfer wiring ECM_IN_ + 1. To the X register 54 via the selector 362.

  In the next clock cycle # 3, the X register 54 is in a latched state when the clock signal CLKX rises, and the held data is set in a state corresponding to the transfer data D [i + 1]. In clock cycle # 3, precharge instruction signal / ECM_PRC is again activated to the L level, and the output signal from inverter IV2 of switch circuit 360 again becomes the H level. Further, the transfer enable signal ECM_EN is set to the inactive L level, the tristate buffer 364 is set to the output high impedance state, and the selector 362 is set to a state of transferring data from the corresponding entry to the X register 54.

  The X register 54 is configured by a normal latch circuit or flip-flop, and may be set to latch the internal data when the clock signal CLKX rises. Even when the switch circuit 360 is in a precharged state and its output signal is initialized when the clock signal CLKX rises, the X register 54 is not affected by the initialization signal from the switch circuit 360. Certainly, the transfer data is latched.

  As shown in FIG. 18, in transfer cycle # 2, data D [i] from entry i is transferred as transmission data ECM_Out from the corresponding data output unit via the data transfer wiring, and in next clock cycle # 3. The data D [i + 1] transferred from the adjacent entry can be held in the X register 54.

  Note that the amount of data movement between entries is not limited to data movement between adjacent entries, and data movement between up to 256 entries can be performed by one transfer operation.

  When the data transfer movement amount between entries is different from the data movement amount (for example, ± 1, ± 2, and ± 4... ± 256) set in the data transfer wiring, this transfer cycle is repeated (data in the shift register mode). By performing (transfer), data transfer between entries separated by an arbitrary distance (for example, communication with an entry separated by an odd number of entries such as entry +257) can be realized. Thereby, data transfer between arbitrary entries can be realized with a small number of cycles.

  Further, in the data transfer between the entries, each entry performs data transfer in parallel and takes in data, thereby realizing efficient data transfer.

  Further, the switch circuit 360 drives an internal node precharged by an open drain method, so that the number of transistors of the switch circuit 360 can be reduced and data transfer can be performed at high speed. In addition, one data transfer wiring corresponds to data movement between a plurality of entries, and the wiring area can be reduced.

[Embodiment 2]
FIG. 19 shows a configuration of the inter-ALU interconnection switch circuit according to the second embodiment of the present invention. FIG. 19 also shows the configuration of the inter-ALU connection circuit arranged corresponding to one entry. The inter-ALU connection circuit 65 shown in FIG. 19 differs from the inter-ALU connection circuit 65 shown in FIG. 17 in the following points. That is, a selector 370 that receives data read from the corresponding entry and data held in the X register 54 is provided between the X register 54 and the tristate buffer 364. When the transfer load enable signal ECM_LD_EN is activated, the selector 370 selects the data read from the corresponding entry and supplies it to the tristate buffer 364. When the transfer load enable signal ECM_LD_EN is inactivated, the selector 370 selects the data output from the X register 54 and supplies it to the tristate buffer 364.

  The other configuration of the inter-ALU connection circuit 65 shown in FIG. 19 is the same as the configuration of the inter-ALU connection circuit 65 shown in FIG. 17, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 20 is a timing chart showing a data transfer operation of the inter-ALU interconnection circuit shown in FIG. FIG. 20 also shows a timing chart at the time of data transfer from the adjacent entry (i + 1) to the entry i. The data transfer operation of the ALU interconnection circuit shown in FIG. 19 will be described below with reference to FIG.

  In clock cycle # 1, precharge instruction signal / ECM_PRC is in an active state at an L level, while transfer enable signal ECM_EN and transfer load enable signal ECM_LD_EN are in an inactive state at an L level. The selector 360 is set to select data from the corresponding entry, and the selector 370 is set to select the output data held in the X register 54. Switch circuit 360 is in a precharge state, and node ND is at the power supply voltage level.

  In clock cycle # 2, data is read from the corresponding entry. This reading is executed in the same manner as the bit serial calculation described in FIG. That is, a word line is selected according to the address pointer in the memory cell mat, then the sense amplifier is activated, and the data in the selected memory cell is transferred toward the arithmetic unit (load instruction is executed).

  In clock cycle # 2, and in parallel with data reading, transfer enable signal ECM_EN and transfer load enable signal ECM_LD_EN are set in an active state in synchronization with the rise of clock signal CLKX. Precharge instruction signal / EMC_PRC is in an active state. Accordingly, data read from the corresponding entry is selected by selector 370, amplified by tristate buffer 364, and data corresponding to read data D [i] is output from the corresponding entry as transfer output data ECM_OUT. Is done.

  Next, in clock cycle # 2, in synchronization with the fall of clock signal CLKX, precharge instruction signal / ECM_PRC is set to an inactive state, and entry selection signal ECM_EN_ + 1 is set to an active state. Accordingly, the switch circuit 360 is enabled, and the data D [i + 1] transmitted from the adjacent entry (i + 1) to the input unit ECM_IN_ + 1 via the data transfer wiring is selected. At this time, the selector 362 is set to select the output signal of the switch circuit 360 in accordance with the transfer enable signal ECM_EN, and the data corresponding to the data D [i + 1] from the switch circuit 360 via the selector 362 is Transferred to the X register 54.

  When clock signal CLKX falls to L level in clock cycle # 2, X register 54 enters a through state and takes in the applied data. In clock cycle # 3, when clock signal CLKX rises to H level, X register 54 latches the fetched data, and the retained data is determined as data D [i + 1].

  In this case, therefore, data read from the memory cell mat and inter-entry communication are performed in clock cycle # 2. As a result, the operation of once holding the transfer data in the X register 54 becomes unnecessary, and the number of clock cycles required for inter-entry communication can be reduced.

As described above, by bypassing the X register 54, transfer data is generated according to the data from the corresponding entry, and transferred to the data output unit of the data transfer wiring path.
A cycle for storing transfer data in a register is not required, and high-speed communication between entries can be realized.

  The entry designation signal ECM_EN_k, the entry transfer instruction signal ECM_EN, and the precharge instruction signal / ECM_PRC are generated according to the instruction stored in the program instruction (microinstruction memory) 21 from the controller 22 shown in FIG.

  As the configuration of the arithmetic unit, either the configuration shown in FIG. 8 including the X register, the XH register, and the XL register, or the configuration shown in FIG. 6 in which only the X register is provided for data transfer may be used. good. The configuration shown in FIG. 17 or FIG. 19 is provided for the register for data transfer in the arithmetic unit.

  Also in the configuration of the inter-ALU connection circuit according to the second embodiment, when data transfer is performed with an entry other than the communicable entry on one data transfer wiring, the data transfer operation is repeatedly executed. That is, by sequentially setting the transfer entry selection signal ECM_EN_ ± j to j and performing a data transfer cycle (operation in cycle # 2), the transfer data can be sequentially shifted and transferred to the target entry. Data communication between arbitrary entries can be realized.

  As described above, by using the communication function between the entries, the data stored in the memory cell mat can be shifted between the entries as in the case of using a valve shifter, for example. Data transfer operation similar to the data transfer that has been performed can be realized. By using this data transfer function, it is possible to execute data copy operations, calculations using adjacent pixel data in filter processing using a pixel matrix in image data processing, and the like at high speed.

  The present invention is applied to a semiconductor arithmetic processing unit in which a memory cell mat is divided into a plurality of entries, and an arithmetic unit is arranged corresponding to the entry, thereby transferring data at high speed with a small wiring layout area. It is possible to realize a multi-functional high-speed arithmetic processing device.

  This semiconductor arithmetic processing device is applied to processing a large amount of data such as image data or audio data, thereby realizing high-speed arithmetic processing when processing is performed using data between entries such as filter processing. be able to.

1 is a diagram schematically showing an overall configuration of a semiconductor processing unit to which an interentry transfer circuit according to the present invention is applied. FIG. FIG. 2 is a diagram schematically showing a configuration of a main arithmetic circuit shown in FIG. 1. FIG. 3 is a diagram schematically showing an arithmetic sequence in the main arithmetic circuit shown in FIG. 2. FIG. 3 is a diagram showing an internal timing of an arithmetic processing sequence in the main arithmetic circuit shown in FIG. 2. It is a figure which shows roughly the control aspect of the controller shown in FIG. It is a figure which shows an example of a structure of the calculator shown in FIG. FIG. 7 is a diagram showing a list of commands for performing data movement between entries when the arithmetic unit shown in FIG. 6 is used. It is a figure which shows schematically the other structure of the calculator shown in FIG. It is a figure which shows the connection at the time of 2-bit calculation of the calculator shown in FIG. It is a figure which shows the internal connection at the time of 1 bit calculation of the calculator shown in FIG. FIG. 9 is a diagram showing a list of instructions for designating data movement between entries using the main arithmetic unit shown in FIG. 8. FIG. 9 is a diagram showing a list of data movement instructions between entries when the arithmetic unit shown in FIG. It is a figure which shows roughly the wiring of the inter-ALU interconnection switch circuit according to Embodiment 1 of this invention. FIG. 14 is a diagram showing a list of register values at the time of data transfer of the X register in the wiring layout shown in FIG. 13. FIG. 14 schematically shows a data transfer path between entries at both ends of the memory cell mat in the wiring layout shown in FIG. 13. It is a figure which shows roughly the structure of the wiring connection of the inter-ALU interconnection switch circuit and arithmetic unit according to Embodiment 1 of this invention. FIG. 17 schematically shows a configuration of an ALU interconnection circuit 65 shown in FIG. 16. FIG. 18 is a timing chart showing an operation of the inter-ALU interconnection circuit shown in FIG. 17. It is a figure which shows roughly the structure of the connection circuit between ALUs (inter-entry transfer circuit) according to Embodiment 2 of this invention. FIG. 20 is a timing diagram showing an operation of the inter-ALU interconnection circuit shown in FIG. 19.

Explanation of symbols

  1 arithmetic processing system, 2 system LSI, FB1-FBh basic arithmetic block, 20 main arithmetic circuit, 30 memory cell mat, 31 arithmetic unit (ALU), 32 ALU interconnection switch circuit, 22 controller, 54 X register, 65 ALU connection circuit, 300 data transfer wiring, XP1, XP2, XP4, XN1, XN2, XN4 transfer data sending section, 320 unit wiring area, 330p, 330n wiring for shifting operation between memory cell entry ends, 305a, 305h, 305l Transfer data output unit, 340a, 340h, 340l Transfer wiring bundle, 350a, 350h, 350l Transfer data input unit, 360 switch circuit, 362 selector, 364 tristate buffer, PSQ256, PSQ1, NSQ1, NSQ256 selection Tchigeto, 370 selector.

Claims (5)

A memory array that is divided into a plurality of entries, each having a plurality of memory cells;
A plurality of arithmetic units arranged corresponding to the entries, each for performing arithmetic processing on given data; and
A transfer circuit for transferring data between the plurality of entries;
The transfer circuit includes:
A plurality of transfer wiring paths arranged corresponding to the entries, each of which transfers the data of the corresponding entry to one of a plurality of different entries, and each of the transfer wiring paths includes data of the corresponding entry Receiving the data output unit and a plurality of data sending units coupled to each of the different plurality of different entries, transfer data is transferred from the data output unit toward the data sending unit,
Wherein the plurality of transfer lines path is aligned in a second direction and in the first direction are arranged in a plurality of rows in the as one entry the data output unit is shifted a second direction, the semi-conductor processing apparatus. A memory array that is divided into a plurality of entries, each having a plurality of memory cells;
A plurality of arithmetic units arranged corresponding to the entries, each for performing arithmetic processing on given data; and
A transfer circuit for transferring data between the plurality of entries;
The transfer circuit includes:
A plurality of transfer wiring paths arranged corresponding to the entries, each of which transfers the data of the corresponding entry to one of a plurality of different entries, and each of the transfer wiring paths includes data of the corresponding entry Receiving the data output unit and a plurality of data sending units coupled to each of the different plurality of different entries, transfer data is transferred from the data output unit toward the data sending unit,
In the transfer circuit, a plurality of transfer wiring path sending units are arranged corresponding to one entry,
Each of the arithmetic units includes a register circuit,
The transfer circuit further includes:
Arranged corresponding to each of the entries, coupled to the transmission unit of the corresponding plurality of transfer wiring paths, selected one transmission unit according to the selection signal, and transmitted on the transfer wiring path of the selected transmission unit A switch circuit that generates a signal corresponding to the signal;
The data from the corresponding entry and the output data of the switch circuit are received, the output data of the switch circuit is transferred to the register circuit according to a transfer instruction, and the data from the corresponding entry is transferred to the register circuit according to a transfer non-instruction A selection circuit to transfer to,
The transfer data held from the register circuit in accordance with an instruction and a transmission circuit for transmitting the output of the corresponding transfer path, semiconductors processor. A memory array that is divided into a plurality of entries, each having a plurality of memory cells;
A plurality of arithmetic units arranged corresponding to the entries, each for performing arithmetic processing on given data; and
A transfer circuit for transferring data between the plurality of entries;
The transfer circuit includes:
A plurality of transfer wiring paths arranged corresponding to the entries, each of which transfers the data of the corresponding entry to one of a plurality of different entries, and each of the transfer wiring paths includes data of the corresponding entry Receiving the data output unit and a plurality of data sending units coupled to each of the different plurality of different entries, transfer data is transferred from the data output unit toward the data sending unit,
In the transfer circuit, a plurality of transfer wiring path sending units are arranged corresponding to one entry,
Each of the arithmetic units includes a register circuit,
The transfer circuit further includes:
A switch that is arranged corresponding to an entry, is coupled to a transmission unit of a plurality of corresponding transfer wiring paths, selects one transmission unit according to a selection signal, and generates a signal corresponding to the transmission signal of the selected transmission unit Circuit,
The data from the corresponding entry and the output data of the switch circuit are received, the output data of the switch circuit is transferred to the register circuit according to a transfer instruction, and the data from the corresponding entry is transferred to the register circuit according to a transfer non-instruction A first selection circuit to transfer to
A second selection circuit that receives the data held in the register circuit and the data from the corresponding entry, and transfers the data from the corresponding entry in accordance with the activation of the selection transfer instruction signal;
And a transmission circuit for transmitting the data applied from the second selection circuit in accordance with the transfer instruction to the output of the corresponding transfer path, semiconductors processor. The switch circuit is
A precharge element for precharging the internal node to a predetermined precharge voltage in accordance with the activation of the precharge instruction signal;
A plurality of selection switch gates provided corresponding to each of the plurality of sending units and selectively driving the internal node to a voltage level different from the precharge voltage in accordance with an entry selection signal and a signal from the corresponding sending unit; 4. A semiconductor processing apparatus according to claim 2 or 3 . Each of the selection switch gates is connected in series between the internal node and a node for applying a reference potential, and the first and second transistors receive the entry selection signal and the signal from the corresponding sending unit at the respective gates. The semiconductor arithmetic processing apparatus of Claim 4 provided with an element.

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