JP2003186854A - Simd processor and verification apparatus thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SIMD (single instruction multiple datastream) processor capable of externally knowing the contents of an internal register in the processor without having effect on original program processing. <P>SOLUTION: The SIMD processor is provided with a global processor 2 for decoding a program and controlling the whole processor, and a processor element block 3 comprising a plurality of processor elements for processing multiple data. An input-output part accessible from the outside is arranged in the incorporated mirror register of an arbitrary processor element, by incorporating a mirror register file 37 for always copying and storing contents of registers 31 for use in normal imperative operation processing into each processor element, and inputting an address designating a processor element. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microprocessor,
In particular, SIMD (Single-Instruction)
n Stream Multiple Data-St
The present invention relates to a ream) type processor and its verification device.

[0002]

2. Description of the Related Art In recent years, images have come to be treated as electrical data, and in the signal processing for such image data, the same arithmetic processing is applied to all pixels forming one image. There are many. In the SIMD type microprocessor, the same arithmetic processing can be simultaneously performed on a plurality of data with one instruction. Due to this structure, the SIMD type processor is used for the above-mentioned image processing and the like, which has the same calculation but has a very large amount of data.

The arithmetic processing in the SIMD type microprocessor described above can be realized by arranging a plurality of arithmetic units, but the data to be arithmetically operated needs to access the memory or the like at a speed commensurate with the arithmetic speed. If it is not in time, the performance of the processor is determined by the data access speed.

Normal type (SISD (Single-I
nStructure Stream Single
In the processor of Data-Stream)), the operation data is sequentially accessed from the memory by the program of the processor. In this case, the data access speed is determined by the bit width of the memory and the transfer time.

If this method is used even in the SIMD type, the data access becomes sequential processing in parallel with the parallel processing of the operations, and the processing capacity is lowered to the level of the SISD type. Therefore, in the SIMD type processor, the operation target data is not accessed by the instruction of the processor, but the input / output registers inside the processor are directly accessed from the external memory data transfer device. Generally, this input / output register is divided into input only and output only. The processing flow in the processor and the external memory data transfer device is performed as follows.

The external memory data transfer device transfers the operation target data to the input register. The processor transfers the calculation target data from the input register that has already transferred the calculation data from the outside to the calculation register and starts the calculation. The processor executes a predetermined operation. During this time, the external memory data transfer device transfers the next calculation target data to the input register. In addition, data that has been processed (result data)
If is in the output register, the external memory data transfer device transfers the result data from the output register to the memory. The processor finishes the operation and transfers the result data to the output register.

As described above, the external memory data transfer device transfers the operation target data at the same time when the processor executes the operation, thereby achieving high speed operation.

Conventionally, access to the input / output register has been performed by a shift register system or a serial memory system. In this method, which register is to be accessed is determined by the number of transfers, and for example, 25
6 processor elements (PE: Processor)
SIMD type processor with Element)
The first data transfer is the 0th PE register, the 2nd data is the 1st PE register, and the 256th time is 25
The transfer was performed such as the register of the fifth PE.

By the way, a debugging method for reducing the time required for developing a program for the SIMD type processor is disclosed in Japanese Patent Laid-Open No. 10-254841. In this publication, verification for each 1PE is performed sequentially,
It is described centering on the procedure for verification of all PEs.
This publication does not mention observation of the internal register of the PE, and the contents of the register are output in a general SAM (Serial Access Memory) according to the embodiment.
output only to y).

Further, Japanese Unexamined Patent Publication No. 10-269189 describes a method which is an evolution of the above-mentioned Japanese Unexamined Patent Publication No. 10-254841. This publication is the same in that the description is centered on the procedure of sequentially verifying one PE at a time and verifying all PEs, but it is characterized by including an apparatus for arbitrarily selecting a PE to be verified. . The selection change method of the selection circuit is performed by the control device inside the processor. This publication also does not mention observation of the internal register of the PE, and the contents of the register are output only to the general SAM in the embodiment.

Further, Japanese Patent Laid-Open No. 11-7432 discloses a SIMD type processor having a mechanism capable of randomly accessing each PE although it is not a proposal of a debugging method. This processor is a normal SIM
The structure is such that it has two buses for delivering data to each PE of the D-type processor, and one of the buses is connected to an external interface. The feature is that even the control of the external interface is performed on the processor side. The output of the register contents is the output of the external interface.

Further, the applicant of the present application has proposed a SIMD type processor having a port capable of externally accessing a register incorporated in any PE by inputting an address designating each PE (Japanese Patent Laid-Open No. 2001-2001). -84229).

FIG. 1 shows the overall configuration of the SIMD type processor described above. As shown in FIG. 1, the SIMD type processor includes a processor element block 3 composed of, for example, 256 PEs, and an external interface 4 connected to an external memory or the like. The operation data is input / output to / from the input / output register inside the processor via the external interface 4.

The global processor 2 is a so-called SI.
SD (Single-Instruction Str)
It is a processor of an easy single data-stream type and has a program RAM and data RA.
It incorporates M, decodes the program, and generates various control signals. This control signal is supplied to the register file 31 and the arithmetic array 36 which constitute the processor element block 3 in addition to the control of various built-in blocks. Also,
When a GP (global processor) instruction is executed, various arithmetic processing and program control processing are performed using a built-in general-purpose register, ALU (arithmetic logic operation unit) and the like.

The register file 31 holds data processed by a PE (processor element) instruction. The PE instruction is SIMD (Single-Instrument).
action Stream Multiple Dat
a-Stream) type instruction, which simultaneously performs the same processing on a plurality of data held in the register file 31. Control of reading / writing of data from the register file 31 is performed by control of the global processor 2. The read data is sent to the arithmetic array 36, and is written in the register file 31 after the arithmetic processing in the arithmetic array 36.

Further, the register file 31 can be accessed from the outside of the processor, and a specific register is read / written from the outside in addition to the control of the global processor 2.

The arithmetic array 36 performs arithmetic processing of PE instructions. All processing control is performed from the global processor 2.

FIG. 2 is a block diagram showing the detailed structure of the SIMD type processor described above. The configuration of the SIMD type processor described in Japanese Patent Laid-Open No. 2001-84229 will be described with reference to FIG.

The global processor 2 has a built-in program RAM for storing a program of the processor and a data RAM for storing operation data. Further, a program counter (PC) that holds the address of the program, G0 to G3 registers that are general-purpose registers for storing data for arithmetic processing, a stack pointer (holds the address of the save destination data RAM at the time of register saving and restoration ( SP), a link register (LS) that holds the caller's address when calling a subroutine, and I
LI and L holding branch source addresses at RQ and NMI
An N register and a processor status register (P) holding the state of the processor are built in.

A GP instruction is executed by using these registers and an instruction decoder, an arithmetic logic circuit (ALU), a memory control circuit, an interrupt control circuit, an external I / O control circuit, and a GP arithmetic control circuit which are not shown. Be seen.

When the PE instruction is executed, an instruction decoder, a register file control circuit (not shown), and a PE operation control circuit are used to control the register file and the operation array.

The register file 31 has one PE 3a.
32 8-bit registers are built in as a unit.
A set of 56 PEs has an array configuration. The registers are R0, R1, R2 ,. ． ． It is called R31. Each register has one read port and one write port for the arithmetic array 36, and is accessed from the arithmetic array 36 by the 8-bit read / write bus 38. Of the 32 registers, 24 are accessible from outside the processor,
External clock (CLK) and address (Address)
s), the read / write control (RWB) can be input to read / write any register.

For the access from the outside of the register, one register of each PE can be accessed through one external port, and the PE number (0 to 2) can be accessed by the address input from the outside.
55) is designated. Therefore, a total of 24 sets of external ports for register access are mounted. Further, access from the outside is 16-bit data with a set of even PE and odd PE, and two registers can be simultaneously accessed by one access.

The arithmetic array 36 contains a 16-bit ALU 34, a 16-bit A register 35a, and an F register 35b. The operation by the PE instruction basically stores the result in the A register 35a with the data read from the register file 31 as the input on one side of the ALU 34 and the content of the A register 35a on the other side. Therefore, the A register 35a and the R0 to R31 registers are operated.

A 7-to-1 multiplexer 32 is placed in the connection between the register file 31 and the arithmetic unit, and data 1, 2, and 3 apart to the left and data 1, 2, and 3 apart to the right and the center in the PE direction. Is selected as the calculation target. The 8-bit data in the register file 31 is shifted to the left by an arbitrary bit by the shift & expansion circuit 33 and input to the ALU. Further, an 8-bit condition register (T) (not shown) controls the execution / invalidation of each PE, so that only a specific PE 3a can be selected as an operation target.

[0026]

[Problems to be solved by the invention] JP-A 2001-8422
The invention described in Japanese Patent No. 9 makes it possible to read / write the contents of the input / output register in a minimum time.

On the other hand, however, the SIMD type processor described above has many ports for freely accessing the registers of the PE. This is inconvenient when monitoring data movements in real time, such as during program development.

Usually, in a SISD type processor, the data movement is monitored in real time by monitoring a signal terminal such as a data bus which is output to the outside. SI
Similarly, in the MD type processor, the input / output terminals such as the data bus are observed.

In comparison with the conventional SIMD type processor, PE
To realize free access to a register of the same
The SIMD type processor disclosed in Japanese Patent No. 84229 realizes a port for accessing a plurality of registers, and
Since one set of ports accessing one register has not only the data bus but also the input of the address designating the PE, the address bus is included in the monitoring target in addition to the data bus. Therefore, the monitoring device must be large-scale.

Further, not only the SIMD type processor described in Japanese Patent Laid-Open No. 2001-84229 but also the conventional SIMD type processor has no means for knowing the contents of the register during the calculation in the above steps. Normally, the SISD type processor takes a means to infer the contents of the internal register by monitoring the data input / output to / from the processor. S
The same is not impossible with the IMD type processor, but the amount of data to be traced increases in proportion to the number of PEs and the number of registers, and once in the SIMD type processor that takes time to input and output data, Since the read data tends to be used internally in parallel as much as possible, it is difficult in reality.

The present invention has been made in view of the above-mentioned conventional problems, and provides a SIMD type processor capable of externally knowing the contents of internal registers of the processor without affecting the original program processing. The purpose is to do.

[0032]

A SIMD type processor of the present invention is a SIMD type processor having a global processor for decoding a program and controlling the entire processor, and a plurality of processor elements for processing a plurality of data. A copy register (hereinafter referred to as a mirror register) in which each processor element always copies and stores the contents of a register used in a normal instruction calculation process.
And an input / output unit accessible from the outside to the mirror register incorporated in any processor element by inputting an address designating the processor element.

According to the above configuration, by reading the contents of the mirror register from the outside, the contents of the internal register of the processor can be known outside without affecting the original program processing. Then, if the value of the internal register of the processor can be directly known, only the data input / output port is monitored, and the value of the internal register during arithmetic processing can be monitored with high precision as compared with the case where there is no analogy. .

In the SIMD type processor of the present invention, it is preferable that the mirror register incorporated in each processor element is provided with an input signal for selecting which normal register contents are always copied.

According to the above configuration, the register to be monitored can be freely selected, and the selection can be switched at any time for the convenience of the outside by performing the selection from the processor external terminal.

Further, the SIMD processor of the present invention may be configured so that the mirror register incorporated in each processor element has a register for setting which normal register contents are always copied.

According to the above configuration, it is possible to select which register the mirror register has a copy of, and the selection can be switched for the convenience of the processor by making the selection from the register incorporated in the processor. Can be controlled by. If it can be controlled by a program on the processor side, it corresponds to a software-like part, so that no extra hardware is required.

The verification device of the present invention has the SIMD type microprocessor and the trace memory described in any of the above, and is external to the mirror register incorporated in any processor element in the SIMD type microprocessor described in any of the above. And a device for storing the contents read from the input / output unit in the trace memory described above.

Further, according to the above configuration, by storing the data read from the mirror register in the memory, it is possible to confirm a periodic change in the register contents. So-called tracing is possible.

Further, the verification device of the present invention has the IMD type microprocessor described in any of the above, and externally enters the mirror register built in any processor element in the SIMD type microprocessor described in any of the above. A device connected to an accessible input / output unit for monitoring the content read from the input / output unit and breaking the program processing of the processor according to the read content.

Further, according to the above configuration, the contents of the data read by the register monitoring block are immediately transmitted to the outside, so that the debugging can be facilitated. It is also possible to immediately stop the operation of the processor (break) when the specific data is read and check the status of the processor.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Since most of the SIMD type processors shown in FIGS. 1 and 2 are common, the same parts are denoted by the same reference numerals, and different parts will be mainly described in order to avoid duplication of description.

FIG. 3 is a block diagram showing the overall configuration of the SIMD type processor according to the present invention. As shown in FIG. 3, the SIMD type processor has 256 P
It is composed of a processor element block 3 made of E and an external interface 4 connected to an external memory or the like. The operation data is input / output to / from the input / output register inside the processor via the external interface 4.

The processor element block 3 is a register (mirror register) in which the register file 31, the arithmetic array 36, and the PE, which is a feature of the present invention, are always copied and stored in the contents of the registers used in the normal instruction arithmetic processing.
And a file 37.

As described above, the global processor 2
Is a so-called SISD (Single-Instruct).
action Stream Single Data-S
stream) type processor, and the program R
Built-in AM and data RAM, it decodes programs and generates various control signals. This control signal is used in addition to the control of various built-in blocks
Are supplied to the register file 31, the mirror register file 37, and the operation array 36 that configure the above.

The register file 31 holds data processed by a PE (processor element) instruction. The PE instruction is SIMD (Single-Instrument).
action Stream Multiple Dat
a-Stream) type instruction, which simultaneously performs the same processing on a plurality of data held in the register file 31. Control of reading / writing of data from the register file 31 is performed by control of the global processor 2. The read data is sent to the arithmetic array 36, and is written in the register file 31 after the arithmetic processing in the arithmetic array 36.

When the data processed by the PE instruction is stored in the register file 31, the mirror register file 37 always copies and stores the contents.

The register file 31 can be accessed from the outside of the processor, and a specific register can be read / written from outside in addition to the control of the global processor 2.

The arithmetic array 36 performs arithmetic processing of PE instructions. All processing control is performed from the global processor 2.

FIG. 4 is a block diagram showing the detailed structure of the embodiment of the present invention, and the SIMD shown in FIG.
Since many of them are the same as the type processor, the description will be given for different parts.

As shown in FIG. 4, in this embodiment, one 8-bit register 37b is added to each PE 3a in the register file 31 portion. These registers 37b are called mirror registers, and each PE3
In a, the operation array 36 is provided with one write port, and is accessed from the operation array 36 by the 8-bit read / write dual-purpose bus 38. The mirror register 37b is connected to the external interface 4 and is accessible from outside the processor. By inputting a clock and an address from the outside, the mirror register 37b is arbitrarily registered.
7b can be read. Unlike the registers R0 to R31, the mirror register 37b cannot be written. The mirror register 37b can be accessed from the outside by one external port and one mirror register 37b of each PE 3a can be accessed, and the PE number (0 to 255) is designated by the address input from the outside. In addition, access from the outside is 16-bit data for one set of even PE and odd PE, and two registers are simultaneously accessing by one access.

The mirror register 37b is controlled so as to have the same contents as the data stored in one of the registers R0 to R31. The control is performed by a method in which, when data is written from the arithmetic array 36 to the target register 31b via the read / write bus 38, the mirror register 37b is simultaneously written with the same data from the read / write bus 38. These controls are performed by the register file control circuit like other registers.

Although a register is added as compared with FIG. 2, it is not a register as a programming model, so that at the instruction level there is no mirror register 37b, that is, the instruction set is exactly the same as that of the processor of FIG.

As described above, the mirror register 37b
Is connected to the external interface 4 and is accessible from the outside of the processor, and any register 37b can be read by inputting a clock and an address from the outside. This structure will be described with reference to FIG. Here, the external port is composed of an 8-bit address, a clock indicating a transfer timing, and 8-bit data which is transfer data. These signals are connected to the external interface 4 of the processor, where they are timed and buffered and address as internal signals of the processor,
Converted to clock and data.

Although these signals are supplied to the mirror register 37b of the register file, only the PE3a that decodes the address for each PE3a ... And matches the address indicating each PE3a ... Performs the read operation. for that reason,
Each PE 3a has an address decode and read control circuit 39, and the input / output register has its control signal (R1).
The data is transferred to and from the data bus (D1) connected to the external interface 4. Since the mirror register transfers data with the operation array, it has the other input port, and the data (D2) connected to the operation array 36 is transferred from the data (D2) connected to the operation array 36 by the write (W2) control signal created in the global processor 2 by the instruction. Transfer.

Although FIG. 5 shows only the structure of two PEs, 256 sets of the address decode & read control circuit 39 and the mirror register 37b are required to match the structure of the 256PE of FIG. Become. Also,
In order to select 256, the bit width of the address is 8 bits. Therefore, the bit width of the address also changes as the number of PEs increases or decreases. Although the bit width of the data is 8 bits here, it also changes depending on the amount of data transferred at one time.

In FIG. 4, Japanese Patent Laid-Open No. 2001-84229.
Although the present invention has been described with reference to FIG. 2 which is the configuration described in Japanese Patent Publication No. JP-A-2003-264, in the present invention, SIMs other than the configuration shown in FIG.
It is also effective for D-type processors. Read / write PE register data serially from outside S
FIG. 6 shows a configuration example when the present invention is applied to an IMD type processor. In the example of FIG. 6, the external interface is divided into an input interface and an output interface.
When accessing the register of E, the register 31b is sequentially accessed according to the order of PE, and read or write is performed. This interface accesses the PEs in order and therefore does not require an address as in the example of FIG. Even for a SIMD type processor having such a configuration, each PE has an 8-bit mirror register 37b.
And is accessed from the arithmetic array 36 by an 8-bit read / write bus 38. It is connected to the external interface and is accessible from outside the processor, and any register can be read by inputting the clock and address from the outside.

Although the external port is described as an external terminal in the embodiment shown in FIG. 5, the register monitoring block 301 is mounted on the same chip as in the embodiment of FIG. Even if the port is not output, the mirror register file 3 of each PE is processed by the register monitoring block 301 mounted on the same chip by address decoding and read control in PE units of FIG.
7 can be accessed. The register file 31 is connected to the memory transfer block 302, and data is transferred between the memory 5 and the register file 31 via the memory transfer block 302.

Next, another embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. In this embodiment, as shown in FIG. 8, the register file control circuit 311 built in the global processor 2 has the registers R0 to R3 of the PE 3a.
A write signal is sent to 1. Multiplexer 32to1MUX31 that selects one signal from 32 input signals
0 inputs 32 write signals sent to the registers R0 to R31, and determines which input signal is selected by the content of the 5-bit mirror selection signal at the external terminal. The signal selected by this is the mirror register 3
It is sent to 7b as a write signal. Since the mirror register write signal selected by the mirror select signal of the external terminal has the same content as the write signal of the desired register of the registers R0 to R31, each PE 3a performs mirror write at the same time as writing to the selected register 31b. The same content is written in the register 37b. A register to be monitored can be freely selected from outside the processor by a mirror selection signal input from the outside.

Next, a different embodiment of the present invention will be described with reference to FIG. In this embodiment, as shown in FIG. 9, the register file control circuit 311 built in the global processor 2 uses the registers R0 to R of the PE 3a.
A write signal is sent to 31. 1 out of 32 input signals
Multiplexer 32to1MUX3 for selecting book signals
The 10a inputs 32 write signals to be sent to the registers R0 to R31, and determines which input signal to select based on the content of the mirror selection signal which is the content of the 5-bit mirror selection register 312. The signal selected by this is sent to the mirror register as a write signal. The mirror register write signal selected by the contents of the mirror selection register 312 is registered in the registers R0 to R.
Since the contents are the same as the write signal of the desired register 31 of 31, the selected register 31b in each PE 3a ...
At the same time as writing to, the same contents are written to the mirror register 37b. Mirror selection register 312
Registers to be monitored can be freely selected by setting the contents of the register to a desired register number.

Next, a further different embodiment of the present invention will be described with reference to FIG. In this embodiment, FIG.
As shown in 0, the register monitoring block 301 connected to the port that accesses the mirror register file 37.
There is a trace memory 6 and a register monitoring block 30.
1 can store the content read from the mirror register 37b in the trace memory 6.

Next, still another embodiment of the present invention will be described with reference to FIG. In this embodiment, FIG.
, The register monitoring block 301 connected to the port that accesses the mirror register file 37.
Monitors the contents of the mirror register 37b and transmits the obtained information to the external debug system 7. The external debug system 7 issues NMI (non-maskable interrupt request) to the processor based on the information from the register monitoring block 301, breaks the program processing of the processor, and grasps the status of the register inside the processor.

[0063]

As described above, according to the first aspect of the present invention, the PE has a copy register (mirror register) for always copying and storing the contents of the PE register, and the contents of the mirror register are read from the outside. By having a port that can be used, the contents of the internal registers of the processor can be known externally without affecting the original program processing. Then, if the value of the internal register of the processor can be directly known, only the data input / output port is monitored, and the value of the internal register during arithmetic processing can be monitored with high precision as compared with the case where there is no analogy. .

Further, in the structure of the second aspect, it is possible to select which register the mirror register has a copy of, that is, which register contents can be monitored outside the processor. Therefore,
The ability to select the target register has the advantage that the target register to be monitored can be freely selected. By selecting from the processor external terminal, the selection can be switched at any time due to external reasons. In addition, since the processor does not request a dedicated instruction or procedure, it does not affect the original operation of the processor.

Further, in the structure of the third aspect, which register the mirror register has a copy of can be selected, that is, which register contents can be monitored outside the processor. Therefore,
The ability to select the target register has the advantage that the target register to be monitored can be freely selected. By performing the selection from the register incorporated in the processor, the selection can be switched for the convenience of the processor, and there is an advantage that it can be controlled by a program on the processor side. If it can be controlled by a program on the processor side, it corresponds to a software part, so that no extra hardware is required.

Further, in the structure of the fourth aspect, by storing the data read from the mirror register in the memory, it is possible to confirm the periodic change of the register contents. So-called tracing is possible.

Further, in the structure according to the fifth aspect, the contents of the data read by the register monitoring block are immediately transmitted to the outside, so that the debugging can be facilitated. It is also possible to immediately stop the operation of the processor (break) when the specific data is read and check the status of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a SIMD type processor.

FIG. 2 is a block diagram showing a detailed configuration of a SIMD type processor described in Japanese Patent Laid-Open No. 2001-84229.

FIG. 3 is a block diagram showing an overall configuration of a SIMD type processor according to the present invention.

FIG. 4 is a block diagram showing a detailed configuration of an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 6 is a block diagram showing another detailed configuration of the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration in which a register monitoring block is mounted on the same chip, and particularly when an external port is not output as an external terminal.

FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a different embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of still another embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of still another embodiment of the present invention.

[Explanation of symbols] 2 Global processor 3 processor element block 3a Processor element 4 External interface 31 register file 36 Arithmetic array 37 Mirror register file

Claims (5)

[Claims] 1. A SIMD comprising a global processor for decoding a program and controlling the entire processor, and a plurality of processor elements for processing a plurality of data.
Type processor, each processor element has a built-in copy register that always copies and stores the contents of the register used in normal instruction operation processing, and by inputting an address that specifies the processor element, any processor element can be built The SIM having the above-mentioned copy register provided with an input / output unit accessible from the outside.
D-type microprocessor. 2. The SIMD type microprocessor according to claim 1, wherein said copy register incorporated in each processor element is provided with an input signal for selecting which normal register contents are always copied. . 3. The SIMD type microprocessor according to claim 1, wherein the copy register incorporated in each processor element includes a register for setting which normal register contents are always copied. 4. S according to any one of claims 1 to 3.
It has an IMD type microprocessor and trace memory,
The copy register incorporated in any processor element of the SIMD type microprocessor according to any one of claims 1 to 3 is connected to an externally accessible input / output unit, and the contents read from the input / output unit are described above. And a device for storing the trace memory in a trace memory of the SIMD type microprocessor. 5. S according to any one of claims 1 to 3.
An IMD type microprocessor is provided, and the IMD type microprocessor is provided.
Any of the processor elements in the SIMD type microprocessor described in any one of (1) to (5) is connected to an input / output unit that is externally accessible, and the contents read from this input / output unit are monitored and read. And a device for breaking the program processing of the processor according to the contents described above.