JP4560398B2 - Data processing circuit - Google Patents

Description

The present invention relates to a data processing circuit capable of transferring data by a direct memory access (abbreviated as DMA) system.

In recent years, color processing has been implemented in data processing apparatuses that process image data and are mounted on a composite apparatus that combines functions such as a copying apparatus, a scanner apparatus, a printer apparatus, and a facsimile apparatus. Such a data processing device is required to increase the data processing speed. In data processing equipment, direct memory access (Direct Memory Access)
Data is transferred at high speed by transferring data by the Access (abbreviated as DMA) system.

  The first prior art is disclosed in Patent Document 1. This prior art device includes a central processing unit (abbreviated as CPU), which is a main control unit, and a programmable DMA control device. The CPU downloads the necessary DMA transfer program and parameters to the DMA controller. The DMA control device which is a memory processing unit executes a DMA transfer program to perform data transfer. When the DMA controller completes the data transfer, it sends an interrupt to the CPU.

  FIG. 6 is a block diagram showing the configuration of the data processing apparatus 1 according to the second prior art. FIG. 7 is a flowchart for explaining the DMA-related operation of the CPU 2. The conventional data processing apparatus 1 includes a memory 3, a CPU 2 that is a main control unit, and three internal blocks 4. Each internal block 4 includes a register 5 and a DMA circuit 6 which is a memory processing unit.

  A setting condition from the CPU 2 is given to the register 5. The DMA circuit 6 performs at least one of data writing to the memory 3 and data reading from the memory 3 based on the setting conditions stored in the register 5. The DMA circuit 6 is activated in response to an activation command from the CPU 2. When at least one of data writing to the memory 3 and data reading from the memory 3 is completed, the DMA circuit 6 gives an interrupt request to the CPU 2.

  In such a data processing device 1, each DMA circuit 6 gives an interrupt request to the CPU 2 every time at least one of data writing to the memory 3 and data reading from the memory 3 by each DMA circuit 6 is completed. . When given an interrupt request, the CPU 2 sets the register of the DMA circuit 6 to be activated next, and gives an activation command to the DMA circuit 6. As a result, the DMA circuits 6 are sequentially activated.

Japanese translation of PCT publication No. 2001-502082

  In the first prior art, when performing different data transfer sequentially, the DMA controller sends an interrupt to the CPU every time the data transfer is completed, and the CPU transfers the necessary DMA transfer every time an interrupt is given. Programs and parameters need to be downloaded to the DMA controller. Therefore, there is a problem that the processing load of the CPU is generated and the performance of the CPU is lowered.

  In the second prior art, when each DMA circuit 6 is sequentially activated, each DMA circuit 6 interrupts each time at least one of data writing to the memory 3 and data reading from the memory 3 is completed. When a request is given to the CPU 2 and the interrupt request is given, the CPU 2 needs to set a register of the DMA circuit 6 to be activated next, and to give an activation command to the DMA circuit 6. The second conventional technique has the same problem as the first conventional technique.

An object of the present invention is to provide a data processing circuit capable of reducing the processing load of the main control unit and preventing the deterioration of the performance of the main control unit.

The present invention provides a memory capable of writing data and reading data,
A main control unit that outputs a start instruction to write data to the memory and to read data from the memory;
Based on the input start command, at least one of data writing to the memory and data reading from the memory is performed, and when at least one of the data writing to the memory and the data reading from the memory is completed, an end notification is issued. A plurality of DMA circuits for outputting
A selector circuit provided in a one-to-one correspondence with each DMA circuit, the selector circuit connected to the corresponding DMA circuit so as to be able to output a start command to the corresponding DMA circuit ,
Each selector circuit is connected to all the DMA circuits other than the main control unit and the corresponding DMA circuit so that the start command from the main control unit and the end notification from all the DMA circuits other than the corresponding DMA circuit can be input. And
Each selector circuit is configured to output a start command in response to a start command from the main control unit or an end notification from each DMA circuit not corresponding to the corresponding DMA circuit,
Sets whether to output the start command to the corresponding DMA circuit by each selector circuit in response to the start command from the main control unit or the end notification from each DMA circuit that is not supported The data processing circuit is configured to be capable of being configured.

In the present invention, the main control unit outputs a selection command indicating which one of the start command from the main control unit and the end notification from each DMA circuit is selected,
Each selector circuit outputs a start command in response to any one of a start command from the main control unit designated by a selection command from the main control unit and an end notification from each DMA circuit that does not correspond. It is characterized by.

  According to the present invention, the memory can write and read data. The memory processing unit performs at least one of writing data to the memory and reading data from the memory. By this memory processing unit, data transfer by the DMA method can be realized.

There are a plurality of memory processing units, and an activation command unit is provided for each memory processing unit. Each start command unit outputs a start command for starting each memory processing unit. Each memory processing unit is activated in response to an activation command from each activation command unit. Each memory processing unit can be activated simultaneously.

  The main control unit outputs a start command for writing data into the memory and reading data from the memory. Each memory processing unit outputs an end notification when at least one of data writing to the memory and data reading from the memory is completed. Each start command unit outputs a start command in response to a start command from the main control unit or an end notification from each memory processing unit.

  In this way, each start command unit can output a start command in response to not only the start command from the main control unit but also the end notification from each memory processing unit. Therefore, when a start command from the main control unit is given to any one of the start command units, each start command unit is not given a start command from the main control unit to the other start command units. Each memory processing unit can be activated sequentially.

  In other words, the memory processing units can be linked without using the main control unit. Therefore, as in the second prior art, each memory processing unit issues an interrupt request to the main control unit every time at least one of data writing to the memory and data reading from the memory is completed. This eliminates the need to output a start command from the main control unit. As a result, the processing load on the main control unit can be reduced, and a decrease in the performance of the main control unit can be prevented.

  According to the present invention, the main control unit outputs a selection command indicating which of the start command from the main control unit and the end notification from each memory processing unit is selected. Each start command unit outputs a start command in response to any one of the start command from the main control unit specified by the selection command from the main control unit and the end notification from each memory processing unit. Therefore, the activation order of the memory processing units can be set by a selection command from the main control unit, and the versatility of the apparatus can be improved.

  FIG. 1 is a simplified block diagram showing a data processing device 21 according to an embodiment of the present invention. The data processing apparatus 21 is mounted on a composite apparatus that combines functions of a copying apparatus, a scanner apparatus, a printer apparatus, a facsimile apparatus, and the like. The data processing device 21 is used for processing image data.

  The data processing device 21 can transfer data by a direct memory access (abbreviated as DMA) method. In other words, the data processing device 21 performs at least one of writing data to the memory 23 and reading data from the memory 23 without going through a central processing unit (abbreviated as CPU) 22 described later. Can do.

  The data processing device 21 includes a memory 23, a plurality (three in this embodiment) of DMA circuits 24, a CPU 22, and a plurality (three in this embodiment) selector circuits 25. Hereinafter, each DMA circuit 24 may be referred to as first to third DMA circuits 24a to 24c. Each selector circuit 25 may be referred to as first to third selector circuits 25a to 25c.

  The memory 23 can write data and read data. The memory 23 is realized by, for example, a random access memory (abbreviated as RAM).

  The DMA circuit 24 is a memory processing unit. Each DMA circuit 24 can realize data transfer by the DMA system. Each DMA circuit 24 accesses a common memory 23. Each DMA circuit 24 performs at least one of writing data to the memory 23 and reading data from the memory 23. Each DMA circuit 24 outputs an end notification when at least one of the writing and reading ends.

  Each DMA circuit 24 is activated in response to an activation command from each selector circuit 25 described later. In other words, each DMA circuit 24 starts at least one of data writing to the memory 23 and data reading from the memory 23 in response to a start command from each selector circuit 25 described later.

  More specifically, the first DMA circuit 24a is activated in response to an activation command from the first selector circuit 25a. The second DMA circuit 24b is activated in response to the activation command from the second selector circuit 25b. The third DMA circuit 24c is activated in response to the activation command from the third selector circuit 25c.

  The CPU 22 is a main control unit. The CPU 22 outputs a start command for writing data to the memory 23 and reading data from the memory 23. Further, the CPU 22 outputs a selection command indicating which of the start command from the CPU 22 and the end notification from each DMA circuit 24 is selected.

  The selector circuit 25 is a start command unit. Each selector circuit 25 outputs a start command for starting each DMA circuit 24. Each selector circuit 25 outputs a start command in response to a start command from the CPU 22 or an end notification from each DMA circuit 24.

  More specifically, the first selector circuit 25a outputs a start command in response to a start command from the CPU 22 or end notifications from the second and third DMA circuits 24b and 24c. The second selector circuit 25b outputs a start command in response to a start command from the CPU 22 or an end notification from the third and first DMA circuits 24c and 24a. The third selector circuit 25c outputs a start command in response to a start command from the CPU 22 or end notifications from the first and second DMA circuits 24a and 24b.

  In the present embodiment, each selector circuit 25 outputs a start command in response to any one of a start command from the CPU 22 specified by a selection command from the CPU 22 and an end notification from each DMA circuit 24. In other words, whether each selector circuit 25 responds to the start command from the CPU 22 or the end notification from each DMA circuit 24 is determined by the selection command from the CPU.

  FIG. 2 is a diagram for explaining an example of data writing to the memory 23 and data reading from the memory 23 by each DMA circuit 24. The first DMA circuit 24a is set to write data to the memory 23, the start address is set to address A, and the number of transfer bytes is set to N bytes. The second DMA circuit 24b is set to read data from the memory 23, the start address is set to address A, and the number of transfer bytes is set to N bytes. The third DMA circuit 24c is set to write data to the memory 23, the start address is set to address B, and the transfer byte count is set to M bytes.

  The first selector circuit 25a is set to output a start command in response to a start command from the CPU 22. The second selector circuit 25b is set to output an activation command in response to the end notification from the first DMA circuit 24a. The third selector circuit 25c is set to output a start command in response to the end notification from the second DMA circuit 24b.

  When each DMA circuit 24 and each selector circuit 25 are set as described above, when the CPU 22 outputs a start command, the first selector circuit 25 a outputs a start command in response to the start command from the CPU 22. The first DMA circuit 24a is activated in response to the activation command from the first selector circuit 25a. The first DMA circuit 24 a writes data to the memory 23. At this time, data is written for N bytes sequentially from address A of the memory 23. When the first DMA circuit 24a finishes writing data to the memory 23, it outputs an end notification.

  The second selector circuit 25b outputs a start command in response to the end notification from the first DMA circuit 24a. The second DMA circuit 24b is activated in response to the activation command from the second selector circuit 25b. The second DMA circuit 24 b reads data from the memory 23. At this time, N bytes of data are sequentially read from address A of the memory 23. When the second DMA circuit 24b finishes reading data from the memory 23, it outputs an end notification.

  The third selector circuit 25c outputs an activation command in response to the end notification from the second DMA circuit 24b. The third DMA circuit 24c is activated in response to the activation command from the third selector circuit 25c. The third DMA circuit 24 c writes data to the memory 23. At this time, M bytes of data are written in order from address B of the memory 23.

  FIG. 3 is a block diagram showing the overall configuration of the data processing device 21. The data processing device 21 includes the memory 23, a memory controller 31 that controls the memory 23, an arbiter & selector 32, a plurality (three in this embodiment) of internal blocks 33, and the CPU 22. Hereinafter, each internal block 33 may be referred to as first to third internal blocks 33a to 33c.

  The arbiter & selector 32 is interposed between the memory controller 31 and each internal block 33. The arbiter & selector 32 arbitrates the bus use right of each internal block 33. In other words, the arbiter & selector 32 selects any one of the internal blocks 33 and assigns a bus use right to the selected internal block 33.

  Each internal block 33 includes the DMA circuit 24 and the selector circuit 25. More specifically, the first internal block 33a includes a first DMA circuit 24a and a first selector circuit 25a. The second internal block 33b includes a second DMA circuit 24b and a second selector circuit 25b. The third internal block 33c includes a third DMA circuit 24c and a third selector circuit 25c.

  The DMA circuit 24 of each internal block 33 can control the memory controller 31 via the arbiter & selector 32 and thereby access the memory 23. In other words, the DMA circuit 24 of each internal block 33 controls the memory controller 31 via the arbiter & selector 32, thereby performing at least one of writing data into the memory 23 and reading data from the memory 23. Can do.

  Each internal block 33 has a different function. As an example, each internal block 33 has any one of a function for scan input, a function for compression / decompression input / output, a function for rotation input / output, and a function for laser output. The function which each internal block 33 has is not limited to these.

  FIG. 4 is a block diagram showing a configuration of the first internal block 33a. Since each internal block 33 is similar, only the first internal block 33a will be described, and description of the second and third internal blocks 33b and 33c will be omitted. The first internal block 33a includes a register 36, a control circuit 37, the DMA circuit 24, and the selector circuit 25.

  The CPU 22 gives the CPU address CPU_ADR to the register 36. The CPU address CPU_ADR indicates the address of the register 36. The CPU 22 gives CPU data CPU_DATA to the register 36. The CPU data CPU_DATA indicates setting conditions of the control circuit 37, the DMA circuit 24, and the selector circuit 25. The CPU 22 is provided with CPU data CPU_DATA from the register 36. The CPU data CPU_DATA indicates the status of the control circuit 37, the DMA circuit 24, and the selector circuit 25.

  The register 36 decodes the CPU address CPU_ADR. The register 36 latches the CPU data CPU_DATA at an address specified by the CPU address CPU_ADR at the time of writing by the CPU 22, that is, at the time of writing. The register 36 transfers the CPU data CPU_DATA from the address specified by the CPU address CPU_ADR at the time of reading by the CPU 22, that is, at the time of reading.

  The control circuit 37 calculates data based on the setting conditions of the control circuit 37 stored in the register 36. The control circuit 37 gives the status of the control circuit 37 to the register 36. The control circuit 37 controls the input / output device 38. The control circuit 37 gives data to the input / output device 38. The control circuit 37 is supplied with data from the input / output device 38. Control circuit 37 includes a buffer circuit for storing data.

  As an example, when the first internal block 33a is an internal block having a function for scan input, the control circuit 37 includes a timing generation circuit and a buffer circuit. The timing generation circuit generates timing for reading scan data read from an original by an image reading unit which is the input / output device 38. The buffer circuit stores scan data.

  The DMA circuit 24 transfers data based on the setting conditions of the DMA circuit 24 stored in the register 36. The setting conditions of the DMA circuit 24 indicate a start address and the number of transfer bytes. The DMA circuit 24 gives the status of the DMA circuit 24 to the register 36.

  The DMA circuit 24 is activated in response to an activation command D_TRG1 from the selector circuit 25 described later. The DMA circuit 24 reads data stored in the buffer circuit in the control circuit 37 and writes this data in the memory 23. Alternatively, the DMA circuit 24 reads data stored in the memory 23 and writes this data to the buffer circuit in the control circuit 37.

  More specifically, the DMA circuit 24 provides the DMA address DMA_ADR1 to the memory controller 31 via the arbiter & selector 32. The DMA address DMA_ADR1 indicates the address of the memory 23. The DMA circuit 24 supplies a DMA control signal DMA_CONT 1 to the memory controller 31 via the arbiter & selector 32. The DMA control signal DMA_CONT1 indicates a write command to the memory 23 and a read command from the memory 23. The DMA circuit 24 is supplied with a DMA control signal DMA_CONT1 from the memory controller 31 via the arbiter & selector 32. This DMA control signal DMA_CONT 1 indicates the status of the memory controller 31.

  Such a DMA circuit 24 designates the address of the memory 23 by the DMA address DMA_ADR1. The DMA circuit 24 commands at least one of writing and reading by the DMA control signal DMA_CONT1. In this way, the DMA circuit 24 can perform at least one of writing data to a designated address in the memory 23 and reading data from a designated address in the memory 23. This data corresponds to the DMA data DMA_DATA in FIG.

  When at least one of data writing to the memory 23 and data reading from the memory 23 is completed, the DMA circuit 24 outputs an end notification DMA_END1 and an interrupt request INTR1. The setting condition of the DMA circuit 24 also indicates whether to mask the interrupt request INTR1. When the interrupt request INTR1 is masked, the DMA circuit 24 does not output the interrupt request INTR1 even when at least one of the writing and reading is completed.

  The interrupt request INTR1 is given to the OR circuit 39. The OR circuit 39 is supplied with interrupt requests INTR1 to INTR3 from the DMA circuit 24 of each internal block 33. The OR circuit 39 outputs an interrupt request INTR when any one of these interrupt requests INTR1 to INTR3 is given. This interrupt request INTR is given to the CPU 22.

  The selector circuit 25 outputs an activation command based on a selection command that is a setting condition of the selector circuit 25 stored in the register 36. The selector circuit 25 responds to one of the start command DMA_TRG1 given from the CPU 22 via the register 36 and the end notifications DMA_END2 and DMA_END3 from the DMA circuits 24 of the second and third internal blocks 33b and 33c. The start command D_TRG1 is output.

  FIG. 5 is a flowchart for explaining the DMA-related operation of the CPU 22. This figure assumes that each DMA circuit 24 is activated in the order of the first DMA circuit 24a, the second DMA circuit 24b, and the third DMA circuit 24c.

  When a predetermined operation start command is input, in step s0, the CPU 22 starts a DMA-related operation and proceeds to step s1. In step s1, the CPU 22 sets the register of the control circuit 37 of each internal block 33 by giving the setting condition of the control circuit 37 of each internal block 33 to the register 36 of each internal block 33, and proceeds to step s2. .

  In step s2, the CPU 22 sets the register of the first DMA circuit 24a by giving the setting condition of the first DMA circuit 24a to the register 36 of the first internal block 33a, and proceeds to step s3. In step s3, the CPU 22 sets the register of the second DMA circuit 24b by giving the setting condition of the second DMA circuit 24b to the register 36 of the second internal block 33b, and proceeds to step s4. In step s4, the CPU 22 sets the register of the third DMA circuit 24c by giving the setting condition of the third DMA circuit 24c to the register 36 of the third internal block 33c, and proceeds to step s5. In these steps s2 to s4, the start address and the number of transfer bytes are set.

  In step s5, the CPU 22 gives a selection command that is a setting condition of each selector circuit 25 to the register 36 of each internal block 33, and proceeds to step s6. In FIG. 5, a selection command indicating that a start command is selected from the CPU 22 is given to the register 36 of the first internal block 33a. The register 36 of the second internal block 33b is given a selection command indicating that an end notification is selected from the first DMA circuit 24a. The register 36 of the third internal block 33c is given a selection command indicating that an end notification is selected from the second DMA circuit 24b. In this way, the CPU 22 performs a linkage setting for linking the DMA circuits 24 by giving a selection command to the register 36 of each internal block 33.

  In step s6, the CPU 22 performs setting for masking unnecessary interrupt requests in the register 36 of each internal block 33, and proceeds to step s7. The unnecessary interrupt request is an interrupt request from the remaining DMA circuit 24 except for the DMA circuit 24 that is activated lastly among the DMA circuits 24 to be activated. In FIG. 5, the interrupt requests from the first and second DMA circuits 24a and 24b are masked.

  In step s7, the CPU 22 outputs a start command, thereby setting the start bit of the first DMA circuit 24a, and proceeds to step s8. In step s8, when the CPU 22 is given an interrupt request by the DMA circuit 24, or in FIG. 5, an interrupt request by the third DMA circuit 24c, the process proceeds to step s9. In step s9, the CPU 22 ends the DMA related operation.

  In step s7, when the CPU 22 outputs a start command, the first selector circuit 25a outputs a start command in response to the start command from the CPU 22. The first DMA circuit 24a is activated in response to the activation command from the first selector circuit 25a. In response to the end notification from the first DMA circuit 24a, the second selector circuit 25b outputs a start command. The second DMA circuit 24b is activated in response to the activation command from the second selector circuit 25b. In response to the end notification from the second DMA circuit 24b, the third selector circuit 25c outputs an activation command. The third DMA circuit 24c is activated in response to the activation command from the third selector circuit 25c. The third DMA circuit 24c outputs an interrupt request when at least one of data writing to the memory 23 and data reading from the memory 23 is completed. The interrupt request is given to the OR circuit 39. The OR circuit 39 gives an interrupt request to the CPU 22.

  In this manner, until the CPU 22 is given an interrupt request after the CPU 22 outputs the start command, each DMA circuit 24 writes data to the memory and reads data from the memory without passing through the CPU 22. it can. During this time, the CPU 22 can execute another process.

  According to the present embodiment as described above, each selector circuit 25 can output a start command in response to not only the start command from the CPU 22 but also the end notification from each DMA circuit 24. Therefore, when a start command from the CPU 22 is given to any one of the selector circuits 25, each selector circuit 25 is connected to each DMA circuit 24 even if the start command from the CPU 22 is not given to the other selector circuits 25. Can be activated sequentially.

  In other words, the DMA circuits 24 can be linked without using the CPU 22. Therefore, as in the second prior art, each DMA circuit 24 issues an interrupt request to the CPU 22 each time at least one of data writing to the memory 23 and data reading from the memory 23 is completed. It becomes unnecessary to output a start command from the CPU 22. As a result, the processing load on the CPU 22 can be reduced, and a decrease in the performance of the CPU 22 can be prevented.

  More specifically, in order to sequentially start up the three DMA circuits 24, the second prior art requires that the CPU 22 be given an interrupt request three times. Need only be given one interrupt request.

  Further, since the CPU 22 sets the registers of all the DMA circuits 24 to be activated before outputting the start command, even if the DMA circuits 24 are linked without using the CPU 22 as described above, The register setting of the circuit 24 can be performed.

  Each selector circuit 25 outputs a start command in response to any one of the start command from the CPU 22 specified by the selection command from the CPU 22 and the end notification from each DMA circuit 24, so the selection from the CPU 22 The activation order of each DMA circuit 24 can be set by a command. Thus, since the starting order of each DMA circuit 24 is programmable, the versatility of the apparatus can be improved.

  The above-described embodiment is merely an example of the present invention, and the configuration can be changed within the scope of the present invention. In the foregoing embodiment, the internal block 33 includes one DMA circuit 24. However, in another embodiment of the present invention, the internal block 33 includes the DMA circuit 24 for reading data from the memory 23, and A DMA circuit 24 for writing data into the memory 23 may be included. As a result, the data stored in the memory 23 is read out, the data stored in the buffer circuit in the control circuit 37 is read out while the data is written in the buffer circuit in the control circuit 37, and the data is stored in the memory 23. Can write.

It is a block diagram which simplifies and shows the data processor 21 of one Embodiment of this invention. 4 is a diagram for explaining an example of data writing to a memory 23 and data reading from the memory 23 by each DMA circuit 24. FIG. 2 is a block diagram showing an overall configuration of a data processing device 21. FIG. It is a block diagram which shows the structure of the 1st internal block 33a. 4 is a flowchart for explaining a DMA-related operation of a CPU 22; It is a block diagram which shows the structure of the data processing apparatus 1 of the 2nd prior art. It is a flowchart for demonstrating the DMA related operation | movement of CPU2.

Explanation of symbols

21 Data processing device 22 CPU
23 Memory 24 DMA Circuit 25 Selector Circuit 31 Memory Controller 32 Arbiter & Selector 33 Internal Block 36 Register 37 Control Circuit 38 Input / Output Device 39 OR Circuit

Claims (2)

A memory capable of writing and reading data, and
A main control unit that outputs a start command for writing data to the memory and reading data from the memory;
Based on the input start command, at least one of writing data to the memory and reading data from the memory is performed. A plurality of DMA circuits for outputting
A selector circuit provided in a one-to-one correspondence with each DMA circuit, the selector circuit connected to the corresponding DMA circuit so as to be able to output a start command to the corresponding DMA circuit ,
Each selector circuit is connected to all the DMA circuits other than the main control unit and the corresponding DMA circuit so that the start command from the main control unit and the end notification from all the DMA circuits other than the corresponding DMA circuit can be input. And
Each selector circuit is configured to output a start command in response to a start command from the main control unit or an end notification from each DMA circuit not corresponding to the corresponding DMA circuit,
Sets whether to output the start command to the corresponding DMA circuit by each selector circuit in response to the start command from the main control unit or the end notification from each DMA circuit that is not supported A data processing circuit characterized by being configured. The main control unit outputs a selection command indicating which one of the start command from the main control unit and the end notification from each DMA circuit is selected,
Each selector circuit outputs a start command in response to any one of a start command from the main control unit designated by a selection command from the main control unit and an end notification from each DMA circuit that does not correspond. The data processing circuit according to claim 1.

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