JP4413905B2 - SIMD type processor - Google Patents

Description

  The present invention relates to a single instruction stream multiple data stream (SIMD) type processor that processes a plurality of image data and the like in parallel by one arithmetic instruction.

  In recent years, in digital copying machines, facsimile machines, and the like, improvement of images has been attempted by increasing the number of pixels or making it compatible with color. As the image is improved, the number of data to be processed has increased. By the way, data processing in a copying machine or the like often performs the same arithmetic processing on all pixels. Therefore, a SIMD type processor that performs the same arithmetic processing simultaneously on a plurality of data with one instruction is used. Here, arithmetic processing can be realized by arranging a plurality of arithmetic units, but it is necessary to access the memory etc. at a speed commensurate with the arithmetic speed for the data to be operated. Processor performance is determined by speed. In a normal type SIDS (Single Instruction Single Data) processor, operation data is sequentially accessed from a memory by a program of the processor. In this case, the data access speed is determined by the bit width of the memory and the transfer time. If this method is also used in the SIMD type processor, the computation is parallel processing, whereas the data access is sequential processing, and the processing capability is reduced to the same level as the SISD type processor.

  For this reason, the SIMD type processor is configured such that the operation target data is not accessed by a processor instruction, but an input / output register inside the processor is directly accessed from an external memory data transfer device. In other words, simultaneously with the execution of the operation by the processor, the memory data transfer device provided outside transfers the data to be processed next to the input register, or the calculated data is transferred from the output register to the memory data transfer device. The data processing speed is increased by transferring the data to the memory.

The processing flow between the processor and the external memory data transfer device is performed as follows.
(1) The external memory data transfer device transfers the operation target data to the input register.
(2) The processor starts the operation by transferring the operation target data from the input register to which the operation data has been transferred from the outside to the operation register.
(3) The processor executes a predetermined operation. During this time, the external memory data transfer device transfers the next calculation target data to the input register. In addition, when the operation processed data (result data) is in the output register, the external memory data transfer device transfers the result data from the output register to the memory.
(4) The processor finishes the operation and transfers the result data to the output register.

  As described above, the speed is increased by the external memory data transfer device transferring the calculation data simultaneously with the execution of the calculation of the processor.

As this data transfer method, a shift register method or a serial access memory method is adopted. In this shift register system, for example, as described in Patent Document 1 ( Japanese Patent Laid-Open No. 5-67203 ) , data held in a register is sequentially shifted bit by bit in synchronization with a clock input. It is a method. According to this shift register system, for example, in the case of a SIMD type processor having 256 processor elements, the data transferred for the first time is held in the input register of the 0th processor element and shifted by 1 bit by the next clock input. And held in the input register of the first processor element. A total of 256 clock inputs are required until the data transferred for the first time is held in the input register of the 255th processor element.

In the serial access memory system, for example, as described in Patent Document 2 ( Japanese Patent Laid-Open No. 6-4690 ) , the input pointer generates an input pointer signal in which one processor element is set to logic “H”. In this method, input data is written to an input SAM (serial access memory) of a processor element designated by logic “H”. In this serial access memory system, the input pointer signal is sequentially shifted bit by bit in synchronization with the clock input. Therefore, according to this serial access memory system, for example, in the case of a SIMD type processor having 256 processor elements, in the first data transfer, the input pointer signal specifies the 0th processor element, and the 0th processor element Data is held in the input SAM. Next, in the second data transfer, the input pointer signal is shifted by 1 bit in synchronization with the clock input to designate the first processor element, and the data is held in the input SAM of the first processor element. In this way, a total of 256 clock inputs are required until data is held in the input SAM of the 255th processor element.
JP-A-5-67203 Japanese Patent Laid-Open No. 6-4690

  However, according to these methods, there is a problem that even when data is transferred only to even-numbered processor elements, it must be transferred to odd-numbered processor elements. Further, there is a problem that even when data is to be transferred only to the latter half of the processor elements (128th to 255th), it must be transferred to all the processor elements. That is, there is a problem that data cannot be directly transferred only to a specific processor element. Therefore, there is a problem that it takes more time than necessary to transfer the necessary data, and the data processing becomes slow.

  In the data processing performed by the processor, the bit width of the input register required to hold the input data, the bit width of the output register required to hold the output data, and the bit of the register required to temporarily hold the data The width depends on the application to be executed. In a conventional SIMD type processor, the bit width of data that can be held by an input register, an output register, or a register that temporarily holds data has been fixed. Therefore, there is a problem that data cannot be processed if the data exceeds the bit width that can be held in these registers.

  In the prior art, the bit widths of the input / output registers and the input / output ports are the same, and it is necessary to access only the number of PEs in order to transfer the data of all the processor elements (PE), which increases the transfer time. was there.

  Further, depending on the application, a large number of line buffers are required, and a register built in the processor element is used for this purpose. However, since the number of registers is fixed, there is a problem that cannot be applied to an application that requires a line buffer exceeding this value.

  The present invention has been made paying attention to such a conventional problem, and enables data to be directly transferred to an arbitrary processor element, thereby speeding up data transfer, and thus data processing. The purpose is to speed up. Another object of the present invention is to enable data processing flexibly corresponding to the number of bits of data by making the usage of the register flexible.

The SIMD type processor according to the present invention includes a plurality of processor elements each having an arithmetic means for arithmetically processing data and data holding means for holding data arithmetically processed by the arithmetic means and holding data arithmetically processed by the arithmetic means And a data transfer bus connected to each of the processor elements, a designation means for designating a predetermined processor element, an address bus connected to each of the processor elements, and data to be processed are obtained from the data transfer bus Generation of an acquisition signal for holding in the data holding means or an output signal for outputting the processed data held in the data holding means from the data transfer bus to the data holding means And the data holding means includes a plurality of means. A first register group having a plurality of registers, and a second register group having a plurality of registers, wherein the designation means addresses a predetermined processor element, and the predetermined data of the specified processor element When the signal generating means gives a signal to the holding means, a predetermined number of registers are selected from the first register group and the second register group in the data holding means, and the selection in the data holding means The data is acquired or output from the data transfer bus to the registered register.

  According to this, the data holding means acquires and holds the data to be processed by giving the data holding means an acquisition signal for holding the data to be processed by the signal generating means to the data holding means. It functions as a thing. Further, the signal generation means provides the data holding means with an output signal for outputting the processed data held in the data holding means, so that the data holding means outputs the processed data. Function. As described above, by making the usage of the register flexible, it is possible to perform data processing flexibly corresponding to the number of bits of input data and output data.

  As described above in detail, according to the present invention, the data to be processed is held in the data holding means of the addressed processor element, so that the data can be directly transferred to any processor element. Also, when data processed by the arithmetic means is output, the data held in the data holding means of the addressed processor element is output. Therefore, the data transfer can be performed at high speed, and the data processing can be performed at high speed.

  The data holding means has a function as an input register and also functions as an output register. Thus, by making the usage of the data holding means flexible, it is possible to perform data processing flexibly corresponding to the number of bits of data.

(First embodiment)
An embodiment of a SIMD type processor 1 according to the present invention will be described below with reference to FIGS.

SIMD processor 1, as shown in FIG. 1, consists of an external Inn tough Esu 4 connected global processor 2, the processor element block 3 consisting of processor elements 3a to be described later of the 256 sets in this embodiment, the memory controller 5 Is done. The memory controller 5 directly accesses the operation target data from the memory 6 to the input / output register fill 31 in the processor based on the instruction of the global processor 2.

First, the memory controller 5 will be described. As shown in FIG. 1, note Rico controller 4, which is connected via a register file 31 and the data transfer port of the external interface 4 of the SIMD processor 1, data transfer from the register file 31 to memory 6, the memory 6 To the register file 31. The registers controlled by the memory controller 5 are mapped in the I / O space, and can be read and written by outputting addresses, clocks, and read / write controls in accordance with instructions from the global processor 2.

  An I / O address, data, and control signal are given from the global processor 2 to the memory controller 5 via a bus. The global processor 2 sets commands such as an operation method in some operation setting registers (not shown) of the memory controller 5. Finally, the global processor 2 writes a start code in a start register (not shown) of the memory controller 5 so that the memory controller 5 automatically performs an operation according to the setting. With this configuration, the data in the register file 31 is input / output simultaneously with the calculation based on the instruction control of the processor.

  FIG. 2 shows the configuration of the memory controller 5 used in the present invention. The memory controller 5 controls the write buffer unit 54 that writes data to the memory 6, the read buffer unit 55 that reads data from the memory 6, the PE control unit 52 that controls the PE register file, and the memory 6. It comprises a RAM control unit 53 and a sequence unit (SCU) 51.

  An output port of the external interface 4 of the SIMD processor 1 is connected to the write buffer unit 54, and an input port of the external interface 4 is connected to the read buffer unit 55.

  As shown in FIG. 3, the global processor 2 includes a global processor 2, a processor element block 3, a program RAM 21 storing a program for controlling the external interface 4 and the memory controller 5, and the global processor 2 based on the program RAM 21. , A processor element block 3, an external interface 4, and a sequence unit 22 for controlling the memory controller 5. Specifically, the sequence unit 22 controls an arithmetic logic unit 23 (hereinafter referred to as “ALU 23”), which will be described later, provided in the global processor 2.

  The sequence unit 22 controls a later-described register file 31 and a later-described arithmetic array 36 that constitute the processor element block 3. The arithmetic array 36 includes a multiplexer 32, a shift extension circuit 33, an arithmetic logic unit 34 (hereinafter referred to as “ALU 34”), and a register 35. The global processor 2 is a so-called SISD type, and performs one arithmetic process for one arithmetic instruction.

  Further, the sequence unit 22 sends operation setting data and commands for data transfer to the memory controller 5 described later. Based on the operation setting data and commands of the sequence unit 22, the memory controller 5 instructs an address control signal for addressing the processor element 3a, and a data read / write to a register 31b, which will be described later, constituting the processor element 3a. A read / write control signal and a clock control signal for supplying a clock signal are supplied to the external interface 4.

  Here, the write control signal among the read / write control signals refers to a signal for obtaining data to be processed from a data bus 41d described later and holding it in the register 31b of the processor element 3a. On the other hand, the read control signal among the read / write control signals is a signal for instructing the register 31b to supply the processed data held in the register 31b of the processor element 3a to the data bus 41d described later. Say.

The memory controller 5 receives a command from the global processor 2, a signal for designating the address of the processor element 3a constituting the processor element block 3 (hereinafter, referred to as "addressing signal".) Create and external in tough Esu 4 to the register controller 31a (to be described later) of the processor element 3a via the address bus 41a. Further, the memory controller 5 reads a signal (hereinafter referred to as “read / write instruction signal”) for instructing data read / write to a register 31b constituting the processor element 3a as will be described later. A read / write signal is given to a register controller 31a (to be described later) of the processor element 3a via the / write signal 41b. Further, the memory controller 5 gives a clock signal from the external interface 4 to a register controller 31a (to be described later) of the processor element 3a via the clock signal 41c.

  Further, as described above, the memory controller 5 places the data stored in the memory 6 provided outside the SIMD type processor 1 on the data bus 41d as 8-bit parallel data in the present embodiment. The 8-bit parallel data can be appropriately changed according to the data. The data bus 41d is also used when the processed data held in the register 31b is sent to the memory 6 provided outside the SIMD type processor 1.

  Note that the memory 6 stores data to be subjected to arithmetic processing and stores data subjected to arithmetic processing, and there is no problem even if these memories 6 are provided inside the SIMD type processor 1. Also, data transfer between the memory controller 5 and the memory 6 is handled as being transferred as 8-bit parallel data in this embodiment, but there is no problem even if it is appropriately changed according to the data. Other operations performed by the memory controller 5 will be described later.

  In addition, the global processor 2 includes an ALU 23 that performs arithmetic logic operations and a data RAM 24 that stores operation data in accordance with instructions from the sequence unit 22. Further, the global processor 2 includes a register group 25 for holding data to be processed.

  The register group 25 includes a program counter PC that holds a program address, G0 to G3 registers that are general-purpose registers for storing data for arithmetic processing, and a stack that holds the address of the save destination data RAM at the time of register save and return. Pointer (SP), link register (LS) that holds the address of the caller at the time of a subroutine call, LI and LN registers that hold branch source addresses at the time of IRQ and NMI, and a processor status register that holds the state of the processor (P) is incorporated.

  The register group 25 is connected to a later-described register 35 of the processor element block 3, and data is exchanged with the register 35 under the control of the sequence unit 22.

  As shown in FIGS. 1 and 3, the processor element block 3 includes a register file 31, a multiplexer 32, a shift / extension circuit 33, an arithmetic logic unit 34 (hereinafter referred to as “ALU 34”), and a register 35 as one unit. A plurality of processor elements 3a. The register file 31 includes 32 8-bit registers for each processor element 3a. In this embodiment, a set of 256 processor elements has an array configuration. The register file 31 stores R0, R1, R2,... For each processor element (PE) 3a. . . A register called R31 is incorporated. Each register file 31 has one read port and one write port for the arithmetic array 36 and is accessed from the arithmetic array 36 by an 8-bit read / write bus. Of the 32 registers, 24 are accessible from outside the processor, and any register can be read and written by inputting a clock, an address, and read / write control from the outside.

  Access from the outside of the register allows one register of each processor element (PE) to be accessed by one external port, and the number (0 to 255) of the processor element (PE) is designated by an address input from the outside. Therefore, a total of 24 external ports for register access are installed. Access from the outside is 16-bit data in one set of even-numbered processor elements (PE) and odd-numbered processor elements (PE), and two registers are accessed simultaneously by one access.

  In the present embodiment, the number of processor elements 3a is assumed to be 256. However, the number of processor elements 3a is not limited to this, and may be changed as appropriate. Addresses 0 to 255 are assigned to the processor element 3a in the order of closeness to the external interface 4 by the sequence unit 22 of the global processor 2.

  The register file 31 of the processor element 3a includes a register controller 31a and two types of registers 31b and 31c. In this embodiment, as shown in FIG. 3 and FIG. 4, for each unit of processor element 3a, 24 sets of register controller 31a and register 31b are provided, and 8 registers 31c are further provided. 4 shows a part of the register file 31 in the two sets of processor elements 3a, and 1PE in FIGS. 3 and 4 represents one processor element 3a. Here, in the present embodiment, the registers 31b and 31c are handled as 8-bit registers, but the present invention is not limited to this and may be used with appropriate modifications.

  As shown in FIG. 4, the register controller 31a is connected to the external interface 4 via the address bus 41a, the read / write signal 41b, and the clock signal 41c described above. When the register controller 31a is supplied from the memory controller 5 to the external interface 4 and receives an address designation signal via the address bus 41a, the register controller 31a decodes the address designation signal. If the decoded address matches the address assigned to its own processor element 3a, it is given from the memory controller 5 to the external interface 4 and read / read in synchronization with the clock signal from the clock signal 41c. A read / write instruction signal sent from the memory controller 5 is obtained via the write signal 41b. This read / write instruction signal is applied to the register 31b.

  The register 31b holds data input from the outside that will be calculated in the ALU 34, which will be described later, or holds the data processed in the ALU 34 for output to the outside. Alternatively, it functions as an output register. Further, it also has a function as a register 31c, which will be described later, such as temporarily holding data to be processed or calculated data. In this embodiment, the register 31b is handled as one that can hold 8-bit data, but there is no problem even if it is appropriately changed according to the data. When the write instruction signal is given from the register controller 31a described above, the register 31b acquires the data to be processed from the data bus 41d and holds it. On the other hand, when a read instruction signal is sent from the register controller 31a, the register 31b gives the data processed and held to the data bus 41d. This data is given from the external interface 4 to the write buffer unit 54 of the memory controller 5 and stored in the memory 6 from the write buffer unit 54.

  The register 31b is connected to the multiplexer 32 via a data bus 36 for transferring 8-bit data in parallel in this embodiment. Data processed by the ALU 34 or data processed by the ALU 34 is transferred to the register 31b via the data bus 36. This transfer is performed via a read signal 26 a and a write signal 26 b connected to the global processor 2 according to an instruction from the sequence unit 22 of the global processor 2. Specifically, when a read instruction signal is sent from the sequence unit 22 of the global processor 2 via the read signal 26a, the register 31b receives the data processed by the ALU 34 sent via the data bus 36. Hold. On the other hand, when a write instruction signal is sent from the sequence unit 22 of the global processor 2 via the write signal 26b, the register 31b puts the data to be processed on the data bus 36. This data is sent to the ALU 34 and processed.

  The register 31c temporarily holds the data to be processed by the register 31b or before the calculated data is supplied to the register 31b. Unlike the register 31b described above, the register 31c does not transfer data to or from the memory 6 via the memory controller 5.

  The arithmetic array 36 includes a multiplexer 32 shift / expansion circuit 33, a 16-bit ALU 34, and a 16-bit register 35. The register 35 includes a 16-bit A register and an F register.

  The calculation by the instruction of the processor element (PE) 3a basically uses the data read from the register file 31 as input on one side of the ALU 34 and the contents of the A register of the register 35 as input on the other side and the result into the A register. Store. Therefore, the operation between the A register and the R0 to R31 registers of the register file 31 is performed. A (7 to 1) multiplexer 32 is placed between the register file 31 and the operation array 36. The data is 1, 2, 3 away from the left in the processor element (PE) direction, and 1, 2, 3 away from the right. Data and center data are selected for calculation. The 8-bit data in the register file 31 is shifted to the left by an arbitrary bit by the shift / extension circuit 33 and input to the ALU 34. In addition, the execution / invalidation control of each processor element 3a is controlled by an 8-bit condition register (T) (not shown) so that only a specific processor element 3a can be selected as an operation target. ing.

  As described above, the multiplexer 32 is connected to the data bus 36 provided in its own processor element 3a, and is also connected to the data bus 36 provided in the three adjacent processor elements 3a. The multiplexer 32 selects one of the seven processor elements 3 a and sends the data held in the register registers 31 b and 31 c in the selected processor element 3 a to the ALU 34. Alternatively, the data processed by the ALU 34 is sent to the register registers 31b and 31c in the selected processor element 3a. As a result, arithmetic processing using data held in the register registers 31b and 31c in the adjacent processor element 3a becomes possible, and the arithmetic processing capability of the SIMD type processor 1 can be enhanced.

  The shift / extension circuit 33 shifts the data sent from the multiplexer 32 by a predetermined bit and sends it to the ALU 34. Alternatively, the arithmetically processed data sent from the ALU 34 is shifted by a predetermined bit and sent to the multiplexer 32.

  The ALU 34 performs arithmetic logic operations based on the data sent from the shift / expansion circuit 33 and the data held in the register 35. In this embodiment, the ALU 34 is handled as being capable of handling 16-bit data, but there is no problem even if it is appropriately changed according to the data. The processed data is held in the register 35 and transferred to the shift / expansion circuit 33 or transferred to the general-purpose register 25 of the global processor 2.

Next, external access to the register file 31 of the processor element 3a will be described with reference to FIG. In FIG. 4, the external port of the external in tough Esu 4 8-bit address, the read / write selection signal indicating a write operation to a high level during a read operation to a low level when the clock indicating the timing of the transfer is a transfer data 8 It consists of bit data. These signals are connected to the external interface 4 of the processor, where they are timing and buffered, and converted into addresses, read / writes, clocks, and data as internal signals.

These signals are supplied to each register of the register file 31. However, only the processor element 3a corresponding to the address indicating each processor element 3a... Decodes the address for each processor element 3a. Do it. Therefore, each processor element 3a is provided with a register controller 31a that performs address decoding and read / write control. The input / output register 31b transfers data to the data bus 41d connected to the external interface 4 based on the read / write instruction signals (write signal W1, read signal R1) given from the read / write signal 41b. . For input and output register 31b is used for transferring both the operation array 36 data has the other input and output ports are created in global processor 2 by the instruction, the read signal 26a and the write signal 26b from the given et the light (W2) In response to the read (R2) control signal, data is transferred from the data bus 37 (D2) connected to the arithmetic array 36.

  In FIG. 4, only the configuration for two processor elements 3a is shown, but in order to match the configuration of the 256 processor elements 3a ... in FIG. 3, 256 sets of register controllers 31a and register files 31b are required. Become. In order to select 256 sets, the bit width of the address is 8 bits. Therefore, the bit width of the address also changes as the number of processor elements 3a increases or decreases. The bit width of the data is 8 bits here, but it varies depending on the amount of data transferred at one time.

  Since the SIMD type processor 1 according to the present embodiment configured as described above performs the following operation, the following advantages can be obtained.

  When the memory controller 5 sends the data stored in the memory 6 to the processor element 3a, by designating the address assigned to the processor element 3a, only one clock signal is input. Data can be sent to the processor element 3a. For example, if it is desired to transfer data only to the even-numbered processor element 3a, the even-numbered processor element 3a may be addressed. Therefore, since there is no need to transfer data to the odd-numbered processor elements 3a, the data transfer can be performed at high speed, and the data processing can be performed at high speed.

  On the contrary, even when the arithmetically processed data held in the register 31b is transferred to the memory 5, the memory controller 5 designates the address assigned to the processor element 3a, so that 1 The data held in the register 31b of the designated processor element 3a can be transferred to the memory 6 only by inputting the clock signal for the first time. Accordingly, even in this case, only necessary data can be transferred, so that the data transfer can be performed at a high speed, and the data processing can be performed at a high speed.

  As described above, 24 registers 31b provided for each processor element 3a hold data to be processed or hold data that has been processed, so-called input registers. Or functions as an output register. For example, data sent from the memory controller 5 to the processor element 3a, ie, input data is 56 bits, data sent from the processor element 3a to the memory controller 5, ie, output data is 32 bits, and temporarily Consider an application where the data to be retained is 80 bits. In this case, seven registers 31b are used as holding 56-bit input data (8 bits × 7 = 56 bits), and four registers 31b are used as holding 32-bit output data. (8 bits × 4 pieces = 32 bits). Thus, regardless of the number of bits of input data and the number of bits of output data, the sum of the number of bits of input data and the number of bits of output data must exceed 8 bits × 24 = 192 bits. For example, the application can be executed.

  In the present embodiment, eight registers 31c for temporarily storing data are provided for each processor element 3a. Therefore, 8 bits × 8 pieces = 64 bits can be held. However, as in this example, when the data to be temporarily stored is 80 bits, 16 bits (= 80 bits−64 bits) of data cannot be stored only by the register 31c. Even in this case, in the present embodiment, the register 31b also has a function of temporarily holding data as described above. Therefore, 11 (= 24−7−4) registers 31b that are not used are used. Of these, two (8 bits × 2 = 16 bits) may be used for temporary data retention.

  Thus, since the usage of the register 31b is flexible, data processing that flexibly corresponds to the number of data bits is possible. This has the advantage that the range of applications that can be processed by the SIMD type processor 1 is increased, and the usage is expanded.

  In the above embodiment, the external port of the external interface 4 is described as an external terminal. However, as in the embodiment of FIG. 5, the transfer destination memory 6 and the memory transfer block 7 are mounted on the same chip. In particular, even when an external port is not output as an external terminal, each of the processor elements 3a... In the memory transfer block 7 etc. mounted on the same chip by address decoding and read / write control in units of the processor elements 3a. Any register can be accessed.

  Next, a modified example of the above embodiment will be described with reference to FIG. The configuration shown in FIG. 6 has two basic configurations shown in FIG. That is, in the embodiment shown in FIG. 3, there are 24 input / output registers 31b in total, and 8 are operation registers 31c used for temporary data storage for operation processing accessible only from the operation array 36. is there. Since these two types of registers are 32 in total, for example, in an application that requires 56 bits of input data, 32 bits of output data, and 80 bits for temporary data retention, 7 input / output registers 31b are externally provided. This can be realized by assigning four input / output registers 31b as external output registers and a total of ten operation registers 31c and two input / output registers 31b for temporary data storage. In other words, if the total of the bit width of input data and output data is up to 192 bits and the total bit width including the bit width of temporary data retention is up to 256 bits, the register usage can be freely set Can be realized. On the other hand, in the conventional processor, the input register, the output register, and the arithmetic register have a fixed bit width, and thus an application exceeding any one of the bit widths cannot be realized.

(Second Embodiment)
A second embodiment of the SIMD type processor 1 according to the present invention will be described below with reference to FIG. Here, the points different from the first embodiment described above will be described, and the description of the same points will be omitted. Moreover, the same code | symbol is attached | subjected about the same component as 1st Embodiment mentioned above.

  The SIMD type processor 1 in the second embodiment assigns even numbers and odd numbers to two adjacent processor elements 3a as one set, and assigns the same address to this set of processor elements 3a. It is characterized by. Further, an even data bus 46a for the processor element 3a to which the even number is assigned and an odd data bus 46b for the processor element 3a to which the odd number is assigned are respectively assigned to the processor elements 3a of each set. It is characterized by being. Further, 16 bits may be transferred in parallel between the memory controller 4 and the memories 5 and 6 provided outside the SIMD type processor 1 instead of 8 bits as in the first embodiment. Features. This 16-bit data is composed of 8 bits given to the processor element 3a assigned with the even number and 8 bits given to the processor element 3a assigned with the odd number. Hereinafter, this embodiment will be specifically described.

  First, an I / O address, data, and control signal are given from the global processor 2 to the memory controller 5 via a bus. The global processor 2 sets commands such as an operation method in some operation setting registers (not shown) of the memory controller 5. Finally, the global processor 2 writes a start code in a start register (not shown) of the memory controller 5 so that the memory controller 5 automatically performs an operation according to the setting.

  When receiving the address control signal from the memory controller 5, the external interface 4 sends an address designation signal to the processor element block 3 via the address bus 41a. Thereby, a set of processor elements 3a, ie two processor elements 3a, are addressed simultaneously. The register controller 31a decodes the address designation signal sent, and if the decoded address matches the address assigned to itself, the register controller 31a sends the clock sent from the memory controller 5 via the clock signal 41c. In synchronization with the signal, a read / write instruction signal sent from the memory controller 4 is obtained via the read / write signal 45a or 45b. Specifically, the register controller 31a to which the even number is assigned obtains the read / write instruction signal sent from the memory controller 4 via the even read / write signal 45a. On the other hand, the register controller 31a to which the odd number is assigned obtains the read / write instruction signal sent from the memory controller 4 via the odd read / write signal 45b. At this time, the read / write instruction signals sent to the register controller 31a of the processor element 3a constituting the set may be different. That is, when the instruction signal sent to the register controller 31a assigned with the even number is a read instruction, the instruction signal sent to the register controller 31a assigned with the odd number may be a write instruction. The read / write instruction signal is given to the register 31b.

  When a write instruction signal is sent from the register controller 31a to both processor elements 3a, the register 31b of the processor element 3a to which the even number is assigned uses the data (8 bits) to be processed for an even number. Obtained from the data bus 46a and held. Further, the register 31b of the processor element 3a to which the odd number is assigned acquires the data (8 bits) to be processed from the odd data bus 46b and holds it. On the other hand, when a read instruction signal is sent from the register controller 31a to both the processor elements 3a, the register 31b of the processor element 3a to which the even number is assigned receives the processed data (8 bits). The data is sent to the even data bus 46a. In addition, the register 31b of the processor element 3a to which the odd number is assigned sends the arithmetically processed data (8 bits) to the odd data bus 46b.

  As described above, data can be transferred to the processor element 3a to which the even number is assigned, and can be transferred to the processor element 3a to which the odd number is assigned. For this reason, the number of times of data transfer can be reduced, and data transfer can be performed at high speed. Therefore, data processing can be performed at high speed. Also in the present embodiment, the same advantages as in the first embodiment can be obtained by addressing the processor element 3a as in the first embodiment.

  Next, a modified example of the above embodiment will be described with reference to FIG. The configuration shown in FIG. 8 has two basic configurations shown in FIG. That is, in the embodiment shown in FIG. 3, there are 24 input / output registers 31b in total, and 8 are operation registers 31c used for temporary data storage for operation processing accessible only from the operation array 36. is there. Since these two types of registers are 32 in total, for example, in an application that requires 56 bits of input data, 32 bits of output data, and 80 bits for temporary data retention, 7 input / output registers 31b are externally provided. This can be realized by assigning four input / output registers 31b as external output registers and a total of ten operation registers 31c and two input / output registers 31b for temporary data storage. In other words, if the total of the bit width of input data and output data is up to 192 bits and the total bit width including the bit width of temporary data retention is up to 256 bits, the register usage can be freely set Can be realized.

(Third embodiment)
A third embodiment of the SIMD type processor 1 according to the present invention will be described below with reference to FIG. In the second embodiment described above, the processor element 3a is addressed. However, the present embodiment is not applied to the addressing specification of the processor element 3a, but applied to a pointer specifying method, that is, a serial access memory method. Is. Here, the points different from the second embodiment described above will be described, and the description of the same points will be omitted. Moreover, the same code | symbol is attached | subjected about the same component as 2nd Embodiment mentioned above.

  First, an I / O address, data, and control signal are given from the global processor 2 to the memory controller 5 via a bus. The global processor 2 sets commands such as an operation method in some operation setting registers (not shown) of the memory controller 5. Finally, the global processor 2 writes a start code in a start register (not shown) of the memory controller 5 so that the memory controller 5 automatically performs an operation according to the setting. The memory controller 5 generates this reset signal based on the command of the global processor 2 and sends it to the processor element block 3 from the external interface 4 via the reset signal 47. As a result, the register controller 31a is reset. Then, a clock signal is sent from the memory controller 5 to the register controller 31a closest to the external interface 4 via the external interface 4 and the clock signal 41c. In synchronization with this clock signal, the register controller 31a obtains a read / write instruction signal sent from the memory controller 5 via the read / write signal 45a or 45b. This read / write instruction signal is applied to the register 31b of the processor element 3a to which the even number is assigned and to the register 31b of the processor element 3a to which the odd number is assigned. At this time, the read / write instruction signals sent to the register controller 31a of the processor element 3a constituting one set may be different from each other as in the case of the second embodiment.

  As a result, as in the case of the second embodiment described above, data can be transferred to the processor element 3a assigned with an even number by one pointer designation, and can also be transferred to the processor element 3a assigned with an odd number. For this reason, the number of times of data transfer can be reduced, and data transfer can be performed at high speed. Therefore, data processing can be performed at high speed.

(Fourth embodiment)
A fourth embodiment of the SIMD type processor 1 according to the present invention will be described below with reference to FIGS. Here, the points different from the first embodiment described above will be described, and the description of the same points will be omitted. Moreover, the same code | symbol is attached | subjected about the same component as 1st Embodiment mentioned above.

  In the present embodiment, as shown in FIG. 10, a line buffer 61 is separately provided outside the processor element 3a. In FIG. 10, two line buffers 61 are shown, but the number of line buffers 61 may be changed as appropriate. In this line buffer 61, calculation processing has been completed, but data necessary for referring to the upper and lower pixels of the target pixel is held, or when the number of pixels in one line is large, the processor element 3a. It is used for holding the number of processed pixels exceeding. In FIG. 10, the line buffer 61 is connected to the input / output register file 31, and a part of the data held in the input / output register file 31 is sent to and held in the line buffer 61. Further, the data held in the line buffer 61 is sent to the input / output register file 31 as necessary, and used as operation processing data. Here, each block of the input / output register file 31 means 256 register controllers 31a and 31b arranged in a line horizontally in FIG.

  As in the embodiment described above, a processor having 256 processor elements 3a... Can store data in the internal register file 31 up to 256 pixels. When the number of pixels exceeds that, the same line is divided and held in a plurality of registers. By having the line buffer 61 outside as described above, it is possible to fetch data from the line buffer 61 in units of 256 pixels, and by repeatedly performing the same processing for lines of 256 pixels or more, the number of pixels can be increased as much as possible. Can do. However, the upper limit of the number of images is determined by the capacity of the line buffer 61. Thus, by providing the line buffer 61 outside, even if the number of pixels in one line increases, the processing can be easily performed.

  Also, by holding the data held in the input / output register file 31 in the line buffer 61, the empty input / output register file 31 can be used for other arithmetic processing, and the arithmetic processing can be performed efficiently. Can do. That is, it becomes possible to process data exceeding the capacity of the register 31b of the processor element 3a.

  Note that the line buffer 61 can be separately provided outside the processor element 3a regardless of the type of the register file. That is, as shown in FIG. 11, an input register file having a function of only acquiring and holding data to be processed and an output register file having a function of only outputting the processed data to the data bus 41d. You may connect and provide. In this case, some data held in the output register file is sent to the line buffer 61 and held. Further, the data held in the line buffer 61 is sent to the input register file as necessary, and used as data for arithmetic processing.

It is a block diagram which shows the SIMD type | mold processor in embodiment of this invention. It is a block diagram which shows the structure of the memory controller 5 used for this invention. It is a figure which shows the internal structure of the SIMD type | mold processor in 1st Embodiment of this invention. It is a figure which shows the internal structure of the processor element in 1st Embodiment. FIG. 3 is a block diagram showing an embodiment in which a transfer destination memory and a memory transfer block are mounted on the same chip. It is a figure which shows the internal structure of the processor element in 1st Embodiment. It is a figure which shows the internal structure of the processor element in 2nd Embodiment. It is a figure which shows the internal structure of the processor element in 2nd Embodiment. It is a figure which shows the internal structure of the processor element in 3rd Embodiment. It is a block diagram explaining the connection of the line buffer in 4th Embodiment. It is a block diagram explaining the connection of the line buffer in 4th Embodiment.

1 SIMD type processor 2 Global processor 4 External interface 5 Memory controller 26a Read signal 26b Write signal 31a Register controller 31b Register 34 ALU
41a Address bus 41b Read / write signal 41d Clock signal 45a Even read / write signal 45b Odd read / write signal 46a Even data bus 46b Odd data bus 47 Reset signal

Claims (1)

A plurality of processor elements each having a computing means for computing data and data holding means for holding data computed by the computing means and holding data computed by the computing means, and connected to each of the processor elements Data transfer bus, a designation means for designating a predetermined processor element, an address bus connected to each of the processor elements, and data to be processed are obtained from the data transfer bus and held in the data holding means A signal generating means for providing the data holding means with an acquisition signal for causing the data holding means or an output signal for outputting the processed data held in the data holding means from the data transfer bus,
The data holding means has a first register group having a plurality of registers and a second register group having a plurality of registers, and the designation means addresses a predetermined processor element, and When the signal generating means gives a signal to the predetermined data holding means of the processor element, a predetermined number of registers are selected from the first register group and the second register group in the data holding means, A SIMD type processor characterized in that data is acquired or output from the data transfer bus to a selected register in a data holding means.

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