JP4482356B2 - Image processing method and image processing apparatus using SIMD processor - Google Patents

Description

  The present invention relates to an image processing method and an image processing apparatus using a SIMD type microprocessor.

  As a general image process for binary image data, there is a labeling process in which the same label (for example, ascending numbers) is assigned to connected feature pixels.

  As a method of connection, there are a four-connection concept for determining the connection between the upper, lower, left, and right four pixels of the target pixel, and an eight-connection concept for determining the connection with the surrounding eight pixels by adding an oblique direction to the four connections. However, in the present specification, the explanation will be made with the concept of all four connections as an example. When labeling processing is performed on binary image data arranged two-dimensionally in the storage device, for example, refer to the processing result for the pixel adjacent to the left as viewed from the target pixel or the pixel adjacent to the top. However, sequential processing must be performed in which binary image data is scanned in the right direction (main scanning direction) and the lower direction (sub-scanning direction) in order from the upper left pixel. In this sequential processing, the processing time becomes enormous.

  In addition, when two or more areas to which different labels (temporary labels) are assigned by the process in the front are connected by the process in the rear (when it is determined that they are connected areas), the temporary label The value must be updated and the same label value reassigned. To realize this process, first, the connection information between the temporary labels is stored, and after the provisional labeling process for all the pixels is completed, the connection information is referred to for all the connected characteristic pixels. Until the same label is assigned, it is conceivable to perform a process of repeatedly scanning the image data (this labeling process). However, if multiple areas with different labels are indirectly linked, etc., there is a possibility that an enormous storage area may be required unless the connection information storage method is devised. There is a possibility that a part of the connection information is lost.

  By the way, the SIMD type microprocessor can simultaneously execute the same arithmetic processing with respect to a plurality of data with one instruction. With this structure, the SIMD type microprocessor is frequently used in processing (for example, image processing in a digital copier, etc.) that performs the same operation all at once although the amount of data is very large.

  In normal image processing in a SIMD type microprocessor, a plurality of arithmetic units (Processor Element [PE]; processor elements) are arranged in the main scanning direction, and high-speed arithmetic is performed by simultaneously executing the same arithmetic on a plurality of data. Processing is possible.

  Even in this SIMD type microprocessor, how to perform the above-described labeling process is an issue.

  Therefore, in Patent Document 1, the processing time of the labeling process is reduced by processing a part of the image data performed in the provisional labeling process in parallel by a part of the SIMD processor. However, since the processing to be performed for each pixel is complicated, hardware to be added to the SIMD processor for temporary labeling processing becomes large.

Further, in Patent Literature 2, image data arranged in a two-dimensional manner is converted into temporary label values that are already assigned to pixels adjacent to the left and pixels adjacent to the top in parallel for each pixel in the diagonal direction. With reference to the above, the provisional labeling process performs all the processing on the image data performed in the provisional labeling process by the parallel processing by the SIMD processor. In addition, since more PEs are required than the number of pixels existing in one line, the processing capacity of SIMD calculation is reduced.
Japanese Patent No. 2734959 JP 2002-230540 A

  The present invention reduces the processing time by adding simple hardware such as a data control device and a storage device to the SIMD type microprocessor, and processing a part of the provisional labeling process in parallel by the SIMD type microprocessor. An object of the present invention is to efficiently perform labeling processing even when binary image data of a complicated figure is given. It is another object of the present invention to speed up the temporary labeling process by reducing the number of times a predetermined memory is accessed in the temporary labeling process.

The present invention has been made to achieve the above object.
The image processing apparatus according to claim 1 according to the present invention,
A SIMD type microprocessor having a plurality of processor elements for processing a plurality of data;
A data control device connected to a data transfer port for accessing a general-purpose register built in each processor element from outside the processor;
An image processing apparatus that performs provisional labeling processing on binary image data arranged in a two-dimensional manner by determining whether or not adjacent pixels in the main scanning direction are connected in the data control apparatus. is there. In the image processing apparatus,
A data register for storing pixel data read from the data transfer port;
A label counter for newly generating a temporary label by the data control device;
A label register for storing a temporary label assigned to the previous pixel;
A memory for storing connection information between linked temporary labels;
The temporary label assigned to the pixel data read from the data transfer port is obtained from the data register data, the temporary label counter data, the label register data, and the connection information between the temporary labels read from the memory, A label controller to determine;
A memory control device for determining an address and data for controlling the memory from a processing result of the label control device;
And an external interface control unit that controls the data transfer port so that pixel data can be sequentially read from the left and the right in the main scanning direction with respect to the target binary image data.

An image processing apparatus according to claim 2 of the present invention is provided.
The connection information between the temporary labels stored in the memory is checked by scanning once in the ascending order of the address, and a temporary label that is missing is found during the labeling process, and is larger than the temporary label that is missing. The temporary label of the value is shifted forward so that there are no missing temporary labels, so that the connection information between the temporary labels is updated to the table conversion data for converting from the temporary label to the actual label. Being
An image processing apparatus according to claim 1 .

An image processing apparatus according to claim 3 of the present invention is provided.
The data control device sequentially reads out the pixel data assigned the temporary label from the data transfer port, and refers to the table conversion data for converting the temporary label stored in the memory into the actual label. Configured to convert a label to a book label,
An image processing apparatus according to claim 1 .

An image processing apparatus according to claim 4 of the present invention is provided.
The data control device has a line buffer for temporarily storing image data being processed outside of the data control device, and the image data after provisional labeling processing performed by scanning from the left side in the main scanning direction of the image data is 1 Store until line processing is complete,
After the processing for one line is completed, the image data stored in the line buffer is read from the right side in the main scanning direction so that temporary labeling processing can be performed.
The image processing apparatus according to claim 1 .

  By using the present invention, the following effects can be obtained.

  The process of determining the connection of pixels in the main scanning direction during the temporary labeling process is performed by scanning twice from the left and the right in the main scanning direction for each target line, and the connection information between different temporary labels is updated. The provisional labeling process can be performed at a high speed by reducing the processing for the connection, and the procedure for describing the connection information can be devised to save the memory used for storing the connection information.

  The provisional labeling process can be realized by adding simple hardware (data control device, memory, etc.) to the SIMD type microprocessor. Similarly, by adding simple hardware, the connection information between temporary labels can be updated to the table conversion data used in the main labeling process, and the main labeling process can also be realized. It becomes like this.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 11 is a block diagram showing the configuration of the image processing apparatus according to the present invention. The image processing apparatus includes a SIMD type microprocessor 2 and a data control apparatus 11. Further, the SIMD type microprocessor 2 is generally composed of a global processor 4, a register file 6, an operation array 8, and an external interface 7.

(1) Global processor 4
The global processor 4 itself is a so-called SISD (Single Instruction Stream, Single Data Stream) type processor. A program RAM 10 and a data RAM 12 are built in (see FIG. 12), and the program is decoded to generate various control signals. This control signal is supplied to the register file 6, the arithmetic array 8, and the data control device 11 in addition to the control of various built-in blocks. When a GP (global processor) instruction is executed, various arithmetic processes and program control processes are performed using a built-in general-purpose register, an ALU (arithmetic logic unit), and the like.

(2) Register file 6
It holds data processed by PE (processor element) instructions. As is well known, the PE (processor element) 3 is a structural unit that executes individual operations in a single instruction-stream (SIMD) type microprocessor. As shown in the register file 6 and the operation array 8 in FIG. 12, the SIMD type microprocessor 2 in FIG. 12 includes 256 PE3. The PE instruction is a SIMD type instruction, and simultaneously performs the same processing on a plurality of data held in the register file 6. Control of reading / writing of data from the register file 6 is performed by control from the global processor 4. The read data is sent to the arithmetic array 8 and is written in the register file 6 after the arithmetic processing in the arithmetic array 8.

  Further, the register file 6 can be accessed from the data control device 11 outside the processor via the external interface 7, and read / write to a specific register is performed from the outside separately from the control of the global processor 4. Is called.

(3) Arithmetic array 8
Processing of PE instruction is performed. All processing control is performed from the global processor 4.

(4) Data control device 11
The clock, address, and read / write control are output to the port of the external interface 7, and data can be read from the register of any PE3 and processed. All processing control is performed from the global processor 4.

  FIG. 12 is a block diagram showing a more detailed configuration of the SIMD type microprocessor 2 according to the present invention.

  The global processor 4 includes a program RAM 10 for storing the program of the processor 2 and a data RAM 12 for storing operation data. Furthermore, a program counter (PC) 14 that holds a program address, G0, G1, G2, and G3 registers (16, 18, 20, and 22), which are general-purpose registers for storing data for arithmetic processing, A stack pointer (SP) 24 that holds the address of the save destination data RAM, a link register (LS) 26 that holds the address of the call source at the time of a subroutine call, and an NMI (Non-Non−) when IRQ (Interrupt Request) A LI register 28 and an LN register 30 that hold a branch source address at the time of maskable interrupt request (inhibit disable interrupt request), and a processor status register (P) 32 that holds the state of the processor are incorporated.

  The GP instruction is executed using these registers, an instruction decoder (not shown), an ALU, a memory control circuit, an interrupt control circuit, an external I / O control circuit, and a GP operation control circuit.

  When executing the PE instruction, the instruction decoder (not shown), the register file control circuit (not shown), and the PE operation control circuit (not shown) are used to control the register file 6 and the operation array 8. I do.

  The register file 6 incorporates 32 8-bit registers in one PE unit, and (32) sets of 256 PEs have an array configuration. The register 34 is called R0, R1, R2,... R31 for each PE. Each register 34 has one read port and one write port for the arithmetic array, and is accessed from the arithmetic array by an 8-bit read / write bus. Of the 32 registers, 24 (R0 to R23) are accessible from the outside of the processor via the external interface 7, and the clock (CLK), address (Address), and read / write control (RWB) are input from the outside. By doing so, it is possible to read / write from / to any register 34.

  In accessing from the outside of the register 34, one register 34 of each PE can be accessed by one external port. The PE number (0 to 255) is designated by an address input from the outside. Therefore, a total of 24 external ports for register access are installed. Further, external access is performed with 16-bit data, and two registers (one set of even-numbered PE registers and odd-numbered PE registers) are accessed simultaneously by one access.

  The arithmetic array 8 includes a 16-bit ALU 36, a 16-bit A register 38, and an F register 40. The operation by the PE instruction is performed by using the data read from the register file 6 or the data supplied from the global processor 4 as an input on one side of the ALU 36 and the content of the A register 38 as an input on the other side. The calculation result is stored in the A register 38. Therefore, an operation is normally performed on the data supplied from the R0 to R31 register 34 or the global processor 4 and the data stored in the A register 38.

  A 7 to 1 (7 to 1) multiplexer 42 is placed between the register file 6 and the operation array 8. As shown in FIG. 12, when viewed from a certain multiplexer 42, the data in the R0-R31 register 34 included in the three PE3 in the left direction, the data in the R0-R31 register 34 included in the three PE3 in the right direction, It is set so that the data in the R0 to R31 register 34 included in the PE 3 to which it belongs can be selected as an operation target. The 8-bit data of the register file 6 is shifted to the left by an arbitrary bit by the shift / extension circuit 44 and input to the ALU 36.

  Furthermore, the execution / invalidation control of the operation is controlled for each PE 3 by an 8-bit condition register (not shown), and only a specific PE 3 can be selected as an operation target.

<< First Embodiment >>
First, an image processing method according to the first embodiment of the present invention will be described (see FIGS. 1 and 2). In the following, an example of labeling processing when 9 × 9 binarized image data as shown in FIG. It is assumed that the binary image data is arranged two-dimensionally on the register file 6 of PE3. Usually, the number of pixels in one line of image data is larger than the number of PEs. In this case, although not shown, a data transfer device 11 and a memory 15 as a line buffer are arranged in the external interface 7, and image data is stored in the memory (line buffer) 15, and a register of the PE 3 is processed according to processing. The image data may be sequentially transferred to the file 6.

  In this specification, pixel processing is performed from the top to the bottom (particularly on the drawing) in the sub-scanning direction. On the other hand, in the main scanning direction, there are particularly those performed from left to right and those performed from right to left.

The binary image data and (temporary) label handled in this specification are defined as follows.
Binary image data Background pixel: 0000h (represented by a blank in the figure)
Characteristic pixel 8000h (represented by black circles in the figure)
-(Tentative) Label: Number from 0001h to 7FFFh (Indicated in the figure from 0001h to 7FFFh)
Note that “h” at the end of the number as described above indicates hexadecimal notation.

  The reason for this definition is that in the binary image data, the background pixel and the feature pixel need only be determined by the most significant 1 bit of the 16-bit data, and from 0000h including the (provisional) label. This is because the simplicity of processing in which a large number should be determined as a feature pixel is taken into consideration.

First, the flow of the temporary labeling process will be described. The temporary labeling process according to the first embodiment is roughly classified into the following process A1 and process B1.
Process A1... Process for determining pixel connection in the sub-scanning direction in binary image data. This processing is performed by parallel processing in the arithmetic array 8 of PE3 shown in FIG.
Process B1... Process for determining the connection of pixels in the main scanning direction in the binary image data. This processing is performed by sequential processing in the data control device 11 connected to the external interface 7 of the PE 3 shown in FIG.

In the process B1, a 15-bit counter (corresponding to the maximum temporary label 7fffh) is used to newly generate a temporary label, and this counter is called a temporary label counter. In the process B1, the memory 15 for storing connection information between temporary labels is used. The temporary label is associated with the address, and the value of another temporary label connected to the temporary label is described in the data. ing. When the memory data of the address value addr is expressed as RAM [addr], specifically, connection information is stored as follows.
When RAM [addr] = 8000h (initial value, initialized before starting the labeling process), there is no temporary label addr.
When RAM [addr] = addr, there is no other temporary label connected to the temporary label addr, or its own value is the smallest among the plurality of connected temporary labels.
When RAM [addr] = A (A! = 8000h, A! = Addr), the temporary label addr and the temporary label A are connected.

Then, it is the detail of the process A1 and the process B1.
<< Process A1 >>
<Process A1-1>
If a temporary label (0001h to 7fffh) is assigned to the pixel data of the line one line higher than the target line, and the pixel data in the same column of the target line is a feature pixel (8000h), the temporary label Is copied to the target line.

<< Process B1 >>
In the process B1, any of the following processes B1-1 to B1-5 is performed on the target pixel. Which process is executed depends on the data of the target pixel and the pixel immediately before the target pixel (when the image data is scanned from the left to the right in the main scanning direction, the pixel adjacent to the left of the target pixel). It is determined by a combination with the assigned temporary label. In the process B1, a process for updating the connection information between the temporary labels is also performed.

<Process B1-1>
When the target pixel is the background pixel (0000h), 0000h is written back to the target pixel as it is. The process of updating the value of the temporary label counter, the target pixel data, and the connection information after the process is as follows.
・ Temporary label counter value: No increment ・ Target pixel data: 0000h
・ Update connection information: Do nothing

<Process B1-2>
When the pixel immediately before the target pixel is the background pixel (0000h) and the target pixel is the feature pixel (8000h), the value of the temporary label counter is incremented by 1, a new temporary label is generated, and assigned to the target pixel. The process of updating the value of the temporary label counter, the target pixel data, and the connection information after the process is as follows.
Temporary label counter value: 1 increment ・ Target pixel data: Temporary label counter value after incrementing ・ Update of connection information: RAM [temporary label counter value] = temporary label counter value

<Process B1-3>
When the pixel immediately before the target pixel is a background pixel (0000h) and the target pixel is a temporary label (value lab_A: 0001h to 7fffh), the value of RAM [lab_A] is assigned to the target pixel as a temporary label. The process of updating the value of the temporary label counter, the target pixel data, and the connection information after the process is as follows.
-Temporary label counter value: No increment-Target pixel data: RAM [lab_A]
・ Update connection information: Do nothing.

<Process B1-4>
When the previous pixel of the target pixel is a temporary label (value lab_A: 0001h to 7fffh) and the target pixel is a feature pixel (8000h), the same temporary label as the temporary label lab_A assigned to the previous pixel is targeted Assign to pixels. The process of updating the value of the temporary label counter, the target pixel data, and the connection information after the process is as follows.
-Temporary label counter value: No increment-Target pixel data: lab_A
・ Update connection information: Do nothing

<Process B1-5>
When the pixel immediately before the target pixel is a temporary label (value lab_A: 0001h to 7fffh) and the target pixel is a temporary label (value lab_B: 0001h to 7fffh), the value of lab_A is compared with the value of RAM [lab_B] Is assigned to the target pixel as a temporary label. The process of updating the value of the temporary label counter, the target pixel data, and the connection information after the process is as follows. Here, the minimum value of a and b is expressed as min (a, b), and the maximum value is expressed as max (a, b).
-Temporary label counter value: No increment-Target pixel data: min (lab_A, RAM [lab_B])
Connection information update: RAM [max (lab_A, RAM [lab_B])] = min (lab_A, RAM [lab_B])

  Normally, when pixel concatenation processing by sequential processing such as the above processing B1 is performed only from one direction of image data, different temporary labels collide with each other, and the connection information between the temporary labels is updated (processing B1-5). Each time, the data in the memory 15 is checked for the number of existing temporary labels, and the smallest value among the other temporary labels connected to itself is left as connection information. Processing has to be performed, and the more temporary labels that are present, the more time is required for the temporary labeling processing.

  In the present embodiment, pixels in the main scanning direction that perform sequential processing are connected twice from the left and right in the main scanning direction for each line of image data. Therefore, the same temporary label is assigned to all connected pixels in the target line. Then, the process for rewriting the connection information can be omitted.

  FIGS. 3 (1), (2), (3),... To FIG. 8 (19) show examples in which the temporary labeling processing of the present embodiment is performed on the binary image data of FIG. . This series of provisional labeling processing examples shows the state of the image at the time when both the processing from the left and the right in the main scanning direction is completed, except for the processing of the sixth line and the eighth line.

  Next, a description will be given of the main labeling process in which the same label is reassigned to different connected temporary labels for the image data after the provisional labeling process shown in FIG. In the present labeling process, connection information between temporary labels created during the temporary labeling process is used as table conversion data. At this time, connection information immediately after the provisional labeling process as shown in FIG. 8 (20) is used as it is, provisional label 1 → 1, provisional label 2 → 2, provisional label 3 → 2, provisional label 4 → 2, provisional label. If this label is assigned such as 5 → 3 and temporary label 6 → 5, a missing label such as “label 4” may appear.

  For this reason, before performing the main labeling process, the following process C1 is performed on the connection information between the temporary labels, and a process of rewriting the appropriate table conversion data for the main labeling process is required. In the process C1, one counter for counting the label value assigned as the actual label is used. This counter will be referred to as the present label counter.

<< Process C1 >>
In the process C1, any one of the following processes C1-1 to C1-2 is performed on the data in the memory 15, and RAM [addr] = 8000h (indicating that there is no temporary label corresponding to the initial value, addr). Until it becomes, addr is incremented from 1 in ascending order and executed. This label counter is initialized to “0000h” before the processing is started.

<Process C1-1>
When RAM [addr] = addr, the label counter is incremented by 1, and the incremented value is written back to RAM [addr].
<Process C1-2>
RAM [addr]! When = addr, the value of RAM [RAM [addr]] is written back to RAM [addr].

FIG. 9 (21) shows the result of executing the process C1 on the connection information of FIG. 8 (20). First, the initial value of this label counter is set to 0, and the initial value of addr is set to 1.
RAM [1] = 1
So, the incremented counter value 1 is written back to RAM [1],
RAM [2] = 2
So, the incremented counter value 2 is written back to RAM [2],
RAM [3] = 2 (! = 3)
So RAM [RAM [3]] = RAM [2] = 2 is written back to RAM [3],
In this way, the value of addr is incremented by 1 in order.
Since RAM [7] = 8000h, the processing ends at that time.

  This labeling process performed using the table conversion data created by the process C1 will be described as process D1 below.

<< Process D1 >>
In the process D1, the image data after the provisional labeling process is sequentially scanned in the main scanning direction and the sub-scanning direction, and any one of the following processes D1-1 to D1-2 is performed on the target pixel.
<Process D1-1>
When the target pixel is the background pixel (0000h), 0000h is written back to the target pixel as it is.
<Process D1-2>
When the target pixel is a temporary label (value lab_A: 0001h to 7fffh), RAM [lab_A] is written back to the target pixel as the main label.

  FIG. 9 (22) shows the result of performing the main labeling process D1 on the image data after the provisional labeling process shown in FIG. 9 (21).

  FIG. 2 shows a schematic flowchart of a series of labeling processes by the processes A1, B1, C1, and D1 described above.

<< Second Embodiment >>
FIG. 1 is a block diagram showing a configuration of a data control apparatus 11 according to the second embodiment of the present invention. The data control device 11 according to the first embodiment
An external interface control unit 52 that controls the external interface by supplying clock, address, and read / write control to the external interface 7;
Memory control for controlling the memory 15 by supplying clock, address, read / write control, and data to the memory 15 for storing connection information between temporary labels connected to the data control device 11 Part 64,
Read the pixel data read from the register file of PE3 via the external interface 7, the data read from the memory 15, and the value of the temporary label assigned to the pixel adjacent to the target pixel in the previous process, Label determination circuit 58 for determining the value of the temporary label to be assigned to
A counter 56 for newly generating a (temporary) label based on the determination result in the label determination circuit;
The temporary label generated by the counter 56, the data of the target pixel already assigned with the temporary label, the temporary label assigned to the pixel adjacent to the target pixel in the previous process, and the data read from the memory are input. A multiplexer 60 for outputting the data determined as the temporary label by the label determination circuit 58;
A label register 62 for receiving data from the multiplexer 60 and writing the data back to the external interface 7 as a temporary label
It is composed of

  In the above configuration, among the data read into the label determination circuit 58, the “temporary label assigned to the pixel adjacent to the target pixel in the previous process” is stored in the label register 62 of the target pixel before the process starts. It is equivalent to data. The external interface control unit 52 incorporates an address counter for generating an address to be supplied to the external interface 7. The address counter uses an up / down counter so that pixel data can be transferred from the left or the right in the main scanning direction.

  The memory control unit 64 generates an address from the built-in up counter at the time of memory initialization before the temporary labeling process is started, and issues the value of the built-in register as input data to the memory 15. At the time of the temporary labeling process, according to the algorithm of the process B1, the value of the temporary label counter 56, the data of the target pixel, the value of the label register 62, or the data read from the memory 15 is issued as an address, and the temporary label counter 56 , The value of the label register 62, and the data read from the memory 15 are issued as input data to the memory 15.

<< Third Embodiment >>
The data control device 11 according to the third embodiment has substantially the same configuration as the data control device 11 according to the second embodiment. Therefore, the difference will be mainly described.

  The data control apparatus 11 according to the third embodiment is configured such that the process C1 can be performed in the data control apparatus 11 according to the second embodiment shown in FIG. That is, if the data read from the memory 15 is 8000h (indicating that there is no temporary label corresponding to the initial value and address), the process is terminated. If the data and the address match, this label is displayed. The counter is incremented by 1, and the memory control unit 64 is controlled so as to write back the value of the incremented label counter as data in the memory 15. If the data and the address do not match, the data read from the memory 15 is addressed. As a result, a determination circuit for controlling the memory control unit 64 is added so as to write back the read data as data in the memory 15.

<< Fourth Embodiment >>
The data control device 11 according to the fourth embodiment has substantially the same configuration as the data control device 11 according to the third embodiment. Therefore, the difference will be mainly described.

  The data control apparatus 11 according to the fourth embodiment is configured such that the process D1 can be performed in the data control apparatus 11 according to the third embodiment. That is, when the target pixel is the background pixel (0000h), 0000h is written back to the target pixel as it is, and when the target pixel is the temporary label (value lab_A: 0001h to 7fffh), RAM [lab_A] is written as the main label to the target pixel. This can be realized by adding a determination circuit for controlling the label register 62 so as to return.

<< Fifth Embodiment >>
The data control device 11 according to the fifth embodiment has substantially the same configuration as the data control device 11 according to the fourth embodiment. Therefore, the difference will be mainly described.

  FIG. 10 is a schematic block diagram of the data control device 11 and its peripheral devices according to the fifth embodiment. In the fifth embodiment, a line buffer 80 is provided as a memory for the data control apparatus 11 according to the first embodiment shown in FIG.

  Image data obtained as a result of the process B1 scanned from the left side in the main scanning direction is sequentially transferred to the line buffer 80 until the process for one line is completed. When the processing for one line is completed, image data is read from the line buffer 80 from the right side in the main scanning direction, and processing B1 can be performed.

  If this line buffer 80 does not exist, the data transfer of the frame memory storing the image data → the PE register file → the data control device → the PE register file → the frame memory in the temporary labeling process is processed in one line. It must be repeated until is finished. On the other hand, if the line buffer 80 is used, the frame memory → PE register file → data control device → line buffer (pixel data for one line) → data control device → PE register file → frame memory is simplified. Can be Therefore, the processing speed can be increased.

It is a block diagram which shows the structure of the data control apparatus which concerns on the 2nd Embodiment of this invention. 3 is a schematic flowchart of a series of labeling processes in the image processing method according to the first embodiment of the present invention. (1) is an example of binary image data. The transition of image data and the state of updating the inter-label connection information storage memory <1> when the temporary labeling process is performed on the binary image data of (1) are shown. The transition of the image data and the state <2> of the update of the inter-label connection information storage memory when the temporary labeling process is performed on the binary image data of FIG. The transition of the image data and the state <3> of the update of the inter-label connection information storage memory when the temporary labeling process is performed on the binary image data of FIG. The transition of the image data and the state of updating the inter-label connection information storage memory <4> when the temporary labeling process is performed on the binary image data in FIG. The transition of the image data and the state <5> of updating the inter-label connection information storage memory when the temporary labeling process is performed on the binary image data of FIG. The transition of the image data and the state <6> of updating of the inter-label connection information storage memory when the temporary labeling process is performed on the binary image data of FIG. The transition of the image data and the state <7> of updating the inter-label connection information storage memory when the temporary labeling process is performed on the binary image data of FIG. FIG. 10 is a schematic block diagram of a data control device and its peripheral devices according to a fifth embodiment. It is a block diagram which shows the structure of the image processing apparatus which concerns on this invention. It is a block diagram which shows the further detailed structure of the SIMD type | mold microprocessor which concerns on this invention.

Explanation of symbols

4 ... global processor, 6 ... register file, 7 ... external interface, 11 ... data control device, 15 ... (temporary label connection information storage) memory, 52 ... external interface control 58, label determination circuit, 62, label register, 64, memory control unit.

Claims (4)

A SIMD type microprocessor having a plurality of processor elements for processing a plurality of data;
A data control device connected to a data transfer port for accessing a general-purpose register built in each processor element from outside the processor;
In an image processing apparatus that performs temporary labeling processing on binary image data arranged two-dimensionally by determining whether or not adjacent pixels in the main scanning direction are connected in the data control apparatus. ,
A data register for storing pixel data read from the data transfer port;
A label counter for newly generating a temporary label by the data control device;
A label register for storing a temporary label assigned to the previous pixel;
A memory for storing connection information between linked temporary labels;
The temporary label assigned to the pixel data read from the data transfer port is obtained from the data register data, the temporary label counter data, the label register data, and the connection information between the temporary labels read from the memory, A label controller to determine;
A memory control device for determining an address and data for controlling the memory from a processing result of the label control device;
An external interface control unit for controlling the data transfer port so that pixel data can be sequentially read from the left and the right in the main scanning direction with respect to the target binary image data.
An image processing apparatus comprising: The connection information between the temporary labels stored in the memory is checked by scanning once in the ascending order of the address, and a temporary label that is missing is found during the labeling process, and is larger than the temporary label that is missing. The temporary label of the value is shifted forward so that there are no missing temporary labels, so that the connection information between the temporary labels is updated to the table conversion data for converting from the temporary label to the actual label. Being
The image processing apparatus according to claim 1 . The data control device sequentially reads out the pixel data to which the temporary label is assigned from the data transfer port and refers to the table conversion data for converting the temporary label stored in the memory into the actual label. Configured to convert a label to a book label,
The image processing apparatus according to claim 1 . The data control device has a line buffer for temporarily storing image data being processed outside of the data control device, and the image data after provisional labeling processing performed by scanning from the left side in the main scanning direction of the image data is 1 Store until line processing is complete,
After the processing for one line is completed, the image data stored in the line buffer is read from the right side in the main scanning direction so that temporary labeling processing can be performed.
The image processing apparatus according to claim 1 .

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