JP5369669B2 - SIMD type microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SIMD type microprocessor allowing high-speed simultaneous processing of more image data by improving processing performance during data transfer without increasing a circuit scale or a layout scale. <P>SOLUTION: In the SIMD (Single Instruction-stream, Multiple Data-stream) type microprocessor 1, first word lines 6 are connected to registers having different numbers for each 16 pieces between a plurality of processor elements PE0-PEn, and second word lines 8 are connected to the registers each having the same number between the plurality of processor elements PE0-PEn. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a SIMD (Single Instruction-stream, Multiple Data-stream) type microprocessor that processes a plurality of data in parallel with one arithmetic instruction.

  In recent years, in image processing such as digital copying machines and facsimile machines, image quality has been improved by increasing the number of pixels and diversifying image processing. As the image is improved, the number of data to be processed has increased.

  In such image processing, the same arithmetic processing is often applied to all pixels. Therefore, SIMD (Single Instruction-stream Multiple Data-stream) type microprocessors that perform the same arithmetic processing simultaneously on a plurality of data with one instruction are often used. In this SIMD type microprocessor, the same arithmetic processing can be simultaneously performed on a plurality of data with one instruction.

  The SIMD type microprocessor includes an arithmetic unit and a register in a unit called a processor element, and has a plurality of the processor elements. A global processor is provided as a control unit for simultaneously controlling the plurality of processor elements. By controlling the global processor, it is possible to simultaneously process a plurality of data with one instruction. At this time, each processor element is usually in charge of image processing of one pixel.

  As described above, the SIMD type microprocessor can be easily realized by arranging a plurality of arithmetic units in parallel and simultaneously controlling them by a global processor. Furthermore, since the arithmetic processing is performed by a plurality of processor elements at the same time, the necessary arithmetic processing is performed at a higher speed.

  However, no matter how fast the arithmetic processing can be, if the transfer efficiency of the target data is poor, the effect of the SIMD type microprocessor is reduced. For this reason, it is necessary to access a memory or the like at a speed corresponding to the calculation speed for data transfer. If this speed is not met, the processor performance is determined by the data access speed.

  In an ordinary type SISD (Single Instruction-stream Single Data-stream) type microprocessor, arithmetic data is accessed sequentially from memory by a processor program. In this case, the data access speed is determined by the bit width and transfer time of the memory. To do. If this method is used also in the SIMD type microprocessor, the computation is parallel processing, whereas the data access is sequential processing, so that the processing capability is reduced to the level of the SISD type microprocessor.

  In order to improve the transfer efficiency with this external data, the SIMD type microprocessor does not access the operation target data with the processor instruction, but directly accesses the input / output registers inside the processor from the external memory transfer port. doing. In other words, simultaneously with the execution of the operation by the processor, the data to be processed next is transferred from the external transfer port to the input register, or the processed data is transferred from the output register to the external memory via the external transfer port. The data processing is speeded up by transferring to.

The data transfer flow between the SIMD type microprocessor and the external memory is performed as follows.
(1) Transfer the operation target data from the external memory to the input register via the external transfer port.
(2) The processor starts operation from the register to which operation data has been transferred from the outside.
(3) The processor executes a predetermined operation. During this time, the next operation target data is transferred from the external memory to the input register. Also, if the processed data (result data) is in the output register, the result data is transferred from the output register to the external memory via the external transfer port.
(4) The processor finishes the operation and transfers the result data to the output register.

  As described above, the speed is increased by the external memory data transfer device transferring the calculation data simultaneously with the execution of the calculation of the processor. However, although calculation processing and data transfer can be performed simultaneously, the calculation processing time can be executed simultaneously regardless of the number of processor elements, whereas the data transfer time increases in proportion to the number of processor elements. . In the process of transferring data from the external memory to the register of the processor element, since data is usually transferred to one processor element in one cycle, for example, if it is a SIMD type microprocessor having 512 processor elements This means that 512 cycles are required for data transfer. Therefore, no matter how much processing is performed on 512 processor elements at the same time, the SIMD microprocessor cannot be effective as long as the data cannot be transferred accordingly.

  In order to solve the problem, in Patent Document 1, two sets of data lines from the PE interface are arranged for the even-numbered processor element and the odd-numbered processor element, and a simultaneous access method is applied to the even-numbered processor element and the odd-numbered processor element. A method is described in which the transfer time is halved by using it. Thus, if the bandwidth of the transfer data is increased, the transfer efficiency is improved accordingly.

Japanese Patent Laid-Open No. 2004-228867 provides a plurality of data lines by providing multi-ports at the time of data transfer from a register to an ALU for the problem of a reduction in processing capability related to data array conversion. It is described that a route for transferring to the element is provided. Patent Document 3 also describes that a configuration is adopted in which a different register can be selected at the time of data transfer from a register to an ALU with a plurality of divided word lines, in response to the problem of a decrease in processing capacity related to data array conversion. ing.
Japanese Patent No. 3971535 Japanese Patent No. 4020804 JP 2006-164183 A

  However, in the method described in Patent Document 1, the transfer efficiency is improved by increasing the transfer data bandwidth, but increasing the number of data lines means that a layout area is required. There is a problem that the cost is sacrificed. Considering the processing speed from the register to the arithmetic circuit, it is necessary to make the layout size of the register as small as possible, and the increase in the layout area also affects the performance of the arithmetic speed.

  Furthermore, even the methods described in Patent Documents 2 and 3 have a problem that the circuit scale and the layout area are increased.

  The present invention aims to solve such problems.

  That is, the present invention provides a SIMD type microprocessor capable of improving the processing capability at the time of data transfer without increasing the circuit scale and layout scale and simultaneously processing more image data at a high speed. It is an object.

The invention described in claim 1 controls a plurality of processor elements having n registers (n is a natural number of 2 or more) assigned with a unique number and an arithmetic unit, and operations of the plurality of processor elements. A control unit that controls communication from the n registers to the outside, a first data line to which each of the n registers is connected, and the control unit that connects the first data line A first word line that selects a register that communicates with the arithmetic unit via the second arithmetic line, a second data line to which the registers having the same number between the plurality of processor elements and the external interface are connected, And a second word line for selecting a processor element with which the external interface communicates via the second data line. In IMD microprocessors, the external interface is provided in a manner in correspondence to the respective numbers of the registers, among n number of processor elements, the same first word line in the register of different numbers The first word line is connected to a register between a plurality of processor elements , and the second word line is connected to a register of the same number between a plurality of processor elements. have a SIMD microprocessor, characterized in that.

The invention described in claim 2 controls a plurality of processor elements including n registers (n is a natural number of 2 or more) assigned with a unique number and an arithmetic unit, and operations of the plurality of processor elements. A control unit that controls communication from the n registers to the outside, a first data line to which each of the n registers is connected, and the control unit that connects the first data line A first word line that selects a register that communicates with the arithmetic unit via the second arithmetic line, a second data line to which the registers having the same number between the plurality of processor elements and the external interface are connected, And a second word line for selecting a processor element with which the external interface communicates via the second data line. In IMD microprocessors, among n pieces of processor elements, such that the same in the register of different numbers first word line and the same of said second word lines are connected to each other, the first word line and the second word line is connected to the register among a plurality of processor elements are SIMD microprocessor according to claim Rukoto.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the control unit selects a register that communicates with the arithmetic unit via the first data line. The first word line of another type is further provided, and the same first word line of the same different type is connected to the register of the same number of each processor element .

The invention described in claim 4 has a function of changing at least the connection relation of the first word lines in the invention described in any one of claims 1 to 3 , and the first mode and Switching means for selecting any one of the second modes is further provided . In the first mode, the switching means causes each other between the n processor elements at least for the first word line. A mode in which the first word line is connected to a register among a plurality of processor elements is maintained so that the same first word line is connected to registers of different numbers, and the second In the mode, the n registers in each processor element are divided into a plurality of register groups, and at least the registers in each register group are divided by the switching means. Regarding the first word line, the same first word line is connected to registers having different numbers between the number of processor elements indicated by the number of registers included in the register group in one processor element. As described above, the aspect in which the first word line is connected to a register among a plurality of processor elements is maintained .

According to the first aspect of the present invention , the first word line includes a plurality of processor elements so that the same first word line is connected to registers having different numbers among n processor elements. Since the second word lines are connected to the registers having the same number among the plurality of processor elements, the registers having different numbers can be simultaneously selected for each processor element. The external interface is provided for each register number so that all the external interfaces can transfer data simultaneously. Therefore, external data is simultaneously transferred from each external interface to a register with a different number in each processor element. Can be transferred. In addition, since the data after the arithmetic processing can be read simultaneously without performing array conversion, the data transfer efficiency is improved. Furthermore, since a selected word line of a register used for arithmetic processing is not newly added, the circuit scale and layout scale can be increased.

According to the second aspect of the present invention, the first first word line and the same second word line are connected to the registers having different numbers among the n processor elements. Since the word line and the second word line are connected to a register between a plurality of processor elements, even if the external interface is not provided independently for each register and is controlled simultaneously in synchronization, It is possible to transfer directly to the register used for the above. Therefore, it is possible to configure a register with improved data transfer efficiency without increasing the address signal.

According to a third aspect of the present invention, there is further provided another type of first word line for the control unit to select a register to communicate with the arithmetic unit via the first data line. Since the same different type of first word line is connected to the register of the same number of each processor element, a word line capable of operating at a higher transfer speed according to the application, It is possible to switch between different word lines that can input and output different data in parallel for each external data transfer port. In that case, only one word line is added per register, and the layout scale is rarely increased.

According to the fourth aspect of the present invention, in the first mode, the switching means causes the same first word line to a register having a different number between n processor elements for at least the first word line. Are maintained in such a manner that the first word line is connected to the registers among the plurality of processor elements, and in the second mode, n registers in each processor element include a plurality of registers. Divided into groups, and by the switching means, the number of processor elements indicated by the number of registers included in the register group in one processor element differs at least for the first word line in each of the register groups. A plurality of first word lines are connected so that the same first word line is connected to the number register. Since those aspects which are connected to the register between the processor elements is maintained, thereby enabling to improve the data transfer efficiency for each divide the plurality of register areas.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a SIMD type microprocessor according to the first embodiment of the present invention. FIG. 2 is an explanatory diagram of a register transfer operation in the SIMD type microprocessor shown in FIG.

  The SIMD type microprocessor 1 shown in FIG. 1 includes a global processor 2, a plurality of processor elements PE0 to PEn, and a PE interface 4.

  The global processor 2 as a control unit includes a program RAM for storing programs, a data RAM for storing arithmetic data, a program counter for holding program addresses, a general-purpose register for storing arithmetic processing data, an ALU, The stack pointer that holds the address of the save destination data RAM at the time of register saving and restoration, the link register that holds the address of the call source at the time of a subroutine call, and the branch source address at the time of interrupt and NMI (non-maskable interrupt) A register for holding, a processor status register for holding the state of the global processor 2, a sequence unit for decoding various instructions and generating various control signals, and the like are provided. Then, an instruction is executed using these, and a control signal including a first word line 6 described later is supplied to each of the processor elements PE0 to PEn.

  As shown in FIG. 1, n (n is a natural number of 2 or more) processor elements PE0 to PEn are arranged in one row. Each processor element includes 16 registers from register R0 to register R15, and an ALU 3a.

  The registers R0 to R15 store data calculated by the ALU 3a and data calculated by the ALU 3a. Further, a unique number is assigned to each register, such as 0 for the register R0 and 1 for the register R1.

  The ALU 25 as an arithmetic unit is an arithmetic logic unit, which obtains data stored in the registers R0 to R15 via a first data line 5 to be described later and performs an operation designated by a control signal from the global processor 2. Is output to the registers R0 to R15 via the first data line 5 again.

  The 16 registers R0 to R15 and the ALU 3a are connected to each other by the first data line 5 which is a common data line inside the processor element. Which register the ALU 3a accesses from the global processor 2 The first word line 6 to be output is selected.

  The first word line 6 is a word line for selecting a register of each processor element from the global processor 2, and is connected to a register having a different number for each processor element. For example, the first word line 6 connected to the register R0 of the processor element PE0 shifts the register number by one each time the processor element moves, such as the register R1 in the processor element PE1 and the register R2 in the processor element PE2. Connected. In the present embodiment, if n> 15, the first word line 6 connected to the register R0 of the processor element PE0 is connected to the register R15 of the processor element PE15. Connected to select. In other words, every n pieces are connected to different numbers of registers.

  The PE interface 4 as an external interface is an external transfer port for transferring data between the registers R0 to R15 in the processor elements PE0 to PEn and the SIMD type microprocessor 1. The PE interface 4 is provided with 16 PEIF (R0) to PEIF (R15) for each register number in the processor element. The PEIF (R0) to PEIF (R15) and the registers R0 to R15 of each processor element are provided. Are connected by a second data line 7. That is, the second data line 7 output from the PERF (R0) is connected to the register R0 of each processor element, and the second data line 7 output from the PERF (R1) is connected to the register R1 of each processor element. And so on. That is, PEIF is provided corresponding to each of the plurality of registers.

  A second word line 8 for controlling selection of a processor element for inputting / outputting data using the second data line 7 is output from PEIF (R0) to PEIF (R15) and connected to registers R0 to R15 of each processor element. Has been. That is, as with the second data line 7, the second word line 8 output from the PERF (R0) is connected to the register R0 of each processor element and output from the PERF (R1). The second word line 8 is connected to the register R1 of each processor element and so on. That is, the plurality of processor elements are connected to the same numbered registers.

  Each register of each processor element having the above-described configuration normally stores data corresponding to one pixel, and one pixel is composed of 8-bit or 16-bit data. That is, each register is configured with a width of 8 bits or 16 bits. The n processor elements are configured to correspond to one column of pixel data, and desired image processing can be realized by processing these data simultaneously.

  Next, a method of transferring data to the registers R0 to R15 of the processor elements PE0 to PEn in the SIMD type microprocessor 1 having the above configuration will be described. Conventionally, one PEIF is used to transfer one column of image data to the register of the same number of each processor element. In this embodiment, one column of image data is distributed to all PEIFs for data transfer. I do. For example, the first pixel is transferred from PEIF (R0), the second pixel is transferred from PEIF (R1), and the third pixel is transferred from PEIF (R2). In this way, 16-pixel data can be transferred simultaneously, and the time required for data transfer to the processor elements PE0 to PEn is reduced to 1/16.

  That is, each of PEIF (R0) to PEIF (R15) uses the second data line 7 and the second word line 8 to transfer data to different numbers of registers. Therefore, the first pixel is transferred to the register R0 of the processor element PE0, the second pixel is transferred to the register R1 of the processor element PE1, and the third pixel is transferred to the register R2 of the processor element PE2. The 16th pixel is transferred to the register R15 of the processor element PE15.

  The image data transferred to the registers of the processor elements PE0 to PEn in this way is activated when the above-described global processor 2 activates one of the first word lines 6. The register connected to is selected. The selected data is transferred to the ALU 3a via the first data line 6. Since the data stored in the selected register is originally image data arranged in one column, the image data transferred from the PE interface 4 is not subjected to array conversion on the processor element, and the operation of the ALU 3a is performed. Can be used as data.

  Data after the arithmetic processing is transferred in the reverse order of the processing before the arithmetic processing, and is stored in registers of different numbers between different processor elements, and then 16 pieces of data are simultaneously extracted from the PE interface 4. Therefore, there is no loss of processing time due to data array conversion, and the transfer time reduced to 1/16 leads to a reduction in processing time.

  In the SIMD type microprocessor 1 that performs arithmetic processing such as image data, the processing speed can be improved by performing parallel processing of image data. However, as the number of processor elements increases, the data transfer rate becomes dominant in the processing time, and it can be said that improving the transfer efficiency leads to the performance improvement of the SIMD type microprocessor 1.

  FIG. 2 is a diagram showing the data transfer method described above more simply. For simplification, the case where the number of processor elements is 8 and the number of registers is 4 is taken as an example here. First, in the first data transfer with the PE interface 4, the data is transferred by the second data line 7 and the second word line 8 to the portions of the four processor elements PE 0, PE 1, PE 2, and PE 3 that are surrounded by thick lines. In the second data transfer, data is transferred to the portion surrounded by the thick lines of the four processor elements PE4, PE5, PE6, and PE7. Thereafter, the data of the portions surrounded by the thick lines of all the processor elements are collectively transferred to the ALU 3a side simultaneously by the first data line 5 and the first word line 6, and the arithmetic processing is executed. The data transfer after the arithmetic processing is the same except that the order is reversed.

  In this embodiment, in order to distribute data such as an external memory to a plurality of PEIFs, a bus connection and a selection circuit such as a multiplexer are required. However, most of the SIMD type microprocessor 1 is composed of a plurality of processor elements. Compared to the case of not using multiple PEIFs, it can be said that the influence of circuit addition in the peripheral part is small.

  According to this embodiment, the first word line 6 is connected to a register having a different number for every 16 pieces among the plurality of processor elements PE0 to PEn, and the second word line 8 is connected to the plurality of processor elements PE0 to PEn. Since the PEn is connected to the register having the same number, the PE interface 4 stores the 16 processor elements in different register numbers and transfers the stored data to the ALUs 3a of the processor elements all at once. Therefore, the number of word lines from the global processor 2 is not increased and the layout size is not increased. The circuit configuration on the global processor 2 side can be made completely the same as the conventional example. In short, by using the configuration of the present invention, the transfer speed can be easily improved without increasing the layout size.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. Note that the same parts as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted. FIG. 3 is a block diagram of the SIMD type microprocessor 1 according to the second embodiment of the present invention.

  In this embodiment, in addition to the first embodiment, a first word line 6 ′ and an OR gate 3b are added.

  That is, two word lines are wired per register as a word line for selecting a register from the global processor 2, and are input to the register via the OR gate 3b. One of the word lines is a first word line 6 connected to a register having a different number for each processor element as in the first embodiment, and the other is the same number for each processor element. A first word line 6 'connected to the register. That is, the first word line 6 includes two types of word lines connected to a register having a different number for every n and a word line connected to a register having the same number among a plurality of processor elements. Is provided.

  The first word line 6 'is a word line for transferring data sequentially from one PEIF to each processor element as in the prior art. That is, in this embodiment, the conventional transfer method and the transfer method shown in the first embodiment coexist.

  According to the present embodiment, two of the first word lines 6 and 6 'are wired to each register. Therefore, depending on the application, the mode in which the transfer speed is increased and the data different for each PEIF are used. It is possible to switch the mode to input / output in parallel and use them properly. In that case, only one word line is added per register, and the layout scale is rarely increased.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first and second embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 4 is a block diagram of a SIMD type microprocessor according to the third embodiment of the present invention. FIG. 5 is a block diagram of the WL-Selector of the SIMD type microprocessor shown in FIG. FIG. 6 is an explanatory diagram of a register transfer operation in the SIMD type microprocessor shown in FIG.

  This embodiment is different from the first embodiment in that a WL-Selector 3c is provided between a plurality of registers R0 to R15.

  The WL-Selector 3c as the switching means is a circuit composed of four transfer gates 3d1, 3d2, 3d3, 3d4, two input terminals WLLI, WLRI, and two output terminals WLLO, WLRO per PE. The four transfer gates 3d1, 3d2, 3d3, 3d4 are ON / OFF controlled by SEL and SELN signals input from the global processor 2. The first word line 6 is connected to the input terminals WLLI and WLRI and the output terminals WLLO and WLRO, respectively.

  Explaining the operation of the WL-Selector 3c, the signals SEL and SELN input from the global processor 2 are set to mutually exclusive signal levels. That is, when SEL is at “Hi” level, SELN is set at “Low” level, and when SEL is at “Low” level, SELN is set at “Hi” level. First, when SEL is at “Hi” level and SELN is at “Low” level, the four transfer gates 3d1, 3d2, 3d3, and 3d4 have the transfer gate 3d1 turned off, the transfer gate 3d2 turned on, and the transfer gate 3d3 turned on. Since ON and transfer gate 3d4 are OFF, a signal input from input terminal WLLI is output from output terminal WLRO via transfer gate 3d2, and a signal input from input terminal WLRI passes through transfer gate 3d3. And output from the output terminal WLLO. In other words, the n registers are not divided into a plurality of register groups, and the first mode is selected in which registers each having a different number are selected for every n registers.

  Next, when SEL is at the “Low” level and SELN is at the “Hi” level, the four transfer gates 3d1, 3d2, 3d3, and 3d4 have the transfer gate 3d1 ON, the transfer gate 3d2 OFF, and the transfer gate 3d3 OFF. Since the transfer gate 3d4 is turned on, the signal input from the input terminal WLLI is output from the output terminal WLLO via the transfer gate 3d1, and the signal input from the input terminal WLRI is output via the transfer gate 3d4. Output from terminal WLRO. That is, the n registers are divided into a plurality of register groups, and the mode is switched to the second mode in which different numbers of registers are selected for each number of registers in each register group.

  Therefore, when the SEL is at the “Hi” level and the SELN is at the “Low” level, the first word line 6 is connected across the two blocks. The SEL is at the “Low” level and the SELN is at the “Hi” level. In this case, the first word line 6 is connected so that different registers are selected in the two blocks.

  In the present embodiment, the plurality of registers R0 to R15 are divided into a plurality of blocks by the WL-Selector 3c so that the data transfer format can be changed for each block. For example, in the case of FIG. 4, the 16 registers are divided into 2 +14. At this time, the number of registers in one block may be an arbitrary number. Of course, the number of blocks may be divided into three or more.

  FIG. 6 shows switching of the selection of the first word line 6 in the present embodiment. For the sake of simplicity, FIG. 6 shows an example of the first word line 6 in which the registers R0 and R2 of the processor element PE0 are headed when the register number of 4 is divided into 2 + 2 blocks. . In the figure, the register position through which the arrow passes is selected at the same time.

  In this embodiment, the register is divided from that of the first embodiment. However, the present embodiment may be applied to the second embodiment. In this case, one block of two registers can perform data transfer with a bandwidth using a plurality of PEIFs simultaneously, and the other block can perform data transfer from the same PEIF for each register.

  According to the present embodiment, since the WL-Selector 3c for dividing the plurality of registers R0 to R15 is provided, it is possible to divide the plurality of registers and improve the data transfer efficiency for each region. Therefore, it is possible to achieve a good balance between improvement in data transfer efficiency and parallelism of data transfer.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIG. The same parts as those in the first to third embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 7 is a block diagram of a SIMD type microprocessor 1 according to the fourth embodiment of the present invention.

  In the first to third embodiments, the PE interface 4 exists independently for each register. However, in this embodiment, the PE interface 4 is controlled simultaneously in synchronization. Therefore, the second word line 7 output from the PEIF-Dec 4a which is a block having a function of generating and outputting the second word line 7 in the PE interface 4 is different for each processor element as in the first word line. Connect to the numbered register. For example, the second word line 7 connected to the register R0 of the processor element PE0 is shifted by one, such as the register R1 in the processor element PE1 and the register R2 in the processor element PE2. That is, the first word line 6 and the second word line 8 are connected to a register having a different number for every n pieces among a plurality of processor elements.

  In this way, it is possible to realize transfer to different numbered registers of different processor elements, as in the case where the PE interface 4 is independent for each register.

  Also in this embodiment, the conventional word line connection and register block division described in the second and third embodiments may be performed.

  According to the present embodiment, since both the first word line and the second word line are connected to registers having different numbers for each processor element, data is simultaneously transferred from the PE interface 4 to the registers by a common address signal. It is possible to transfer directly to a register used for arithmetic processing. Therefore, it is possible to configure a register with improved data transfer efficiency without increasing the address signal.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 is a block diagram of a SIMD type microprocessor according to a first embodiment of the present invention. It is explanatory drawing of the register transfer operation | movement in the SIMD type | mold microprocessor shown in FIG. It is a block diagram of the SIMD type | mold microprocessor 1 concerning the 2nd Embodiment of this invention. It is a block diagram of a SIMD type microprocessor according to a third embodiment of the present invention. FIG. 5 is a configuration diagram of a WL-Selector of the SIMD type microprocessor illustrated in FIG. 4. FIG. 5 is an explanatory diagram of a register transfer operation in the SIMD type microprocessor shown in FIG. 4. It is a block diagram of the SIMD type | mold microprocessor 1 concerning the 4th Embodiment of this invention.

Explanation of symbols

1 SIMD type microprocessor 2 Global processor (control unit)
3a ALU (calculator)
3c WL-Selector (switching means)
4 PE interface (external interface)
5 First data line (first data line)
6 First word line (first word line)
6 'first word line (first word line)
7 Second data line (second data line)
8 Second word line (second word line)
PE0 to PEn Processor element R0 to R15 Register

Claims (4)

A plurality of processor elements having n registers (n is a natural number of 2 or more) assigned with a unique number and an arithmetic unit, a control unit for controlling the operations of the plurality of processor elements, and the n registers An external interface for controlling communication from the outside to the outside, a first data line to which each of the n registers is connected, and the control unit communicate with the arithmetic unit via the first data line A first word line for selecting a register to perform, a second data line to which the registers having the same number between the plurality of processor elements and the external interface are connected, and the external interface to the second data line SIMD type microprocessor provided with a second word line for selecting a processor element that communicates via Oite,
The external interface is provided in a manner in correspondence to the respective numbers of the registers,
Between the n processor elements, the first word line is connected to a register among a plurality of processor elements so that the same first word line is connected to registers of different numbers , and
The second word line is connected to a register of the same number among a plurality of processor elements ;
SIMD type microprocessor characterized by the above. A plurality of processor elements having n registers (n is a natural number of 2 or more) assigned with a unique number and an arithmetic unit, a control unit for controlling the operations of the plurality of processor elements, and the n registers An external interface for controlling communication from the outside to the outside, a first data line to which each of the n registers is connected, and the control unit communicate with the arithmetic unit via the first data line A first word line for selecting a register to perform, a second data line to which the registers having the same number between the plurality of processor elements and the external interface are connected, and the external interface to the second data line SIMD type microprocessor provided with a second word line for selecting a processor element that communicates via Oite,
Among the n processor elements, the first word line and the second word line are connected such that the same first word line and the same second word line are connected to registers having different numbers. SIMD microprocessor the word line and said Rukoto is connected to the register among a plurality of processor elements. Another type of first word line is further provided for selecting a register with which the control unit communicates with the arithmetic unit via the first data line,
3. The SIMD type microprocessor according to claim 1 , wherein the first word line of the same different type is connected to a register having the same number of each processor element . A switching means for selecting at least one of the first mode and the second mode, and having a function of changing the connection relation of at least the first word line ; and
In the first mode, the switching means connects at least the first word line with the same first word line to registers having different numbers among the n processor elements. A mode in which the first word line is connected to a register between a plurality of processor elements is maintained,
In the second mode, n registers in each processor element are divided into a plurality of register groups, and at least the first word line in each of the register groups is divided by the switching unit in the one processor element. Among the number of processor elements indicated by the number of registers included in the register group, the first word line includes a plurality of processor elements so that the same first word line is connected to registers having different numbers. The mode of being connected to the register between is maintained,
The SIMD type microprocessor according to any one of claims 1 to 3, wherein the SIMD type microprocessor is provided.

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