JP4408113B2 - Signal processing method - Google Patents

Description

The present invention relates to a signal processing method using a single instruction stream multiple data stream (SIMD) type processor that processes a plurality of image data in parallel by a single arithmetic instruction, and is suitable for image processing such as digital copying. It is about the method .

  In recent years, in digital copying machines, facsimile machines, and the like, improvement of images has been attempted by increasing the number of pixels or making it compatible with color. As the image is improved, the number of data to be processed has increased. By the way, data processing in a copying machine or the like often performs the same arithmetic processing on all pixels. Therefore, a SIMD processor that performs the same arithmetic processing on a plurality of data simultaneously with one instruction is used.

  Normally, when image processing is performed using a SIMD processor, processor elements (PE) are developed in the main scanning direction. For this reason, when performing image processing such as filter processing, reference pixels above and below the target pixel are required, and it is conceivable that pixel data of the previous line is delayed in line and stored in the line memory.

  FIG. 16 shows a schematic block diagram of an image processing apparatus using the SIMD method. As shown in the figure, the image processing apparatus includes an external image memory (RAM) 101 in which image data is stored, for example, a processor element block 103 including 1024 processor elements, and a global processor 104.

  Each processor element (PE) has n general-purpose registers (R0 to Rn-1) and an operation array, and the general-purpose registers are in the form of having a register file outside the normal operation array. Each register is accessible as a shift register to the outside through a serial port. In the figure, the shaded area is a unit processor element.

  The global processor 104 has an address generation means for a program memory (PRAM) 105, reads an instruction code given to the processor element of the processor element block 103 from the PRAM 105, and controls the operation array and the register file.

  The device connected to the serial port of the general-purpose register of each PE differs depending on the system configuration. However, in a system that requires only a line delay of two lines, for example, pixel data of two lines before in R0 and one line before in R1 Assuming that the current line pixel data is arranged in the pixel data R2, the serial-parallel converter 102 is arranged in the serial ports R0 and R1, and is connected to the external RAM 101.

  For example, SVP (SERIAL VIDEO PROCESSOR) is known as an example of the image processing apparatus having the above-described configuration.

Since most conventional SIMD processors have processor elements larger than the number of pixels in the main scanning direction, difficult processing is not required for controlling the external memory (RAM) 101. In order to realize a scaling function such as enlargement or reduction in image processing such as digital copying, an ASIC is separately attached or JP-A-08-123683 (IPC: G06F 9/38) (Patent Document 1). This can be realized by adopting a configuration in which a scaling control flag is provided inside a SIMD processor as described in (1).
Japanese Patent Laid-Open No. 08-123683

  However, the accuracy of image processing has been increasing in recent years, and the number of pixels in the main scanning direction tends to increase. Further, in a conventional SIMD type processor, an increase in the circuit scale is usually prevented by using a small-scale circuit, for example, a processor having a large number of processor elements uses a 1-bit arithmetic array.

  When an SIMD type processor is applied to digital copying, for example, when an A4 size image is handled with an accuracy of 600 DPI (Dot Per Inch), the number of processor elements of 7000 pixels or more is required. It is not realistic to increase In order to solve this problem, it is conceivable to perform processing by dividing the main scanning direction. However, a dual port memory (RAM) is required as a line memory, which increases the circuit scale.

  On the other hand, in Japanese Patent Laid-Open No. 10-326258 (IPC: G06F 15/16), the processing time is obtained by dividing the pixels in the main scanning direction into two and dividing the total number of processor elements in half to perform pipeline processing. There has been proposed a data operation system that can shorten the time. However, with this method, it is not possible to perform processing with the number of pixels exceeding the size of the data memory accessible to the processor element.

  Furthermore, in a configuration in which a processor element has a scaling control flag, the processing becomes complicated when the number of divisions increases, so it is desirable to implement scaling processing outside the SIMD type processor. However, if the scaling function is realized separately using an ASIC, the versatility of the processor is reduced.

Therefore, the present invention provides a signal processing method using a SIMD processor having a simple configuration capable of incorporating a magnification changing function while simultaneously suppressing an increase in circuit scale by using a single port memory (RAM). Objective.

The present invention relates to a processor element of a SIMD type processor comprising a computing means for computing data and data holding means for holding data computed by the computing means and holding data computed by the computing means; A data transfer bus connected to each of the plurality of processor elements; designation means for designating a predetermined processor element based on addresses assigned to the plurality of processor elements; and an address bus for supplying an address to the designation means; A data transfer interface for accessing the data holding means incorporated in the plurality of processor elements from outside the processor, and the predetermined processor element connected to the data transfer interface and supplied to the address bus is designated A memory controller that generates an address for reading data, reads data stored in an external memory, writes data to the processor element, reads data from the processor element, and writes data to the memory; And when the memory controller transfers data from the data holding means of each processor element to the memory via the data transfer interface, the address of the processor element that starts the transfer and the processor that ends the transfer The address of the element is specified, the calculated data is read from each processor element except for a predetermined number of data, the address of the processor element to start the transfer is set, and this data is stored in the memory based on this address. When data is transferred from the memory to the data holding means of each processor element via the data transfer interface, addresses corresponding to the predetermined number of data excluded in the previous processing are returned. A new address is set, data is read from the memory based on the address value, an address for designating the predetermined processor element supplied to the address bus is generated, and data is written to the processor element. It is characterized by performing .

With the configuration as described above, in the case where the number of processor elements is less than the number of pixels in the main scanning direction, easy to arithmetical operations at SIMD processors, effective when performing weighting operation such as a filter over treatment Only pixels can be transferred.

The memory controller may be configured to perform write transfer and read transfer to the memory in a time-sharing manner and control the single port memory as a FIFO or LIFO memory.

With this configuration, the line memory can be realized while using a sheet ring Le port memory.

The data transfer interface can be configured to simultaneously access data holding means of processor elements having even addresses and processor elements having odd addresses.

  With the above configuration, the time for transferring data to the data holding means of all the processor elements can be halved. Further, it is possible to provide a margin for memory access time.

Image data is stored in the memory, the number of processor elements of the SIMD processor is configured to be smaller than the number of pixels in the main scanning direction, and the memory controller divides all pixels in the main scanning direction into two or more. It can be configured to control the processing of writing and reading data so as to perform processing .

  By configuring as described above, when realizing an image processing apparatus having a very large number of pixels in the main scanning direction, such as digital copying, without changing the SIMD processor architecture itself, such as increasing or decreasing the number of processor elements. An image processing apparatus can be constructed.

As described above, according to this invention, when the number of processor elements is less than the number of pixels in the main scanning direction, easy to arithmetical operations at SIMD processors, effective when performing weighting operation, such as the Filtered Can transfer only correct pixels.

  Embodiments of a SIMD type processor 1 according to the present invention will be described below with reference to the drawings.

First, the overall configuration of the SIMD type processor according to the present invention will be described with reference to FIG. SIMD processor 1 of the present invention, as shown in FIG. 1, the external-in tough Esu connected global processor 2, the processor element block 3 consisting of processor elements 3a to be described later of 1024 pairs in the present embodiment, the memory controller 5 It is composed of four. Based on instructions from the global processor 2, the memory controller 5 provides image data to be calculated from an external image memory 6 composed of a single port memory (RAM) to an input / output register file 31 inside the processor, and performs arithmetic processing. The processed data is transferred from the register file 31 to the image memory (RAM) 6.

  As shown in FIG. 2, the global processor 2 includes a processor element block 3, a program RAM 21 in which a program for controlling the external interface 4 and the memory controller 5 is stored, and a global processor 2 and a processor element block based on the program RAM 21. 3, a sequence unit 22 for controlling the external interface 4 and the memory controller 5 is provided. Specifically, the sequence unit 22 controls an arithmetic logic unit 23 (hereinafter referred to as “ALU 23”), which will be described later, provided in the global processor 2.

  The sequence unit 22 controls the register file 31 and the arithmetic array 36 that constitute the processor element block 3. The arithmetic array 36 includes a multiplexer 32, a shift extension circuit 33, an arithmetic logic unit 34 (hereinafter referred to as “ALU 34”), and a register 35. The global processor 2 is a so-called SISD type, and performs one arithmetic process for one arithmetic instruction.

  Further, the sequence unit 22 sends operation setting data and commands for data transfer to the memory controller 5. Based on the operation setting data and command of the sequence unit 22, the memory controller 5 is an address control signal for addressing the processor element 3a, and instructs the register 31b constituting the processor element 3a to read / write data. A clock control signal for supplying a read / write control signal and a clock signal is supplied to the external interface 4.

  Here, the write control signal among the read / write control signals refers to a signal for acquiring data to be processed from the data bus 46a (46b) and holding it in the register 31b of the processor element 3a. On the other hand, of the read / write control signals, the read control signal is used to instruct the register 31b to supply the processed data held in the register 31b of the processor element 3a to the data bus 46a (46b). A signal.

  In the processor element block 3 in this embodiment, an even number and an odd number are assigned to two adjacent processor elements 3a to form one set, and the same address is assigned to this set of processor elements 3a.

The memory controller 5 receives a command from the global processor 2, a signal for designating the address of the processor element 3a constituting the processor element block 3 (hereinafter, referred to as "addressing signal".) Create and external in tough Esu 4 to the register controller 31a of the processor element 3a via the address bus 41a. As will be described later, the memory controller 5 sends a signal for instructing the register 31b constituting the processor element 3a to read / write data (hereinafter referred to as “read / write instruction signal”). A read / write signal is supplied to a register controller 31a (to be described later) of the processor element 3a through a read / write signal line 45a (45b). The even read / write signal line 45a provides a read / write signal to the even number processor element 3a, and the odd read / write signal line 45b provides a read / write signal to the odd number processor element 3a.

  Further, the memory controller 5 gives a clock signal from the external interface 4 to a register controller 31a (to be described later) of the processor element 3a through the clock signal line 41c.

  Further, as described above, the memory controller 5 supplies the data stored in the image memory 6 provided outside the SIMD type processor 1 to the external interface 4 as 16-bit parallel data in this embodiment. This 16-bit data is composed of 8 bits given to the processor element 3a assigned with the even number and 8 bits given to the processor element 3a assigned with the odd number. The 8-bit data is applied to the even data bus 46a and the odd data bus 46b. The 8-bit parallel data can be appropriately changed according to the data. The data buses 46 a and 46 b are also used when the processed data held in the register 31 b is sent to the image memory 6 provided outside the SIMD type processor 1.

  The image memory 6 stores data to be subjected to arithmetic processing and stores data subjected to arithmetic processing. These image memories 6 may be provided inside the SIMD type processor 1 without any problem. Also, in this embodiment, data transfer between the memory controller 5 and the image memory 6 is treated as being transferred as 32-bit parallel data, as will be described later. However, the data transfer is appropriately changed according to the data. There is no problem. Other operations performed by the memory controller 5 will be described later.

  In addition, the global processor 2 includes an ALU 23 that performs arithmetic logic operations and a data RAM 24 that stores operation data in accordance with instructions from the sequence unit 22. Further, the global processor 2 includes a register group 25 for holding data to be processed.

  The register group 25 includes a program counter PC that holds a program address, G0 to G3 registers that are general-purpose registers for storing data for arithmetic processing, and a stack that holds the address of the save destination data RAM at the time of register save and return. Pointer (SP), link register (LS) that holds the address of the caller at the time of a subroutine call, LI and LN registers that hold branch source addresses at the time of IRQ and NMI, and a processor status register that holds the state of the processor (P) is incorporated.

  The register group 25 is connected to a later-described register 35 of the processor element block 3, and data is exchanged with the register 35 under the control of the sequence unit 22.

As shown in FIGS. 1 and 2, the processor element block 3 includes a register file 31, a multiplexer 32, a shift / expansion circuit 33, an arithmetic logic unit 34 (hereinafter referred to as “ALU 34”), and a register 35 as one unit. A plurality of processor elements 3a. The register file 31 includes 32 8-bit registers in one processor element 3a. In this embodiment, a set of 1024 processor elements has an array configuration. The register file 31 stores R0, R1, R2,... For each processor element (PE) 3a. . . A register called R31 is incorporated. Each register file 31 has one read port and one write port for the arithmetic array 36 and is accessed from the arithmetic array 36 by an 8-bit read / write bus. Of the 32 registers, 24 are accessible from outside the processor, and any register can be read and written by inputting a clock, an address, and read / write control from the outside.

  Access from the outside of the register allows one register of each processor element 3a to be accessed by one external port, and the processor element number (0 to 1023) is designated by an address inputted from the outside. Therefore, a total of 24 external ports for register access are installed. As described above, externally accessed data is 16-bit data for one set of even-numbered processor elements 3a and odd-numbered processor elements 3a, and two registers are accessed simultaneously by one access. ing.

  In the present embodiment, the number of processor elements 3a is described as 1024. However, the number of processor elements 3a is not limited to this, and may be changed as appropriate. Addresses 0 to 1023 are assigned to the processor element 3a in the order of closeness to the external interface 4 by the sequence unit 22 of the global processor 2.

The register file 31 of the processor element 3a includes a register controller 31a and two types of registers 31b and 31c. In the present embodiment, as shown in FIG. 3, each unit of processor element 3a includes 24 sets of register controller 31a and register 31b, and further includes 8 registers 31c. 3 shows a part of the register file 31 in the two sets of processor elements 3a, and one processor element in FIG. 3 represents one processor element 3a. Here, in the present embodiment, the registers 31b and 31c are handled as 8-bit registers, but the present invention is not limited to this and may be used with appropriate modifications.

  As shown in FIG. 3, the register controller 31a is connected to the external interface 4 via the address bus 41a, the even read / write signal line 45a, the odd read / write signal line 45b, and the clock signal line 41c. ing.

  When receiving the address control signal from the memory controller 5, the external interface 4 sends an address designation signal to the processor element block 3 via the address bus 41a. Thereby, a set of processor elements 3a, ie two processor elements 3a, are addressed simultaneously. The register controller 31a decodes the address designation signal sent, and if the decoded address matches the address assigned to itself, the register controller 31a sends the clock sent from the memory controller 5 via the clock signal 41c. In synchronization with the signal, a read / write instruction signal sent from the memory controller 5 is obtained via the read / write signal 45a or 45b. Specifically, the register controller 31a to which the even number is assigned obtains the read / write instruction signal sent from the memory controller 5 through the even read / write signal 45a. On the other hand, the register controller 31a to which the odd number is assigned obtains the read / write instruction signal sent from the memory controller 5 via the odd read / write signal 45b. At this time, the read / write instruction signals sent to the register controller 31a of the processor element 3a constituting the set may be different. That is, when the instruction signal sent to the register controller 31a assigned with the even number is a read instruction, the instruction signal sent to the register controller 31a assigned with the odd number may be a write instruction. The read / write instruction signal is given to the register 31b.

  When a write instruction signal is sent from the register controller 31a to both processor elements 3a, the register 31b of the processor element 3a to which the even number is assigned uses the data (8 bits) to be processed for an even number. Obtained from the data bus 46a and held. Further, the register 31b of the processor element 3a to which the odd number is assigned acquires the data (8 bits) to be processed from the odd data bus 46b and holds it. On the other hand, when a read instruction signal is sent from the register controller 31a to both the processor elements 3a, the register 31b of the processor element 3a to which the even number is assigned receives the processed data (8 bits). The data is sent to the even data bus 46a. In addition, the register 31b of the processor element 3a to which the odd number is assigned sends the arithmetically processed data (8 bits) to the odd data bus 46b.

  As described above, data can be transferred to the processor element 3a to which the even number is assigned, and can be transferred to the processor element 3a to which the odd number is assigned. For this reason, the number of times of data transfer can be reduced, and data transfer can be performed at high speed.

  The register 31b holds data input from the outside that will be calculated in the ALU 34, which will be described later, or holds the data processed in the ALU 34 for output to the outside. Alternatively, it functions as an output register. Further, it also has a function as a register 31c, which will be described later, such as temporarily holding data to be processed or calculated data. In this embodiment, the register 31b is handled as one that can hold 8-bit data, but there is no problem even if it is appropriately changed according to the data. When the write instruction signal is given from the register controller 31a described above, the register 31b acquires and holds data to be processed from the data bus 46a or the data bus 46b. On the other hand, when a read instruction signal is sent from the register controller 31a, the register 31b gives the data processed and held to the data bus 46a or the data bus 46b. This data is given from the external interface 4 to the write buffer unit 54 of the memory controller 5 and stored in the image memory 6 from the write buffer unit 54.

  In the present embodiment, the register 31b is connected to the multiplexer 32 via a data bus 37 for transferring 8-bit data in parallel. Data processed by the ALU 34 or data processed by the ALU 34 is transferred to the register 31b via the data bus 37. This transfer is performed via a read signal line 26 a and a write signal line 26 b connected to the global processor 2 in accordance with an instruction from the sequence unit 22 of the global processor 2. Specifically, when a read instruction signal is sent from the sequence unit 22 of the global processor 2 via the read signal line 26a, the register 31b puts the data to be processed and held in the data bus. This data is sent to the ALU 34 and processed. On the other hand, when a write instruction signal is sent from the sequence unit 22 of the global processor 2 via the write signal line 26b, the register 31b holds the data processed by the ALU 34 sent via the data bus 37. To do.

  The register 31c temporarily holds the data to be processed by the register 31b or before the calculated data is supplied to the register 31b. Unlike the register 31b described above, the register 31c does not transfer data to or from the image memory 6 via the memory controller 5.

  The arithmetic array 36 includes a multiplexer 32, a shift / expansion circuit 33, a 16-bit ALU 34, and a 16-bit register 35. The register 35 includes a 16-bit A register and an F register.

In the calculation by the instruction of the processor element 3a, basically, the data read from the register file 31 is input to one side of the ALU 34 and the content of the A register of the register 35 is input to the other side, and the result is stored in the A register. Therefore, the operation between the A register and the R0 to R31 registers of the register file 31 is performed. A (7 to 1) multiplexer 32 is placed in the connection between the register file 31 and the arithmetic array 36, and the data 1, 2, 3 away to the left and the data 1, 2, 3 away to the right in the processor element direction, The center data is selected as the calculation target. The 8-bit data in the register file 31 is shifted to the left by an arbitrary bit by the shift / extension circuit 33 and input to the ALU 34. In addition, the execution / invalidation control of each processor element 3a is controlled by an 8-bit condition register (T) (not shown) so that only a specific processor element 3a can be selected as an operation target. ing.

  As described above, the multiplexer 32 is connected to the data bus 37 provided in its own processor element 3a, and is also connected to the data bus 37 provided in the three adjacent processor elements 3a. The multiplexer 32 selects one of the seven processor elements 3 a and sends the data held in the registers 31 b and 31 c in the selected processor element 3 a to the ALU 34. Alternatively, the data processed by the ALU 34 is sent to the registers 31b and 31c in the selected processor element 3a. As a result, arithmetic processing using data held in the registers 31b and 31c in the adjacent processor element 3a becomes possible, and the arithmetic processing capability of the SIMD type processor 1 can be increased.

  The shift / extension circuit 33 shifts the data sent from the multiplexer 32 by a predetermined bit and sends it to the ALU 34. Alternatively, the arithmetically processed data sent from the ALU 34 is shifted by a predetermined bit and sent to the multiplexer 32.

  The ALU 34 performs arithmetic logic operations based on the data sent from the shift / expansion circuit 33 and the data held in the register 35. In this embodiment, the ALU 34 is handled as being capable of handling 16-bit data, but there is no problem even if it is appropriately changed according to the data. The processed data is held in the register 35 and transferred to the shift / expansion circuit 33 or transferred to the general-purpose register 25 of the global processor 2.

  An I / O address, data, and control signal are given from the global processor 2 to the memory controller 5 via a bus. The global processor 2 sets commands such as an operation method in some operation setting registers (not shown) of the memory controller 5. Finally, the global processor 2 writes a start code in a start register (not shown) of the memory controller 5 so that the memory controller 5 automatically performs an operation according to the setting. With this configuration, the data in the register file 31 can be input / output simultaneously with the calculation based on the instruction control of the processor.

  FIG. 4 shows the configuration of the memory controller 5 used in the present invention. The memory controller 5 includes a write buffer unit 54 that writes data to the image memory 6, a read buffer unit 55 that reads data from the image memory 6, and a PE control unit 52 that controls the register file 31 of the processor element. A RAM control unit 53 that controls the image memory 6 and a sequence unit (SCU) 51 are included.

  The memory controller 5 is connected to the register file 31 of the SIMD type processor 1 via a data transfer port in the external interface 4, transfers data from the register file 31 to the image memory 6, and transfers from the image memory 6 to the register file 31. Data transfer. This data transfer port includes an output port and an input port. In addition, as described above, the registers controlled by the memory controller 5 in this embodiment are mapped to the I / O space, and output addresses, clocks, and read / write controls in accordance with instructions from the global processor 2. By doing so, it is possible to read and write.

An output port of the external interface 4 of the SIMD processor 1 is connected to the write buffer unit 54, and an input port of the external interface 4 is connected to the read buffer unit 55. Each data transfer port has independent input and output ports for even processor elements and odd processor elements, and can be configured to access data for one set of even and odd processor elements at a time in one cycle. Has been. The data buses between the write buffer unit 54, the read buffer unit 55, and the image memory 6 are each configured with a data width for four processor elements, and data for four processor elements can be accessed at one time in one cycle. In this embodiment, the data for one processor element is 8 bits. The bit width of the data bus between the external interface 4 and the write buffer 54 and read buffer 55 is 16 bits. Accordingly, the bit width between the memory controller 5 and the image memory 6 is 32 bits.

As a result, while performing the transfer between the data transfer port and the memory controller 5 of the external interface 4 twice, so that the transfer between the image memory 6 and the memory controller 5 may be performed once.

  The write buffer unit 54 of the memory controller 5 takes in the pixel data output from the external interface 4 of the SIMD type processor 1 twice, shapes it into data for four processor elements, and transfers it to the image memory 6. ing. The read buffer unit 55 performs an operation of dividing the data for the four processor elements read from the image memory 6 into two times and transferring them to the external interface 4 of the SIMD type processor 1.

  FIG. 5 shows a schematic block diagram of an embodiment of the processor element (PE) control unit 52.

  As shown in FIG. 5, the PE control unit 52 outputs the address, clock, and read / write control signal of the processor element 3 a to the external interface 4 of the SIMD processor 1, and registers the processor elements 3 a in the SIMD processor 1. Data in the file 31 can be read and written.

The PE control unit 52 includes a processor element (PE) address counter 521, transfer number counters 522 and 523, and a valid data number counter 524. In the case of write transfer (transfer from the register file 31 of the processor element 34a to the image memory 6), the PE address counter 521 is initially loaded with “0” at the start of transfer, and read transfer (register from the image memory 6 to the processor element 34a). In the case of (transfer to file 31), the value stored in the transfer start PE address register 525 is initially loaded at the start of transfer, and generates the address of the processor element to which data is transferred. The transfer number counters 522 and 523 are down counters that can initially load the number of data to be transferred, and are used to manage the transfer number. The transfer counter 522 is set with the number of data to be written, and the transfer counter 523 is initially loaded with the number of data to be read.

  The valid data number counter 524 is a counter that manages the number of valid data stored in the image memory 6. When data is transferred from the image memory 6 to the register file 31 of the processor element 3 a, the valid data number counter 524 has a valid data number that is larger than the transfer number. The transfer is performed only when there are more people. With this configuration, data loss is prevented.

  FIG. 6 shows a schematic block diagram of the first embodiment of the memory (RAM) control unit 53.

  As shown in FIG. 6, the RAM control unit 53 is controlled by control lines from the write buffer unit 54 and the read buffer unit 55, and clocks, addresses, and reads to the image memory (RAM) 6 composed of a single port memory. / Write control and byte select are output.

  The RAM control unit 53 includes a RAM address adjuster 531, a write pointer register 532, a read pointer register 533, and a multiplexer 534. Each block is connected via an address setting bus (hereinafter abbreviated as AB).

  The write pointer register 532 is a register that stores a pointer to be written to the image memory 6 next, and the read pointer register 533 is a register that similarly stores a pointer to be read from the image memory 6 next.

  In the write pointer register 532 and the read pointer register 533, the pointer updated by the RAM address adder / subtractor 531 is input from the AB 535 and stored after accessing the pointer in the image memory 6. The RAM address adder / subtractor 531 outputs a value corresponding to the RAM access size to the value of the write pointer at the time of write access and the read pointer at the time of read access, and adds the subtracted value to the AB 535 in the FIFO operation mode. .

  The sequence unit 51 includes an address decoder and a control register. By accessing a control register mapped to the I / O space from the global processor 2, the sequence unit 51 controls the entire memory controller 5, or the global processor 2 controls the memory controller. 5 can be monitored. Further, the time division of the write transfer and the read transfer is also performed in the block of the sequence unit 51. Further, by generating two clocks, a clock to the write buffer unit 54 and a clock to the read buffer unit 55, write transfer and read transfer can be performed simultaneously.

  Next, a description will be given of a pixel data transfer method in the case of using an SIMD type processor in which the number of processor elements 3a is smaller than the number of pixels in the main scanning direction. FIG. 7 shows an explanatory diagram of a pixel data transfer method when a SIMD processor having a smaller number of processor elements 3a than the number of pixels in the main scanning direction is used.

  When the number of processor elements 3a is smaller than the number of pixels in the main scanning direction, the pixel data in the main scanning direction is divided and the memory controller 5 stores the pixel data in the register file 31 of the processor element 3a of the SIMD processor 1 in the image memory 6 This process is repeatedly executed. That is, when the number of processor elements is smaller than the number of pixels in the main scanning direction, pixel data in the main scanning direction is divided and the arithmetic processing is repeatedly executed by the SIMD processor 1.

Usually, in image processing using a SIMD type processor, when processing including processing referring to pixel data before and after a pixel of interest is performed, such as filter processing, invalid data remains in data at both ends of the SIMD. For this reason, when data is stored in the image memory 6 from the register file of the processor element 3a, it is necessary to store the data excluding the data at both ends. Further, when data is transferred from the image memory 6 to the register file 31 of the processor element 3a, it is necessary to transfer reference pixel data before and after the target pixel. That is, transfer of pixel data in weighting processing such as filter processing is performed in the following order. Here, the number of reference pixels is a.

  1. The pre-processing pixel data is transferred from the image memory 6 to the corresponding register file 31 of the processor element 3a of the SIMD processor 1.

  2. Image processing by the SIMD processor 1 is performed. At this time, the a data before and after the SIMD processor element 3a are invalidated due to the absence of the reference pixel. That is, the hatched portion in FIG. 7 is the number of effective pixels.

  3. The processed pixel data is transferred from the SIMD processor 1 to the image memory 6. At this time, effective pixels excluding a pixels before and after both ends are transferred to the image memory 6.

  The transfer of pixel data between the image memory 6 and the SIMD processor 1 will be described with reference to FIG. The processor element (PE) 3a of the SIMD processor 1 includes n, that is, PE0 to PEn-1, and sends pixel data from the image memory 6 to the processor elements 3a. Pixel data is transferred from 3a to the image memory 6.

First, in the first transfer, that is, the 1st SIMD transfer in the figure, a reference pixel a is transferred before and after the processor element 3a of the SIMD processor 1. In the example shown in FIG. 7, the RAM control unit 53 first stores 0 in the read pointer 533, and reads the number corresponding to the RAM access size, in this embodiment, 32 bits of data from the image memory 6. And stored in the read buffer unit 55. The address adder / subtractor 531 outputs a value corresponding to the RAM access size to the read pointer value in the FIFO operation mode, and outputs the subtracted value to the AB 535 in the LIFO operation mode. Stored. By PE address counter 521 of the PE control unit 52, an address is generated based on the address, data is written to the processor element 3a ... corresponding externally in tough Esu 4. The transfer number counter 522 is decremented by a number corresponding to the RAM size each time image data is written, ie, 4 in this embodiment. The above processing is repeatedly executed until the value of the transfer counter 522 becomes 0, and the pixel data from the image memory 6 is transferred from PE0 to PEn-1 of the SIMD processor 1.

When the processed pixel data is transferred to the image memory 6, the a pixel data before and after the pixel data are invalid, and therefore, the pixel data to be transferred is a to (na-1) among n pixels from PE0 to PEn-1. ) Pixels up to (n−2 × a). For this reason, the value of the transfer start PE address register 525 is loaded into the PE address counter 521 of the PE control unit 52 at the start of transfer, and data is read from the corresponding processor element 3a. The image data is written from 4 to the write buffer unit 54. Each time data is read, the transfer number counter 523 is decremented by a number corresponding to the RAM access size, ie, 4 in this embodiment. When 32-bit data is stored in the write buffer unit 54, the image data is transferred to the image memory 6. First, the RAM control unit 53 stores a in the write pointer 532 and transfers the image data stored in the write buffer unit 54, in this embodiment, 32-bit data to the image memory 6. The address adder / subtractor 531 outputs a value corresponding to the RAM access size to the read pointer value in the FIFO operation mode, and outputs the subtracted value to the AB 535 in the LIFO operation mode, and the value is stored in the write pointer 532. The In this way, PEa to PEn of the SIMD processor 1
Image data up to −2 × a is transferred to the image memory 6.

  Subsequently, the second transfer is performed in the same manner. In the second SIMD transfer in the figure, since the pixels from (n−a) to (2n−3 × a) are processed as the target pixel, (n−2 × a) to (n−a−1) are used as reference pixels. ) And (2n−3 × a) to (2n−2 × a−1) pixel data are sent together. After the data processing, (n−3 × a) pixels (n−a) to (n−2 × a) are stored in the image memory 6. Similar processing is only repeated when the number of SIMD divisions in the main scanning direction is large.

  In order to realize the above processing, in the case of data write to the image memory 6, “a” is set in the transfer start PE address register 525 in the embodiment of the processor element (PE) control unit 52 of the present invention. In this case, “(n−2 × a)” may be set in the transfer number counter 522.

  Since all the setting numbers are based on the PE address, there is no need to change the setting for each SIMD. In the case of reading data from the image memory 6, an operation of returning the read pointer 533 after the transfer is completed is necessary. In the above example, the value is returned to (n−2 × a). In the embodiment of the hitting 1 of the RAM control unit 53, it is necessary to set the value of the read pointer 533 from the global processor 2 after the transfer is completed.

  In the case of data writing to the image memory 6, it is not necessary to operate the write pointer 532.

  FIG. 8 is a schematic block diagram showing a second embodiment of the RAM control unit 53 according to the present invention.

  The RAM control unit 53 shown in FIG. 8 is obtained by adding a read offset generator 536 to the RAM control unit 53 shown in FIG. The RAM control unit 53 returns the value of the read pointer 533 after the transfer to the processor element 3a is completed when data is transferred from the memory 6 to each register file of the processor element 3a of the SIMD processor 1 by the read offset generator 536. It has changed to be able to.

  The read offset generator 536 monitors the PE address input from the PE control unit 52. When the PE address becomes equal to the set value, the read offset generator 536 holds the value of the read pointer 533 at that time and sends the set transfer number. Continue forwarding until finished. When the transfer is completed, the held value is reloaded into the read pointer 533. In the example shown in FIG. 7, (n−2 × a−1) is set. Since all setting values are based on the PE address, it is not necessary to change the setting for each SIMD as in the first embodiment of the RAM control unit 53.

  FIG. 9 is a schematic block diagram showing a third embodiment of the RAM control unit 53 according to the present invention.

  In addition to the above processing, the RAM control unit 53 shown in FIG. 9 can use only a specific area of the image memory 6 in a ring shape.

  The RAM control unit 53 is obtained by adding two registers 537 and 538 and a comparator 539 to the RAM control unit shown in FIG. The register (LADDR) 537 sets the lower limit value of the address of the image memory 6, and the register (UADDR) 538 sets the upper limit value of the address of the image memory 6. The comparator 539 compares the current pointer 532 (533) with the values set in the LADDR 537 and UADDR 538, respectively.

  In the FIFO mode, when the UADDR 538 and the pointer 532 (533) coincide with each other and the value output from the address adjuster 531 exceeds the UADDR 538, the output from the address adjuster 531 to the AB 535 is negated, and the LADDR 537 receives the AB 535. Assert the output to

  Conversely, in the LIFO mode, when the LADDR 537 matches the pointer 532 (533) and the value output from the address adjuster 531 is lower than the LADDR 537, the output from the address adjuster 531 to the bus AB 535 is negated, and the UADDR 538 Assert the output to AB535. By configuring as described above, only a specific space of the memory space of the image memory 6 can be used.

  FIG. 10 is a schematic block diagram of the write buffer unit 54 and the read buffer unit 55 according to the embodiment of the present invention.

  The write buffer unit 54 and the read buffer unit 55 in this embodiment have dedicated ports for the even-numbered processor element 3a and the odd-numbered processor element 3a, and are configured to be able to access data for two processor elements in one cycle. It is possible to transfer data with the number of cycles that is half of the total number of processor elements.

  The write buffer unit 54 is configured to perform write access to the image memory 6 when data for four processor elements is stored in the buffer.

  Data for two processor elements supplied from the transfer port of the external interface 4 to the write buffer unit 54 is first stored in the flip-flops 541 and 542 and then transferred to the flip-flops 543 and 544 in the next stage. Subsequently, the given two processor elements are stored in flip-flops 541 and 542. Then, the data for four processor elements stored in the flip-flops 541 to 544 are stored in the latches 545 to 548, respectively. When the data for four processor elements is stored in the latches 545 to 548, the write buffer unit 54 performs write access to the image memory 6.

  The read buffer unit 55 stores data read from the image memory 6 for four processor elements in flip-flops 551 to 554 as buffers. Two processor elements are selected from the data for four processor elements by the multiplexer 555 and stored in the latches 556 and 557. The image data stored in the latches 556 and 557 is transferred to the register file 31 of the SIMD processor 1 via the external interface 4.

When the transfer of data for four processor elements is completed, read access to the image memory 6 is performed again. Since the image memory 6 can access data for four processor elements at a time, if the access can be realized once in two cycles, the interface with the SIMD processor 1 can be taken, and the access time limit of the image memory 6 can be relaxed.

  FIG. 11 illustrates a thinning write operation for realizing reduction among the scaling processes often performed in digital copying, facsimile, and the like.

  In FIG. 11, the pixel data of the processor element (0), the processor element (2), etc. are stored in the image memory 6 as they are, and the pixel data of the processor element (1), the processor element (3), etc. are not stored in the image memory 6. Is thinned out.

  The memory controller 5 has two external write control signals for determining whether to thin out the data of the even-numbered processor element 3a and the odd-numbered processor element 3a. The memory controller 5 has an external terminal for notifying the memory controller 5 of the timing for starting transfer in order to synchronize the write control signal. The external synchronization signal for starting the transfer is input to the sequence unit, and when the synchronization signal is asserted, the sequence unit 51 starts the transfer.

  The sequence unit 51 detects the value of the write control signal, and when the external write control signal is “0”, writes the data in the buffer in the write buffer unit 54. Further, the sequence unit 51 detects the value of the write control signal, and when “1” is set, the sequence unit 51 suppresses storing the data in the buffer in the write buffer unit 54.

  Since the write buffer unit 54 does not output a transfer request to the image memory 6 to the RAM control unit 53 until data for four processor elements is stored, except for exceptions at the start and end of transfer, the address pointer The update of the data, the output to the image memory 6, the read / write control, and the byte select are not performed until the data for four processor elements is stored in the write buffer unit 54. Data reading from the data transfer port of the SIMD processor 1 continues regardless of the write control signal.

  FIG. 12 illustrates an overlapping read operation for realizing enlargement in the above scaling process. In FIG. 12, the data of the image memory 6 is written into the registers such as the processor element (0) and the processor element (2) sequentially from the position of the read pointer, and the registers such as the processor element (1) and the processor element (3) are written. The value written in the register of the previous processor element is written in duplicate.

  The memory controller 5 has two external read control signals for deciding whether or not the same data as before is written when the data of the even-numbered processor element 3a and the odd-numbered processor element 3a is written. .

  In order to synchronize the memory controller 5 and the overlap control signal, an external terminal for notifying the memory controller 5 of the timing for starting the transfer is provided. The external synchronization signal for starting the transfer is input to the sequence unit 51. When the synchronization signal is asserted, the sequence unit 51 starts the transfer.

The sequence unit 51 detects the value of the read control signal. When “1” is set, the sequence unit 51 controls the multiplexer of the read buffer unit 55 to store the register of the processor element having the previous PE address. The data to be transferred can be output again. The read buffer unit 55 transfers the data to the image memory 6 to the RAM control unit 53 until all the data for the four processor elements read from the image memory 6 are unnecessary, except for exceptions at the start and end of the transfer. Since the read data transfer request is not output (for example, if the read control is always “0”, the data transfer port is accessed twice, and no data is required while the read control signal is 1). The updating of the address pointer and the output of the clock, read / write control, and byte select to the image memory 6 are not performed until all the data for the four processor elements are unnecessary. Data writing to the external interface 4 of the SIMD processor 1 continues regardless of the read control signal.

In the above-described embodiment, the data can be transferred to the processor element 3a to which the even number of the SIMD processor 1 is assigned, and the data can be transferred to the processor element 3a to which the odd number is assigned. However, the transfer of image data to the SIMD processor 1 is not limited to this method. For example, as shown in FIG. 13, the present invention can also be applied to a configuration in which the processor element 3a of the SIMD processor 1 is configured to sequentially transfer data by address designation without distinguishing between odd and even. That is, as shown in FIG. 11, the register controller 31a is connected to the external interface 4 via the address bus 41a, the read / write signal 45c, and the clock signal 41c. When the register controller 31a is supplied from the memory controller 5 to the external interface 4 and receives an address designation signal via the address bus 41a, the register controller 31a decodes the address designation signal. If the decoded address matches the address assigned to its own processor element 3a, it is given from the memory controller 5 to the external interface 4 and read / read in synchronization with the clock signal from the clock signal 41c. A read / write instruction signal sent from the memory controller 5 is obtained via the write signal 41b. This read / write instruction signal is applied to the register 31b.

  In this embodiment, data stored in the image memory 6 provided outside the SIMD type processor 1 is placed on the data bus 46c as 8-bit parallel data. The data bus 46c is also used when the processed data held in the register 31b is sent to the image memory 6 provided outside the SIMD type processor 1.

  Address, read / write, clock, and data signals given from the external interface 4 are supplied to each register of the register file 31. Then, the address is decoded for each processor element 3a..., And only the processor element 3a that matches the address indicating each processor element 3a.

  When the memory controller 5 sends the data stored in the image memory 6 to the processor element 3a, the SIMD processor 1 configured as described above designates the address assigned to the processor element 3a once. Is input to the designated processor element 3a. In this example, since data is not simultaneously sent to the even and odd processor elements 3a, the data transfer takes time compared to the first embodiment, but the circuit configuration can be simplified.

  In the above-described embodiment, the processor element 3a is addressed. However, the present invention can also be applied to a pointer designation method, that is, a serial access memory method, instead of a method of addressing designation of the processor element 3a. This example will be described with reference to FIG. Here, the points different from the first embodiment described above will be described, and the description of the same points will be omitted. Moreover, the same code | symbol is attached | subjected about the same component as 1st Embodiment mentioned above.

First, an I / O address, data, and control signal are given from the global processor 2 to the memory controller 5 via a bus. The global processor 2 sets commands such as an operation method in some operation setting registers (not shown) of the memory controller 5. Finally, the global processor 2 writes a start code in a start register (not shown) of the memory controller 5 so that the memory controller 5 automatically performs an operation according to the setting. The memory controller 5 generates this reset signal based on the command of the global processor 2 and sends it to the processor element block 3 from the external interface 4 via the reset signal 47. As a result, the register controller 31a is reset. Then, a clock signal is sent from the memory controller 5 to the register controller 31a closest to the external interface 4 via the external interface 4 and the clock signal 41c. In synchronization with this clock signal, the register controller 31a ′ obtains a read / write instruction signal sent from the memory controller 5 via the read / write signal 45a or 45b. This read / write instruction signal is applied to the register 31b of the processor element 3a to which the even number is assigned and to the register 31b of the processor element 3a to which the odd number is assigned. At this time, the read / write instruction signals sent to the register controller 31a ′ of the processor element 3a constituting one set may be different from those in the first embodiment.

  As a result, as in the case of the first embodiment described above, data can be transferred to the processor element 3a to which the even number is assigned by one pointer designation, and can also be transferred to the processor element 3a to which the odd number is assigned.

  FIG. 15 is a block diagram showing the configuration of another embodiment of the image processing apparatus including the memory controller 5 of the present invention described above. In FIG. 15, a memory controller 5 is arranged between data transfer ports of two independent register files 3. The present invention can also be applied to such a configuration.

It is a block diagram which shows the SIMD type | mold processor in embodiment of this invention. It is a block diagram which shows the internal structure of the SIMD type | mold processor in 1st Embodiment of this invention. It is a block diagram which shows the internal structure of the processor element in 1st Embodiment of this invention. It is a block diagram which shows the structure of the memory controller 5 used for this invention. It is a schematic block diagram of embodiment of the processor element (PE) control part 52 of the memory controller 5 used for this invention. It is a schematic block diagram of 1st Embodiment of the memory (RAM) control part 53 of the memory controller 5 used for this invention. It is explanatory drawing about the transfer method of pixel data at the time of using the processor of a SIMD system with the number of processor elements 3a smaller than the number of pixels of the main scanning direction. It is a schematic block diagram which shows 2nd Embodiment of RAM control part 53 of the memory controller 5 used for this invention. It is a schematic block diagram which shows 3rd Embodiment of the RAM control part 53 of the memory controller 5 used for this invention. 3 is a schematic block diagram of a write buffer unit 54 and a read buffer unit 55 of the memory controller 5 used in the present invention. FIG. It is explanatory drawing of the thinning-out write operation | movement for implement | achieving reduction | restoration among scaling processes. It is explanatory drawing of duplication read operation | movement among scaling processes. It is a block diagram which shows the internal structure of the SIMD type | mold processor in other embodiment of this invention. It is a block diagram which shows the internal structure of the SIMD type | mold processor in further different embodiment of this invention. It is a schematic block diagram which shows other embodiment of this invention. It is a schematic block diagram of the image processing apparatus using the conventional SIMD system.

DESCRIPTION OF SYMBOLS 1 SIMD type processor 2 Global processor 4 External interface 5 Memory controller 6 Image memory 51 Sequence unit 52 PE control part 53 RAM control part 54 Write buffer part 55 Read buffer part

Claims (4)

A processor element of a SIMD type processor comprising a computing means for computing data and a data holding means for holding data computed by the computing means and holding data computed by the computing means;
A data transfer bus connected to each of the plurality of processor elements;
Designation means for designating a predetermined processor element based on an address assigned to the plurality of processor elements;
An address bus for supplying an address to the designation means;
A data transfer interface for accessing the data holding means contained in the plurality of processor elements from outside the processor;
It is connected to this data transfer interface, generates an address for designating the predetermined processor element supplied to the address bus, reads data stored in an external memory, and writes data to the processor element. And a memory controller that reads data from the processor element and writes data to the memory,
When the memory controller transfers data from the data holding means of each processor element to the memory via the data transfer interface, the address of the processor element that starts the transfer and the address of the processor element that ends the transfer Specify and read the calculated data from each processor element except for a predetermined number of data, set the address of the processor element to start transfer, and write this data to the memory based on this address,
When data is transferred from the memory to the data holding means of each processor element via the data transfer interface, a new address is set in which addresses corresponding to the predetermined number of data excluded in the previous processing are returned. Then, data is read from the memory based on the address value, an address for designating the predetermined processor element supplied to the address bus is generated, and data is written to the processor element. Signal processing method . The signal processing method according to claim 1, wherein the memory controller performs write transfer and read transfer to the memory in a time-sharing manner, and controls the single port memory as a FIFO or LIFO memory. 3. The signal processing according to claim 1, wherein the data transfer interface is capable of simultaneously accessing a data holding unit of a processor element having an even address and a processor element having an odd address. Method. Image data is stored in the memory, the number of processor elements of the SIMD processor is configured to be smaller than the number of pixels in the main scanning direction, and the memory controller divides all pixels in the main scanning direction into two or more. 4. The signal processing method according to claim 1, wherein control of data writing and reading processing is performed so as to perform processing.

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