JP2013161325A - Simd (single instruction-stream multiple data-stream) type microprocessor, processor system and data processing method for simd type microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SIMD type microprocessor, a processor system and the data processing method of the SIMD type microprocessor for enabling each PE (Processor Element) to quickly perform processing of referring to the data of different addresses such as rotation processing only by adding a few circuits.SOLUTION: An SIMD type microprocessor 2 includes: a PE-RAM 20 for inputting and outputting data only with a register file 14 of a processor element group 6; a DMA device 22 for controlling data transfer with the PE-RAM 20 and the register file 14. The DMA device 22 successively reads independent address values stored in an R31 register of each PE 44 in the order of PE numbers, and successively rewrites the data stored in the PE-RAM 20 to the R31 register.

Description

  The present invention relates to a single instruction-stream multiple data-stream (SIMD) type microprocessor that processes a plurality of data such as image data in parallel by one arithmetic instruction, a processor system having a SIMD type microprocessor, and a SIMD type microprocessor. The present invention relates to a data processing method.

  In the SIMD type microprocessor, the same arithmetic processing can be executed simultaneously on a plurality of data with one instruction. With this structure, it is used for the purpose of performing the same operation on a lot of data to be subjected to image processing and the like.

  In a SIMD type microprocessor, normal arithmetic processing can be realized by arranging a plurality of arithmetic units and executing the same operation on a plurality of data at the same time, but non-linear processing in which arithmetic processing cannot be expressed by an expression is subject to calculation. The same processing cannot be executed at the same time because the arithmetic expression is changed depending on the data.

  An example of this kind of non-linear image processing is a process called rotation. This is a process of obtaining an appropriate image by rotating an image scanned by an angle distorted with respect to a horizontal plane when an original is distorted with respect to a contact glass in a digital copying machine or the like.

  In Patent Document 1, with respect to the original data before the rotation in the rotation process, the deviation amount in the sub-scanning direction is calculated according to the rotation angle, the data after the rotation is sampled, and the interpolation calculation is performed by bilinear or bicubic. It is described that the rotation processing is realized.

  In Patent Documents 2 and 3, each processor element (PE) provided in the SIMD type microprocessor has an individual SRAM (Static Random Access Memory), and the displacement amount in the sub-scanning direction is determined by each PE. Data can be referred to using the calculated value as an address.

  Patent Document 4 describes a configuration in which non-linear processing represented by LUT (Look Up Table) is performed at high speed without having an independent SRAM in each PE.

  In order to perform the invention described in Patent Document 1 with a SIMD type microprocessor, there is no choice but to sequentially read data stored in a memory accessible from the PE while incrementing the address in the order of the PE number. There is a problem that the number of cycles is enormous when executed as an instruction.

  In the inventions described in Patent Documents 2 and 3, since the SRAM built in all PEs has an address decoder, the SIMD microprocessor with a large number of PEs increases the circuit scale and costs. There was a problem of doing.

  Patent Document 4 has a problem that it can be applied only to processing using the same reference memory in each PE, such as gamma correction.

  The present invention aims to solve such problems.

  That is, the present invention provides a SIMD microprocessor, a processor system, and a data processing method for a SIMD microprocessor that can perform high-speed processing for referring to data at different addresses for each PE, such as rotation processing, with only a small number of additional circuits. The purpose is to provide.

  In order to solve the problems described above, the invention described in claim 1 is a SIMD type microprocessor having a plurality of processor elements each having a plurality of registers that can be read or written by a predetermined address. A memory capable of inputting / outputting data only to / from an element and having a data bit width accessible by at least two or more processor elements simultaneously, and a value stored in one of the plurality of registers A data transfer unit that sequentially reads out each processor element and outputs the read value as an address of the memory, and at least an address corresponding to the data is read from the data read from the memory The register of the processor element; And write control means for controlling to store the data, a SIMD microprocessor that comprising the.

  According to the first aspect of the present invention, a value stored in one register among a plurality of registers is read for each processor element, and the read value is input / output only with the processor element. The address of the memory having a data bit width that can be accessed simultaneously by at least two or more of the processor elements is used, and at least the address corresponding to the data is read from the data read from the memory. Since each processor element is stored in the register of the processor element, each processor element refers to data at a different address, such as rotation processing, with only a few additional circuits, without having a memory having an independent address decoder for each processor element. Can be performed at high speed.

It is a block diagram of the processor system concerning the 1st Embodiment of this invention. It is a block diagram which shows the more detailed structure of the processor element group especially of a SIMD type | mold microprocessor. FIG. 2 is a main part configuration diagram of the SIMD type microprocessor shown in FIG. 1. It is explanatory drawing which described the address setting value in R31 register shown by FIG. FIG. 4 is a timing chart showing a data read operation from the PE-RAM of the SIMD type microprocessor shown in FIG. 3. FIG. 4 is a flowchart showing a data read operation from the PE-RAM of the SIMD type microprocessor shown in FIG. 3. It is a principal part block diagram of the SIMD type | mold microprocessor concerning the 2nd Embodiment of this invention. FIG. 8 is a configuration diagram illustrating a configuration of the decoder illustrated in FIG. 7. It is explanatory drawing which showed the decoding conditions of the write decoder shown by FIG. FIG. 8 is an explanatory diagram illustrating an example of an address setting value stored in an R30 register of the SIMD type microprocessor illustrated in FIG. 7 and data after data shaping is performed on the example. FIG. 8 is a timing chart showing a data read operation from the PE-RAM of the SIMD type microprocessor shown in FIG. 7. FIG. It is a principal part block diagram of the SIMD type | mold microprocessor concerning the 3rd Embodiment of this invention.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is a configuration diagram of a processor system according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a more detailed configuration of the SIMD type microprocessor, particularly the processor element group. FIG. 3 is a block diagram of the main part of the SIMD type microprocessor shown in FIG. FIG. 4 is an explanatory diagram in which an address set value is described in the R31 register shown in FIG. FIG. 5 is a timing chart showing a data read operation from the PE-RAM of the SIMD type microprocessor shown in FIG. FIG. 6 is a flowchart showing a data read operation from the PE-RAM of the SIMD type microprocessor shown in FIG.

  FIG. 1 shows a processor system 1 according to a first embodiment of the present invention. The processor system 1 includes a SIMD type microprocessor 2, a memory controller 10, and a memory 12 according to the first embodiment of the present invention.

  The SIMD type microprocessor 2 includes a global processor 4, a processor element group 6, an external interface 8, and a DMA device 22.

  The global processor (GP) 4 is a so-called SISD (Single Instruction Stream, Single Data Stream) type processor, which includes a program RAM and a data RAM, decodes the program, and generates various control signals. This control signal is supplied to a register file 14, an arithmetic array 16, a memory controller 10, and a DMA device 22, which will be described later, in addition to control of various built-in blocks. When a GP instruction, which is an instruction executed by GP4, is executed, various arithmetic processes and program control processes are performed using a built-in general-purpose register, ALU (arithmetic logic unit), and the like.

  The processor element group 6 includes a register file 14, an operation array 16, and a PE-RAM 20.

  The register file 14 is a register group (file) that holds data processed by a processor element (PE) instruction. That is, it is a collection of register portions of each PE (see FIG. 2). The PE instruction is an instruction of the SIMD (Single Instruction Stream, Multiple Data Stream) type, and is an instruction that simultaneously performs the same processing on a plurality of data held in the register file 14. Control of reading / writing of data from the register file 14 is performed by control from the GP 4. The read data is sent to the arithmetic array 16 described later, and is written in the register file 14 after arithmetic processing in the arithmetic array 16.

  The register file 14 can be accessed from the memory controller 10 outside the SIMD type microprocessor 2 via the external interface 8, and a specific register is read / written from the outside separately from the control of the GP4. Furthermore, data read from the PE-RAM 20 is written to some registers of the register file 14 under the control of the DMA device 22 described later.

  The arithmetic array 16 is a block in which arithmetic processing of a PE instruction is performed. That is, it is a collection of arithmetic units (including ALU) of each PE (see FIG. 2). All processing control is performed from GP4.

  The external interface 8 performs an input / output interface between the register file 14 and the memory controller 10 such as data and control signals.

  The memory controller 10 outputs a clock, an address, and a read / write control signal to the external port 18, and outputs a clock, an address, and a read / write control signal to the single port memory 12. Data transfer is performed with the memory 12. All processing control is performed from GP4.

  FIG. 2 is a block diagram showing a more detailed configuration of the SIMD type microprocessor 2, particularly the processor element group 6.

  The GP 4 includes a program RAM 23 for storing the GP 4 program and a data RAM 24 for storing operation data. Furthermore, a program counter (PC) 25 that holds the address of the program, G0 to G3 registers (26, 28, 30, 32) that are general-purpose registers for storing arithmetic processing data, and a save destination data RAM at the time of register saving and restoration Stack pointer (SP) 34 that holds the address of the link, link register (LS) 36 that holds the address of the caller at the time of the subroutine call, and the branch source address at the time of interrupt (IRQ) and non-maskable interrupt (NMI) An LI register 38, an LN register 40, and a processor status register (P) 42 for holding the state of the processor are provided.

  The GP instruction is executed using these registers and an instruction decoder, ALU, memory control circuit, interrupt control circuit, external interface control circuit, and GP arithmetic control circuit (not shown). When the PE instruction is executed, the register file 14 and the operation array 16 are controlled using an instruction decoder, a register file control circuit (not shown), and a PE operation control circuit.

  Next, in the register file 14, 32 8-bit registers 50 are built in one PE unit, and a set of 256 PEs has an array configuration (one PE is indicated by a point 44). This is a portion corresponding to the inside of the chain line, and consists of a register 46 and a calculation unit 48). The register 50 is provided with 32 registers R0, R1, R2,..., R31 registers for each PE. Each register 50 has one read port and one write port for the arithmetic unit 48, and is accessed from the arithmetic unit 48 by an 8-bit read / write bus. Of the 32 registers 50, 24 are accessible from outside the processor via the external interface 8, and the designated register 50 is read and written by inputting a clock, an address, and a read / write control signal from the outside. That is, the PE 44 includes a plurality of registers that can be read or written by a predetermined address.

  When accessing from the outside of the register 50, one register 50 of each PE can be accessed by one external port, and the PE number (0 to 255) is designated by the address inputted from the outside (in the PE) The numbers from 0 to 255 are assigned as PE numbers in order from the left side of Fig. 2. The PE numbers are also called PE addresses.) Therefore, a total of 24 external ports for register access are installed.

  The arithmetic unit 48 includes a 7-to-1 multiplexer 58, a shift extension circuit (shifter) 60, a 2-to-1 multiplexer (MPX) 61, a 16-bit ALU 52, an A register 54, and an F register 56. I have.

  The 7-to-1 multiplexer 58 is provided at the connection portion between the register 50 and the arithmetic unit 48, and the data of the register 50 that is 1, 2, and 3 away from the front (the smaller PE number) in the PE parallel direction. The data of the register 50 that is one, two, three away from the rear (the one with the larger PE number) and the data of the register 50 in the center (that is, the same PE) can be selected as an operation target. The 8-bit data in the register 50 can be shifted to the left by an arbitrary bit by the shift extension circuit 60 and input to the ALU 52.

  The 16-bit ALU 52 is 16 bits of data read from the register 50, data given from the GP 4 (output of the 2-to-1 multiplexer 61), or data read from the F register 56 in the operation by the PE instruction. The input of one side of the ALU 52 is input, the content of the A register 54 is input to the other side, and the result is stored in the A register 54. Therefore, an operation is performed on the A register 54 and data supplied from the R0 to R31 registers or GP4. The F register 56 is also referred to as a temporary register, and is used for saving the operation result stored in the A register 54. The result of the F register 56 can also be used for the operation by the 16-bit ALU 52. is there. In addition, an 8-bit condition register (also referred to as a T register) (not shown) enables invalidation / validation control of operation execution for each PE 44, and only a specific PE 44 can be selected as an operation target.

  The PE-RAM 20 is a work memory for storing data in the middle of arithmetic processing, and can read or write data held in the register file 14 (register 46) at a time as shown in FIG. . That is, the PE-RAM 20 has a data bit width (8 bits × 256) for all PEs. The address and read / write control are performed from the DMA device 22. A control signal such as an address input from the DMA device 22 is input to an address decoder 22a, and data at a specified address is read or written. That is, the PE-RAM 20 can input / output data only to / from the PE 44 and has a data bit width that can be accessed by at least two or more PEs 44 at the same time. Data is read out.

  The DMA device 22 includes a counter 22a and an FF 22b. The DMA device 22 accesses the PE-RAM 20 by a DMAStart signal from the GP 4. Multiplexers (MPX) 22c, 22d, and 22e are provided between the PE-RAM 20, the GP4, and the DMA device 22. The multiplexer 22 c switches the address (A) for the PE-RAM 20 to one output from either the GP 4 or the DMA device 22. The multiplexer 22 d switches the read / write control signal (R / W) for the PE-RAM 20 to one output from either the GP 4 or the DMA device 22. The multiplexer 22 e switches the chip select (CS) for the PE-RAM 20 to one output from either the GP 4 or the DMA device 22.

  Switching of each multiplexer (22c, 22d, 22e) is switched by a DMA signal (see FIG. 5) output from the DMA device 22. The DMA signal is a Hi level when the DMAStart signal is input, and becomes a Low level when the data transfer is completed. In the case of the Hi level, each multiplexer supplies a signal output from the DMA device 22 to the PE-RAM 20. It is like that.

  Although detailed operation will be described later, the counter 22a is sequentially incremented by setting the PE address. In other words, the initial value is set to “0” and increments sequentially until counting to “255”. The FF 22b is a register (flip-flop) in which data output from the R31 register of the register file 14 input from the common data bus 51 is stored. After being stored in the FF 22b, the FF 22b is sent to the multiplexer 22c as an address of the PE-RAM 20. Is output.

  As shown in FIG. 3, the data read from the PE-RAM 20 can be written to the R31 register of the register file 46 of each PE 44. For this purpose, the data is generated in the counter 22a and the DMA device 22. A decoder 57 is provided corresponding to the R31 register of each PE 44, to which the PE designation address line 53 and the R / W control signal line 55 to which the R / W signal to be output is input are input and the R31 register is read and written. ing.

  FIG. 4 is different from FIG. 3 in that the R31 register of PE44 (PE (0)) to which PE number 0 is assigned is A0, the R31 register of PE (1) is A1,..., PE (255). It is the figure which showed that A255 was stored in the R31 register. In this embodiment, different values are set in advance in the respective R31 registers as described above, and as shown in the timing chart of FIG. 5, when a DMAStart signal is subsequently input from GP4, the initial value “0” is output from the counter 22a. Is output to the PE designation address line 53 and the R / W control signal line 55 is output as a value indicating read. Then, the value (A0) of the R31 register of PE (0) is read to the common data bus 51.

  In the next cycle (after two clocks in FIG. 5), the counter 22a is incremented, the value (A1) of the R31 register of PE (1) is read to the common data bus 51, and the PE read to the FF 22b in the previous cycle. The value (A0) of the R31 register (0) is stored, the value (A0) is given as the address of the PE-RAM 20, and the data stored at the address A0 is output from the PE-RAM. That is, the DMA device 22 functions as a data transfer unit that sequentially reads the values stored in the R31 register for each PE 44 and outputs the read values as addresses of the PE-RAM 20.

  The data at the address A0 output from the PE-RAM 20 is written into the R31 register of PE (0) at the end of the cycle. The decoder 57 has a pipeline register therein, the read address input from the PE designation address line 53 is delayed by the timing at which data is read from the PE-RAM 20, generates a write enable signal, and supplies it to the R31 register. . In this way, control at the time of reading and writing can be performed substantially only by the PE designation address line 53. In addition to the method of delaying the write enable signal by the decoder 57 of each PE 44, only PE (0) may be delayed, and after PE (1), the interval between PEs may be shifted. In other words, the decoder 57 functions as a write control unit that performs control to store the data read from the PE-RAM 20 in at least the R31 register of the PE 44 from which the address of the data is read.

  Then, by repeating the above-described cycle, each PE44 stored in the R31 register sequentially reads the independent address values A0 to A255 from PE (0), and the data stored in the PE-RAM 20 is read. Sequentially writing back to the R31 register can be performed with a shorter cycle number than before. Conventionally, in order to do this, it has been necessary to specify PE44, set the address of the designated PE44, and read from the PE-RAM 20 with an instruction by GP4, which took many cycles. .

  The operations described above are summarized in the flowchart of FIG. First, an address is set in the R31 register of each PE 44 using a PE instruction or the like (step S1), and when a DMAStart signal is input from GP4, the DMA device 22 starts operating (step S2). The address value is read from the R31 register of the PE 44 specified in (Step S3), output to the PE-RAM 20, and the data at the address is read and stored in the R31 register of the corresponding PE 44 (Step S4).

  Then, the value of the counter 22a is judged (step S5), and if the value of the counter 22a indicates the last PE number, the process ends. If not, the counter 22a is incremented (step S6) for the next PE44. Steps S3 and S4 are repeated. Whether or not it is the last PE number may be determined by, for example, setting the number of PEs in the DMA device 22 in advance and comparing it with the set value by a control circuit (not shown) in the DMA device 22.

  According to the present embodiment, the SIMD type microprocessor 2 controls the PE-RAM 20 in which data is input / output only to / from the register file 14 of the processor element group 6, and the data transfer control between the PE-RAM 20 and the register file 14. The DMA device 22 is provided, and the DMA device 22 sequentially reads the independent address values stored in the R31 register of each PE 44 in the order of the PE number, and sequentially writes the data stored in the PE-RAM 20 to the R31 register. In order to restore it, it is possible to perform a process of referring to data at different addresses by each PE 44, such as a rotation process, by adding only a small number of circuits.

  In addition, since the GP 4 and each PE 44 can perform other processing not related to the PE-RAM 20 during the data transfer by the DMA device 22, the processing efficiency of the SIMD type microprocessor 2 can be improved.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. Note that the same parts as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted. FIG. 7 is a block diagram showing the principal part of a SIMD type microprocessor according to the second embodiment of the present invention. FIG. 8 is a configuration diagram showing the configuration of the decoder shown in FIG. FIG. 9 is an explanatory diagram showing the decoding conditions of the write decoder shown in FIG. FIG. 10 is an explanatory diagram showing an example of an address setting value stored in the R30 register of the SIMD type microprocessor shown in FIG. 7 and data after data shaping is performed on the example. FIG. 11 is a timing chart showing a data read operation from the PE-RAM of the SIMD type microprocessor shown in FIG.

  As shown in FIG. 7, in this embodiment, the configuration of the DMA device 22 and the configuration of the decoder 57 are different from those in the first embodiment. In this embodiment, an address value is set in the R30 register of the register file 14, and the data read from the PE-RAM 20 is stored in the R31 register.

  The DMA device 22 is provided with an adder 22g instead of the counter 22a. The adder 22g is a circuit having an addition function in addition to the increment function of the counter 22a. The DMA device 22 is provided with a decoder 22f. The decoder 22f outputs an operation control signal (increment or addition, addition value) to the adder 22g according to the value read from the R31 register stored in the FF 22b.

  As shown in FIG. 8, the decoder 57 (57 ′) according to the present embodiment includes a read decoder (Read-DEC) 57a, a write decoder (Write-DEC) 57b, an FF 57c, and an AND circuit 57d. I have.

  As in the first embodiment, the read decoder 57a reads the Read decode signal when its own PE number is indicated based on the address value input from the PE designation address line 53 (PEA terminal of the DMA device 22). (Read enable signal) is asserted and output to the R30 register.

  The write decoder 57b is true when the self PE number is greater than or equal to the value input from the PE designation address line 53, and false otherwise. FIG. 9 shows conditions for each PE 44. “==” in FIG. 9 means that the left side and the right side are equal, and “<=” means that the right side is equal to or greater than the left side. That is, the output becomes active (Hi) when the condition that the self PE number is greater than or equal to the value input from the PE designation address line 53 is satisfied.

  The FF 57c is a pipeline register for delaying the output of the write decoder 57b. Although FIG. 8 shows a single stage, the number of stages may be appropriately adjusted in accordance with the read timing from the PR-RAM 20.

  The AND circuit 57d is a circuit that performs an AND operation on the output of the FF 57c, the R / W control signal line 55, and the most significant bit (MSB) of the FF 22b. Note that the R / W control signal line 55 and the most significant bit of the FF 22b are operated with signals with inverted logic levels. That is, when the FF 57c is at Hi level, the R / W control signal line 55 is at Low level, and the most significant bit of the FF 22b is at Low level, the write decode signal (write enable signal) is asserted and output to the R31 register.

  In this embodiment, when the same address continues in the reading order among the addresses stored in the R30 register, data is written to the R31 register of the PE 44 having the same address in one access. For example, when an address value as shown in FIG. 10A is stored in the R30 register of each PE 44, the following 10 instructions are first executed for the processor element group 6. That is, if the same address continues among the addresses stored in the R30 register, when the address is first output as the address of the PE-RAM, it is written to the R31 register of the PE 44 indicating the same address. And writing to the PE 44 corresponding to the same value thereafter is controlled to be restricted.

(1) If the condition that the value of the R30 register is the same value as the PE 44 with the previous PE number is true, the value of the temporary register (F register 56) is set to “81h”.
(2) If the condition of (1) is true and the value of the R30 register is equal to the PE with the next PE number, “1” is added to the value of the temporary register.
(3) If the condition of (1) is true and the value of the R30 register is equal to the PE whose number is two behind, the value of the temporary register is incremented by “1”.
(4) If the condition of (1) is true and the value of the R30 register is equal to the PE whose number is three behind, the value of the temporary register is incremented by “1”.
(5) If the condition of (1) is true and the value of the R30 register is the same as that of the PE whose number is four behind, the value of the temporary register is incremented by “1”.
(6) If the condition of (1) is true and the value of the R30 register is equal to the PE whose number is five behind, the value of the temporary register is incremented by “1”.
(7) If the condition of (1) is true and the value of the R30 register is equal to the PE whose sixth PE number is six, the value of the temporary register is incremented by “1”.
(8) If the condition of (1) is true and the value of the R30 register is the same as that of the PE whose number is seven behind, the value of the temporary register is incremented by “1”.
(9) If the condition of (1) is false, the value of the original data is set in the temporary register.
(10) Transfer the value of the temporary register to the R30 register.

  The above 10 instructions are sequentially executed by each PE 44 as PE instructions, whereby the data in FIG. 10A is shaped into data as shown in FIG. In the data shaping column of FIG. 10B, the MSB, the original data value, or the value accumulated in the temporary register by the instruction is described in this order. By operating as described above, in this embodiment, among the 8 bits of the register, the MSB is a code for identifying whether it is an address or a continuous number, and the following 7 bits are an area for storing the address or the continuous number.

  For example, in the case of PE (0), the conditions of the instructions (1) to (8) of the result of 10 instructions are false, the conditions of the instructions of (9) and (10) are true, and the original data is stored in the R30 register. The value A0 is set (MSB is “0” and the remaining 7 bits are “A0”). In the case of PE (1), the conditions of the instructions (2) to (9) of the 10 instructions are false, the conditions of the instructions (1) and (10) are true, and “81h” is set in the R30 register. (MSB is “1” and the remaining 7 bits are “1”). That is, PE (0) stores an address and PE (1) stores a continuous number. Although the number of instructions is 10 in the above, the range to be referred to needs to be a range in which PE 44 can be referred to by one instruction, and therefore the number of instructions may vary depending on the configuration of the processor element group 6.

  FIG. 11 shows a timing chart of the operation of this embodiment. The R30 register stores the value after data shaping by the above 10 instructions. Thereafter, when the DMAStart signal from GP4 is input, the adder 22g outputs the initial value “0” to the PE designation address line 53 and the R / W control signal line 55 outputs a value indicating read. Then, the value (0, A0) of the R31 register of PE (0) is read to the common data bus 51 (cycle T1).

  In the next cycle T2 (after two clocks in FIG. 11), the adder 22g is incremented and the value (1, 1) of the R30 register of PE (1) is read to the common data bus 51, and the FF 22b is read in the previous cycle. The value (0, A0) of the read R30 register of PE (0) is stored, the value (0, A0) is given as the address of PE-RAM 20, and the data stored at address A0 from PE-RAM 20 Is output. In this cycle, the R / W control signal line 55 is switched to a value indicating writing.

  The data at the address A0 output from the PE-RAM 20 is written into the R31 registers of PE (0) to (255) at the end of the cycle. As described above, the write decoder 57b becomes true when the self PE number is equal to or greater than the value input from the PE designation address line 53. Therefore, when the PE designation address line 53 is "0", the PE (0 ) To (255), the above condition is satisfied. Therefore, the write enable signal is asserted with respect to the R31 registers of PE (0) to (255) and writing is performed.

  In the next cycle T3, the adder 22g is incremented, the value (0, A2) of the R30 register of PE (2) is read to the common data bus 51, and the PE (1) read in the previous cycle to the FF 22b. The value (1, 1) of the R30 register is stored. Although this value (1, 1) is given as an address to the PE-RAM 20, when the MSB of the FF 22b is “1” due to the configuration of the decoder 57 ′ shown in FIG. 8, the AND circuit 57d asserts the write enable signal. Therefore, the data read from the PE-RAM 20 is not written to the R31 register of any PE 44.

  In the next cycle T4, the adder 22g is incremented, the value (0, A3) of the R30 register of PE (3) is read to the common data bus 51, and the PE (2) read in the previous cycle to the FF 22b. The value (0, A2) of the R30 register is stored, the value (A2) is given as the address of the PE-RAM 20, and the data of the address A2 is output from the PE-RAM 20. At this time, the data read from the PE-RAM 20 is written to the R31 registers of PEs (2) to (255) at the end of the cycle, as in the case of writing the data at the address A0.

  In the next cycle T5, the adder 22g is incremented and the value (1, 2) of the R30 register of PE (4) is read to the common data bus 51, and the R30 of PE (3) read in the previous cycle to the FF 22b. The register value (0, A3) is stored, the value (0, A3) is given as the address of the PE-RAM 20, and the data of the address A3 is output from the PE-RAM 20. At this time, the data read from the PE-RAM 20 is written to the R31 registers of PEs (3) to (255) at the end of the cycle, as in the case of writing the data at the addresses A0 and A2.

  In the next cycle T6, the adder 22g is incremented, the value (1, 1) of the R30 register of PE (5) is read to the common data bus 51, and the PE (4) read in the previous cycle to the FF 22b. The value (1, 2) of the R30 register is stored. Although the values (1, 2) are given as addresses to the PE-RAM 20 as in the cycle T3, the write enable signal is not asserted from the decoder 57 'shown in FIG. Data is not written to the R31 register of any PE44. The same applies to the next cycle T7.

  In the next cycle T8, the adder 22g is incremented and the value (1, 3) of the R30 register of PE (7) is read to the common data bus 51, and at the same time, the R30 of PE (7) read to the FF 22b in the previous cycle. The register value (0, A6) is stored, the value (0, A6) is given as the address of the PE-RAM 20, and the data of the address A6 is output from the PE-RAM 20. At this time, the data read from the PE-RAM 20 is written to the R31 registers of PEs (6) to (255) at the end of the cycle, as in the case of writing the data at the addresses A0, A2, and A3.

  In the next cycle T9, the adder 22g is incremented, the value (1, 2) of the R30 register of PE (8) is read to the common data bus 51, and the PE (7) read in the previous cycle to the FF 22b. The value (1, 3) of the R30 register is stored. Although this value (1, 3) is given as an address to the PE-RAM 20 as in the cycles T3, T6, and T7, the write enable signal is not asserted from the decoder 57 'shown in FIG. The read data is not written to the R31 register of any PE 44.

  In cycle T9, since the MSB of FF 22b is “1” and the value of the lower 7 bits of FF 22b is 3 or more, the value obtained by subtracting “1” from the value of the lower 7 bits is added by adder 22g. Yes. That is, the decoder 22f controls to add “2” obtained by subtracting “1” from “3” which is the value of the lower 7 bits to the adder 22g. The adder 22g performs the increment operation except when the condition that the MSB of the FF 22b is “1” and the value of the lower 7 bits of the FF 22b is 3 or more is satisfied.

  In the next cycle T10, since the value calculated in the previous cycle is stored in the adder 22g, the value (0, A10) of PE (10) is read to the common data bus 51. That is, one PE number is skipped when skipping from cycle T9 to cycle T10. As shown in FIG. 10A, the skipped PE (9) has an address “A6”, and the value read from the address A6 is already R31 of the PE (9) in cycle T8. Since it is also written in the register, there is no problem even if it is skipped. That is, among the addresses stored in the R30 register, the PE number for reading the address stored in the R30 register is skipped according to the number of consecutive identical addresses.

  By operating as described above, the data at address A0 is written to the R31 register of PE (0), (1), the data at address A2 is written to the R31 register of PE (2), and PE (3 ) To (5), the data of the address A3 is written into the R31 register, and the data of the address A6 is written into the R31 registers of the PEs (6) to (9), as shown in FIG. Address data is written to each PE 44.

  According to the present embodiment, first, the address value stored in the R30 register in advance is subjected to data shaping, and either the address value itself or data indicating that the same address continues is stored. In the case of an address value, the data read from the PE-RAM 20 is written to the R31 register only for the PE 44 that satisfies the condition that its own PE number is equal to or greater than the PE number input from the DMA device 22. In the case of data indicating that the same address is continuous, the writing to the R31 register is not performed. Therefore, when the same address is continuous, the data writing can be completed at once.

  In addition, the data indicating that the same address is continuous includes a continuous number. When the continuous number is 3 or more, a value obtained by subtracting 1 from the continuous number is added to the adder for specifying the PE number. Therefore, when the same address continues for a long time, the PE number can be skipped (skip), and the number of cycles for data transfer can be reduced. In particular, in image processing such as small-angle rotation, since the number of PEs accessing the same address is relatively large, the configuration of this embodiment is effective in reducing the number of cycles of the image processing.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. The same parts as those in the first and second embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 12 is a main part configuration diagram of a SIMD type microprocessor according to the third embodiment of the present invention.

  In the present embodiment, a scale setting register 22h, an offset setting register 22i, a multiplier 22j, an adder 22k, and an FF 22m are added to the DMA device 22 with respect to the second embodiment. Is different.

  The scale setting register 22h is a register that sets a scale value (multiplier) for the address value read from the R30 register. The offset setting register 22i is a register for setting an offset value (addition number) for the address value read from the R30 register. Note that the scale setting register 22h and the offset setting register 22i can be set by an instruction executed by GP4, a data bus (not shown), or the like.

  The multiplier 22j multiplies the value stored in the FF 22b and the scale value set in the scale setting register 22h. The adder 22k adds the offset value set in the offset setting register 22i to the output of the multiplier 22j.

  The FF 22m is a register (flip-flop) in which the output of the adder 22j is stored, and the output of the FF 22m is output from the DMA device 22 as the address of the PE-RAM 20. Needless to say, the bit width of the data output through the multiplier 22j and the adder 22k is the same as the bit width of the address given to the PE-RAM 20.

  According to the present embodiment, since the scale can be set in the scale setting register 22h and the offset value can be set in the offset setting register 22i, the bit width of the address set in the R30 register is, for example, 7 bits. However, it is possible to specify an address in a range beyond that. In addition, various data reading methods (data storage methods) from the PE-RAM 20 are possible, for example, by using a value obtained by doubling a value read from the R30 register as an address. That is, the bit width of the effective address can be increased as the address of the PE-RAM 20 even with a register having a small bit width.

  In the third embodiment described above, only one of the register 22h for setting the scale and the register 22i for setting the offset may be provided. Of course, in that case, only a circuit corresponding to the multiplier 22j and the adder 22k is provided.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 processor system 2 SIMD type microprocessor 8 external interface 12 memory (external memory)
20 PE-RAM (memory)
22 DMA device (data transfer means)
22h Scale setting register (register to set multiplier)
22i Offset setting register (register for setting offset value)
R30, R31 registers (multiple registers that can be read or written by specified addresses)

Japanese Patent No. 4504861 Japanese Patent Laid-Open No. 03-211688 JP 2005-269502 A Japanese Patent No. 4294190

Claims (6)

In a SIMD type microprocessor having a plurality of processor elements each having a plurality of registers that can be read or written by a predetermined address,
A memory capable of inputting / outputting data only to / from the processor element and having a data bit width accessible by at least two or more processor elements simultaneously;
A data transfer means for sequentially reading a value stored in one of the plurality of registers for each of the processor elements, and outputting the read value as an address of the memory;
Write control means for performing control for storing data read from the memory in at least the register of the processor element from which an address corresponding to the data is read;
A SIMD type microprocessor characterized by comprising:   When the same value continues among the values stored in the one register, the write control means controls to write to the register of the processor element in which the same value is stored by one reading. 2. The SIMD type microprocessor according to claim 1, wherein control is performed so as to restrict subsequent writing of the processor element corresponding to the same value to the register.   The data transfer means skips the processor element that reads the value stored in the one register according to the number of consecutive same values among the values stored in the one register. The SIMD type microprocessor according to claim 2.   The data transfer means includes at least one of a register for setting an offset value and a register for setting a multiplier for an address read from the register, a register for setting the offset value, a register for setting the multiplier, and the register An SIMD type microprocessor according to any one of claims 1 to 3, further comprising: an arithmetic unit that performs an operation on a value read from the processor. In a processor system having a SIMD type microprocessor having an external interface for performing data transfer control with the outside, and an external memory capable of writing or reading data from the external interface data,
The processor system, wherein the SIMD type microprocessor is the SIMD type microprocessor according to any one of claims 1 to 4. In a data processing method of a SIMD type microprocessor having a plurality of processor elements each having a plurality of registers that can be read or written by a predetermined address,
A value stored in one of the plurality of registers is read for each processor element,
The read value is an address of a memory having a data bit width that allows data input / output only with the processor element and is accessible to at least two or more processor elements simultaneously,
A data processing method for a SIMD type microprocessor, wherein the data read from the memory is stored in at least the register of the processor element from which an address corresponding to the data is read.

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