JP2018156119A - Simd type parallel arithmetic apparatus, simd type parallel arithmetic semiconductor chip, simd type parallel arithmetic method and apparatus including simd type parallel arithmetic apparatus and semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a SIMD type parallel arithmetic algorism that maximizes an efficiency of parallel operation of the SIMD type (single instruction/multiple data) and increases integration degree, increases a calculation speed by making it possible to drive a calculation core 100%, significantly reducing power consumption, realizing arbitrary degree of parallelism and computation time, and easily installing into a semiconductor ASIC and FPGA.SOLUTION: An arithmetic apparatus 203 configured by a memory cell group 202 consisting of a number of memory cells 104 and N arithmetic units 109 reads data in which one data is configured by two or more memory cells 104 by accessing N pairs at once by an address line 102 for accessing a memory cell 104 of the memory cell group 202, inputs them into an arithmetic input of N arithmetic units 109 in parallel, and writes N pairs of arithmetic result data of arithmetic outputs of the N arithmetic units into the N memory cells 109 at once.SELECTED DRAWING: Figure 2

Description

The present invention relates to a SIMD type parallel arithmetic device, a SIMD type parallel arithmetic semiconductor chip, a SIMD type parallel arithmetic method, a SIMD type parallel arithmetic device, and a device including a semiconductor chip.

In order to clarify the object of the present invention, problems of CPU and GPU will be shown.
FIG. 1 is an example of feature data collation.
In the database, 8-bit (0 to 255) data from feature 1 to feature N is registered from subject A to subject Z, and inquiry matching data to be collated with this database is given. The difference between the characteristic data of each other is obtained, the sum of the differences (difference sum operation) is obtained, and it is shown that the object C is determined as the similarity matching result, assuming that the smallest one is the most similar object. Yes.

If the target of verification is to match the terrorists and criminal faces entering and leaving the international airport, the number of moths (persons) from subject A to subject Z is 1,000,000 (1M). 1K), it is necessary to repeat the difference sum calculation 1K * 1M = 1G times.
If the difference calculation 119 per time is set to 10 nsec with one CPU, it takes 10 seconds and cannot be used in real time.

If the collation target is collation of handwritten characters, if the number of characters from the object A to the object Z is Japanese, 3000 (3K) characters and 256 types of features are used, and 256 * 3K = 768K difference / sum operations 119 needs to be repeated.

If the difference calculation per time is set to 10 ns as before, 7.68 msec is required, and only about 130 characters can be read in one second. Time is required.

The above is an example of the difference-sum operation 119 for evaluating the degree of similarity that is convenient for explaining the intent and purpose of the present invention, but the product-sum operation 120 and other matrix operations (vector operations) are also the same. The application has no time for enumeration such as biometric authentication such as fingerprints and veins and collation of seals.
Matrix operations are also indispensable for simulations of weather and fluid molecules that handle huge amounts of data.
Iterative processing of a large amount of data, such as calculation of matrix data, is a very difficult process for a general CPU.
The CPU is a general-purpose processor that performs all processes of information processing. However, since it is based on sequential processing, various problems remain in information processing in which repeated calculations occur frequently.

A GPU used to alleviate such problems of the CPU attempts to solve these problems by carrying a large number of arithmetic cores in one chip and performing parallel processing.
The GPU was born for the purpose of realizing image processing requiring a large amount of arithmetic processing at high speed, but basically follows an information processing architecture similar to that of a CPU.

Recently, GPGPU is used for information processing that requires a large amount of matrix vector calculations such as protein structure analysis, fluid analysis, and vibration analysis, in addition to image processing.
GPUs are mostly used in SIMD type information processing, but follow the same information processing architecture as CPUs. Therefore, each GPU has its own dedicated memory and a dedicated memory. The computing unit is configured to perform computation independently based on each program and data.

Since each arithmetic unit operates independently as described above, for example, the arithmetic unit includes a circuit for decoding a program, a circuit for controlling an arithmetic task, a memory address decoder, and an arithmetic core. It is necessary to have each circuit independently, such as a memory for moving, resulting in overlapping circuits and memories.

In addition, since each has a structure that operates independently, the OS of the GPU is normally activated under the control of the CPU, and the program is controlled in parallel so that the load of the GPU computing unit is always appropriate and can be operated evenly. However, it is difficult to apply processing equally to each arithmetic core, and even if there are many arithmetic cores that cause play of arithmetic cores, it is meaningless if there are many arithmetic cores playing.

Also, when the GPU has thousands of computing cores, for example, it consumes a large amount of power exceeding 300 watts, for example, and heat generation increases, and it cannot be used as the brain of a mobile device or a robot.

The limit of semiconductor miniaturization technology is approaching, and the time when performance improvement cannot be expected with the conventional architecture will soon come. However, there are increasing expectations for improvement of computing performance and power saving in various fields.

Even in the neural network which is one of the artificial intelligence technologies that have recently been talked about, the scale of the system has become extremely large, and it has become a major obstacle for practical use in order to proceed with development.
For example, a neural network needs to be repeatedly trained with various conditions in order to obtain an optimal operation. However, for a large-scale network, for example, even if 16,000 CPUs are used, the learning time is several days. It takes about a week to publish online.

Needless to say, it is difficult to obtain an optimum operation by one learning, and tuning must be performed repeatedly and repeatedly to obtain an optimum operation.
Even if such a huge amount of hardware resources is used, it takes a lot of learning time, which hinders the growth of this technology.

As will be described later, if the neural network needs to execute a large number of product-sum operations 120, the calculation performance can be improved without making a large-scale system, a small power saving and low heat generation device can be realized, and the learning time can be shortened. The evolution of this technology is greatly accelerated.

As described above, there is an increasing demand for efficient parallel processing without making the system large-scale.

The feature of the present invention is that the SIMD type (single instruction / multiple data) parallel arithmetic processing can be shared, and it is common to remove unnecessary circuits and functions, thereby improving the degree of integration, power consumption and heat generation. The parallel computing device and the parallel semiconductor computing chip that provide the highest effect of SIMD type parallel computing processing are provided.

Optimizing memory access methods is indispensable in order to increase the computing power of GPUs, and various techniques have been adopted for this purpose. However, since GPUs are based on SIMD type operations, GPUs have been greatly streamlined. Obviously, if the degree of integration is increased and the calculation efficiency of the calculator is increased, the speed can be increased.

The inventor of the present application has proposed that a memory-type processor based on memory-type computing can solve various problems of Neumann-type computers, and has filed various patents so far and has been putting it into practical use. The literature is shown.

Japanese Patent No. 4588114, a memory having an information narrowing detection function is a memory type processor that realizes image and sound pattern matching at an ultra-high speed.
It has been proven to be tens of thousands of times faster than conventional software pattern matching.

Japanese Patent Application No. 2013-264863 is a memory type processor that searches for a record in a database at a very high speed.
It has been demonstrated that it is several tens of thousands of times faster than conventional software search, and this technique has triggered the present invention.

The Japanese Patent Application No. 2008-123479 of the invention of another person and the memory array structure therefor are composed of a SIMD type processor and a memory, but for the purpose of avoiding data collision, the purpose and method are completely different. Is.

Japanese Patent Application No. 2011-023037 A parallel data processing apparatus includes a SIMD array and performs an operation for each block independently, but the method is completely different.

Although details are not clear, a micron automaton arithmetic chip reads out a 256-row × 49512-column DRAM array in parallel and realizes an ultra-high-speed automaton arithmetic on the net, but the purpose of the present invention is It is different, and there is no SIMD type arithmetic system that directly drives the memory address line as in the present invention from other prior inventions.

Japanese Patent No. 4588114 Japanese Patent Application No. 2013-264863 Japanese Patent Application No. 2008-123479 Japanese Patent Application No. 2011-023037

Conventional SIMD type parallel computation such as GPU is composed of an independent computation core and its memory, so the circuit scale becomes large and the degree of integration does not increase. Also, preparation processing for GPU drive via CPU and GPU OS Data transfer to the memory, the accompanying overhead of computing units within the GPU, task allocation control and management, and the play of the computing units itself are sacrificed, and the calculation speed tends to increase, and the power consumption tends to increase.

The present invention maximizes the efficiency of SIMD type parallel operation to improve the integration degree, and not only enables the hardware-limited operation speed to be realized, but also makes it possible to select an appropriate operation speed and an appropriate power consumption. A SIMD parallel operation algorithm that can realize an arbitrary parallelism and operation time by using a plurality of elements and can be easily mounted on a semiconductor ASIC and an FPGA is provided.

According to a first aspect of the present invention, there is provided an arithmetic unit comprising a memory cell group composed of a large number of memory cells and N arithmetic units, and an address line for accessing the memory cell of the memory cell group has one data. A plurality of data access means capable of batch-accessing N sets of data composed of two or more memory cells is provided, and N sets of data on the collectively accessed address lines are read in batches and used as calculation inputs of the N computing units. Means for inputting in parallel and means for collectively writing N sets of operation result data of operation outputs of the N arithmetic units to the N sets of memory cells of the address line accessed in batch. Features.

In claim 2, the arithmetic unit is (1) arithmetic operation (2) floating point operation (3) comparison operation (4) logic operation (5) shift operation (6) or more multistage operation or more (1) to (6 It is an arithmetic unit that executes any one of the operations (1).

According to a third aspect of the present invention, there is provided an arithmetic means for masking a part of the arithmetic unit and a part of the input bits of the arithmetic unit and eliminating the influence of the arithmetic operation on a part of the arithmetic unit and a part of the input bits of the arithmetic unit 109. It is characterized by having.

According to a fourth aspect of the present invention, there is provided means for externally outputting the calculation result of the calculator.

According to a fifth aspect of the present invention, there is provided means for inputting data from the outside in parallel to the arithmetic inputs of the N arithmetic units of the arithmetic unit.

According to a sixth aspect of the present invention, the parallel arithmetic device according to the first aspect is configured in one semiconductor chip.

The present invention is characterized in that it is combined with another LSI such as a CPU or GPU and configured in one semiconductor chip.

An eighth aspect of the present invention is characterized in that the parallel computing device according to the first aspect is mounted on an FPGA.

According to a ninth aspect of the present invention, the memory cell group and the arithmetic unit are divided, and the memory cell is an independent chip.

According to a tenth aspect of the present invention, the memory cell group and the arithmetic unit are divided, and the arithmetic unit is an independent chip.

According to an eleventh aspect of the present invention, a plurality of semiconductor chips according to the sixth, seventh and eighth aspects are prepared and operated in parallel.

According to a twelfth aspect of the present invention, a plurality of memory chips according to the ninth aspect and a single arithmetic chip according to the tenth aspect are combined and operated in parallel.

According to a thirteenth aspect of the present invention, one memory chip according to the ninth aspect and a plurality of arithmetic chips according to the tenth aspect are combined and operated in parallel.

According to a fourteenth aspect of the present invention, data of a plurality of addresses are combined and operated in parallel as one data.

In claim 15, (1) SIMD type parallel arithmetic device (2) SIMD type parallel arithmetic semiconductor chip (3) SIMD type parallel arithmetic semiconductor memory chip (4) SIMD type parallel arithmetic semiconductor of claim 1 to claim 10 Arithmetic chip.
A system including any of (1) to (4) above.

FIG. 1 is an example of data collation (feature data collation). (Example 2) FIG. 2 shows an example of the overall configuration of a parallel arithmetic device or a semiconductor parallel arithmetic chip. FIG. 3 is a detailed configuration example of a parallel arithmetic device or a semiconductor parallel arithmetic chip. (Example 1) FIG. 4 is a configuration example of a neural network. Example 3 FIG. 5 is an example of a neural network unit.

FIG. 2 is an overall configuration diagram of the parallel arithmetic device and the parallel arithmetic semiconductor chip 201.
This figure omits the detailed circuit configuration of the memory and the calculation function, and is for explaining only the concept of the present invention. The upper part of the figure is the memory part 202, and the lower part of the figure is the calculation part. 203.

As will be described later, the type of the memory cell and the type of the arithmetic unit are arbitrary, and the device is configured by combining a plurality of LSIs, mounted on one semiconductor chip, or a semiconductor chip incorporating other functions. Is also free.

This parallel arithmetic device or parallel arithmetic semiconductor chip 201 is configured such that N arithmetic groups from arithmetic group 1 to arithmetic group N can perform completely parallel arithmetic.

The memory 103 is connected to one address line 102 so that data composed of a plurality of memory cells 104 can be accessed by one address 101 in all N groups, and an arbitrary address 101 can be selected (accessed). It is configured.

In this example, the address X to the address X + n is a memory cell 104 in which one data is 9 + 9 bits and the address Y to the address Y + m is 17 + 17 bits, and either one of the arithmetic input data A123 side or the arithmetic input data B124 side of the arithmetic unit 109 or It is configured to be added to both inputs.

The allocation of the memory cells may be determined in consideration of the necessary data width, sign, carry, etc. Needless to say, the data width affects the calculation accuracy.
Further, the memory cell 104 can be set to either the operation input data A123 side or B124 side.
The number of addresses is also arbitrary, and the number of operation groups is also arbitrary.
It is optional to have addresses with various data widths and to mix various operations.

For each bit line (data line) 105 of the arithmetic unit 203, the data of the memory cell group is read and assigned to the arithmetic input data 123 or 124 side of the arithmetic unit 109, or the arithmetic result 110 of the arithmetic unit 109 is stored in the memory. An R / W changeover switch 106 is provided for switching between writing to the cell group.

The arithmetic units 109 are arranged in N columns for each arithmetic group, and N pieces of data read out through the bit lines (data lines) 105 of the memory cells 104 that are accessed by designating addresses are input to the arithmetic units 109. In this example, external input data 125 (9 bits in this example) can be input to the arithmetic input data A123 side of the arithmetic unit 109, although it does not necessarily require external input data. ing.

It is also possible to perform batch processing calculations using only data stored in memory cells without using external input data.

The calculation result 110 of the calculator 109 is connected to the input / output interface 113, and the calculation result can be output as the calculation output 108 in an arbitrary output form such as PCI-e.
The memory storage data 108 can be input from the input / output interface 113 from the outside as data stored in the memory cell 104.

As described above, the calculation result 110 can be written to the memory 103 at the address specified and accessed through the bit line (data line) 105.
Although only an example, for example, when multiplication is performed between signed 8-bit data, a carry occurs. Therefore, it is only necessary to write to an address having a 17-bit data width from address Y to address Y + m shown in the figure.

Accordingly, in the case of this example, the NMD data in the memory unit and the N input data given from the outside are directly subjected to SIMD calculation in parallel with the N data, and the calculation result can be output or stored in the memory.

FIG. 3 shows details of one operation group.
This figure shows details of the memory 103, the arithmetic unit 109, the input data 125, and the input / output interface 113 of one group among the arithmetic groups 1 to N connected in parallel.
The memory cell 104 is composed of a total of 9-bit data of 8 bits data + signature 1 bit from address X to address X + n, and 2 sets of 8 bits data + 17 bits data of sign 1 bit in total from address Y to address Y + m. It consists of

As described above, the length of data and the allocation of the data are arbitrary.
In this example, the memory cell 104 is attached to both the arithmetic input data A123 side and the arithmetic input data B124 side of the arithmetic unit 109, and both data are read out, or only one of the memory cells is read out, or vice versa. It is possible to arbitrarily select whether to write both data or only one of the memory cells.

The above processing is performed by masking a part of the arithmetic unit 109, a part of the input bits of the arithmetic unit 109, and a part of the arithmetic output so that a part of the arithmetic unit 109 and a part of the arithmetic unit 109 are input. It is also possible to give a calculation condition so as to eliminate the influence of the calculation, or to ignore (mask) a part of the calculation result and store it in the memory cell.

The arrangement and usage of the memory cells, such as the type and length of data to be used, can be arbitrarily determined.

When the R / W switch 106 is R (read), data from the memory cell 104 at the accessed address is input to the arithmetic unit 109 through the bit line (data line) 105.
When the R / W switch 106 is W (write), it is possible to write the calculation result of the calculator 109 to the memory cell 104 at the accessed address.

Input data 125 (9 bits in this example) input from the outside is added to the input on the operation input data A123 side of the operation unit 109 through the read bit line of the memory cell and the OR gate described above.
This input data 125 is given in common (in parallel) from the arithmetic unit 1 to the arithmetic unit N.

In this example, the case where the input data 125 given from the outside is given to all the arithmetic units is shown, but different data can be inputted to each arithmetic unit 109.

It is also possible to connect the computing units 109 in multiple stages. In this case, it is not necessary to temporarily store the computation result 110 every time in the memory, so that the computation is extremely efficient and the speed can be increased accordingly. Details will be described later.

The feature of such SIMD type parallel circuit is compared with a circuit such as a GPU realized by an independent memory and an independent computing unit,
(1) The memory unit does not require a program storage memory for each arithmetic unit, and only a memory for arithmetic data storage is required, and only one address selection circuit (including an address decoder) is required.
(2) With respect to the calculation unit, a program decoder circuit for each calculation unit, a calculation task control and management circuit for each calculation unit, and the like become unnecessary.
The common partial circuit and the like can be largely omitted. Therefore, the degree of integration increases and the economic efficiency increases.

What is more characteristic is that accessing the address line 102 directly executes SIMD type parallel operations, so it is extremely efficient and fast without letting all the operation groups that have given a role play even for a moment. It becomes possible to make calculations.

In general operations, at least two cycles of reading data from the memory and operations based on the data are required.
In this method, one cycle can be achieved, that is, the highest speed operation can be performed by balancing the memory latency and the operation latency.
In general, the memory latency is larger. For example, if the memory is configured to directly drive a memory such as a register inside a computing unit or a high-speed cache memory, the ultra-high-speed parallel computation of the current semiconductor technology becomes possible. Become.

Therefore, without worrying about the operating rate of each computing unit as in the case of a normal GPU, the performance of parallel computing is always fast and reliable without being affected by the performance of the OS of the CPU or GPU and the skill level of the programmer. It is possible to produce a simple calculation result.

A case where the handwritten character collation shown in FIG. 1 is realized by the parallel arithmetic device or the parallel arithmetic semiconductor chip 201 of the present invention will be described.
Since the Japanese language used on a daily basis is about 3000 characters, the calculation group N is 3000 (3K). In this example, there are 256 types of features per character, and 3000 sets (groups) of memory and calculators are prepared. It shall be.

Since the characteristic data of this handwritten character is unsigned 8-bit data (0 to 255), one character is unsigned from address X to address X + 255 shown in FIG. Register (write).
This completes the preparation of the database and calculation.

In the above state, when obtaining the difference between the feature 1 of the collation data and the feature 1 of the database, first, the R / W selector switch 106 is set to R, that is, the reading mode, and the calculator 1 to the calculator N are externally connected. A subtraction command is given from the calculation condition 114 input.

At the time of collation, the collation data is given in parallel (simultaneously) from input 7 to input 0 of the input data 125, and is given in parallel (simultaneously) from the arithmetic group 1 to the arithmetic input data A123 side of the arithmetic units in the arithmetic group N.

By accessing and reading the address X stored in the feature 1 database and inputting it to the operation input data B 124 side, both operation data AB are added in parallel (simultaneously) from the operation unit 1 to the input of the operation unit N. It will be.

When calculation is performed under the above input and subtraction calculation conditions, the difference data of feature 1 is output in parallel (simultaneously) to the output of all 3K calculators 109.

Next, the R / W selector switch 106 is set to W, that is, the write mode, the address Y is accessed, and the above calculation result is temporarily stored in the calculation input data B124 side of the memory cell.

Similarly, when the difference of the feature 2 of the database is obtained, the R / W selector switch 106 is set to R, a subtraction command is given from the computing unit 1 to the computing unit N, and the feature of the collation data from the outside is given to the computation input data A123 side. Two pieces of data are given, and the arithmetic input data B124 side accesses and reads the address X + 1 in which the database of the characteristic 2 is stored, so that the arithmetic data of both AB are added in parallel from the arithmetic unit 1 to the arithmetic unit N.

By performing the calculation under the above input and calculation conditions, difference data is output in parallel to the outputs of all the arithmetic units 109.
The R / W selector switch 106 is set to W, and this calculation result is temporarily stored in parallel on the calculation input data A123 side of the address Y.

Next, when the R / W selector switch 106 is set to W, the calculation condition of the calculator 109 is added, and the previously stored address Y is read and input to the calculator 109, the two differences are added, and the characteristics 1 and 2 Are calculated in parallel.

This calculation result is temporarily temporarily stored again in parallel on the calculation input data B124 side of the address Y. The calculation input data B124 side of the address Y is the accumulated difference sum calculation result.
By repeating the above to the feature 256, the difference calculation 119 of 3000 characters is completed.

In this example, the arithmetic unit has a configuration of one stage per group. However, in the case of a configuration in which both the difference arithmetic unit and the sum arithmetic unit are prepared and connected in multiple stages, it is not necessary to temporarily store the feature difference data at the address Y every time. Therefore, more efficient calculation becomes possible.

Although this method can improve the performance to the hardware limit speed, as an example, if the difference calculation time of one of the above features is 1 nsec, the total matching calculation time of 256 features is 256 nsec, which is 10 nsec Even if it is 10n seconds, which is 2.56 microseconds, it is surely 3K times faster than the processing by one CPU described above.
In normal cases, it is often impossible to know how much throughput will be obtained unless the processing is actually executed, but this method always promises the calculation speed as the actual value.

The difference sum operation 119 result may be output through an interface such as PCI-e, and the minimum value may be obtained by a normal CPU or the like.

The following is an application to the neuro-network that has become a hot topic recently.
Although there are various types of neuro-networks, only the main points related to the present invention are shown in the most basic contents.

FIG. 4 is a configuration example of a neural network.
As shown in the figure, a general neuro network consists of several layers such as an input layer, an intermediate layer, and an output layer composed of a number of neuro units, and the output of one layer is the input of the next layer. It consists of a wired network.
Although the number of units constituting the neuronetwork is various, in this example, the case where the input layer, the intermediate layer, and the output layer are each 1000 (1K) and 3000 (3K) in total will be described.

FIG. 5 is a conceptual diagram of one unit of the intermediate layer constituting the neuro network.
One unit of the intermediate layer is given 1K inputs in parallel from the input layer, and the calculation results of the parallel inputs are aggregated and output as one output.
When this unit receives analog output data from the input neuron unit of the 1K input layer, the unit multiplies the connection load data set for each input 1 to n (1K in this example) by the value of the analog input data. A product-sum operation 120 of all input data and combined weight data is executed, and after completion of all the product-sum operations, a predetermined operation such as a threshold operation or a sigmoid function is performed and the result is output.

Needless to say, this processing is the most burdensome processing, and 1000 (1K) neuro units each need to repeat 1000 (1K) times for a total of 1 million (1M) times of product-sum operation 120. Will occupy the majority.
Similar product-sum operation processing must be performed in the output layer neural unit, and the entire network needs to perform a total of 2 million (2M) operations.

The above description shows an example of positive propagation, which is a general operation of a neural network from the input layer to the intermediate layer and from the intermediate layer to the output layer.
In the case of the calculation time of the positive propagation, if one CPU performs a product-sum operation in 10 nsec, it is 10 nsec * 2M times = 20 msec, which is not a particularly problematic number.

A neural network attempts to obtain a predetermined calculation result from a network by performing appropriate learning for the network.
Normally, this learning involves repeating backpropagation called backpropagation from the output layer to the intermediate layer and from the intermediate layer to the input layer, and it is necessary to repeat the learning until the error level of the evaluation function is less than or equal to a predetermined value for each learning. There is.

For example, in the case of a handwritten character or the like, for example, when learning “A”, for example, a handwritten character written by 100 people is read, and any character is repeatedly learned until “A” is output. It is necessary to perform back propagation operation for learning repeatedly until it becomes optimal.

This calculation usually needs to be repeated thousands of times per character, and the same processing needs to be repeated 3000 times, so learning at least 10M times (10 million times) is required.

Although details of the back propagation operation are omitted, these back propagation operations are also repeated for each unit of product-sum operation. In the neural network like this example, the 2M product-sum operation described above is reversed 10M times. The number of product-sum operations when propagation learning is performed is 20T.
Even if one CPU performs one product-sum operation continuously in 10 ns, if it repeats the operation 20T times, it takes 200,000 seconds and 55.5 hours for the product-sum operation alone. It becomes waiting time.

The learning as described above is rarely completed once, and it is necessary to tune the coupling load and the threshold value shown above while looking at the learning result.
The above is the biggest problem in the neural network technology. When the number of network units per layer exceeds 10,000 as in image recognition, the key is how to reduce the computation time using the GPU.
However, when aiming at high speed with a conventional GPU, the heat generation is large and the system becomes large and wastes a large amount of power.

Many FPGAs currently on the market are equipped with more than a thousand arithmetic units and SRAM as standard equipment. By combining these arithmetic units and memories, the present invention can be easily realized even with FPGAs. In a typical FPGA, since it is about several watts to several tens of watts, a chip with low power and high parallelism can be easily realized.

For example, when a 3K parallel arithmetic unit is mounted on the FPGA 1 chip and one product-sum operation 120 is 10 nsec, the time required for the product-sum operation of the learning time is reduced to 1 / 3K, that is, 66 seconds.
Needless to say, by using a plurality of these, it is possible to realize a system that is super parallel and ultra high speed and low power consumption.

The present invention using an FPGA whose circuit configuration can be freely modified is optimal for finding an optimum circuit by trial and error as in the case of a neural network.

When a semiconductor chip is formed according to the present invention, the calculation time can be shortened by about an order of magnitude as compared with an FPGA, and there is no useless circuit of a conventional SIMD circuit such as a GPU. I can do it.
In addition, since each core of the GPU is driven, overhead such as preprocessing is not required, and play of the arithmetic core can be eliminated, so that the hardware limit performance can be obtained.
This technology is therefore a slim, ultra-high speed new GPU dedicated to SIMD.

The precautions and applications of this technology are described below.

The feature of this technology is the address line drive capability.
Moreover, the inrush current of a large number of memory cell drives and arithmetic units can be limited by dividing the arithmetic group into several banks and reading / writing data with a slight time shift.
By switching the clock frequency, it is possible to freely control one calculation time, such as 1 ns to 10 ns, and to select an arbitrary calculation time depending on whether calculation performance is prioritized or power consumption is prioritized. It is possible to realize a computing unit having a large computing capacity per 1 W.
As described above, the limit of the semiconductor miniaturization technology is approaching, and it will produce extremely great value in the near future where the performance improvement cannot be expected with the conventional architecture.

So far, the arithmetic unit 109 has been described with a focus on the real four arithmetic operations 115. However, it is assumed that the arithmetic operation is a floating-point operation 127, and comparison operations 116 such as coincidence, magnitude, and range, and logical operations such as AND, OR, and NOT. 117, it can be used in common for the arithmetic operation of the arithmetic unit, the shift operation of the data across the arithmetic units, and the SIMD operation in which the above are combined in multiple stages.

For example, in the case of floating-point arithmetic, memory cell data may be allocated in accordance with the performance of the arithmetic unit 109.

In the case of long data having a long data length, it is also possible to repeatedly read data at a plurality of memory addresses and calculate the data read a predetermined number of times as one long data.

The memory cell 104 of the present invention can be used not only for SRAM memory, DRAM memory, and FLASH memory but also for all memory cells such as resistance memory and magnetic memory that will be on the market in the future.
Various memories and various memories can be mixed for each address in consideration of calculation performance and calculation cost.

When the memory unit 202 and the arithmetic unit 203 are independently separated and a device and a semiconductor chip that are independently separated are used in combination, it is possible to efficiently use memory resources and arithmetic unit resources without waste.

101 Address 102 Address line
103 memory
104 memory cells
105 bit line (data line)
106 R / W selector switch
107 Calculation input
108 Operation output & Memory storage data
109 Calculator
110 Operation result
111 Operation result register
112 OR gate
113 I / O interface
114 Calculation conditions
115 Arithmetic operations
116 Comparison operation
117 logical operations
119 Difference sum operation
120 multiply-add operation
123 Operation input data A
124 Calculation input data B
125 input data
126 code
127 Floating-point arithmetic 201 Parallel arithmetic device and parallel arithmetic semiconductor chip 202 Memory unit 203 Arithmetic unit

The SIMD type parallel arithmetic unit according to the present invention has a wide range of applications, increases the degree of parallel arithmetic integration, and can be freely set from a general arithmetic speed to an extremely high arithmetic speed. The optimal usage environment can be provided.
Since it can be easily realized with an FPGA, it is suitable not only for general data computation but also for an authentication function of a mobile device and a brain of a robot, and can replace many GPU needs with this technology.

Recently, GPGPU is used for information processing that requires a large amount of matrix vector calculations such as protein structure analysis, fluid analysis, and vibration analysis, in addition to image processing.
GPUs are mostly used in SIMD type information processing, but follow the same information processing architecture as CPUs, so there are many independent computing units or computing groups and dedicated memories for each computing unit. Each computing unit is configured to perform computation independently based on each program and data.

Since each arithmetic unit or arithmetic group operates independently as described above, for example, in an arithmetic unit, a circuit for decoding a program, a circuit for controlling an arithmetic task, a memory address decoder, It is necessary to have each circuit independently, such as a memory for operating an arithmetic core, resulting in overlapping circuits and memories.

Conventional SIMD type parallel computations such as GPUs are composed of independent computation cores or computation groups and their memories, so the circuit scale increases and the degree of integration does not increase. Also, GPU-driven through the CPU and GPU OS Preparatory processing, data transfer to the memory, the accompanying overhead of computing units in the GPU, task allocation control and management, etc., and the play of the computing units themselves, sacrifices the computation speed and tends to increase power consumption. .

When a semiconductor chip is formed according to the present invention, the calculation time can be shortened by about an order of magnitude as compared with an FPGA, and there is no useless circuit of a conventional SIMD circuit such as a GPU. I can do it.
In addition, since the computation cores and computation groups of the GPU are driven, overhead such as pre-processing is not necessary, and play of the computation core can be eliminated, so that the hardware limit performance can be obtained.
This technology is therefore a slim, ultra-high speed new GPU dedicated to SIMD.

Claims (15)

An arithmetic unit comprising a memory cell group consisting of a large number of memory cells and N arithmetic units, and an address line for accessing the memory cells of the memory cell group includes two or more data A plurality of data access means capable of collectively accessing N sets of data composed of memory cells is provided, and N sets of data of the address lines accessed in batch are read out at a time and input in parallel to the arithmetic inputs of the N arithmetic units. Means for simultaneously writing N sets of operation result data of operation outputs of the N arithmetic units to the N sets of memory cells of the address line accessed in batch. Type parallel computing device. The arithmetic unit is any one of (1) four arithmetic operations, (2) floating point operations, (3) comparison operations, (4) logic operations, (5) shift operations (6) or more combined, and more than (1) to (6) 2. The SIMD type parallel arithmetic device according to claim 1, wherein the arithmetic unit is configured to execute the above-described arithmetic operation. A calculation means is provided that masks a part of the arithmetic unit and a part of the input bits of the arithmetic unit, and eliminates the influence of the operation on a part of the arithmetic unit and a part of the input bits of the arithmetic unit 109. The SIMD type parallel arithmetic apparatus according to claim 1, wherein: 2. The SIMD type parallel arithmetic apparatus according to claim 1, further comprising means for outputting the arithmetic result of the arithmetic unit externally. 2. The SIMD type parallel arithmetic device according to claim 1, further comprising means for inputting external data to arithmetic inputs of the N arithmetic units of the arithmetic unit. 2. The SIMD parallel arithmetic semiconductor chip according to claim 1, wherein the parallel arithmetic device is configured in one semiconductor chip. A SIMD type parallel operation semiconductor chip characterized by being combined with a CPU and other LSIs and configured in one semiconductor chip. 2. The SIMD type parallel operation semiconductor chip according to claim 1, wherein the parallel operation device is mounted on an FPGA. 8. The SIMD parallel arithmetic semiconductor memory chip according to claim 5, wherein the memory cell group and the arithmetic unit are divided, and the memory cell is an independent chip. 8. The SIMD type parallel arithmetic semiconductor arithmetic chip according to claim 5, wherein the memory cell group and the arithmetic unit are divided, and the arithmetic unit is an independent chip.   9. A SIMD type parallel operation method comprising preparing a plurality of semiconductor chips according to claim 6, 7 and 8 and performing parallel operations. A SIMD type parallel arithmetic method, wherein a plurality of memory chips according to claim 9 and one arithmetic chip according to claim 10 are combined and operated in parallel. 10. A SIMD type parallel operation method, wherein one memory chip according to claim 9 and a plurality of operation chips according to claim 10 are combined and operated in parallel.   A SIMD type parallel operation method comprising combining data of a plurality of addresses and performing parallel operation as one data. 11. (1) SIMD type parallel arithmetic device (2) SIMD type parallel arithmetic semiconductor chip (3) Memory chip of SIMD type parallel arithmetic semiconductor (4) SIMD type parallel arithmetic semiconductor arithmetic chip according to claim 1.
A system including any of (1) to (4) above.