JP4612352B2 - Labeling processing apparatus and labeling processing method - Google Patents

Description

The present invention, labeling processing method for performing labeling processing for binary image data, and a labeling processor.

  As a general image process performed on image data binarized to white or black, there is a labeling process. In the following, if white pixels are referred to as background pixels and black pixels are referred to as feature pixels, the labeling process is a process of assigning the same label (for example, ascending numbers) to the connected feature pixels. . By performing this labeling process, it is possible to distinguish a plurality of objects existing in the image data and obtain the area and the center of gravity for each object.

The method of determining the connection is roughly
(1) The concept of 4 connections (4 neighborhoods) for determining the connection between the target pixel and the 4 pixels on the top, bottom, left and right;
(2) There is a concept of 8 connections (near 8) that determines connection with surrounding 8 pixels obtained by adding an oblique direction to the 4 connections of (1).

  When performing binary labeling processing on binary image data arranged two-dimensionally in a storage device such as a memory, for example, a pixel adjacent to the left as viewed from the target pixel, and an upper adjacent pixel data. It is necessary to perform sequential processing of scanning binary image data from the upper left end toward the lower right end while referring to the processing result of at least two pixels. Further, when performing the labeling process with eight connections, for example, at least of the pixel adjacent to the left as viewed from the target pixel, the pixel adjacent to the upper left, the pixel adjacent to the upper, the pixel adjacent to the upper right, Sequential processing that refers to the processing results for four pixels must be performed.

  In addition, when different temporary labels are connected at the target pixel, it is necessary to access the memory to store the connection information. In particular, in the case of the 8-connected labeling process, details will be described later. As will be described, there is a possibility that three or more different temporary labels exist in the adjacent four pixels to be referred to, and in order to store connection information between these three different temporary labels, processing of one target pixel is performed. In some cases, the memory must be write-accessed at least twice. The labeling process is listed as one of the image processes that takes a long processing time due to the access to the memory and the sequential processing.

  In order to increase the processing speed of the labeling process, it is conceivable to use a plurality of target pixels as a plurality of target pixels and process them simultaneously. However, as described above, if the number of colliding temporary labels increases, the number of accesses to the memory increases, so that a sufficient effect cannot be obtained.

  In Patent Document 1, a total of four pixels including a target pixel to which a temporary label is allocated and three neighboring pixels adjacent to the target pixel are read by a raster scan method, and a temporary label to be allocated to the target pixel is determined based on a pixel pattern of these four pixels. Although a labeling processing apparatus and a method for performing processing for storing connection information between temporary labels have been disclosed, a method of setting a target pixel to be a plurality of two or more pixels without reducing the processing speed in one processing. Is not disclosed.

  By the way, in a single instruction stream, multiple data stream (SIMD) type microprocessor, the same arithmetic processing (SIMD processing) can be executed simultaneously with a single instruction for a plurality of data. This structure is frequently used in applications related to processing that has the same computation but a very large amount of data (for example, image processing capable of computation in parallel). In normal image processing in a SIMD type microprocessor, a plurality of arithmetic units (Processor Element [PE]; processor elements) are arranged in the main scanning direction, and high-speed arithmetic is performed by simultaneously executing the same arithmetic on a plurality of data. Processing is possible.

When performing sequential processing such as labeling processing, the configuration of the SIMD type processor cannot be fully utilized with respect to processing speed. Even in this SIMD type microprocessor, how to perform the above-described labeling process is an issue.
JP-A-5-233807

  The present invention uses the SIMD type microprocessor to which simple hardware is added, performs the above 8-connected labeling process at a processing speed equivalent to the 4-connected labeling process, and sets a plurality of target pixels to two or more pixels. It is an object of the present invention to create an image processing method and an image processing apparatus that can obtain a sufficient effect without reducing the processing speed in one process.

The present invention has been made to achieve the above object. The labeling processing method according to claim 1 of the present invention includes:
A labeling processing method for assigning the same label to feature pixels connected by using a SIMD type microprocessor having M processor elements and a global processor for processing a plurality of data,
The labeling method is
A provisional labeling step in which binary image data that is two-dimensionally arranged and binarized into background pixels and feature pixels is primarily labeled ;
Based on the result of the provisional labeling step, the information on the connection between the provisional labels is organized and the provisional labeling step of converting the provisional label into the real label ,
During the temporary labeling process,
The target pixel data is represented by P [M, N] (M = 0, 1, 2,... / N = 0, 1, 2,...)
Furthermore, the data of the pixel one pixel to the left of the target pixel is P [M-1, N], the data of the pixel two pixels to the left of the target pixel is P [M-2, N], and the right of the target pixel is one pixel. The data of the adjacent pixel is P [M + 1, N], the data of the pixel two pixels to the right of the target pixel is P [M + 2, N], and the data of the pixel immediately below the target pixel is P [M, N + 1]. And to represent
P [M−1, N−1], P [M−1, N], and P [M−1, N + 1], which are data of the M−1 column in the N−1th line, the Nth line, and the N + 1th line. Is stored in a register included in the (M−1) -th processor element,
P [M, N−1], P [M, N], and P [M, N + 1], which are M columns of data in the (N−1) th line, the Nth line, and the (N + 1) th line, are Mth processor elements. Stored in a register
P + 1 [M + 1, N−1], P [M + 1, N], and P [M + 1, N + 1], which are M + 1 columns of data in the (N−1) th line, the Nth line, and the (N + 1) th line, are the M + 1th processor element Is stored in a register
(1) In data stored in a register included in a processor element, a global processor determines that P [M, N] is a background pixel, P [M, N + 1] is a feature pixel, and P [M-1, N] is If it is determined that the feature pixel and P [M + 1, N] are feature pixels, the second condition register included in the Mth processor element is set to 1 ,
(2) In the data stored in the register provided in the processor element, the global processor determines that P [M, N] and P [M−1, N] are background pixels, and P [M, N + 1] and P [M− 1, N + 1] is a feature pixel, P [M + 1, N] is a feature pixel, and P [M-2, N] is a feature pixel, the third condition register included in the Mth processor element Set to 1 ,
(3) In the data stored in the register provided in the processor element, the global processor determines that P [M, N] and P [M + 1, N] are background pixels, and P [M, N + 1] and P [M + 1, N + 1] Is a feature pixel, P [M + 2, N] is a feature pixel, and P [M-1, N] is a feature pixel, the fourth condition register included in the Mth processor element is set to 1. And
(4) After determination of (1), (2), and (3) above, if any of the second condition register, the third condition register, and the fourth condition register is set to 1, the target pixel Is a labeling processing method for performing a process of rewriting the data P [M, N] from the background pixel to the feature pixel.

An image processing apparatus according to claim 2 of the present invention is provided.
A SIMD type microprocessor having M processor elements and a global processor for processing a plurality of data;
P [M−2, N], P [M−1, N], and P [M + 1, P] are pixel data on the same line from a processor element that includes a register that stores target pixel data P [M, N]. N], P [M + 2, N] , and P [M-1, N + 1], P [M, N + 1], P [M + 1, N + 1] which are pixel data of the next lower line. 2. The labeling processing method according to claim 1, further comprising means for rewriting a state of its own pixel from a relationship with a pixel stored in the register that can be referred to. It is a labeling processing device.

An image processing apparatus according to claim 3 of the present invention is provided.
First data indicating that the pixel was originally a background pixel is added to the pixel data of the background pixel rewritten to the feature pixel,
The presence of the first data in the pixel data is determined for each background pixel after a predetermined process, and if the first data is added, the data is written back to the background pixel. This is a labeling processing apparatus.

  By using the present invention, the following effects can be obtained.

  When performing 8-connected labeling processing on binary image data, the number of temporary labels with different values that collide at the target pixel point where temporary labeling is performed is reduced, and connection information between temporary labels is stored. By reducing the number of times the memory is accessed, it is possible to perform eight-link temporary labeling processing at high speed.

  Further, when the temporary labeling process is performed on the binary image data, the correct labeling process can be performed on the input binary image data.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 16 is a block diagram showing the configuration of the image processing apparatus according to the present invention. The image processing apparatus includes a SIMD type microprocessor 2 and a data control apparatus 11. Further, the SIMD type microprocessor 2 is generally composed of a global processor 4, a register file 6, an operation array 8, and an external interface 7.

(1) Global processor 4
The global processor 4 itself is a so-called SISD (Single Instruction Stream, Single Data Stream) type processor. A program RAM 10 and a data RAM 12 are built in (see FIG. 17), and the program is decoded to generate various control signals. This control signal is supplied to the register file 6, the arithmetic array 8, and the data control device 11 in addition to the control of various built-in blocks. When a GP (global processor) instruction is executed, various arithmetic processes and program control processes are performed using a built-in general-purpose register, an ALU (arithmetic logic unit), and the like.

(2) Register file 6
It holds data processed by PE (processor element) instructions. As is well known, the PE (processor element) 3 is a structural unit that executes individual operations in a single instruction-stream (SIMD) type microprocessor. As shown in the register file 6 and the operation array 8 in FIG. 16, the SIMD type microprocessor 2 in FIG. 16 includes 256 PE3. The PE instruction is a SIMD type instruction and performs the same process simultaneously on a plurality of data held in the register file 6. Control of reading / writing of data from the register file 6 is performed by control from the global processor 4. The read data is sent to the arithmetic array 8 and is written in the register file 6 after the arithmetic processing in the arithmetic array 8.

  Further, the register file 6 can be accessed from the data control device 11 outside the processor via the external interface 7, and read / write to a specific register is performed from the outside separately from the control of the global processor 4. Is called.

(3) Arithmetic array 8
Processing of PE instruction is performed. All processing control is performed from the global processor 4. As will be described later, a pixel connection determination process in the sub-scanning direction in the temporary labeling process is performed.

(4) Data control device (labeling processing device) 11
The clock, address, and read / write control are output to the port of the external interface 7, and data can be read from the register of any PE3 and processed. All processing control is performed from the global processor 4. As will be described later, a pixel connection determination process in the main scanning direction in the temporary labeling process is performed.

  FIG. 17 is a block diagram showing a more detailed configuration of the SIMD type microprocessor 2 according to the present invention.

  The global processor 4 includes a program RAM 10 for storing the program of the processor 2 and a data RAM 12 for storing operation data. Furthermore, a program counter (PC) 14 that holds a program address, G0, G1, G2, and G3 registers (16, 18, 20, and 22), which are general-purpose registers for storing data for arithmetic processing, A stack pointer (SP) 24 that holds the address of the save destination data RAM, a link register (LS) 26 that holds the address of the call source at the time of a subroutine call, and an NMI (Non-Non−) when IRQ (Interrupt Request) A LI register 28 and an LN register 30 that hold a branch source address at the time of maskable interrupt request (inhibit disable interrupt request), and a processor status register (P) 32 that holds the state of the processor are incorporated.

  The GP instruction is executed using these registers, an instruction decoder (not shown), an ALU, a memory control circuit, an interrupt control circuit, an external I / O control circuit, and a GP operation control circuit.

  When executing the PE instruction, the instruction decoder (not shown), the register file control circuit (not shown), and the PE operation control circuit (not shown) are used to control the register file 6 and the operation array 8. I do.

  The register file 6 incorporates 32 8-bit registers in one PE unit, and (32) sets of 256 PEs have an array configuration. The register 34 is called R0, R1, R2,... R31 for each PE. Each register 34 has one read port and one write port for the arithmetic array, and is accessed from the arithmetic array by an 8-bit read / write bus. Of the 32 registers, 24 (R0 to R23) are accessible from the outside of the processor via the external interface 7, and the clock (CLK), address (Address), and read / write control (RWB) are input from the outside. By doing so, it is possible to read / write from / to any register 34.

  In accessing from the outside of the register 34, one register 34 of each PE can be accessed by one external port. The PE number (0 to 255) is specified by an address input from the outside. Therefore, a total of 24 external ports for register access are installed. Access from the outside is performed with 16-bit data, and two registers (one set of even-numbered PE registers and odd-numbered PE registers) are simultaneously accessed by one access.

  The arithmetic array 8 includes a 16-bit ALU 36, a 16-bit A register 38, and an F register 40. The operation by the PE instruction is performed by using the data read from the register file 6 or the data supplied from the global processor 4 as an input on one side of the ALU 36 and the content of the A register 38 as an input on the other side. The calculation result is stored in the A register 38. Therefore, an operation is normally performed on the data supplied from the R0 to R31 register 34 or the global processor 4 and the data stored in the A register 38.

  A 7 to 1 (7 to 1) multiplexer 42 is placed in the connection between the register file 6 and the arithmetic array 8. As shown in FIG. 17, when viewed from a certain multiplexer 42, the data in the R0-R31 register 34 included in the three PE3 in the left direction, the data in the R0-R31 register 34 included in the three PE3 in the right direction, It is set so that the data in the R0 to R31 register 34 included in the PE 3 to which it belongs can be selected as an operation target. The 8-bit data of the register file 6 is shifted to the left by an arbitrary bit by the shift / extension circuit 44 and input to the ALU 36.

  Furthermore, the execution / invalidation control of the operation is controlled for each PE 3 by an 8-bit condition register (not shown), and only a specific PE 3 can be selected as an operation target.

<< About the pre-requisite 4-link labeling process >>
The present invention relates to image processing that performs 8-connected labeling processing as described above, but 4-connected labeling processing is a prerequisite technology. Therefore, first, the outline of the 4-connected labeling process will be described.

  It is assumed that the binary image data is arranged two-dimensionally on the register file 6 of PE3. Usually, the number of pixels in one line of image data is larger than the number of PEs. In this case, a data transfer device and a memory as a frame buffer are arranged in the external interface 7 (not shown), image data is stored in this memory (frame buffer), and is stored in the PE3 register file according to the processing. The image data may be transferred sequentially.

First, 16-bit binary image data and (temporary) labels handled in the first embodiment are defined as follows.
・ Binary image data Background pixel: 0000h
Characteristic pixel ... 8000h
・ (Temporary) label: 0001h to 7FFFh

  The reason for the above definition is that the determination of the background pixel and the characteristic pixel in the binary image data is left to only the most significant 1 bit of 16-bit data, and from 0000h including the (provisional) label. This is because the simplicity of the process of considering that a large number is a feature pixel should be considered.

  Further, in the temporary labeling process, when different temporary labels are connected in the later process, a memory for storing the connection information is necessary. In this case, the temporary label is associated with the address, and the temporary label is associated with the data. The value of another temporary label connected to the label is described, and the connection information between the temporary labels is stored in the memory.

Here, the memory data of the address value addr is expressed as RAM [addr]. Specifically, the connection information is stored in the memory as follows.
When RAM [addr] = 0000h (initial value, initialized before starting the labeling process), the temporary label addr does not exist.
When RAM [addr] = addr, there is no other temporary label connected to the temporary label addr, or its own value is the smallest among a plurality of connected temporary labels.
When RAM [addr] = A (A! = 0000h and A! = Addr), the temporary label addr and the temporary label A are connected.

  Using the above definitions, the contents of the pixel connection determination process (process A1) in the sub-scanning direction and the pixel connection determination process (process B1) in the main scanning direction will be described below. Note that, in the connection determination process of pixels in the main scanning direction in this specification, provisional labeling is performed simultaneously for two pixels.

<Process A1>
The process A1 is performed in parallel on all the pixels in one line (actually, the pixel data group stored in one transfer from the frame buffer to the register file 6 of the PE3).
The image data of the line one line higher than the target line is referred to, a temporary label is assigned to the pixel in the same column (ie, not 0000h (background pixel)), and 2 in the same column of the target line If the value image data is 8000h (characteristic pixel), the temporary label is copied to the target line.

<Process B1>
The process B1 is performed by transferring the target two-pixel data from the register file 6 of the PE 3 to the data control device 11. The value after processing of the target pixel (2 pixels) is the value before processing of the target pixel (2 pixels) and the pixel adjacent to the 2 pixels (the pixel adjacent to the left when scanning the target line from the left, When the target line is scanned from the right, it is determined by a combination of the values of the three pixels with the value of the pixel adjacent to the right). That is, the process B1 is a sequential process that refers to a process result of a pixel adjacent to the target pixel (2 pixels). The pattern of this processing is shown in FIG.

The symbols used in FIG. 3 are described in Table 1 below.

  Here, how to view FIG. 3 will be described. For example, no. In the case of 13 processing patterns, a temporary label of value A is assigned to adjacent pixels, and the state of (two) target pixels before processing is that the first target pixel is a temporary label of value B. If the first target pixel is a background pixel, the first target pixel is assigned a temporary label having a smaller value of A and RAM [B], and the second target pixel is assigned to the second target pixel. A value (0000h) indicating that it is a background pixel is assigned as it is. Further, at this time, as a process for storing the connection information between the temporary label A and the temporary label B, write access to the memory is performed using the larger value of the value A and RAM [B] as the address and the smaller value as the data. It also shows what to do.

  In addition, No. In the 15 processing patterns, a temporary label is assigned to each of the two target pixels. However, in the case of performing the 4-connected labeling process, when the process A1 is completed, a temporary label having a different value is added to the consecutive feature pixels. Since no assignment is made, it is only necessary to assume a case where the same temporary label is assigned to both two target pixels.

  Further, in the process B1, when temporary labels having different values collide with each other, the process of leaving a temporary label with a lower number (process pattern from No. 12 to No. 15 in FIG. 3) contents is included in the target line. It can happen that different temporary labels are assigned to the same existing area. Therefore, the target line is scanned twice from the left and the right so that the same temporary label is allocated to the same area in one target line. With this process, it is possible to reduce the burden of the process of creating connection information between different temporary labels.

  FIG. 2 shows a flowchart of the provisional labeling process by the process A1 and the process B1. In FIG. 2, for the sake of convenience, the number of pixels in one line is assumed to be smaller than the number of PEs. If the number of pixels in one line is greater than the number of PEs, as described above, the image data is transferred from the frame buffer storing the image data to the PE register file according to the process via the data transfer device. What is necessary is just to transfer sequentially.

FIG. 1 is a block diagram of the data control apparatus 11 for performing the process B1. The data control device 11 shown in FIG.
An external interface control unit 52 that controls the external interface 7 by supplying clock, address, and read / write control to the external interface 7;
Memory control for controlling the memory 15 by supplying clock, address, read / write control, and data to the memory 15 for storing connection information between temporary labels connected to the data control device 11 Part 64,
-Pixel data read from the register file 6 of the PE 3 via the external interface 7, data read from the memory 15 (connection information between temporary labels), and assigned to the pixel adjacent to the target pixel in the previous process A label determination circuit 58 that reads the value of the temporary label and determines the value of the temporary label to be assigned to the target pixel;
A label counter 56 for newly generating a temporary label based on the determination result in the label determination circuit 58;
The temporary label generated by the counter 56, the data of the target pixel already assigned with the temporary label, the temporary label assigned to the pixel adjacent to the target pixel in the previous process, and the data read from the memory 15 are input. A multiplexer 60 for outputting the data determined as the temporary label by the label determination circuit 58;
A label register 62 for receiving data from the multiplexer 60 and writing the data back to the external interface 7 as a temporary label.

  In the above configuration, among the data to be read into the label determination circuit 58, the “temporary label assigned to the pixel adjacent to the target pixel in the previous process” is stored in the label register 62 before the process for the target pixel is started. It is equivalent to the value. The external interface control unit 52 incorporates an address counter for generating an address to be supplied to the external interface 7. The address counter uses an up / down counter so that pixel data can be transferred from the left or the right in the main scanning direction.

  The memory control unit 64 generates an address from the built-in up counter at the time of memory initialization before the temporary labeling process is started, and issues the value of the built-in register as input data to the memory 15. When the temporary labeling process is executed, the value of the label counter 56, the data of the target pixel, the value of the label register 62, or the data read from the memory 15 is issued as an address according to the algorithm of the process B1, and the value of the temporary label counter Either the value of the label register 62 or the data read from the memory 15 is issued as input data to the memory 15. In this configuration, it is easy to change the target pixel so that one pixel or a plurality of two or more pixels can be input.

<< First Embodiment >>
Subsequently, an image processing method according to the first embodiment of the present invention will be described.

  If an attempt is made to perform the 8-label provisional labeling process using the above-described “premise 4-connected labeling process”, the following two problems arise.

  In the 8-connected provisional labeling process, the pixel connection process A1 in the sub-scanning direction is expanded, and as shown in FIG. It is also necessary to refer to the pixels. A process obtained by extending the process A1 is referred to as a process A2. Here, when processing binary image data including a figure as shown in FIG. 5, the temporary label of value A and the temporary label of value B collide with each other in the process of process A2. Must be written to. There is a possibility that a plurality of figures as shown in FIG. 5 exist on the same line, and the processing A2 cannot be processed in parallel by the arithmetic array 8 of the PE3.

  In the case of processing binary image data including a figure as shown in FIG. 6, the process A2 can be performed without any problem, but as a result, the process pattern No. of the process B1. 15 (see FIG. 3), three (or more) different temporary labels may collide. If the connection information between these three temporary labels must be written to the memory, the processing speed will be slower than other processing patterns. Specifically, if the smallest temporary label among the three temporary labels is the temporary label C, the connection information between the temporary label C and the temporary label A and between the temporary label C and the temporary label B must be described. Write (write) access twice. In other processing patterns, there is only a collision between two different temporary labels, so that only one write access to the memory is required.

  Therefore, when a V-shaped figure as shown in FIGS. 5 and 6 appears, a method of temporarily filling pixels between the V-shapes as shown in FIGS. 7 and 8 is effective. By performing the process of practicing this method as a pre-process of the pixel concatenation process (process B1) in the main scanning direction, the above two problems, that is, the process A1 is expanded to the process A2 for the 8-link labeling process. It is possible to solve the problems that occur when this is done.

  Further, it is not necessary to expand the process B1 even in the 8-connected labeling process, and the same process as that in the 4-connected labeling process can be used. Therefore, the data control apparatus 11 shown in FIG. 1 that performs the process B1 can be used as it is. A case where the processing for filling the pixels between the V-shapes (hereinafter referred to as processing C1) is realized by software processing (processing C1) in the SIMD type microprocessor according to the first embodiment of the present invention. Described below.

<< Process C1 >>
In the process C1, an 8-bit condition register (T register) is used. The bit 0 of the T register whose PE number is M (Mth column) is expressed as T0 [M], and bit 1 is expressed as T1 [M]. Since one T register is provided for each PE, it can be used to hold the state of each pixel. All T registers are initialized to 0 before processing C1 is started. When the process C1 is performed on the Nth line image data, the N + 1th line image data is referred to as described above. The pixel data of the Mth column of the Nth line is expressed as “PEn [M]”, and the contents of the processing C1 are described below.

(Step 1.) When the pixel data of the Nth line is 0000h (background pixel), 1 is set to T1 corresponding to the pixel.
PEn [M] = 0000h → T1 [M] = 1

(Step 2.) When the pixel data of the (N + 1) th line is 8000h (characteristic pixel) and 1 is set in T1 corresponding to the pixel, 1 is continuously set in T1. Otherwise, 0 is set in T1.
PEn + 1 [M] = 8000h && T1 [M] = 1 → T1 [M] = 1

(Step 3.) When T1 is set to 1 and both the left and right neighboring pixels of the Nth line pixel are 8000h (feature pixel), 1 is set to T2 corresponding to the pixel.
T1 [M] = 1 && PEn [M-1] = 8000h && PEn [M + 1] = 8000h → T2 [M] = 1

(Step 4.) 1 is set in T1, the pixel on the left side of the pixel on the Nth line is 8000h (characteristic pixel), and the pixel on the right side is 0000h (background pixel). When the value of 1 is 1 and the pixel on the right next is 8000h (feature pixel), 1 is set to T3 corresponding to that pixel.
T1 [M] = 1 && PEn [M-1] = 8000h && (PEn [M + 1] = 0000h && T1 [M + 1] = 1) && PE [M + 2] = 8000h → T3 [M] = 1

(Step 5.) 1 is set in T1, the pixel on the right side of the pixel on the Nth line is 8000h (feature pixel), and the pixel on the left side is 0000h (background pixel). When the value of 1 is 1 and the pixel on the other left is 8000h (feature pixel), 1 is set to T4 corresponding to that pixel.
T1 [M] = 1 && PEn [M + 1] = 8000h && (PEn [M-1] = 0000h && T1 [M-1] = 1) && PE [M-2] = 8000h → T4 [M] = 1

(Step 6.) The pixel on the Nth line in which 1 is set in T2, T3, and T4 is rewritten to a feature pixel (for example, 8000h).
T2 [M] = 1 && T3 [M] = 1 && T4 [M] = 1 → PEn [M] = 8000h

  Next, an outline flow of the eight-link temporary labeling process using the process A2, the process B1, and the process C1 is shown.

《8-link temporary labeling process》
In the following, for convenience of explanation, an example in which the number of pixels in one line is smaller than the number of PEs is described. When the number of pixels in one line is larger than the number of PEs, as described above, a data transfer device and a memory as a frame buffer are arranged in the external interface 7, and image data is stored in this memory (frame buffer). The image data may be sequentially transferred to the register file of PE3 according to the processing.

(Step 1.) Process A2 is performed on the image data of the Nth line. Process A2 is a process for connecting pixels in the sub-scanning direction, and refers to image data on the (N-1) th line.

(Step 2.) The process C1 is performed on the image data of the Nth line. Process C1 is a process of filling pixels between V-shapes, and refers to image data on the (N + 1) th line.

(Step 3.) First, the image data of the Nth line is scanned from the left in the main scanning direction, and processing B1 is performed. Process B1 is a process of connecting pixels in the main scanning direction.

(Step 4.) Next, the image data of the Nth line is scanned from the right in the main scanning direction, and processing B1 is performed.

(Step 5.) The processing steps from Step 1 to Step 4 are repeated until the processing for all the lines of the image data is completed.

  Note that the SIMD type microprocessor reads the image data for the 3rd line of the (N−1) th line, the Nth line (target line), and the (N + 1) th line into the register file 6 of the PE3 in order to realize the process C1. Therefore, the image data of the (N-1) th line can be referred to from the image data of the Nth line for the process A2, and the image data of the (N + 1) th line can be referred to from the image data of the Nth line for the process C1. It is necessary to be possible.

<< Second Embodiment >>
Next, an image processing method according to the second embodiment of the present invention will be described.

In the image processing method according to the second embodiment of the present invention, in the process of filling pixels between V-characters described in the image processing method according to the first embodiment (processing C1), the feature pixel is changed from the background pixel. And a pixel that is originally a feature pixel (referred to as a feature pixel A). That is, binary image data and (temporary) label are defined as follows, and set using a condition register (T register).
・ Binary image data Background pixel: 0000h
Feature pixel A 8000h (only bit 15 is 1)
Feature pixel B ... C000h (bit 15 and bit 14 are 1)
・ (Tentative) label: Number from 0001h to 3FFFh (expressed from bit 0 to bit 13)

  As described in the image processing method according to the first embodiment, the process B1 is performed as the pixel concatenation process in the main scanning direction after the process of filling pixels between the V-characters (process C1). By leaving the information of 15 and bit 14, the feature pixel B can be written back to the background pixel again after the provisional labeling process is completed.

  In the normal labeling process, after the temporary labeling process is completed, the connection information between the temporary labels is organized and a conversion table is created so that the temporary label is converted to the correct label. The temporary label is referenced while referring to the created conversion table. This labeling process is performed to convert to a label. If the process of writing back the characteristic pixel B to the background pixel is performed during the main labeling process, there is no increase in processing steps in the second embodiment.

  The process of organizing connection information between temporary labels and creating a conversion table for the main labeling process will be described as process D1, and the main labeling process will be described as process E1. This process E1 includes a process of rewriting the feature pixel B into the background pixel.

<< Process D1 >>
In the process D1, one of the following processes D1-1 to D1-2 is performed on the data in the memory (conversion table), and “addr” is set in ascending order from 1 until “RAM [addr] = 0000h”. Increment and execute. Here, “0000h” is the initial value of the data in the conversion table, and “RAM [addr] = 0000h” indicates that there is no temporary label corresponding to the addr (FIGS. 10 to 13). reference). In the process D1, one counter is used (referred to as a “label counter”). This label counter is initialized to “0000h” before the process D1 is started.

・ Process D1-1
When RAM [addr] = addr, this label counter is incremented by 1, and the incremented value is written back to RAM [addr].
・ Process D1-2
RAM [addr]! When = addr, the value of RAM [RAM [addr]] is written back to RAM [addr].

<< Process E1 >>
In the process E1, the image data after the provisional labeling process is sequentially scanned, and any one of the following processes E1-1 to E1-3 is performed according to the value of the pixel data. The process E1-2 corresponds to a process of writing the feature pixel B back to the background pixel again.

・ Process E1-1
When the target pixel data is 0000h (background pixel), 0000h is assigned to the target pixel data as it is.
・ Process E1-2
When the most significant 2 bits (bit 15 and bit 14) of the target pixel data are both 1 (that is, the feature pixel B), 0000h is assigned to the target pixel data.
・ Process E1-3
When the target pixel data does not satisfy any of the conditions of processing E1-1 and processing E1-2 (a temporary label converted from the feature pixel A), if this value is Label, RAM [Label] is used as the main label. And assigned to the target pixel data.

  The hardware (data control device) that realizes the processing E1 can be realized with a configuration substantially similar to that of the data control device 11 according to the first embodiment shown in FIG. That is, the label determination circuit 58 included in the data control device 11 may be configured to be additionally modified so that the determination process of the process E1 can be performed in addition to the determination process of the process B1.

  FIG. 9 is a flowchart of the entire labeling process using process A2, process B1, process C1, process D1, and process E1 constituting the image processing method according to the second embodiment of the present invention. The flowchart of FIG. 9 will be schematically described.

  In the labeling process constituting the image processing method according to the second embodiment, first, image data is transferred to the register file 6 of PE3 (for one line) (S32). Next, binarization processing is performed by SIMD processing in the PE unit (S34). Subsequently, processing A2, that is, pixel connection in the sub-scanning direction is performed (S36). Then, the process C1, that is, the process of filling the pixels between the V characters is performed (S38). Further, scanning from the left in the main scanning direction is performed to connect pixels in the main scanning direction (processing B1 and S40), and immediately after scanning from the right in the main scanning direction, pixels are connected in the main scanning direction (processing). B1, S42).

  The processes of S32 to S42 are repeated until the processes for all lines of the image data are completed (S44). When the processing for all the lines of the image data is completed (S44, YES), the conversion table for main labeling processing is created by the data control device 11 (processing D1, S46), and then the main labeling processing is performed by the data control device 11. (Processing E1, S48). This completes the labeling process (S50).

  Stores the state of the image data and the connection information between the temporary labels when the temporary labeling process is performed on the binary image data as shown in FIG. 10A using the process A2, the process B1, and the process C1. FIG. 10 (2) to FIG. 13 (14) show how the memory (conversion table) changes.

  10 to 15, “●” represents a feature pixel A, a blank represents a background pixel, and a numerical value represents a (provisional) label. Further, “★” represents the feature pixel B. If a temporary label of value 3, for example, is assigned to the feature pixel B, “★ 3” is indicated.

  The provisional labeling process is performed according to the flowchart shown in FIG. 9, but is omitted from the drawing when the state of the image data is not changed by the process A2, the process B1, and the process C1.

  FIG. 14 is a conversion table for the main labeling process created from the connection information between temporary labels (FIG. 13 (14)) by the process D1. FIG. 15 shows a state of the image data after the main labeling process is performed on the image data of FIG. 14 by the process E1.

It is a block diagram of a data control device according to the present invention. It is a flowchart of a temporary labeling process. It is a list which shows the pattern of process B1. It is a conceptual diagram of the pixel concatenation process in the sub-scanning direction extended by the eight concatenation temporary labeling process. It is a conceptual diagram which shows the problem which may arise by the temporary labeling process of 8 connection. It is a conceptual diagram which shows the problem which may arise by the temporary labeling process of 8 connection. It is a conceptual diagram which shows the solution of the problem which may arise in the temporary labeling process of 8 connection. It is a conceptual diagram which shows the solution of the problem which may arise in the temporary labeling process of 8 connection. It is a flowchart of the whole labeling process using the process A2, the process B1, the process C1, the process D1, and the process E1 which comprise the image processing method which concerns on the 2nd Embodiment of this invention. State of image data and state of memory (conversion table) for storing connection information between temporary labels when temporary labeling processing is performed on binary image data using processing A2, processing B1, and processing C1 It is a figure which shows the mode of a change. State of image data and state of memory (conversion table) for storing connection information between temporary labels when temporary labeling processing is performed on binary image data using processing A2, processing B1, and processing C1 It is a figure which shows the mode of a change. State of image data and state of memory (conversion table) for storing connection information between temporary labels when temporary labeling processing is performed on binary image data using processing A2, processing B1, and processing C1 It is a figure which shows the mode of a change. State of image data and state of memory (conversion table) for storing connection information between temporary labels when temporary labeling processing is performed on binary image data using processing A2, processing B1, and processing C1 It is a figure which shows the mode of a change. It is the conversion table for this labeling process created from the connection information between temporary labels of FIG. 13 (14) by process D1. This is a state of the image data after the main labeling process is performed on the image data of FIG. 14 by the process E1. It is a block diagram which shows the structure of the image processing apparatus which concerns on this invention. It is a block diagram which shows the further detailed structure of the SIMD type | mold microprocessor which concerns on this invention.

Explanation of symbols

4 ... global processor, 6 ... register file, 7 ... external interface, 11 ... data control device, 15 ... (temporary label connection information storage) memory, 52 ... external interface control 58, label determination circuit, 62, label register, 64, memory control unit.

Claims (3)

A labeling processing method for assigning the same label to feature pixels connected by using a SIMD type microprocessor having M processor elements and a global processor for processing a plurality of data,
The labeling method is
A provisional labeling step in which binary image data that is two-dimensionally arranged and binarized into background pixels and feature pixels is primarily labeled ;
Based on the result of the provisional labeling step, the information on the connection between the provisional labels is organized and the provisional labeling step of converting the provisional label into the real label ,
During the temporary labeling process,
The target pixel data is represented by P [M, N] (M = 0, 1, 2,... / N = 0, 1, 2,...)
Furthermore, the data of the pixel one pixel to the left of the target pixel is P [M-1, N], the data of the pixel two pixels to the left of the target pixel is P [M-2, N], and the right of the target pixel is one pixel. The data of the adjacent pixel is P [M + 1, N], the data of the pixel two pixels to the right of the target pixel is P [M + 2, N], and the data of the pixel immediately below the target pixel is P [M, N + 1]. And to represent
P [M−1, N−1], P [M−1, N], and P [M−1, N + 1], which are data of the M−1 column in the N−1th line, the Nth line, and the N + 1th line. Is stored in a register included in the (M−1) -th processor element,
P [M, N−1], P [M, N], and P [M, N + 1], which are M columns of data in the (N−1) th line, the Nth line, and the (N + 1) th line, are Mth processor elements. Stored in a register
P + 1 [M + 1, N−1], P [M + 1, N], and P [M + 1, N + 1], which are M + 1 columns of data in the (N−1) th line, the Nth line, and the (N + 1) th line, are the M + 1th processor element Is stored in a register
(1) In data stored in a register included in a processor element, a global processor determines that P [M, N] is a background pixel, P [M, N + 1] is a feature pixel, and P [M-1, N] is If it is determined that the feature pixel and P [M + 1, N] are feature pixels, the second condition register included in the Mth processor element is set to 1 ,
(2) In the data stored in the register provided in the processor element, the global processor determines that P [M, N] and P [M−1, N] are background pixels, and P [M, N + 1] and P [M− 1, N + 1] is a feature pixel, P [M + 1, N] is a feature pixel, and P [M-2, N] is a feature pixel, the third condition register included in the Mth processor element Set to 1 ,
(3) In the data stored in the register provided in the processor element, the global processor determines that P [M, N] and P [M + 1, N] are background pixels, and P [M, N + 1] and P [M + 1, N + 1] Is a feature pixel, P [M + 2, N] is a feature pixel, and P [M-1, N] is a feature pixel, the fourth condition register included in the Mth processor element is set to 1. And
(4) After determination of (1), (2), and (3) above, if any of the second condition register, the third condition register, and the fourth condition register is set to 1, the target pixel A labeling processing method for performing processing for rewriting the data P [M, N] from the background pixel to the feature pixel. A SIMD type microprocessor having M processor elements and a global processor for processing a plurality of data;
P [M−2, N], P [M−1, N], and P [M + 1, P] are pixel data on the same line from a processor element that includes a register that stores target pixel data P [M, N]. N], P [M + 2, N] , and P [M-1, N + 1], P [M, N + 1], P [M + 1, N + 1] which are pixel data of the next lower line. 2. The labeling processing method according to claim 1, further comprising means for rewriting a state of its own pixel from a relationship with a pixel stored in the register that can be referred to. Labeling processing device. First data indicating that the pixel was originally a background pixel is added to the pixel data of the background pixel rewritten to the feature pixel,
The presence of the first data in the pixel data is determined for each background pixel after a predetermined process, and if the first data is added, the data is written back to the background pixel. Labeling processing equipment.

Images