JPH0887597A - Image processor - Google Patents

Abstract

PURPOSE: To provide an image processor which can shorten the information processing time between a labeling circuit which has an input/output buffer and a coordinate memory. CONSTITUTION: This image processor has a label adding circuit 12 which scans an input binary image by using a mask of specific size and adds a specific label when an aimed point of the mask is a black pixel, a 1st memory 20 which stores the added label, a coordinate memory 18 which stores the storage address coordinates of the label, a circuit 16 which calculates the address coordinates of the start point and end point of a group of identical successive labels among plural obtained labels, a coordinate memory 18 which stores the address coordinates of the start point and end point of the obtained identical label group, and a control part which updates the contents of the coordinate memories each time the same label is added, prereads a white pixel as a black pixel and propagates nearby labels when the aimed point is the white pixel and a specific mask output, and performs the coordinate processing of a label connected image on the basis of the propagated label.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for extracting, for example, a character image by labeling an input binary image, editing and integrating the input binary image.

[0002]

2. Description of the Related Art In a conventional labeling method, an input binary image is raster-scanned by using, for example, a 2 × 3 mask (hereinafter referred to as a neighborhood mask), and a pixel of interest of the neighborhood mask and its neighborhood pixels are also scanned. And connect the images. For example, the same label number is added to each continuous black pixel, and at the same time, the coordinates (start point / end point) of the same label pixels are compared and the areas are added, and the coordinate information and the area information of the label connected image are obtained as output information. The label obtained at this stage is called a temporary label.

If the target image for labeling is a black image,
In the label numbering neighborhood masking process, a new label is added when the target point becomes a black pixel, or in the case of continuous black pixels, the label is propagated from the vicinity of the target point to obtain the output information. After raster scanning, edit / integrate temporary labels, and if it is found that images with different temporary label numbers are connected, coordinate comparison processing and area addition are performed for different temporary labels. Information of the image obtained by adding the same book label to the image is obtained. A character image, for example, is extracted using the image information obtained in this way.

As described above, the labeling process is used for image extraction in an image processing device, for example, a character reading device. In a character reading device, when a character image is extracted, the target character image generally has approximately the same size, so an extremely small image and an extremely large image are removed by an external CPU process. Edit the remaining images to extract character images.

[0005]

Conventionally, when a target point of a neighborhood mask is a black pixel for an input binary image, label numbering is performed and at the same time, a black pixel is processed by a comparison process of coordinates stored in an external coordinate memory. The continuity of the
Seeking the end point coordinates. In the labeling circuit composed of ASIC, FPGA, etc., a time delay occurs in the input / output buffer provided in the labeling circuit and connected to the external coordinate memory. Therefore, if the operation of reading information from the external coordinate memory is started after it is found that the target point of the neighboring mask is the black pixel, the coordinate calculation takes time.

A similar situation occurs when the temporary label is edited / integrated into this label. Also, when extracting an image, the generated external coordinate memory is directly connected to the external CPU.
It takes a lot of time to carry out the comparison process. Therefore, an object of the present invention is to provide an image processing device capable of shortening the information processing time between a labeling circuit having an input / output buffer and a coordinate memory.

[0007]

An image processing apparatus according to the present invention adds a predetermined label when raster-scanning an input binary image by using a mask of a predetermined size and when a target point of the mask is a black pixel. Means, a first memory for storing the added label, a coordinate memory for storing the storage address coordinates of this label, and the start and end addresses of the same continuous label group among the obtained plurality of labels. A means for obtaining coordinates, a coordinate memory for storing the obtained address coordinates of the start point and the end point of the same label group, means for updating the contents of the coordinate memory each time the same label is added, and the target point being a white pixel. In addition, at the time of a specific mask output, the white pixel is pre-read as a black pixel to propagate the neighboring label, and the means for performing coordinate processing of the label connected image based on the propagated label. Characterized by comprising the, the.

The image processing apparatus of the present invention comprises means for raster-scanning the input binary image using a mask of a predetermined size,
A means for adding a predetermined temporary label when the target point of the mask is a black pixel, and a first means for storing the added temporary label.
Of the temporary label, a coordinate memory for storing the storage address coordinates of the temporary label, a means for obtaining the address coordinates of the start point and the end point of the same continuous label group among the plurality of obtained temporary labels, and the obtained same temporary label. A coordinate memory for storing the address coordinates of the start point and the end point of the group, a means for updating the contents of the coordinate memory each time the same temporary label is added, and a means for updating when the target point is a white pixel and a specific mask output. A means for pre-reading a white pixel as a black pixel to propagate a neighboring label, a means for performing coordinate processing on a temporary label connected image based on the transmitted temporary label, and a coordinate for the obtained temporary label connected image Means for performing editing / integration processing to this label by using the label.

The image processing apparatus according to the present invention raster-scans an input binary image using a mask of a predetermined size, adds a predetermined label when the target point of the mask is a black pixel, and the target point is a white pixel. And at the time of a specific mask output, the labeling circuit that performs the labeling by pre-reading this white pixel as a black pixel and propagating the neighborhood label,
An external coordinate memory for storing the coordinates of the label generated from the labeling circuit, and a buffer circuit connected between the labeling circuit and the external coordinate memory are provided.

[0010]

According to the image processing apparatus of the present invention, an input binary image is raster-scanned using a mask of a predetermined size, a predetermined label is added when the target point of the mask is a black pixel, and the target point is a white pixel. And at the time of a specific mask output, the white pixels are read ahead as black pixels to propagate the neighborhood label, thereby shortening the information processing time between the labeling circuit having the input / output buffer and the coordinate memory. It was done like this.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The processing in the embodiment of FIG. 1 is divided into a temporary label addition processing by raster scanning and a temporary label editing / integration processing. The control signal generator 1 is used as input information during raster scanning.
The binary image data is synchronized with the clock signal for 1, the line end signal in the main scanning direction, the frame end signal for the entire surface of the image, and the clock signal for the label adding unit 12 of the temporary label.

The control signal generator 11 shown in FIG. 1 generates a mask signal for raster scanning, and the labeling unit 12 assigns a label number to the input binary image. Labeling part 12
Fig. 2 shows the configuration of Fig. 2, and Fig. 3 shows the propagation operation of the neighborhood mask and label.
FIG. 4A, FIG. 4B, FIG. 4C, FIG.
Shown in

The control unit 12a included in the labeling unit 12 of FIG. 2 inputs only the binary pixel of interest in the 2 × 3 neighborhood mask M to the attention point P of the neighborhood mask M by the mask signal at the time of raster scanning. . Here, the attention point P of the neighborhood mask M is a binary pixel, and A, B, and C are label numbers numbered one line before and stored in the line buffer. D is a label numbered one pixel before. For the binary pixel P, a new label is attached or a label is propagated, that is, the same label is added, based on the connection relationship with the labels A, B, C, and D. When a new image that is considered to have no connectivity with the image scanned so far is generated, the contents of the new label number generation counter 12b of FIG. 2 are added to P, and the new label number generation counter 12b is set to the next value. Increment for new label. The generated label number of P is stored in the line buffer 12d through the selector 12c for the next line processing and is output to the label bus 13 of FIG.

FIG. 13 is a flow chart of labeling by raster scanning with the neighborhood mask M and its editing / integrating processing. First, the temporary labeling processing of the input binary image in the flowchart of FIG. 13 will be described with reference to FIG.

FIG. 4A shows an input binary image. Here, "1" indicates a black pixel, and the blank portion indicates a white pixel area. Such an input binary image is raster-scanned with a 2 × 3 neighborhood mask M.

At the first step S1, it is checked whether or not the raster scanning by the neighborhood mask M is completed. Since the raster scanning has just been started here, the routine proceeds to the next step S2. In this step S2, it is checked whether or not the target point P has a black pixel.

At the position of the neighboring mask M indicated by J in FIG. 4A, the target point P becomes "1", and the combination of (17) in FIG. 3 is obtained. This is the black pixel first obtained in this input image, which is detected in step S3, and the process proceeds to step S4, and the new label number 1 is added.

As the raster scanning is performed by the neighborhood mask M, an address signal is generated from the control signal generator 11 of FIG. 1 and is supplied to the address generator 16. The address generation unit 16 outputs X, Y coordinate data, which is the label addition unit 12 and the catalog creation unit 1.
7 given. The catalog creating unit 17 creates start point and end point coordinates XL, XR, YT, YB of the connected image described later,
It is given to the external coordinate memory 18. Here, the catalog creating unit 17 is connected to the circuit units 11, 12, 16, 17, and 19 which form the labeling circuit via the label bus 13, the data bus 14, and the command bus 15 of FIG. -Integrated program circuit 21 and CP
It is connected to the U interface circuit 22. CPU
The interface circuit 22 is further connected to a CPU (not shown).

At the same time that the new label number 1 is added, the coordinate data is stored in the external memory in the next step S5. That is, when the new label number 1 is added, the label 1 is written in the concatenation table adrs1 of FIG. 4D and the start point / end point information is written in the coordinate memory adrs1 in correspondence with this.

In the circuit of FIG. 1, the concatenation table address adrs1 is the address of the concatenation table memory 20 connected via the concatenation processing unit 19 connected to the bus 13 and the bus 15, and is the address adrs of the coordinate memory.
1 is buses 13, 14, 15 via the catalog creating unit 17.
This is the address of the external coordinate memory 18 connected to.

When the uppermost pixel 1 in the second column from the right of the input binary image of FIG. 4A comes to the point of interest P in the subsequent scanning, the new combination of (17) in FIG. 3 is obtained. The second new label number 2 will be added. Similarly, each time a new combination (17) in FIG. 3 is obtained,
New label numbers 3, 4, 5 and 6 are added.

The obtained label number is written in the concatenation table memory 20 and the coordinate memory 18 shown in FIG. With respect to the black pixels P of other combinations, a label number is added to the point of interest P from the connection relationship of the black pixels shown in FIG. 3, and the coordinate memory 18 is updated from the size comparison operation with the coordinate memory 18.

When it is detected in step S3 that the pixel is not a new black pixel, the process proceeds to the next step S6 and the label is propagated. For example, at a position lower by one pixel immediately below the position of the neighboring mask M indicated by J in FIG. 4A, at a stage before it is known that the attention point P is “1”, It becomes the combination of (3). In this case, if the target point P is "1", the input 2 in FIG.
The first black pixel and the second black pixel from the right end of the value image are continuous, the new label number is not added, and the second pixel is indicated by the arrow (3) in FIG. As indicated by, the label number 1 is propagated and added. Similarly, FIG.
The label number 1 is propagated and added to the rightmost image of the input binary image except for the lowest pixel.

It is checked in the next step S7 whether or not two different labels are connected when the label is propagated in step S6. For example, when raster scanning of the input binary image of FIG.
Is detected. In this case, since the propagation of the label to the point of interest P cannot be uniquely determined, the label at the point D is tentatively propagated, and in step S8, the concatenated pair table 1 and the concatenated pair of FIG. The label 6 of D and the label 5 of C are stored in the table 2, respectively. The concatenated pair table 1 and the concatenated pair table 2 are stored in the concatenated pair 1 memory 23 and the concatenated pair 2 memory 24, respectively, which are connected via the concatenation processing unit 19 of FIG.

In the case of the combination of the pixels L of FIG. 4A, the coordinate comparison processing of the left end of the mask M is necessary. When a combination of L is generated, a signal L indicating this is supplied to the circuit of FIG. 7 to activate this circuit. When the output of the flip-flop F / F1 is output at the rise of the second clock from the generation of the L signal, the output of the delay circuit 30 and the OR circuit 3
1 and the information of the coordinate XL at the left end of the connected image in the coordinate memory 18 is read by the output signal of the OR circuit 31. Then, the coordinates are compared and the XL coordinate of the attention point P of the combination pixel of L is stored in the external coordinate memory. If it is smaller than the XL coordinate value of the corresponding position of 18, the flip-flop F / F2 at the next clock
Output from the NAND circuit 32 to output the coordinate memory 1
Rewrite 8.

If it is determined in step S2 that the pixel is not a black pixel, the process proceeds to step S9. For example, in the case of the combination of the pixels M of FIG. 4A, the coordinate comparison processing of the right end of the mask M is performed. Although the point of interest P is a white pixel, in this case, it is treated as a special white pixel in step S9, and the label of the black pixel is propagated to this special white pixel in the next step S10. After that, the process proceeds to step S11, the XR information of the coordinate memory 18 is read together with the label number of the next black pixel, and the size comparison process is performed in step S12. As a result, if the input coordinate is large, the figure is displayed in step S13. In the case of the combination (3) of 3, the coordinate memory 18 is rewritten. In this case, the address of the coordinate memory 18 is D
Use the label number of.

Even if P is a white pixel, the combination of the neighboring masks M for propagating the label to P is (3) in FIG.
This is the case of (4), (11), and (12). These are for the right edge coordinate comparison in the black pixel that will occur next.

As described above, with the raster processing by the neighborhood mask M, the temporary labels 1, 2, 3, 4, 5, 6 of FIG. 4B are obtained, and the temporary labels are synchronized with the label numbering. 1 and the processing of the start point / end point coordinates of the connected image are performed by the label adding circuit 12 of FIG. In the concatenation processing unit of FIG. 1, concatenation information is stored in the concatenation table memory 20 from the label information of the leveling unit 12, and concatenation pair information of concatenation pair 1 memory 23 and concatenation pair 2 memory 24 is stored. Further, the address generation unit 16 of the two-dimensional image which receives the address signal of the control signal generation unit 11 of FIG. 1 generates X and Y addresses. When a black pixel or a special white pixel is generated in the labeling unit 12, the coordinates of the same label stored in advance are read from the external coordinate memory 18, the catalog creating unit 17 performs a comparison operation, and the coordinate memory 18 is calculated according to the size relation. Is rewritten. Here, XL means the left end coordinate of the connected image, XR means the right end coordinate, YT means the upper end coordinate, and YB means the lower end coordinate.

The concatenation pair information of FIG. 4 (b) is shown in FIG. 4 (c). A connection table and coordinate information are shown in FIG.
XL1 means the left start point of label 1, XR1 means the right end point of label 1, YT1 means the upper start point of label 1, and YB1 means the lower end point of label 1. The coordinate information of the label 2, the label 3, the label 4, the label 5, and the label 6 follows the respective numbers.
For example, XL2 is the left start point of label 2 and XR2 is the label 2
Will be the right end point of.

Here, the processing configuration of the external coordinate memory 18 is shown in FIG. At the time of raster scanning, the label number data is given to the address terminal of the memory 18 as address data via the buffer 41, and the two-dimensional image address generator 16 of FIG.
The X and Y address data from the are processed according to the combination of pixels in the neighborhood mask M of FIG. When the combination (17) shown in FIG. 3 occurs, a new label signal NN is generated from the labeling unit 12, the signal NN and the clock are sent to the NAND circuit 42, and the result of the NAND operation with the clock and the "0" signal is displayed. obtain. The output of the NAND circuit 42 is given to the NOR circuit 44 together with the clock from the NAND circuit 43, and its output is passed through the buffer 45 to the write terminal WT of the memory 18 and the tri-state buffer (TST).
BF) 46 control terminal. As a result, the coordinate data from the two-dimensional address generation unit 16 is transferred to the selector 47,
It is written to the external coordinate memory 18 through the tri-state buffer (TSTBF) 46 and the bidirectional buffer 48.

On the other hand, in the coordinate comparison process, the label number to be compared is given from the buffer 41 and the external coordinate memory 1
8 information is read via the buffer 48 and latched (L
T1) Latch to 50. The data latched in the latch (LT1) 50 is compared by the comparator (CMP) 52 with the coordinates of the two-dimensional address generation unit 16 selected by the raster scan mask M by the selector 51, and the comparison result according to the magnitude relation is obtained. The NAND circuit 43 is supplied with the NAND output to obtain a clock, and the write signal that has passed through the NOR circuit 44 is supplied to the write terminal WT to rewrite the external coordinate memory 18.

The above process, that is, the frame end signal of FIG. 6 is sent to the control signal generator 11 of FIG. 1, and the program of the editing / integrating program circuit 21 is started at the same time when the raster scanning process is completed.

The editing / integrating process of the temporary label will be described below with reference to the flowchart of FIG. First, in step S21, it is checked whether the number of temporary labels is zero.
If it is not zero, the flow advances to step S22 to check whether the concatenated pair data exists in the memory.

If there is a concatenated pair, the process proceeds to step S23 to read the external coordinates of the concatenated pair 1 label address, and subsequently, in step S24, read the external coordinates of the concatenated pair 2 label address. The operation of connecting the read large label address to the small label value is performed in the next step S25, and the large and small coordinates of the two are compared in step S26. As a result of this comparison, the external coordinates of the small label address are rewritten in step S27. This operation is continuously performed while decrementing the number of temporary labels by one in step S28, and is continued until the number of temporary labels becomes zero.

Thus, the editing / integrating program is shown in FIG.
This is for performing processing on the concatenation table of FIG. 4D using the concatenation information of the temporary labels of the concatenation pair 1 and 2 of (c). As a result, as shown in FIG. 5B, the connection information rooted at label 1 and the information at label 4 are obtained. By finally editing and integrating these, the coordinate information of this label in FIG. 5C is obtained. The coordinate information of FIG. 5C is obtained as the rectangular image information shown in FIG. For example, the left edge coordinate XL = XL16 and the right edge coordinate XR = XR1 of the rectangular image of label 1
6, upper end coordinate YT = YT16, lower end coordinate YB = YB16
Becomes

At the time of editing / integrating processing, the coordinates of the label number of the root (for example, label 1 in the example of FIG. 5) are read from the memory 18 and stored in the latch (LT1) 50 from the buffer 48. Latch coordinates of other label numbers (LT2) 53
The coordinates of the root label address (for example, 1) are rewritten to the contents of the latch (LT2) according to the magnitude relation as a result of the comparison operation in the comparison circuit 52. That is, the latch 5
3 contents from the selector 47 via the tristate buffer (TSTBF) 46 and the buffer 48 to the memory 18
Send to

The buffers 41, 45, 48 are ASIC, F
It is a buffer unique to PGA and has a long delay time. Therefore, during raster scanning, the external coordinate memory 18 is read using two pixel clocks, as shown in FIG. The same idea must be introduced in the editing / integrating process, but this process is switched according to the clock speed. The flow chart is shown in FIG. If the clock speed is high and the coordinate memory 18 cannot be read in one step due to the delay time due to the buffers 41, 45, and 48 in FIG. 8, the external CPU sets the mode 1 in advance as shown in FIG. 9A. Latch (LT1) 5 from coordinate memory 18
0, reading into the latch (LT2) 53 in two steps (ST1A, ST1B), (ST2A, ST2)
By carrying out in B), stable processing can be performed.

On the other hand, when the clock speed is not affected by the delay time, mode 2 is set as shown in FIG.
Reading into the latch (LT1) 50 and the latch (LT2) 53 is processed in one step (ST1, ST2), respectively.

During the editing / integrating process, that is, when the temporary label becomes zero, the process proceeds from step S21 to step S29 to sort (classify) the external memory, and then to step S30. Here, when the coordinate calculation of this label is performed, the rectangular coordinate of this label is compared with the preset rectangular parameter coordinate, and a flag is set according to the comparison result. FIG. 10 shows a configuration example of the circuit.

XL, XR, YT, and YR are the coordinate values of the left, right, top, and bottom of the rectangle stored in the external coordinate memory 18, respectively. Horizontal rectangle length is XR minus XL subtractor SUB
XL is obtained by subtracting by 1. Vertical rectangle length is Y
YL is obtained by subtracting B or YT with the subtractor SUB2. Xmin, Xmax, Ymin, Ymax are the contents of the parameters of the registers 61, 62, 63, 64 which store the parameters given in advance from the external CPU. Xmin × Ymin constitutes the minimum rectangular frame parameter, and Xmax × Ymax constitutes the maximum rectangular frame parameter. The value XL and the parameter Xmin are compared by a comparator (CMP
1) 65 is compared, and XL and Xmax are compared by a comparator (CMP
2) 66 is compared, and YL and Ymin are compared (CMP
3) 67 is compared, and YL and Ymax are compared by a comparator (CMP
4) Compare at 68. Comparators CMP1, CMP2, CM
The comparison result of P3 and CMP4 is input to the next combination circuit 69, and a predetermined flag is output from the state of each comparison result.

FIGS. 11 (a)-(i) illustrate the rectangle length and parameters of the target image. The shaded figure means the rectangular frame of the target image. A small thick frame means a minimum rectangular frame parameter, and a large thick frame means a maximum rectangular frame parameter. (A), (b), (c), (d), (e),
By comparing the rectangular frame of the image as shown in (f), (g), (h), and (i) with the parameters, the flags shown in FIG. 12 are generated according to the respective size and direction states. , Are stored along with the external coordinate memory 18. After the completion of all labeling processing, the external CPU detects only this flag,
For example, (a) is excluded as a small noise, (i) is excluded as a large noise, (f) is determined to be valid as a character image, (b) and (c) are short bars, (d) and (e). )
It can be determined that is a thin ruled line, and (g) and (h) are thick ruled lines.

As described above, according to this embodiment,
By raster-scanning the input binary image using a neighborhood mask of a predetermined size such as 2 × 3, the detected binary black pixels are labeled, and the start point and end point coordinates within the same label are externally labeled. Absorption of delay time between the chip and the external coordinate memory by propagating the label of black pixel only in a specific neighborhood mask even if the target point is a white pixel in the image calculation chip for labeling obtained between coordinate memories. You can

Further, in the internal program for editing / linking from the temporary label to this label, the number of reading steps of the external coordinate memory is switched according to the clock frequency of the chip, so that it is stable regardless of the clock speed. It can be processed.

Further, the size and direction of the rectangular frame obtained from the external coordinate memory of the detected main label image are compared with predetermined parameters, and stored as flag information along with the coordinate information to obtain a complicated figure. Can be processed simply and efficiently by the CPU.

[0045]

As described above, according to the present invention, in the raster scanning real-time processing of the labeling and the editing / integration processing, the input / output buffer of the chip and the chip and the external memory generated by the ACIC of the image processing circuit and the FPGA are realized. High-speed performance can be secured by pre-reading the image data for the delay time between them. Further, by flagging the detected rectangular frame of the connected image according to its size and direction, complicated graphics can be processed easily and efficiently by the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall schematic configuration of labeling hardware according to the present invention.

FIG. 2 is a block diagram showing a hardware configuration for labeling.

FIG. 3 is a diagram showing a relationship between a combination of neighboring masks and labeling.

FIG. 4 is a diagram showing an illustration of labeling and contents of temporary label information.

FIG. 5 is a diagram showing editing of this label and result information.

FIG. 6 is a timing chart showing an input signal of labeling hardware.

FIG. 7 is a block diagram showing a generation circuit of a start point comparison processing signal in the main scanning direction.

FIG. 8 is a block diagram showing hardware for coordinate comparison.

FIG. 9 is a flowchart showing an editing / integration program by switching.

FIG. 10 is a block diagram showing hardware for flag generation.

FIG. 11 is a view showing a form of a flag.

12 is a table showing the relationship between flags and the forms of FIG.

FIG. 13 is a flowchart of the entire labeling process.

[Explanation of symbols]

11 ... Control signal generating unit, 12 ... Labeling unit, 12a ...
Control unit, 12b ... New label number generation counter, 12c ...
Selector, 12d ... line buffer, 13, 14, 15
... bus, 16 ... address generating section, 17 ... catalog creating section, 18 ... external coordinate memory, 19 ... connection processing section, 20 ...
Concatenation table memory, 21 ... Editing / integrating program unit, 222 ... CPU interface, 23 ... Concatenation pair 1 memory, 24 ... Concatenation pair 2 memory, M ... Neighborhood mask, 3
0 ... Delay circuit, 31 ... OR circuit, 32 ... NAND circuit, F
/ F1, F / F2 ... Flip-flops, 41, 45,
48 ... Buffer, 42, 43, 44 ... Logic circuit, 46 ...
Tri-state buffer, 47, 51 ... Selector, 5
0, 53 ... Latch circuit, 52 ... Comparison circuit, 61-64 ...
Registers, 65 to 68 ... Comparator, 69 ... Combination circuit.

Claims (3)

[Claims] 1. A means for raster-scanning an input binary image using a mask of a predetermined size, a means for adding a predetermined label when a target point of the mask is a black pixel, and the added label is stored. A first memory, a coordinate memory for storing the storage address coordinates of this label, a means for obtaining the address coordinates of the start point and the end point of the same continuous label group among the obtained plurality of labels, and the obtained same label group A coordinate memory for storing the address coordinates of the start point and the end point of, a means for updating the contents of the coordinate memory each time the same label is added, and the white pixel when the target point is a white pixel and a specific mask output An image characterized in that it pre-reads the black pixel as a black pixel and propagates the neighborhood label, and means for performing coordinate processing of the label connected image based on the propagated label. Management apparatus. 2. A means for raster-scanning an input binary image using a mask of a predetermined size, a means for adding a predetermined temporary label when a target point of the mask is a black pixel, and the added temporary label. A first memory that stores the coordinates; a coordinate memory that stores the storage address coordinates of the temporary label; a unit that obtains the address coordinates of the start point and the end point of the same continuous label group among the obtained temporary labels; A coordinate memory that stores the address coordinates of the start point and the end point of the same temporary label group, a means that updates the contents of the coordinate memory each time the same temporary label is added, and the target point is a white pixel and a specific mask output In this case, the white pixels are read ahead as black pixels to propagate the neighboring label, the coordinate processing of the temporary label concatenated image based on the propagated temporary label, and the obtained temporary label. And a unit for performing an edit / integration process on the label using the coordinates of the linked image. 3. An input binary image is raster-scanned by using a mask of a predetermined size, a predetermined label is added when a target point of the mask is a black pixel, and the target point is a white pixel and a specific mask output. When this white pixel is read as a black pixel in advance, a labeling circuit that performs labeling by propagating a neighborhood label, an external coordinate memory that stores the coordinates of the label generated from the labeling circuit, and the labeling An image processing apparatus, comprising: a buffer circuit connected between the circuit and an external coordinate memory.