JP2519821B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus suitable for efficiently performing image processing used in an image reader, a printer, a facsimile, and the like. .

[Prior Art] FIG. 6 is a block diagram of a conventional image processing apparatus shown in the document "NEC Technical Report" (Vo1.42 No.5 / 1989), and particularly shows an arithmetic circuit section. The details of this structure are different from the gist of the present invention and are described in the literature, so a special explanation will be avoided, but if only the contour emphasis processing part is taken out, the structure as shown in the partial block diagram of FIG. 7 is obtained. Becomes Seventh
In the figure, (11) is a contour enhancement circuit, and (12) is a contour enhancement line memory.

The operation of the above arrangement will be described below.

Although there is a description of the contour enhancement processing in the above document,
According to this, a method is adopted in which the difference between the data of interest and the average value of its adjacent data is obtained by a spatial filter, and the contour portion is emphasized by adding the difference to the data of interest. And that the natural image is sharp. This method is a well-known general image edge enhancement method. First, image data of a predetermined number of lines is stored in the edge enhancement line memory (12), and then this image data is stored for the input image data. This can be realized by performing arithmetic processing in the contour emphasis circuit (11) using image data. For example, when one line of data is stored in the outline emphasizing line memory (12), the data G (x, y) of the pixel (hereinafter referred to as the pixel of interest) to be calculated as shown in the explanatory diagram of FIG. ) Go (x, y) = G (x, y) + [G (x, y) -1/3 {G (x-1, y) + G (x + 1, y) + G (x, y + 1)}] (1) The contour emphasizing circuit (11) performs the arithmetic processing. By the way, FIG. 4 is an explanatory diagram of a pixel array in the case where contour enhancement is performed on arbitrary pixel data by a related process for one line.
And G (x, y) is read data of an arbitrary pixel,
o (x, y) is the output of the contour enhancement circuit (11) for G (x, y), and x is the main scanning direction label and y is the sub scanning direction label. At this time, G (x, y) and G (x-1,
y) and G (x + 1, y) are the contour emphasis line memories (1
The image data stored in (2) and subsequently input image data G (x, y + 1) are used to draw the contour enhancement circuit (1
The calculation processing is performed in 1).

On the other hand, when two lines of data are stored in the contour emphasizing line memory (12), as shown in the explanatory diagram of FIG. 5, the data of the pixels before and after and to the left and right of the data G (x, y) of the pixel of interest are used. Go (x, y) = G (x, y) + [G (x, y) -1/4 {G (x-1, y) + G (x + 1, y) + G (x, y + 1) + G (x, y-1)}] ... (2) The contour enhancement circuit (11) performs the arithmetic processing. By the way, FIG. 5 is an explanatory diagram of a pixel array in the case where contour enhancement is performed on arbitrary pixel data by a related process for two lines.
Then, G (x, y), G (x-1, y), and G (x
+ 1, y), G (x, y-1) is the outline emphasis line memory (12)
Image data that has been stored in advance and is output by
G (x, y + 1) is pixel data that is subsequently input.

FIG. 2 shows the case where the image data of one line is first stored in the contour emphasis line memory (12), and then the next pixel after the arbitrary pixel data G (x, y + 1) is input to the contour emphasis circuit (11). Contour emphasis line memory (1 until data G (x + 1, y + 1) is input to the contour emphasis circuit (11)
It is a time chart which shows operation of 2). In the figure, (a) is an image data clock, (b) is input image data from the outside, (c) is image data read from the image memory, (d) is image data to be written in the image memory, (e). Is image data output as a result of the arithmetic processing. Here, in order to simplify the description, after a certain arbitrary pixel data G (x, y + 1) is input to the contour emphasis circuit (11), the next pixel data G (x + 1, y + 1) is changed to the contour emphasis circuit (11). ) Image transfer cycle GS
I will say.

First, the operation of the contour emphasizing line memory (12) when storing image data for one line will be described. In order to obtain the data necessary for processing, first, the pixel data G (x + 1, y) is output from the contour emphasis line memory (12) from the contour emphasis circuit (11). Next, in order to process the next line, it is stored in G (x, y + 1) input to the contour emphasis circuit (11) and the empty area created by the above operation. Here, the image data G (x, y) and the pixel data G (x, y-1) are delayed by a latch circuit or the like to obtain data necessary for processing.

Next, the operation of the contour emphasizing line memory (12) when storing image data for two lines will be described. Figure 3 is 2
6 is a time chart for explaining the operation of the contour emphasis line memory (12) in the image transfer cycle GS when storing line image data. In the figure,
(A) is an image data clock, (b) is input image data from the outside, (c) is image data read from the image memory, (d) is image data to be written in the image memory,
(E) is image data output as a result of the arithmetic processing. First, the pixel data G (x + 1, y) is output from the contour emphasizing line memory (12) to the contour emphasizing circuit (11) in order to obtain the data of the first line necessary for processing. Next, the contour enhancement circuit (11) for processing the data of the next line
The pixel data G (x, y + 1) input to is stored in the empty area created by the above operation. Then, the pixel data G (x + 1, y) of the second line necessary for the processing is output to the pixel data G (x, y−1) in order to use it for the next line processing. store.

Generally, a RAM capable of inputting and outputting 8-bit data is used as the contour emphasis line memory (12). However, the RAM has an access time, that is, a time from the input of an address to the actual output of data. Currently available RAM in the market has 100ns access time
Therefore, when two lines of data are stored in the contour emphasizing line memory (12) and the arithmetic processing of equation (2) is performed by the contour emphasizing circuit (11), the image transfer cycle is as shown in FIG. Since it is necessary to read / write the RAM twice during the GS, when a RAM with an access time of 100 ns is used for the contour emphasis line memory (12), the image transfer cycle GS is 400 n.
You need more than s.

Therefore, if the image transfer rate is 2MHz, the image transfer cycle GS
Is the reciprocal of the image transfer rate, so 1/2 × 10 ^-6 sec = 500ns (3), and the data of 2 lines is stored in the edge emphasizing line memory (12), and the arithmetic processing of equation (2) is performed. Contour enhancement circuit (11)
Can be done at.

On the other hand, when the image transfer speed is 4 MHz, the image transfer cycle GS becomes 1/4 × 10 ⁻⁶ sec = 250 ns (4), and two lines of data are stored in the contour emphasis line memory (12), (2 ) Expression calculation circuit for contour enhancement (11)
Can't be done in.

On the other hand, in the conventional image processing apparatus, the number of lines to be stored in the contour emphasis line memory (12) and the arithmetic processing method are determined from the beginning, and accordingly, the contour emphasis line memory (1
It is not possible to change the number of lines stored in 2) and the arithmetic processing method by the contour enhancement circuit (11). That is, one line of data is stored in the contour emphasis line memory (12),
When the contour emphasizing circuit (11) performs the arithmetic processing of the expression (1), the arithmetic processing can be performed even if the image transfer speed is somewhat high, but the arithmetic processing of the expression (2) is performed by the contour emphasizing circuit (11). There is a problem that the image quality is inferior to that in the case of. On the other hand, two lines of data are stored in the contour emphasizing line memory (12), and the arithmetic processing of equation (2) is performed by the contour emphasizing circuit (1
When performing with 1), the calculation distance of (1) is set to the contour emphasis circuit (1
Although the image quality is better than in the case of 1), there is a problem that the arithmetic processing cannot be executed when the image transfer speed becomes high to some extent.

[Problems to be Solved by the Invention] Since the conventional image processing apparatus is configured as described above, the image processing result is inferior regardless of the transfer speed of the input image data, that is, the image transfer cycle GS, but high speed processing is performed. Can be selected, or an image processing result that is superior in image processing result but slow in processing speed can be selected, and image processing of high image quality can be adaptively executed according to the transfer speed of image data. The development of the method was a big issue.

The present invention has been made to solve the above-mentioned problems, and in order to realize image data processing of higher image quality in accordance with the transfer rate of image data, by selecting a calculation processing method according to the transfer rate of data. It is intended to obtain the image processing device of.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention is an image memory means for temporarily storing image data input from the outside, and an image transfer cycle for determining the transfer rate of the image data. A determination unit that determines the number of times the image memory unit can be accessed in one calculation unit based on the capability of the image memory unit, and an optimum number of times that the image memory unit can be accessed based on the determination of the determination unit. It is characterized by comprising an arithmetic processing means for selecting an arithmetic processing method.

[Operation] In the above means, the image processing apparatus of the present invention determines the image transfer cycle by determining the transfer speed of the image data input from the outside in the judging means, and the image memory means in the operation unit of the image transfer cycle determines the image transfer cycle. The number of times of access is determined, and based on the result of the determination, the arithmetic processing means selects the optimal arithmetic processing method corresponding to the number of times the memory means can be accessed, and adds the arithmetic processing to the image data to determine the optimum number. Implements an image processing device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention. In the figure, (3) is an image memory for storing image data, (7) is transfer of image data input from the first input terminal (13) and image data input from the second input terminal (14). A processing unit that performs an image processing operation based on the speed information and sends the operation result as output data from an output terminal (15); (1) a first image processing operation in a processing unit (7); (2) is a second operation unit that executes the second image processing operation in the processing unit (7), and (6) is based on the data transfer rate information from the second input terminal (14). A judging section for selecting a calculation processing method, (5) a first calculating section (1) based on a signal from the judging section (6) for image data from the first input terminal (13).
Alternatively, a 1-2 selector introduced into the second arithmetic unit (2),
(4) is a 2-1 selector that connects access data to the image memory (3) to the first calculation unit (1) or the second calculation unit (2) based on the signal from the determination unit (6), (8)
Is an address to the image memory (3) for the first arithmetic unit (1)
2-1 selector for setting whether to give from the second calculation unit (2) or from the second calculation unit (2),
(9) determines whether to derive the output data to the output terminal (15) from the first arithmetic unit (1) or the second arithmetic unit (2) based on a signal from the judging unit (6). 2-1 to select
It is a selector.

The operation of the above arrangement will be described below.

When image data is input to the processing unit (7) through the first input terminal (13), data transfer rate information is also input to the determination unit (6) through the second input terminal (14). The determination unit (6), which has been input with the data transfer rate, obtains the image transfer cycle GS which is the reciprocal of the transfer rate, and whether or not the image memory (3) can be read / written twice or more during this image transfer cycle GS. And based on the result of the determination, a selection signal is given to the 2-1 selectors (4), (8), (9) and 1-2 selector (5).

As a result of the above determination, when it is determined that the image memory (3) can be read / written more than once during the image transfer cycle GS, the pixel data G (x, y + 1) of the input image data
Is input to the first arithmetic unit (1) through the 1-2 selector (5), and the image memory (3) is connected to the first arithmetic unit (1) through the 2-1 selectors (4) and (8). , The calculation result of the first calculation unit (1) is connected to the output terminal (15) through the 2-1 selector (9). As a result, the first arithmetic unit (1) outputs the pixel data G (x + 1, 1) from the image memory (3).
y) and G (x, y−1) are read, and the read pixel data G (x + 1, y) is delayed to G (x, y), G (x−1, y +).
1) is created and AGo (x, y) = G (x, y) + [G (x, y) -1/4 {G (x-1, y) + G (x + 1, y) + G (x, y + 1) + G (x, y-1)}] (3) The same calculation process as in the formula (2) is executed, and the calculation result AG
O (x, y) is obtained and sent from the 2-1 selector (9) to the output terminal (15) as output data.

On the other hand, as a result of the judgment by the judgment unit (6), the image transfer cycle
When it is determined that the image memory (3) cannot be read / written more than once during GS, the pixel data G (x, y + 1) of the input image data is transferred to the second selector (5) through the second selector (5). Arithmetic unit (2), 2-1 selector (4),
The image memory (3) is connected to the second arithmetic unit (2) through (8).
And the calculation result of the second calculation unit (2) is connected to the output terminal (15) through the 2-1 selector (9). As a result, the second calculation unit (2) reads the pixel data G (x + 1, y) from the image memory (3), delays the read pixel data G (x + 1, y), and then G (x, y), G (x-1, y) is created and BGo (x, y) = G (x, y) + [G (x, y) -1/3 {G (x-1, y) + G (x + 1, y) + G (x, y + 1)}] (4) The same calculation process as in formula (1) is executed and the calculation result BG
O (x, y) is obtained and sent from the 2-1 selector (9) to the output terminal (15) as output data.

Through the above processing, the processing unit (7) obtains the data transfer rate information of the image data input from the first input terminal (13) from the second input terminal (14), and then the determination unit (6). The image transfer cycle GS is calculated, the number of times the image data is accessed to the image memory (3) is determined, and the first calculation unit (1) or the second calculation unit (2) is selected to save the image data. Since the optimum arithmetic processing matching the transfer speed is performed, it is possible to obtain a good image processing result.

In the above embodiment, the edge enhancement processing is described as an example, but the embodiment of the present invention is not limited to this, and the image memory is used to store image data for one line or two lines. It can be effectively applied to a case where arithmetic processing is performed using stored data.
Further, in the above-described embodiment, the configuration of selecting from two types as the calculation method has been illustrated, but it goes without saying that the same is applicable even if there are three or more selectable calculation methods. Further, the selection of the calculation method may be the selection of the calculation routine in software instead of the selection of the hardware.

As described above, according to the present invention, the number of times the image memory can be accessed in the image processing operation is determined according to the transfer speed of the input image data, and the operation processing method is determined based on the determination. By changing it, it is possible to obtain an image processing apparatus capable of performing the arithmetic processing with the highest image quality corresponding to each transfer rate of image data.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a time chart for explaining an arithmetic processing system based on image data of 1 line, and FIG. 3 is image data of 2 lines. 4 is a time chart for explaining an arithmetic processing system based on FIG. 4, FIG. 4 is an explanatory view of a pixel array in the case of performing edge enhancement on an arbitrary pixel data by a related process for one line, and FIG. 5 is an arbitrary pixel data. In contrast, FIG. 6 is an explanatory view of a pixel array in the case where contours are emphasized by a related process for two lines, FIG. 6 is a block diagram of an arithmetic circuit unit including a conventional image processing device, and FIG. It is a partial block diagram which extracts and shows an emphasis function part. In the figure, (1) is a first arithmetic unit, (2) is a second arithmetic unit, (3) is an image memory, (4) is a 2-1 selector,
(5) is a 1-2 selector, (6) is a judgment section, (7) is a processing section, (8) and (9) are 2-1 selectors, (11) is an edge enhancement circuit, and (12) is edge enhancement. A line memory, (13) is a first input terminal, (14) is a second input terminal, and (15) is an output terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An image memory means for temporarily storing image data inputted from the outside, and a judging means for judging a transfer speed of the image data to judge an accessible number of times of the image memory means in an image transfer cycle. An image processing apparatus comprising: an arithmetic processing unit that selects an arithmetic processing method suitable for the number of possible accesses to the image memory unit based on the determination of the determination unit.