JP3212664B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device for performing a lost shadow process on an image, and more particularly to an image processing device for performing a lost shadow process using a line memory.

[0002]

2. Description of the Related Art As one of image processing performed by an image processing apparatus, there is a shadow adding process for adding a shadow to an image. FIG.
It is explanatory drawing which shows an example of the conventional shadow addition process, The closed loop of a solid line (henceforth an image loop) shows an image area | region, The closed loop of a dotted line (henceforth a shadow loop) shows a shadow area | region added, respectively. The described numerical values are shadow area data (described later).

When the shadow adding process shown in FIG. 14 is performed, first, the presence or absence of an image is determined based on the value of image data input to the apparatus, and shadow area data is output. The shadow area data is
When it is determined that there is an image (in the case of binary image data, it is 1), a predetermined numerical value (5 in this case) is determined, and when it is determined that there is no image (in the case of binary image data, it is 0) ) Outputs a numerical value of 0. When this numerical value is a value other than 0, it means that a shadow is added, and it means the remaining length of the shadow to be added. When the output shadow area data is delayed by one line in the sub-scanning direction and by one pixel in the main scanning direction, the area of the shadow area data to which a value of 5 is assigned becomes as shown in FIG. 14 and is outside the image loop. The portion becomes a shadow region (shadow loop).

When the shadow area data of the numerical value of 5 is decremented and further delayed by one line and one pixel, the area in which the numerical value of 4 is described becomes a new shadow. Hereinafter, by repeating the same processing until the numerical value becomes 0, a shadow as shown in FIG. 15 can be added to the image. These processes can be easily performed by hardware using, for example, a line memory, a register, and an arithmetic unit.

The above-described shadow addition processing adds a shadow (three-dimensional shadow) equal to the size of an image (three-dimensional shadow addition processing). In addition, it has a so-called vanishing point that becomes smaller as the distance from the image increases. There is a lost shadow adding process for adding a shadow (hereinafter referred to as a lost shadow). This lost shadow adding process is generally performed by using software.

[0006]

However, according to the conventional image processing apparatus, the lost shadow processing is performed by using software. However, since the image data needs to be temporarily stored in order to perform the processing, it is particularly required. In the case of handling multi-valued image data, a large capacity memory is required, the cost occupied by the memory increases, the apparatus becomes expensive, and the processing takes time.

The present invention has been made in view of the above, and has as its object to reduce the cost of the apparatus and shorten the time required for the process of adding a lost shadow.

[0008]

According to the present invention, there is provided an image processing apparatus for performing a lost shadow adding process for adding a lost shadow to an image. a set value output means for outputting a set value of the shadow area data indicating the length of the shadow of the remaining relative shadow region data
An arithmetic means for performing arithmetic processing for reducing the length of the remaining shadow, and an image
When there is an image to which a shadow should be added based on the data
Selects the shadow area data output from the set value output means
If there is no image to which a shadow should be added,
Means for selecting the shadow area data output from the memory, and storing the shadow area data selected by the selection means in a predetermined memory.
Temporarily storing the shadow area data for a predetermined line and / or
A delay means for delaying readout by a predetermined number of pixels, a shadow area designating means for designating a shadow area using the shadow area data delayed by the delay means,
Shadow area setting means for setting a shadow area based on image data; shadow image data output means for outputting image data of the shadow area; and image data and shadow image data output means based on the setting of the shadow area setting means. And image data synthesizing means for synthesizing the image data output from the image data .
You .

Further, according to the present invention , in an image processing apparatus for performing a lost shadow adding process for adding a lost shadow to an image, setting of shadow region data indicating a shadow region to be added to the image and a remaining shadow length is provided. Setting value output means for outputting a value, calculation means for performing a calculation process for reducing the remaining shadow length on the shadow area data, and an image to which a shadow is to be added based on the image data
Exists, the shadow area output from the set value output means
Area data is selected and there is no image to add shadow
In this case, the first selecting means for selecting the shadow area data output from the calculating means, and the shadow area data selected by the first selecting means are temporarily stored in a predetermined memory to store the shadow area data.
Data for a predetermined line and / or a predetermined pixel
Delaying means, a plurality of shadow area specifying means for specifying a shadow area using the shadow area data delayed by the delay means, and a second selection for selecting data output from the plurality of shadow area specifying means. Means, shadow area setting means for setting a shadow area based on the data selected by the second selection means and the image data, shadow image data output means for outputting image data of the shadow area, and shadow area setting means JP by comprising an image data combining means for combining the image data by the image data and shadow image data output means is output based on the setting
Sign .

[0010] Further , the present invention provides the above-described configuration,
The delay means temporarily stores the shadow area data in a line memory.
In addition to delaying reading by a predetermined line,
Temporarily store shadow area data in a register and store it for a predetermined number of pixels.
Reading is delayed.

[0011]

The image processing apparatus according to the present invention performs the lost shadow adding process in a hardware manner (in real time) using sequentially input image data.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in the order of the first embodiment and the second embodiment with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a digital copying machine to which the image processing apparatus of the first embodiment is applied. An image reading unit 101 for optically reading a document image and an image output from the image reading unit 101 are shown. An image processing unit 102 that performs processing to be described later on image data, an image output unit 103 that outputs an image on recording paper using the image data output from the image processing unit 102, and a control unit that controls the entire copying machine 10
And 4.

The operation of the above configuration will be described. When the start key of the operation unit (not shown) is pressed,
The control unit 104 outputs a control signal to each unit to start an image forming operation. The image reading unit 101 converts an image of a document placed on a contact glass (not shown) into an analog electric signal using a CCD (not shown), and performs shading correction, A / D conversion on the electric signal. It performs conversion and other processing and outputs 8-bit image data. Image reading unit 101
The image data output from is subjected to a lost shadow adding process in the image processing unit 102, input to the image output unit 103, and output as an image on recording paper by the image output unit 103. The image processing unit 102 performs the lost shadow adding process only when a predetermined mode is set by the operation unit.

Next, the image processing unit 10 according to the first embodiment
2 will be described. FIG. 2 shows the image processing unit 102
FIG. 3 is a block diagram showing the configuration of FIG. As illustrated, an image processing unit 102 includes a binarization processing unit 201 that binarizes image data (input image data) input from the image reading unit 101.
And a shadow data generation unit 202 for setting a shadow area to be added to an image using data output from the binarization processing unit 201
And a color data output unit 20 for outputting image data of a shadow area
3 and a data selection unit 204 for selecting input image data and image data output by the color data output unit 203 based on the output of the shadow data generation unit 202. Note that the color data output unit 203 outputs the shadow image data of the present invention.
The data selection unit 204 corresponds to the data output unit.
It corresponds to the image data synthesizing means of the invention.

The operation of the above configuration will be described. The binarization processing unit 201 binarizes the 8-bit input image data using a predetermined threshold and performs shadow data generation.
Output to The shadow data generation unit 202 generates data (shadow data) specifying a shadow area to be added according to the input binary data, and outputs the data to the S terminal of the data selection unit 204. In the data selection unit 204, input image data is input to the A terminal, and image data from the color data output unit 203 is input to the B terminal. The data selection unit 204 determines that the shadow data input to the S terminal is one. (H level) selects the B terminal input, and 0 (L level) selects the A terminal input and outputs from the Y terminal.

Next, the shadow data generator 202 will be described. FIG. 3 shows a circuit diagram of the shadow data generation unit 202,
301 and 302 are selectors, 303 and 304 are line memories, 305 is an adder, 306 to 308 are registers, 309 to 312 are AND gates, 313 is an inverter, and 314 is an OR gate. The register 306
Corresponds to the set value output means of the present invention,
1, a circuit having an adder 305 and an AND gate 310
The path corresponds to the arithmetic means of the present invention, and the selector 302
According to the selection means of the present invention, the line memory 303 and
The register 307 corresponds to the delay means of the present invention, and
Gate 314, line memory 304, AND gate 31
1 and 312 and a register 308
In correspondence with the means for specifying a light shadow area, the AND gate 309 and the
The circuit having the inverter and the inverter 313 corresponds to the shadow region setting of the present invention.
Corresponding to the setting means.

The operation of generating shadow data in the above configuration will be described. The register 306 stores data for adding a shadow having a preset length, and is connected to the terminal B of the selector 302. Selector 302
In addition, the A terminal is connected to the Y terminal of the selector 301, the S terminal is connected to the binarization processing unit 201, and the Y terminal is connected to the line memory 303. Here, the selector 302 selects the B terminal input when the S terminal input is at the H level, and selects the A terminal input when the S terminal input is at the L level, and outputs 8-bit data from the Y terminal. The same applies to the selector 301.

When the binary data output from the binarization processing unit 201 is 0 (L level), the corresponding pixel density is light and no shadow is added, and when it is 1 (H level), the shadow is not added. This is the case where an image is added (when there is an image). Therefore,
The data of the register 306 is input to the line memory 303 when the binary data is 1. The line memory 303 is
In this embodiment, as shown in FIG. 4, D0in to D7in are data input terminals, D0out to D7out are eight line memories of data output terminals, RDCLK is a read clock input terminal, WRCLK is a write clock input terminal, and WE Is a write enable input terminal, bar R
E is a read enable input terminal, RSTW is a reset write input terminal, and RSTR is a reset read input terminal.

As shown in FIG. 4, the read clock input terminal and the write clock input terminal are provided with a pixel clock C.
LK is input, the write enable input terminal and the read enable input terminal are connected to the ground, and a negative logic line synchronization signal LSYNC is input to the reset write input terminal and the reset read input terminal. Here, the pixel clock CLK and the line synchronization signal LSYNC are synchronized with the image data output from the image reading unit 101.

The line memory 303 stores a line synchronization signal L
When SYNC goes high, data reading and writing are performed simultaneously from the head address in synchronization with the pixel clock CLK. The data read and write addresses are the same, and the data from the selector 302 is delayed by one line by the line memory 303.

The data output from the line memory 303 is temporarily stored in the register 307 and is delayed by one pixel, and the data read from the register 307 is input to the B terminal of the adder 305 and the OR gate 314. You.
The OR gate 314 inputs the 8-bit data from the register 307, performs a logical sum (1 except when all 8 bits are 0), and outputs the result to the AND gate 311 and the line memory 304. The line memory 304 delays the data from the OR gate by one line as in the line memory 303 and outputs the data to the AND gate 311.

The AND gate 311 is connected to the OR gate 314.
The logical product of the output and the output of the line memory 304 is calculated and output to the register 308 and the AND gate 312. The register 308 delays the output of the AND gate 311 by one pixel and outputs the delayed output to the AND gate 312.
2 takes the logical product of the output of the AND gate 311 and the output of the register 308, and outputs the result to the AND gates 309 and 310.

On the other hand, in the adder 305, an output in which all the 8-bit data is 1 is input from the control unit 104 to the A terminal, and the A terminal input and the B terminal input (output of the register 307).
Is output from the ， terminal, and the carry output is output from the C terminal. Here, the Σ terminal output means that the B terminal input value is 0
The value obtained by subtracting 1 from the B terminal input value other than at the time of, and the C terminal output becomes 1 except when the B terminal input value is 0.

The AND gate 310 is connected to the C of the adder 305.
The logical product of the terminal output and the output of the AND gate 312 is taken and output to the S terminal of the selector 301. The selector 301 also outputs the output from the A terminal, in which all 8 bits are 0, to the control unit 10
4 and the Σ terminal output of the adder 305 from the B terminal. Therefore, the selector 301 selects the AND gate 3
When the 10 outputs are 1, the Σ terminal output of the adder 305 is output from the Y terminal.

The AND gate 309 is connected to the AND gate 31.
The logical product (shadow data) of the two outputs and the output (binary data) of the binarization processing unit 201 whose output is inverted by the inverter 313 is output. The shadow data is input to the S terminal of the data selection unit 204 as shown in FIG. 2, and the data selection unit 204 receives the B terminal input when the S terminal input is 1.
When the S terminal input is 0, the A terminal input is output from the Y terminal.

Assuming that a closed loop indicated by a solid line is an image area as shown in FIG. 5, the shadow added area according to the first embodiment is a closed loop indicated by a dotted line (that is, the shadow data value is at H level). Here, in the numerical values described in the figure, the upper numerical value is the output value of the register 307, and the lower numerical value is the line memory 3
04 shows the output value. Note that FIG. 5 shows a case where the value stored in the register 306 is 5.

As shown in FIG. 5, in the first embodiment, the shadow area in the main scanning direction is reduced by two pixels every one line away from the image area, and the shadow area in the sub scanning direction is one pixel away from the image area. It can be seen that each time it is reduced by two lines. If the reduction ratio of the shadow is described by the ratio of the number of pixels reduced for each line, the reduction ratio of the shadow in the first embodiment is １ ／. FIG. 6 shows the result of image processing according to the first embodiment.

As described above, in the first embodiment, without using software (without using a frame memory or the like), real-time processing is performed using image data output from a lost shadow addition process in which the shadow reduction ratio is １ ／. Can be done with In this embodiment, the line memory 303 of eight lines is used.
By simply changing the data value or the input value of the A terminal of the adder 305, the length of the shadow to be added can be changed. This is because the pixel density is 8 dots / mm in the first embodiment.
, It means that a shadow having a length of 0 to 32 mm can be arbitrarily added in the main scanning direction.

Next, a second embodiment will be described. The second embodiment has substantially the same configuration as the first embodiment, and only different portions will be described.

FIG. 7 is a circuit diagram showing the configuration of the shadow data generation unit 202 according to the second embodiment. As shown, a selector 701 and a counter 702 are added to the configuration of the first embodiment. An OR gate 314 is provided at the A terminal of the selector 701, an AND gate 312 is provided at the B terminal, and a counter 702 is provided at the S terminal. Connected, and the Y terminal is AND
Connected to gate 310. The selector 302
Corresponds to the first selecting means of the present invention, and the OR gate 31
4, and OR gate 314, line memory 304,
Has AND gates 311 and 312 and register 308
Circuit corresponding to a plurality of shadow area designating means of the present invention,
The selector 701 and the counter 702 are provided in the second embodiment of the present invention.
Corresponds to the selection means.

The operation of the above configuration will be described. In the second embodiment, when the selector 701 outputs only the B terminal input, the shadow area added to the image is the same as that of the first embodiment. When the selector 701 outputs only the A terminal input, FIG. A three-dimensional shadow is added as shown in the conventional example. Here, the data selected by the selector 701 is the B terminal input when the S terminal input is at the H level and the A terminal input when the S terminal input is at the L level, similarly to the other selectors (301 and 302).

The counter 702 is a binary counter for counting the number of lines in the sub-scanning direction. The output is H level when the least significant bit is 0, and L level when it is 1. Therefore, the selector 701 outputs A level when the least significant bit is an even line.
The output of the ND gate 312 is selected, and the output of the OR gate 314 is selected for an odd line. Thus, the AND gate 31
By alternately selecting the two outputs and the OR gate 314 output, the shadow area to be added becomes as shown in FIG. In this example, the reduction ratio of the shadow is 2/3, and the actual image processing result is shown in FIG.

In the second embodiment, the shadow reduction ratio is 2/3.
In addition to the lost shadow addition processing, the output of the counter 702 can be fixed at the H level to perform the same lost shadow addition processing as in the first embodiment. Such a three-dimensional shadow adding process can be performed.

In the first embodiment, as shown in FIG. 10, one shadow area designating means 901 designates a shadow area using data output from a line memory 303 as a delay means. The shape of the shadow to be added can be changed only in length. However, as shown in FIG. 11, in the second embodiment, two shadow area designating means 911 and 912 are provided in the line memory 303, and the selecting means (composed of the selector 701 and the counter 702) 913 By selecting the outputs of the means 911 and 912, shadows of three types of shapes can be added.

As shown in FIG. 12, a line memory 9 capable of storing more lines than the line memory 303 is provided.
21, a shadow area specifying means group 922 including a plurality of shadow area specifying means for specifying a shadow area using data delayed by the line memory 921, and a selection for selecting and outputting data from the shadow area specifying means group 922. Means 923 and 924
With such a configuration, it is possible to add a wide variety of types and lengths of shadows. More specifically, a shadow area designating means for performing a lost shadow adding process with a reduction ratio of 1/3 as shown in FIG. 13 is added to the configuration of the second embodiment. If you make it possible to select
In addition to the three-dimensional shadow adding process and the disappearing shadow adding process in which the reduction ratio is 1/2, 2/3, and 1/3, the reduction ratio is 3/5, 2/5, 2
/ 3 (shadow area is slightly different from that described above). Note that FIG.
In the configuration of FIG.
Means 924 for selecting some of the outputs specified in advance from
Is output to the selecting means 924.
3 is selected in accordance with a preset order (the second means is selected by the selection means 923 and 924).
).

In the present embodiment, the 8-bit image data is binarized to perform the lost shadow adding process. However, the threshold value for binarizing is changed, or a range for outputting 1 is designated. Thus, a shadow can be added only to a portion having a desired image density.

Further, the second embodiment is conceptually shown in FIG.
However, in an actual circuit configuration, two shadow area designating means are connected in series. This has the effect of reducing the number of parts and suppressing an increase in cost when there are a large number of shadow area specifying means and there are overlapping portions in each circuit configuration. Therefore, when a large number of shadow area specifying means are provided, it is desirable to reduce the number of parts by connecting a plurality of shadow area specifying means in series according to the circuit configuration.

[0038]

As described above, according to the present invention, in an image processing apparatus for performing a lost shadow adding process for adding a lost shadow to an image, a shadow area to be added to the image and a remaining shadow length are indicated. A setting value output unit that outputs a setting value of the shadow area data, an operation unit that performs an operation process on the shadow area data to reduce the length of the remaining shadow, and a setting unit that outputs the shadow based on the image data.
If there is an image to be added,
Select the output shadow area data and add the shadow to the image
If there is no shadow area, the shadow area data
Selection means for selecting over data, 該影area De temporarily stored shadow area data selected by the selection means in a predetermined memory
Data for a specified line and / or a specified pixel
Delay means for out delay, set the shadow region designating means for designating an area of the shadow with the shadow region data delayed by the delay means, the designation of the shadow area specifying means, and a shadow area based on the image data Shadow area setting means, shadow image data output means for outputting image data of the shadow area, and image data synthesis for synthesizing the image data and the image data output by the shadow image data output means based on the settings of the shadow area setting means Because of the provision of the means, the cost of the apparatus can be suppressed, and the time required for the lost shadow adding process can be reduced.

Further , according to the present invention, in an image processing apparatus for performing a lost shadow adding process for adding a lost shadow to an image, setting of shadow region data indicating a shadow region to be added to the image and a remaining shadow length is provided. Setting value output means for outputting a value, calculation means for performing a calculation process for reducing the remaining shadow length on the shadow area data, and an image to which a shadow is to be added based on the image data
Exists, the shadow area output from the set value output means
Area data is selected and there is no image to add shadow
In this case, the first selecting means for selecting the shadow area data output from the calculating means, and the shadow area data selected by the first selecting means are temporarily stored in a predetermined memory to store the shadow area data.
Data for a predetermined line and / or a predetermined pixel
Delaying means, a plurality of shadow area specifying means for specifying a shadow area using the shadow area data delayed by the delay means, and a second selection for selecting data output from the plurality of shadow area specifying means. Means, shadow area setting means for setting a shadow area based on the data selected by the second selection means and the image data, shadow image data output means for outputting image data of the shadow area, and shadow area setting means Image data synthesizing means for synthesizing the image data and the image data output by the shadow image data output means on the basis of the setting of (1), so that the cost of the apparatus can be suppressed and the time required for the lost shadow addition processing can be reduced. In addition, a plurality of types of lost shadow addition processing can be performed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a digital copying machine to which an image processing apparatus according to a first embodiment of the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of an image processing unit according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a shadow data generation unit according to the first embodiment.

FIG. 4 is an explanatory diagram illustrating a line memory according to the first embodiment;

FIG. 5 is an explanatory diagram showing a shadow addition area according to the first embodiment.

FIG. 6 is an explanatory diagram illustrating an image processing result according to the first embodiment.

FIG. 7 is a circuit diagram illustrating a shadow data generation unit according to a second embodiment.

FIG. 8 is an explanatory diagram illustrating a shadow addition area according to a second embodiment.

FIG. 9 is an explanatory diagram illustrating an image processing result according to the second embodiment.

FIG. 10 is a schematic conceptual diagram illustrating a shadow data generation unit according to the first embodiment.

FIG. 11 is a schematic conceptual diagram illustrating a shadow data generation unit according to a second embodiment.

FIG. 12 is a schematic conceptual diagram showing a shadow data generation unit according to another embodiment.

FIG. 13 is an explanatory diagram illustrating an image processing result in which the reduction ratio is 1/3.

FIG. 14 is an explanatory diagram showing an example of a shadow adding process in the related art.

FIG. 15 is an explanatory diagram showing an example of a result of a shadowing process in the related art.

[Explanation of symbols]

102 Image processing unit 104 Control unit 201 Binarization processing unit 202 Shadow data generation unit 203 Color data output unit 204 Data selection unit 301 302 701 Selector 303 304 921 Line memory 305 Adder 306 307
308 Register 309 310 311 312 AND gate 313 Inverter 314 OR gate 702 Counter 901 911 912 Shadow area specifying means 922 Shadow area specifying means group 913 923 924 Selection means

Claims (3)

(57) [Claims] An image processing apparatus for performing a lost shadow adding process for adding a lost shadow to an image outputs a set value of shadow region data indicating a shadow region to be added to the image and a remaining shadow length. A setting value output unit, an operation unit for performing an operation for reducing the remaining shadow length on the shadow area data, and an image to which a shadow is to be added based on the image data.
In this case, the shadow area data output from the set value output means
If there is no image to add a shadow to,
Selecting means for selecting the shadow area data output from the calculating means; and transmitting the shadow area data selected by the selecting means to a predetermined area.
Memory and temporarily store the shadow area data for a predetermined line.
Delay means for reading and / or delaying a predetermined number of pixels ; shadow area designating means for designating a shadow area using the shadow area data delayed by the delay means; designation of the shadow area designating means; Shadow area setting means for setting a shadow area based on data; shadow image data output means for outputting image data of the shadow area; and image data and the shadow image data output means based on the setting of the shadow area setting means. An image processing apparatus comprising: image data combining means for combining output image data. 2. An image processing apparatus for performing a lost shadow adding process for adding a lost shadow to an image, wherein a set value of shadow region data indicating a shadow region to be added to the image and a remaining shadow length is output. A setting value output unit, an operation unit for performing an operation for reducing the remaining shadow length on the shadow area data, and an image to which a shadow is to be added based on the image data.
In this case, the shadow area data output from the set value output means
If there is no image to add a shadow to,
First selecting means and said first own the shadow area data selected by the selection means for selecting a shadow region data output from said calculation means
And temporarily store the shadow area data in a predetermined memory.
Delay means for delaying readout for a predetermined number of pixels and / or predetermined pixels; a plurality of shadow area designating means for designating a shadow area using shadow area data delayed by the delay means; Second selecting means for selecting data output by the shadow area specifying means, shadow area setting means for setting a shadow area based on the data selected by the second selecting means, and image data; And an image data synthesizing unit that synthesizes the image data and the image data output by the shadow image data output unit based on the setting of the shadow area setting unit. An image processing apparatus characterized by the above-mentioned. 3. The delay means according to claim 1, further comprising:
Temporarily store in in-memory and delay reading for a given line
And temporarily store the shadow area data in a register.
3. The image processing apparatus according to claim 1, wherein the reading is delayed by a predetermined number of pixels .