JP2806043B2 - Pipeline image processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer-based image processing apparatus, and more particularly, to a binary image pipeline image processing circuit.

[0002]

2. Description of the Related Art Image processing by a computer requires a long processing time for processing by software because the amount of image data is enormous. For this reason, various hardware configurations dedicated to image processing have conventionally been proposed. As dedicated hardware, there are a type in which image processing is divided by a plurality of hardware and a type in which pipeline processing is performed using a line memory.

[0003] The division processing method using a plurality of hardware speeds up the processing, but the amount of hardware becomes enormous and the cost increases. In this regard, the pipeline processing has an advantage of simplifying the circuit configuration.

FIG. 3 shows an example of a conventional pipeline image processing circuit, in which image processing is performed on each pixel of a binary image (black and white image) in relation to its surrounding pixels (near 3 × 3). Input pixel data read from a drawing or a document by an image scanner is temporarily stored in real time in a 3-bit shift register 1 and a line memory 2.
Are written sequentially. The pixel data written in the line memory 2 is temporarily stored in the 3-bit shift register 3 as pixel data delayed by one line of scanning by the image scanner from the input pixel data to the shift register 1. Similarly, the pixel data output of the line memory 2 is sequentially written to the line memory 4, and the line memory 4 obtains the pixel data output delayed by one line of the scanning by the image scanner from the input pixel data to the shift register 3. This data is temporarily stored in 3-bit shift register 5.

Accordingly, 3-bit shift registers 1, 3,
5 have the positional relationship shown in FIG. 4, and the pixel data DA ₁ , DA ₂ , DA of the scanning line A
₃ and pixel data DB ₁ , DB ₂ , DB _{3 of} scan lines B and C
, DC ₁ , DC ₂ and DC ₃ become 3 × 3 neighboring pixel data adjacent to each other. Pixel data of the positional relationship is acquired at once to the processing circuit 6, it is the image processing is taken out as output pixel data to be processed result for the pixel DB _2. In this image processing, for example, for data of a binary image read by an image scanner, when performing thinning processing of a character or a figure, a determination output “0” as to whether a pixel of DB ₂ becomes a white pixel or a black pixel by thinning is performed. "," 1 ".

[0006]

The conventional pipeline image processing simplifies the circuit configuration, for example, by eliminating the need for a frame memory for storing pixel data of the entire screen. Improvement cannot be expected. That is, if the input rate of the input pixel data is higher than the operation speed of the line memory, the shift register, and the processing circuit, processing becomes impossible, and the processing speed of these circuits is limited.

An object of the present invention is to provide a pipeline image processing circuit capable of greatly improving the processing speed.

[0008]

According to the present invention, there is provided a serial-to-parallel conversion circuit for converting a plurality of pixel data of input pixel data sequentially read by image scanning into parallel data as one block. 12 and one or more line memory circuits 13, 15, 14, 16 for supplying blocked pixel data of different lines at horizontal positions corresponding to the blocked input pixel data.
Registers 18, 19, and 20 for temporarily storing a part of pixel data one block before a plurality of pieces of parallel pixel data from the serial-to-parallel conversion circuit and the line memory circuit; A processing circuit array 17 that divides each pixel data of the circuit and the register into a plurality of groups and performs image processing in parallel with each other, and an output editing circuit 21 that edits and outputs a plurality of processing results of the processing circuit array in block units. It is characterized by having.

[0009]

According to the present invention having the above-described structure, input pixel data obtained by image scanning is converted into parallel data in block units, and blocked pixels of different lines at horizontal positions corresponding to the blocked input pixel data. Data is obtained, and these data and some pixel data of one block before a plurality of lines are divided into a plurality of groups, and image processing is performed in parallel, respectively, to perform parallel pipeline processing, and edit processing results. Obtain the result of parallel processing in block units.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention for performing a pipeline process on a binary image having only white pixels and black pixels. The input pixel data is sequentially written to the n-bit shift register 11, and at the writing end timing of n bits, all bits of the shift register 11 are preset in the n-bit register 12, and serial-parallel conversion of the input pixel data is performed. The line memories 13 and 14 are the same as the conventional ones, except that the output from the shift register 11 is sequentially written and shifted in n bits in parallel, thereby delaying the pixel data of the shift register 11 by one and two lines and the same horizontal (H). The block outputs pixel data of the position. In the n-bit registers 15 and 16, pixel data blocked into n bits of the line memories 13 and 14 are preset at the same timing as the shift register 12. With these configurations, n bits of the same horizontal position for three lines of input pixel data are stored in the registers 12 and 1.
5 and 16 are temporarily stored as parallel data.

Each of the n-bit pixel data in the registers 12, 15, and 16 is taken into the processing circuit array 17 as pixel data to be processed. 2-bit registers 18, 19, 20
Temporarily stores the last two bits of pixel data of one block before when the registers 12, 15, and 16 are preset with n bits as one block. Each 2-bit data of each of the 2-bit registers 18, 19, 20 is read at the timing when the data of the registers 12, 15, 16 is read by the processing circuit array 17.

The processing circuit array 17 includes registers 12, 1
N bit × 3 pixel data from registers 5 and 16 and register 1
Parallel image processing is performed by a parallel processing circuit divided into groups of n circuits by using 8 to 20 2-bit × 3 data. (N-
1) The bit register 21 temporarily stores (n-1) -bit data of one block before in the n-bit processing result of the processing circuit array 17, and adds n to the first bit PO3 of the processing result of the current block. Used for editing bit output pixel array data.

FIG. 2 is a diagram showing an operation mode of the present embodiment, in which pipeline processing is performed with four continuous pixel data as one block. When the parallel 4-bit pixel data DAO (0) to DAO (3) are preset in the register 12, the 2-bit register 18 is preset with 2-bit pixel data DAO (2) and DAO (3) one block before. The data DAO (0) to DAO (3) and PA (2), PA (3) are read by the processing circuit array 17 as 6-bit data of line A. Similarly, 4-bit data DBO (0) -DBO of registers 15 and 16
O (3), DCO (0) to DCO (3), and register 1
9, 20 2-bit data PB (2), PB (3), P
Data of 6 bits of lines B and C, which become C (2) and PC (3), are read by the processing circuit array 17.

In the processing circuit array 17, 6 of lines A to C
Parallel processing by four groups is performed on 4-bit pixel data from 4 × 3 pixel data. This process
For example, processing is performed on the 3 × 3 neighboring pixel data shown in FIG.
(3), DAO (0), DAO (1), PB (3), D
BO (1), PC (3), DCO (0), DCO (1)
Perform processing from the data of. Similarly, pixel data DBO
(1) and DBO (2) are processed from the peripheral data. Then, the pixel data PB (3) also has peripheral data PA (2), PA (3), DAO (0),
PB (2), DBO (0), PC (2), PC (3),
Processing is performed from DCO (0). At this time, the pixel data D
BO (3) is processed when the next block data is fetched.

Of the processing results of each group by the processing circuit array 17, pixel data DBO (0) to DBO (2)
Is temporarily stored in the register 21, while the processing result for the pixel data PB (3) is output as it is. Therefore, the output of the register 21 is output with a delay of one block processing, and the pixel data DBO is output.
The result is edited and output as the processing result (output pixel array) for the 4-bit pixel data in synchronism with the next processing result for (3). The processing result of the pixel data PB (3) is the last bit processing result of the previous output pixel array.

The above processing is performed in parallel with four pixels as one block, and the processing speed is quadrupled by continuously performing the block processing, that is, the pipeline processing. This block is shown in the case of 4 pixels, but in the case of n pixels, the number of bits of the registers 12, 15, and 16 is n, the number of parallel processing of the processing circuit 17 is n, and the number of bits of the register 21 is By using (n-1) bits, a pipeline processing circuit having a processing speed of n times is realized.
Further, the pipeline processing can be performed not only for the 3 × 3 neighboring pixels but also for arbitrary pixels such as 2 × 2 and 5 × 5.

In this embodiment, pixel data is represented by 1-bit binary data. However, this is pixel data having a halftone, and image processing such as density average and differentiation is performed based on the density of each pixel. It can be performed. In this case, the register and the line memory perform, for example, storage and delay processing in byte units.

In the embodiment, the registers 18 to 2
0 is to store some data after the block data,
Whether the processing circuit array is divided into groups before, after, right and left of the pixel data is appropriately changed in design depending on the image processing content.

[0019]

As described above, according to the present invention, a plurality of lines of parallel pixel data are obtained by using a plurality of input pixel data as one block, the data is grouped, and the parallel image processing is performed. Since the parallel pipeline processing for editing and outputting in units is performed, pixel data is used in a grouped manner in a grouped manner, and there is an effect that high-speed image processing can be performed while simplifying the circuit configuration by the pipeline processing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is an operation mode diagram of the embodiment.

FIG. 3 is a diagram of a conventional pipeline image processing circuit.

FIG. 4 is a 3 × 3 neighborhood pixel data positional relationship diagram.

[Explanation of symbols]

 11 ... n-bit shift register 12, 15, 16 ... n-bit register 13, 14 ... line memory 18, 19, 20 ... 2-bit register 17 ... processing circuit array 21 ... (n-1) bit register

Claims (1)

(57) [Claims] A serial-parallel conversion circuit (11, 12) for converting a plurality of pixel data of input pixel data sequentially read by image scanning into parallel data as one block, and corresponding to the blocked input pixel data. One or a plurality of line memory circuits (13, 15, 1) for supplying blocked pixel data of different lines at horizontal positions
4, 16) and a register (18, 1) for temporarily storing a part of pixel data one block before the plurality of parallel pixel data from the serial-parallel conversion circuit and the line memory circuit.
9, 20) and a processing circuit array (17) that divides each pixel data of the serial-parallel conversion circuit, the line memory circuit, and the register into a plurality of groups and performs image processing in parallel, respectively.
A pipeline image processing circuit comprising: an output editing circuit (21) for editing a plurality of processing results of the processing circuit array in block units and outputting the result.