JPH05130402A - Picture processor - Google Patents

Abstract

PURPOSE:To reduce the cost of hardware. CONSTITUTION:In this picture processor in which a surrounding picture elements of a noticed picture element is referenced to apply generation, division or gradation-correction to the noticed picture element, thereby implementing picture element processing such as antialiasing, the referencing of the surrounding picture elements is implemented while being divided into primary referencing and secondary referencing, AND gates 301, 302, an OR gate 303 and reference picture element switching circuits 304-306 are used to reference the picture element closest to the noted picture element through the primary referencing and a condition discrimination table 307 revises the secondary referencing picture elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and for example, an image using an image reference method when performing smoothing or interpolation, that is, antialiasing processing performed when a binary image image is printed out. The present invention relates to a processing device.

[0002]

2. Description of the Related Art In the print output of a printer or the like, a high resolution and a high gradation have been advanced due to the progress of the printing mechanism. With these advances, it is necessary to increase the amount of memory for storing images.

However, the current situation is that the cost reduction of the memory cannot compensate for the increase in the capacity corresponding to the printing mechanism.
There is also a demand for continuing to use conventional resources such as bit fonts having size dependence.

In order to fill the gap between the image image with a small memory and the printing mechanism capable of high-quality output,
A method has been proposed in which the performance of a printing mechanism is brought out by performing processing such as image image interpolation.

Poor image quality in a low-resolution binary image image is represented by the fact that, for example, when the interface between two density regions of white / black is inclined, it cannot be expressed smoothly.

The anti-aliasing process for smoothly expressing such a binary interface is performed in a printing mechanism such as a high-resolution laser printer, for example, in a display or a printing mechanism capable of pixel interpolation and multi-gradation output. Is performed by gradation correction or the like.

In this type of interpolation processing, in order to generate the gradation of one pixel, the pixel information around the pixel of interest is referenced, and the gradation of the pixel of interest is generated based on this.

In general, it is possible to carry out more effective processing by taking a wide reference area in the periphery and increasing the amount of information.

[0009]

However, in the above conventional example, the wider the reference area,
The cost of hardware is enormous. For example, the reference area for processing the pixel of interest located at (i, j) on the two-dimensional coordinate is 3 × 3 = up to ± 1 for i and j.
In the case of 9 pixels, when the information of the reference area is put in the address line of the memory and the hardware is realized by the table conversion method in which the read data is used as the gradation information, the memory size is 2 ⁹ = 512. You need a word.

To realize more effective processing, ± 2
When referring to the pixels up to, 5 × 5 = 25,2 ²⁵ ≈3
A memory of 2 × 10 ⁶ words is required, the cost becomes enormous, and the hardware cost expands to an unrealistic size as the reference area expands.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to provide an image processing apparatus capable of reducing hardware costs.

[0012]

[Means for Solving the Problems]
In order to achieve the object, an image processing device according to the present invention refers to a peripheral pixel of a pixel of interest, and in an image processing device that performs image processing of the pixel of interest, an input unit for inputting peripheral pixel data and the input unit. A dividing unit that divides the input peripheral pixel data into a plurality of pieces, a reference unit that refers to the arrangement of the nearest pixel of the pixel data of interest using a part of the peripheral pixel data that is divided by the dividing unit, and a reference unit that references the reference And changing means for changing the peripheral pixel data of the other part divided by the dividing means according to the arrangement of the nearest pixel.

[0013]

According to this structure, the input means inputs the peripheral pixel data, the dividing means divides the peripheral pixel data input by the input means into a plurality of pieces, and the reference means divides a part of the peripheral pixel data by the dividing means. Is used to refer to the arrangement of the nearest pixel of the pixel data of interest, and the changing unit changes the peripheral pixel data of the other part divided by the dividing unit according to the arrangement of the nearest pixel referred to by the reference unit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. <First Embodiment> (Outline) In this embodiment, by referring to the pixel of interest and its nearest neighbor pixel information,
By changing the reference area for the next reference, only the pixel information of high importance is taken out and the size of the conversion table for the condition judgment is suppressed. At the same time, by utilizing the fact that there is vertical symmetry, left-right symmetry, rotational symmetry, and, in the case of binary data, density inversion symmetry, etc., in the pixel arrangement logic that performs secondary reference, various symmetric pixels are The size of the table can be suppressed by treating it as the same information.

FIG. 1 is a diagram for explaining the importance of a peripheral region according to a pattern of neighboring pixels in the first embodiment,
FIG. 2 is a diagram for explaining that the area for secondary reference is switched according to the arrangement of neighboring pixels and the data pattern in the first embodiment.

In general, when interpolation processing is performed, the information of the pixel of interest is the most important, and the pixel information of the nearest neighbor has a lower correlation as it goes away from the pixel of interest, and the importance of the pixel information is high. Go down.

For example, in the case of binary image interpolation processing, it is only the density boundary that requires complicated processing. This is because it is necessary to understand the shape of the interface. Treating a uniform area away from the interface is straightforward. Further, when processing the interface, the importance of the pixel information away from the interface is low.

Therefore, if it is possible to first calculate whether the pixel of interest in the interpolation processing or the like is in contact with the interface and in which region the interface is present, unknown information can be discarded and the amount of hardware can be reduced. It will be possible.

It is possible to estimate whether or not the interface is in contact with such an interface and the interface area from the information of the pixel of interest and the nearest pixel. If the pixel of interest and the nearest neighbor pixel are uniform, it is not the interface. For example, if the pattern of the pixel of interest and the eight nearest neighbor pixels is as shown in FIG. 1, it can be determined that the interface is in the b direction. Therefore, it can be determined that the importance of the information in the shaded area A in FIG. 1 is low, but the importance of the area B indicated by the vertical line is high. The size of the hardware determination mechanism can be reduced by roughly determining the shape of the interface using the primary reference pixels and by secondarily referencing only the pixels that are highly important for more accurate shape recognition. It will be possible.

Next, a method of reducing the amount of hardware using symmetry will be described.

FIG. 14 is a diagram showing an example in which the neighboring pixel patterns of FIG. 6 according to the first embodiment are classified into 12 categories by rotational symmetry.

When performing processing such as pixel interpolation and gradation interpolation
Is for vertical and horizontal symmetrical patterns
The interpolation data output by the determination mechanism is the same. Also
If they are different, the rhombus becomes a parallelogram
Distortion may occur. Also, if two values are treated equivalently, black and white
The result corresponding to the inverted pattern is also the inverse of the original result.
Output. As shown in FIG. 2A, the pixel of interest I,
Nearest pixel x₊ , X_- , Y ₊ , Y_- Determine the reference area from
2B, the pattern shown in FIG.
If l as the reference area_- , L₀ , L₊ 3 pixels are selected
Shall be provided. Focusing on the vertical symmetry,
In the case of the pattern as shown in (c), the reference area m_- , M ₀ , M
₊ Becomes If the pattern of the reference area is the same
Should of course give the same output, so
Pixel l_- And m_- , L₀ And m₀ , L₊ And m₊ Is the same input section
Since it can be treated as a case, it is possible to reduce the input line of the judgment condition
It will be possible. Here, the c corresponding to FIGS.
The hardware configuration will be described with reference to FIG.

FIG. 3 is a block diagram showing a circuit configuration corresponding to FIG. In FIG. 3, 301 and 302 are AND
A gate, 303 is an OR gate, 304 to 306 are reference pixel switching circuits, 307 is a condition judgment table, and 310 to 3
Reference numeral 13 is a line buffer, and 320 to 324 are shift registers.

The OR gate 303 generates a table selection signal. The AND gate 301 has y ₊ · y ₋ · x ₊ · x ₋
・ Only when I is 1, AND gate 302 is y ・ y ₊・ x
₊ · X _- · only becomes one when I. Also, as symmetry,
Considering rotational symmetry about I instead of axial symmetry, the pattern shown in FIG. 2D can also be treated as transparent. In this case, l ₋ and m ₊ and n ₊ , l ₀ and m ₀ and n
₀ , l ₊ , m ₋ and n ₋ can be treated as the same input condition. Necessary pixel information is extracted from the image data serially output to the signal line 300 by scanning.

When the sum of the target pixel and the neighboring pixels is 5 as shown in FIG. 2A, the table T for discriminating the pixels in the reference area requires 2 ⁵ = 32, but if symmetry is used. As shown in FIG. 14, there are 12 groups, and the table size is half or less. In the case of the density symmetric logic, since the groups 1 and 7, 2 and 8, ... Have the same logic, the number of tables T can be further halved.

FIG. 4 is a block diagram showing the constitution of the image processing apparatus according to the first embodiment of the present invention, FIG. 5 is a block diagram showing the constitution of the switching mechanism according to the present embodiment, and FIG. 6 is according to the second embodiment. FIG. 15 is a diagram for explaining the arrangement of neighboring pixels, and FIG.
FIG. 6 is a diagram showing reference areas for each group according to the embodiment of FIG.

As shown in FIG. 15, the reference area may have an arbitrary shape and an arbitrary number of pixels for each pattern. However, if all the tables T are configured by one memory, it is necessary to input addresses for that number of pixels. In this embodiment, the number of tables is reduced to half by using a 90 ^° rotational symmetry and a density inversion symmetrical pattern. Further, groups 1 and 7 and groups 6 and 12 directly generate output data without referring to peripheral pixels, so that the number of tables is finally 4
I'm reducing it. Block S is a table selection signal,
A reference pixel switching signal, a density inversion signal, etc. are calculated from the pixel of interest and the nearest pixel information.

In FIG. 4, 401 is an S block formed by using a gate array or a combination of logic ICs, or simply ROM, and 402 is an S block 4.
A decoder for converting the binary output output from 01 into a selection signal of each table, 403 is a 2-input 4-output demultiplexer, and 404 and 405 are table input and output inverting circuits for utilizing density inversion symmetry. Shown respectively. 406 is group 1, 7 and group 6,
12 is a buffer circuit for generating a data output corresponding to 12. Reference numerals 407 to 412 configure a reference pixel switching circuit, and in particular, reference numerals 409 to 412 are simple data selectors, which select one of four pixels at rotationally symmetrical positions. 407 and 408 are demultiplexers having a mechanism for switching the connection as shown in FIG. 413-416
Indicates a table composed of a memory such as a gate array or a ROM.

In FIG. 4, the pixel is represented by C _ij with the relative value (i, j) from the pixel of interest as a subscript. Therefore, in FIG. 2, x ₋ is C _−1,0 , x ₊ is C _1,0 , y ₋ is C _{0, −1} ,
y is expressed as C _0,1 . The peripheral pixel selection circuits at the time of secondary reference are only those input to the table 413 corresponding to groups 3 and 9. The selection circuits corresponding to the tables 414 to 416 are omitted in this figure.

The decoder 402 may be included in the S block 401 if the output pins of the gate array, ROM, etc. forming the S block 401 have a margin in the structure of the present apparatus, or the tables 413 to 416 side are the ROM. For example, the decoder 402 may be omitted and the address may be directly input.

In the present embodiment, the control signal for pixel selection output from the S block 401 and input to the reference pixel switching circuits 407 to 412 uses rotation symmetry to form one pattern in a maximum of four directions. The control line is 2 bits because it is compressed to. The input of the demultiplexer 403 is 2
In the case of "00" in the base number, a and x, b and y, c and z, d and w are connected, and when the input is "01", a and w, b and x, c and y, d and z. , When the input of the demultiplexer 403 is “10”, a is z, and the others are similarly shifted and connected, and when the input is “11”, a is y, b is z, ...
It is connected in the form. Demultiplexers 407 and 4
08 is effective when there are a plurality of rotationally symmetric pixels with reference to the pixel of interest among the reference pixels. Actually, the data selectors 409 to 412 also select circuits 407 and 408.
It is possible to configure only one of these methods. Further, although the switch row shown in FIG. 6 is shown as 4 × 4, in practice, an arbitrary row of x, y, z, and w is demultiplexer 40.
It may be applied as shown in FIG. The inversion / non-inversion control of the inversion circuits 404 and 405 is S
Block 401 is implemented. Buffer circuit 40
6 outputs Di = I. The buffer circuit 406 becomes active only when the pixel of interest and the 5 pixel pattern in the nearest pixel are groups 6 to 12. At this time, the decoder 402 does not operate. Otherwise, the decoder 402 operates conversely and the buffer circuit 406 does not operate. The case of not referring to the table simply means that all the data are equal to one. This means that no interpolation processing is applied, but if there is no interface like groups 1 and 7 or if there are multiple interfaces, interpolation need not be performed.

As described above, according to the first embodiment, the input of the signal line in the pixel interpolation / gradation correction judgment circuit is reduced by switching, so that the total number of reference pixels can be reduced. It can be realized by hardware.

For example, if the structure of the first embodiment is implemented by the conventional method, the number of inputs of the judgment circuit is 33. In this embodiment, however, the table is 4 with 12 inputs.
This can be realized with a 16K-word ROM and peripheral circuits. <Second Embodiment> The present invention may have a configuration other than that of the first embodiment as a method of obtaining the nearest pixel.

FIG. 7 is a block diagram showing the configuration of the image processing apparatus according to the second embodiment, and FIG. 16 is a diagram showing a representative example of the neighboring pixel pattern according to the second embodiment.

FIG. 6 (a) is used in the first embodiment, but in addition to this, the 3 × 3 square shown in FIG. 6 (b), or as shown in FIG. 6 (d). Rectangular pattern,
Alternatively, there is a method of referring to the pixels in the non-square area shown in FIGS. 6 (a) and 6 (c). Alternatively, as shown in FIG.
The shape as shown in FIG.

Further, although it is possible to refer to a large area, the size of the S block shown in FIG. 4 increases as the number of pixels for primary reference increases, and the number of tables also increases. Therefore, it is more effective not to take too many nearest-neighbor pixels at the time of primary reference.

The present embodiment shows an example of the structure of 3 × 3 pixels shown in FIG. 6 (c). Since the number of pixels is 9, 2 ⁹ =
Although 512 patterns are required, considering the rotational symmetry, the density reversal symmetry, and the symmetry of the upper, lower, left, and right mirror images, FIG.
Are classified into 51 groups shown in. The total number in FIG. 16 includes the density inversion symmetrical pattern.

The configuration according to the second embodiment will be described with reference to FIG.

Compared to FIG. 4, the number of selection circuits and tables is increased, so that the number of tables is 700 and the number of selection circuits is 70.
1, each is shown as a block. Decoder 4
The configuration corresponding to 02 is included in the table 700 side. C _ij
Indicates a neighboring pixel input for primary reference. In the second embodiment, there are nine signal lines. The line input to the selection circuit 701 from the S block 401 has a maximum symmetry value of 8 or 2 ³ excluding the concentration symmetry, and thus has 3 signal lines.

Since the selection signals of the table input to the table 700 from the S block 401 are classified into 51 groups, 2 ⁶ = 64, the signal line is 6
It will be a book. What is expressed by C _{m, n} is a pixel group for secondary reference. The inversion circuits 404 and 405 are the same as those in FIG. 4, and invert the output or output it without inversion by the control input output from the S block 401. In FIG. 6, the buffer circuit 406 also uses the output data on the table 700 and is omitted.

As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained. <Third Embodiment> In the first embodiment, as shown in FIG.
When scanning line interpolation is performed as in (e), the value of the pixel of interest does not exist. Therefore, even in such a case, similar processing can be realized.

In this case, there is no rotational symmetry, and a combined expression of vertical and horizontal symmetry is obtained. 6 pixels for primary reference
Therefore, there are 64 combinations, but they are classified into 14 groups in consideration of symmetry. One group consists of up to four elements and their inverted patterns.

FIG. 17 is a diagram showing a representative pattern of 14 groups in the third embodiment, and FIG. 8 is a block diagram showing the configuration of an image processing apparatus according to the third embodiment. The circuit of FIG. 8 is used only during interpolation.

In FIG. 8, 801, 802, 820,
821 and 822 are OR gates, 830-1 to 830-m.
Indicates a table. , 801 are gates, which generate a group identification signal of a pattern of primary reference pixels and select tables 830-1 to 830-m.
The signals input to the final-stage OR gate 822 are a signal generated in a normal pattern and a signal generated in a density inversion pattern. The logic indicating the density inversion is put together by the OR gate 822 and controls the inversion circuits 404 and 405. The OR gates 820 and 821 generate vertically symmetrical and horizontally symmetrical information. Reference numerals 850-1 to 850-m are reference pixel switching circuits for performing symmetrical image replacement. The values of the pixels for which the above replacement and the left and right replacement are performed at the same time are passed through the reference pixel switching circuit twice, and the value of the table 83
It is input to 0-1 to 830-n. Although it is represented by two sets of data selectors, in reality, only one output is often used, and one set is sufficient.

As described above, also in the third embodiment, the same effect as that of the first embodiment can be obtained. <Output Circuit> Here, an output circuit connected to the subsequent stage of the inverting circuit 404, which is applicable to all of the first to third embodiments, will be described.

FIG. 9 is a block diagram showing the structure of the output circuit to which the first to third embodiments are applied.

In FIG. 9, reference numeral 900 denotes a buffer amplifier, which performs, for example, laser driving of a page printer, thermal head driving, and electron beam intensity adjustment of a CRT. 90
Reference numeral 1 is an A / D converter, which converts a data output into an analog value.

In the output circuit of FIG. 9, the inverting circuit 40
4 outputs D _{0 to} D _n are used as gradation information, and the A / D converter 9
A / D conversion is performed at 01, amplification is performed at the buffer amplifier 900, and output to a printer / display or the like is performed.

Next, modified examples applicable to all the first to third embodiments will be described. (First Modification) FIG. 10 is a block diagram showing a configuration of an output circuit according to a first modification of the application of the first to third embodiments, and FIG. 11 is a diagram for explaining the first modification. is there. Figure 10
In, 1000 is a buffer amplifier, for example,
Laser drive of page printer, thermal head drive, CRT
The electron beam intensity is adjusted. Reference numeral 1001 denotes an n + 1-bit shift register, which serially outputs the data read out in parallel.

As shown in FIG. 11, the pixel of interest is interpreted as a minute pixel divided in the main scanning direction, parallel / serial conversion is performed by the shift register 1001, amplified by the buffer amplifier 900, and then output to a printer / display or the like. Is output. Here, when divided into eight, _n of D _n becomes 7. (Second Modification) FIG. 12 is a block diagram showing a configuration of an output circuit according to a second modification of the application of the first to third embodiments, and FIG. 13 is a view for explaining the second modification. is there. 12
, 1200 is a buffer amplifier that drives a load,
Is. For example, laser drive of a page printer, thermal head drive, electron beam intensity adjustment of a CRT, and the like. 1
Reference numerals 203 and 1204 denote 2-bit and 2-bit shift registers, respectively, which serially output the data read out in parallel. 1205 and 1206 are line buffers, 1
Reference numeral 210 denotes a signal which is H at the time of writing the line buffer and becomes L at the time of outputting the data, and a control signal which connects 805 and 806 together.

The target pixels (D ₀ , D ₁ , D ₂ , D ₃ ) are shown in FIG.
As described above, the matrix is divided into 4 by 2 × 2, converted into 4 times the number of pixels, and the shift registers 1203 and 1204,
Via the line buffers 1205 and 1206, it is amplified by the buffer amplifier 1200 and output to a printer / display or the like. Here, in the second modification, as an example, since it is divided into four, n = 3 of D _n .

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0053]

As described above, according to the present invention, it is possible to realize the hardware with a small scale for the total number of reference pixels.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the degree of importance of a peripheral region according to a pattern of neighboring pixels in the first embodiment.

FIG. 2 is a diagram illustrating that a region for secondary reference is switched depending on an arrangement of neighboring pixels and a data pattern in the first embodiment.

FIG. 3 is a block diagram showing a circuit configuration corresponding to FIG.

FIG. 4 is a block diagram showing the configuration of the image processing apparatus according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration of a switching mechanism according to this embodiment.

FIG. 6 is a diagram illustrating an arrangement of neighboring pixels according to a second embodiment.

FIG. 7 is a block diagram showing a configuration of an image processing apparatus according to a second embodiment.

FIG. 8 is a block diagram showing a configuration of an image processing apparatus according to a third embodiment.

FIG. 9 is a block diagram showing a configuration of an output circuit to which the first to third embodiments are applied.

FIG. 10 is a block diagram showing the configuration of an output circuit according to a first modification of the application of the first to third embodiments.

FIG. 11 is a diagram illustrating a first modified example.

FIG. 12 is a block diagram showing a configuration of an output circuit according to a second modification of the application of the first to third embodiments.

FIG. 13 is a diagram illustrating a second modified example.

FIG. 14 is a diagram showing an example in which the neighboring pixel patterns of FIG. 6 according to the first embodiment are classified into 12 by rotational symmetry.

FIG. 15 is a diagram showing reference areas for each group according to the first embodiment.

FIG. 16 is a diagram showing a representative example of a neighboring pixel pattern according to the second embodiment.

FIG. 17 is a diagram showing a representative pattern of 14 groups in the third embodiment.

[Explanation of symbols]

310-313 line buffer 320-324 shift register 301,302 AND gate 303,801,802,820,821,822 O
R gate 304 to 306 Reference pixel switching circuit 307 Condition determination table 401 S block 402 Decoder 403 Demultiplexer 404, 405 Inversion circuit 406 Buffer circuit 413 to 415 Table 900 Buffer amplifier 901 A / D converter

Claims (1)

[Claims] 1. An image processing apparatus for performing image processing on a pixel of interest by referring to peripheral pixels of the pixel of interest, inputting means for inputting peripheral pixel data, and dividing the peripheral pixel data input by the inputting means into a plurality of pieces. Dividing means, reference means for referring to the arrangement of the nearest pixel of the pixel data of interest using a part of the peripheral pixel data divided by the dividing means, and the dividing means according to the arrangement of the nearest pixel referred to by the reference means An image processing apparatus, comprising: a changing unit that changes peripheral pixel data of another portion divided by.