JPH028314B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control device, and in particular to a memory control device suitable for use in a color display device for processing color images.

Recently, research on processing color images such as designs and aerial photographs using computers has become active. This is largely due to the development of high-performance input/output devices such as drum-type film scanners and high-resolution raster scanning color CRT monitors, and the availability of large-capacity IC memories at low prices over the past few years. This is due to the fact that it has become easier to use color display devices, which are essential for man-machine processing in image processing systems.

A color image display stores image data sent from a computer in the IC memory inside the device, reads it out in synchronization with television (hereinafter abbreviated as TV) read, and displays red (hereinafter abbreviated as R), red (hereinafter abbreviated as R),
Green (hereinafter abbreviated as G), Blue (hereinafter abbreviated as B)
The images are displayed on a high-resolution cathode ray tube monitor via a digital-to-analog (hereinafter abbreviated as DA) converter. Here, TV is used to mean that an address is generated in synchronization with the synchronization signal of a raster scan type CRT display monitor.
When three grayscale images corresponding to R, G, and B that make up a color image are input from a computer to the IC memory, a natural color still image similar to that seen on regular TV broadcasts is displayed on the color monitor. If the original spectra of the three prepared grayscale images deviate from R, G, and B, false color display will occur. False color display is sometimes used for the purpose of displaying specific characteristics in an image in an easy-to-understand manner for humans.

When this natural color or false color display is being performed, there may be cases where it is desired to change part or all of the displayed image. At that time, it is necessary to access the memory in which the image information being displayed is stored, but conventionally, when this access is performed, access to the memory for display is interrupted for the access time. It was necessary to prohibit the display of images. As a result, there was a drawback that the image displayed on the display device flickered.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art, and an object of the present invention is to simultaneously display an image and access the memory in which the image information is stored. An object of the present invention is to provide a novel image memory control device (hereinafter simply referred to as a memory control device) that can eliminate flickering in image display.

Another object of the present invention is to provide a novel memory control device that can easily modify, change, and edit image information stored in an image memory.

Still another object of the present invention is to provide a new image processing apparatus that can be constructed at an extremely low cost by using low-speed memory at high speed.

The above-mentioned objects of the present invention are to provide a plurality of sets of independent memories capable of simultaneously outputting first data and second data, an address control unit that generates a plurality of sets of independent addresses for these memories, and the A memory control device comprising: a data control unit that inputs the first data from a plurality of sets of memories and external data from an external device, calculates and selects them, and outputs them to the plurality of sets of memories; Alternatively, a plurality of sets of independent memories capable of simultaneously outputting the first data and second data, an address control section generating a plurality of sets of independent addresses of these memories, and a plurality of sets of independent memories capable of outputting the first data and the second data simultaneously; a data control unit that inputs first data and external data from an external device, calculates and selects them, and outputs them to the plurality of sets of memories; and the second data from the plurality of sets of memories and a television. A memory control device comprising: a data calculation unit that inputs data from a camera, calculates and selects the data, and outputs the data; and a selection unit that selects and outputs the output of the data calculation unit and the output of the data control unit; achieved by.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an image display device including a memory control device according to the present invention. In the figure, reference number 100 is an address control unit that generates two sets of independent address signals 110 and 111 for memory A and memory B, and 200 is a random data signal output from memories A and B.
a' and b' and external devices (CPU10, CCD scanner 2)
0, external data signal 1 from magnetic disk 30)
The data control unit 300 inputs the sequential signals a and b read from the memories A and B and the data signal 51 from the TV camera 50, and calculates and selects them and outputs them. A data calculation section 400 selects and outputs the output of the data calculation section 300 and the data control section 200.
A selection unit configured by, for example, a multiplexer or the like, which selects and outputs the output of 6
0 is a DA converter, 70 is a CRT (cathode ray tube) display monitor, 500 is a video detection section, and 600 is a color conversion section.

The general operation of the image display device having the above configuration will be explained as follows. External data signals 12 from external devices such as the CPU 10, the CCD scanner, and the magnetic disk 30 pass through the data control section 200 and the selection section 400 under the control of the address control section 100, and are written into the memories A and B. The data stored in memories A and B are read out sequentially (high speed) in synchronization with the TV raster scan synchronization signal, and sequential (high speed) read data signals a,
It is output as b. These sequential data signals a and b are processed by a video detection section 500, a color conversion section 600, and a DA converter 60 according to the intended purpose, and are converted into R, G, and B analog signals and displayed on a monitor 70, for example. Displayed at TV display speed (30 frames/second). At the same time that the sequential data signals a and b are sequentially read out from the memories A and B, their stored contents are read out randomly (at low speed) from the other outputs of the memories A and B, and the random (low speed) data signals are read out from the other outputs of the memories A and B. Output as a′, b′. These random data signals a′,
b′ is fed back to the data control unit 200,
Therefore, for example, calculations such as a'+b', a'-b', b'-a', etc. are performed, and these data are selected by the selection section 400 and written to the memory A and/or the memory B. Sequential data signals a and b output from the memories A and B and the data signal 51 from the TV camera 50 are calculated and selected in the data calculation section 300, and then sent to the selection section 400 or the data control section 2.
The data is written to memories A and B via 00, thereby changing and modifying the display contents.

FIG. 2 shows an embodiment of the detailed block configuration of the address control section 100, which is one of the components of the present invention. In the figure, 101 is a pattern timing control circuit that controls sequential and random pattern read/write timing, and 102 is a pattern address generator that generates graphic addresses and matrix addresses using dots, vectors, and characters. It is composed of, for example, a counter that generates the X address and Y address signals of these patterns, and is used independently for random reading/writing, and for sequential reading/writing.
For writing, the following circuits 103, 104 or 1 are used.
103 is a sequential read control circuit for memory A, 104 is a sequential read control circuit for memory B, and 105 is a sequential write control circuit. The circuits 103, 104, and 105 can be easily configured by, for example, counters.

Next, the operation of the address control section in FIG. 2 will be explained with reference to the time chart shown in FIG. 3. The parameter data signal 11, pattern start signal 13, and sequential write start signal 14 are
Input from CPU10.

The sequential read control circuits 103 and 104 of the memories A and B cooperate with the pattern address control circuit 102 to read the format specified by the parameters from the CPU 10, such as the size, position, and display of the area to be displayed in the memory. Depending on the display position on the screen, enlargement, etc., address signals 110 and 111 (block address signals described later) are generated in TV synchronization.
SRBA, address signal ADD) to memory A,
The data is generated independently for memory B, and the contents of each memory are read out sequentially, that is, at high speed, and displayed on the monitor 70 (see FIG. 1). Furthermore, when the control circuits 103 and 104 execute reading from the memories A and B, the control circuits 103 and 104 output the A wait signal 112 and the B wait signal, respectively.
A wait signal 113 is generated.

The sequential write control circuit 105 is a CPU
10, i.e., for example, memory A→memory A, memory A
→ Memory B, Memory B → Memory A, Memory B → Memory B, or TV camera → Memory A, TV camera → Memory B. Sequential write start signal 14 is generated by specifying the transfer method, transfer area size, and position. When input, address signals 114 and 115 (block address signals described later) are generated in TV synchronization with the cooperation of the pattern address control circuit 102.
(including RRBA and address signal ADD),
Write the contents of the specified memory to the specified memory, or write the output data 5 of the TV camera 50
1 to the designated memory of memories A and B.

Graphics, characters, etc. are read/written by a pattern timing control circuit 101 and a pattern address control circuit 102. First of all, the CPU
By the parameter data signal 11 from 10, the format of figures, characters, etc., that is, the start position and size of reading/writing of characters, figures, etc. in the memory is set in advance in the pattern address control circuit 102. A pattern timing control circuit 101 operates according to a pattern start signal 13 from the CPU 10. In this case, pattern timing control circuit 1
When executing read/write to memory A (hereinafter referred to as A order), 01 checks whether or not the A wait signal 112 is generated from the sequential read control circuit 103 of memory A, and then writes data to memory B. When executing read/write (hereinafter referred to as B order), it is checked whether the B wait signal 113 is generated from the sequential read control circuit 104 of memory B, and if the corresponding wait signal is not output, , outputs an address enable signal 116. The pattern address control circuit 102 receives this address enable signal 1.
16 outputs the address signal of the pattern to the corresponding address bus, calculates the address of the next pattern, waits for the next address enable signal, outputs the address signal of the pattern every time the address enable signal is input, Computes the address of the next pattern. Here, when the sequential write start signal 14 is input and the sequential write control circuit 105 operates, the control circuit 10
5 inputs a sequential write mode signal to the sequential read control circuits 103 and 104 of memories A and B, stops the operation of the control circuits 103 and 104, and prohibits generation of wait signals 112 and 113, and outputs an address signal 114. , 115 to execute a sequential write operation. In this embodiment, sequential reading of memory A and memory B is executed 30 times per second and displayed 30 times.
For example, one reading time can be used to execute sequential writing, and the output data signal 51 from the TV camera 50 is input to the data calculation section 300, either in its raw form or in a processed form. Memory A or memory B through the selection unit 400
written to. The above loop is also used when exchanging the memory contents stored in memory A and memory B, and sequential writing can be executed in a short time of about 1/30 seconds, and in that case, as described above, the read operation, Therefore, although displaying images is also prohibited,
Since the time is extremely short at 1/30 seconds (the display time of one frame), the display screen does not flicker at all.

Therefore, the pattern address control circuit 102
When writing and reading of all patterns are completed, a pattern end signal 117 is output to the pattern timing control circuit 101, and generation of the address enable signal 116 from the control circuit 101 is prohibited. The pattern timing control circuit 101 controls the pattern busy signal 11 from the start of the pattern to the end of the pattern.
8 to the CPU 10 to notify that the pattern is being read/written to memories A and B.
The control circuit 1 is in the process of reading/writing to the corresponding memory.
Wait signals 112, 113 from 03 or 104
is output, the pattern timing control circuit 101 does not generate the address enable signal 116 until the wait signal is released.

Next, referring to FIG. 4, there is shown one embodiment of the data control unit as one component of the present invention. In the figure, 201, 205, 207
is a selection circuit, 202 and 204 are registers, 203
2 shows a shifter, and 206 shows an arithmetic circuit.

Hereinafter, the operation of FIG. 4 will be explained with reference to FIGS. signals) are set in the mask register 204 in advance. Selection circuit 20
If the write data is, for example, 8 bits, 5 is composed of 8 multiplexers, and selects the output of the shifter 203 or the output of the selection circuit 207 for each bit by "1" or "0" of the corresponding bit of the mask signal. do.

External data 12 from the CPU 10, CCD scanner 20, magnetic disk 30, etc., and the selection circuit 207
The read data of memory A or memory B that has been selected and processed by the calculation circuit 206 is selected by the selection circuit 201 by the write data selection signal 15 on the control signal bus 120 from the address control section 100. The selection circuit 207 selects random read data of memory A or B to be read/written (referred to as an order) by the read data selection signal 16 supplied through the control signal bus 120.
Select a′ or b′. The arithmetic circuit 206 calculates a'+b', a'-b',
Perform operations such as b′−a′.

The output of the selection circuit 201 is input to a shifter 203 and can be modified by converting the bit position as shown in FIGS. 5 and 6, that is, changing brightness and density by bit shifting. shifter 203
is constituted by, for example, a normal bidirectional ring shifter. If the shift number is zero, the selection circuit 20
1 is output from the shifter 203 as it is, but in other cases it changes as shown in FIGS. 5a and 5b.

Therefore, the output of the shifter 203 and the selection circuit 2
If the i-th bit of the mask signal applied to the selection circuit 205 is "1", the i-th bit of the shifter 203 is input to the selection circuit 205 as the write data signal. 21
If the i-th bit of the mask signal is "0", the output of the selection circuit 207 is output as the write data signal 210, and is sent to the memory A or the write data signal 210 via the selection circuit 400 shown in FIG. written to B. The effect of the selection circuit 205 is that the bit to be changed in the memory data can be specified by a mask signal, and the data can be selected arbitrarily. Usually, in a two-dimensional memory as shown in Figure 6,
When writing data to a position addressed by X and Y, all bits (e.g. 8 bits in the Z direction) are changed as shown in Figure a. 1”)
However, as shown in b, by using a mask signal, only the bits desired to be changed can be written.

FIG. 7 is a diagram showing an example of the internal configuration of memory A and memory B, which are one of the important components of the present invention, and FIG. 8 is an operation time chart thereof. The memory A and the memory B are constructed in exactly the same manner, and a detailed explanation thereof is described in the specification of Japanese Patent Application No. 54-28916 filed on the same day by the same applicant as the present application. In the figure, the storage device is divided into, for example, 16 blocks, and 16 memories M0 to M
15. Each memory M0-M1
Write data registers WR0 to WR15, sequential read data registers SR0 to SR15, and random read data registers RR0 to RR15 are provided for the inputs and outputs of 5, respectively. D1 is a decoder that decodes the sequential read block address signal SRBA and outputs sequential read block selection signals S0 to S15. D2 is a decoder that decodes the sequential write/random read/write block address signal RRBA and outputs a random read/write block. Selection signal R
0 to R15 and a decoder that outputs sequential write data set signals SW0 to SW15, G1
1 and 2 respectively show gate circuits for the write enable signal WE.

Next, the operation of the circuit shown in FIG. 7 will be explained with reference to the time chart shown in FIG. The block address signals SRBA, RRBA and the address signal ADD are transmitted from the A address bus and B address bus of the address control unit 100 to the read data set signals SRDS,
Control signals such as RRDS are supplied from a control signal bus 120.

When in sequential read mode, Fig. 8a
As shown in the figure, the contents of the 16 blocks of memories M0 to M15 specified by the address signal ADD are simultaneously set to the corresponding sequential read data registers SR0 to SR15 by the sequential read data set signal SRDS, and the contents of the 16 blocks of memories M0 to M15 specified by the address signal ADD are set to the corresponding sequential read data registers SR0 to SR15 at the same time. , block selection signal S0~
S15), the above 16 registers SR0 to SR1
Select and output the contents of 5. That is, parallel-to-serial conversion is performed.

When in sequential write mode, Figure 8c
As shown in , the write data signal WDS is set in the write data registers WR0 to WR15 specified by the block address signal RRBA. That is,
The block address signal RRBA is decoded by decoder D2, and the write data set signal WDSS is used to decode the block address signal RRBA.
ANDed sequential write data set signal
A write data signal is set in the corresponding register by SW0 to SW15. Write data is signal SW0~
Assuming that the corresponding registers are set sequentially by SW15, the contents of the eight registers set by signals SW0 to SW7 are specified by address signals by signals W0 to W7 during the period in which signals SW8 to SW15 are set. memory M0 to memory M7
simultaneously, that is, in parallel, and the signals SW0 to SW7
During the period set by the signal SW8~
The contents of the eight registers set by SW15 are written in parallel to the memories M8 to M15 specified by the addresses by signals W8 to W15. Thus, data signals can be sequentially converted from serial to parallel and can be written at high speed.

In the random read mode, as shown in FIG. 8b, the contents of the memories M0 to M15 specified by the address signal ADD are simultaneously read out and simultaneously set to the registers RR0 to RR15 by the random read data set signal RRDS. However, by enabling the output of only the register specified by the random read/write block address signal RRBA by the signals R0 to R15, the contents of the memory corresponding to the block address signal RRBA are changed to the random read data registers RR0 to R15. Random read data signals a', b' from RR15 (see Figure 1)
is output as These data signals a' and b' are input to the selection circuit 207 of the data control section 200 and are subjected to various image processing such as shifting and masking.
The analysis process is performed as described above.

In the random write mode, the write data signal WDS is changed to the block address signal by the random read/write block address signal RRBA.
The corresponding write data registers RW0 to RW15 are set by the signals SW0 to SW15 corresponding to RRBA, and the contents of the corresponding registers are set to the addresses of the corresponding memories M0 to M15 by the write signals W0 to W15 corresponding to the block address signal RRBA. will be written to the address specified by . FIG. 8B is a time chart exemplifying the operation of randomly writing random read data signals a' or b' read from memory A or memory B to the same or different addresses. In the following sequential read mode and random read mode, block selection signal S0
~S15, R0-R15 independently output enable read data registers SR0-SR15, RR0-RR16, so they can be executed simultaneously and independently, and signals a, a' (or b, b') can be output simultaneously and independently. Can be read.

FIG. 9 shows a data calculation section 300 and a video detection section 5.
00 is a block diagram of a color conversion section 600. The data calculation section 300 includes selection circuits 301 and 30
2. By the data conversion circuits 303 and 304, the video detection section 500 is connected to the comparison circuits 501, 502, 5
03. Due to the priority order circuit 504, the color conversion section 600 is configured by color conversion circuits 601, 602, and 603, respectively.

Selection circuits 301 and 302 select one of data signals a, b, and 51 from memory A, memory B, and TV camera 50 according to parameters from CPU 10. The data conversion circuits 303, 304 and the color conversion circuits 601, 602 are, for example, look up tables (Sakai, Kanai, Kubo,
Ariki, “TV image input and color TV display device for computer image processing research”, IEICE technical report, vol.75, No.148, IE75-74, 1975
), and the conversion data is set from the CPU 10. Comparison circuit 501,5
02,503 is the video signal 310,311
Compare with the specified parameters from CPU10,
When the video signals 310, 311 satisfy the comparison conditions, comparison signals 511, 512, 513 are output.
For example, the comparison circuit 501 is specified to output the comparison signal 511 when the video signal 310 satisfies the upper limit value UA and the lower limit value LA. Further, the comparison circuit 502 is instructed to output a comparison signal 512 if a certain bit of the video signal 311 is "1". Alternatively, the comparison circuit 503 is instructed to output the comparison signal 513 if a certain bit of the video signal 310 and a certain bit are simultaneously "1".

The priority order circuit 504 receives the comparison signals 511, 51
When 2,513 become "1" at the same time, a signal with a high priority is output. For example, signals 511-5
13 has a high priority in the order of 511>512>513, the comparison signals 511, 512, 51
3 become "1" at the same time, only the enable signal 521 is output, and the comparison signals 512 and 513
If both are "1" at the same time, only the enable signal 522 is output. As a result, at a certain time, the color conversion circuits 601, 602, 60 are on the color bus 610.
3 is output, and the corresponding output data is correctly displayed on the monitor 70.

Data conversion circuits 303 and 304 have a function of converting input data signals as shown in FIG. For example, if the input data signal is 8 bits, the input data signal has a value between 0 and 255;
The output is set to the first output using the lookup table described above.
Convert as shown in Figure 0.

For example, if the input data signal is 8 bits, the color conversion circuits 601 and 602 convert the input data signal to 0.
Since the input data signal has a value of ~255, the input data signal is converted into 256 types of color data and output using a lookup table. For example, if the value of input data is i, as shown in FIG.
Ri, Gi, and Bi are output.

When the enable signal 523 is "1", the color conversion circuit 603 outputs color data signals such as red, green, blue, cyan, magenta, yellow, white, and black specified by the CPU 10.

The present invention is constructed and operates as described above, and the following effects are produced according to the present invention.

First, in parallel with the sequential read/write loop of memories A and B, a random read/write loop of memories A and B is performed between the memories A and B, the data control unit 200, and the selection unit 400. As a result, it is possible to simultaneously execute memory access for image display and read/write access for the purpose of modifying or modifying the memory contents of the same memory in which the display image information is stored. Therefore, it is now possible to change the contents of the memory, modify, and analyze the contents of the memory while always maintaining the best image display condition without image flickering without prohibiting image display. .

Second, the data signal 51 from the TV camera
is calculated and selected in the data calculation unit 300 together with the sequential read data signals a and b output from the memories A and B, and the data signal is further outputted to the selection circuit 400 or the data control unit 2.
00 and the selection unit 400, a loop is formed in which the data is written to the memories A and B and displayed.
The stored contents of memories A and B can be exchanged and changed in an extremely short time of about 1/30 seconds and without flickering the display screen, and the data signal 51 output from the TV camera can be exchanged or changed as it is or as desired. By performing various processing processes according to the purpose of the above, it has become possible to easily and accurately write and display data in memory A or B in about 1/30 seconds.

Third, since the low-speed memory is configured to be accessible at high speed and the configuration of its peripheral circuits is simplified, the present invention allows a color image processing device with the same functions as conventional ones to be produced at an extremely low cost. It is now possible to produce.

Although the above description is about one embodiment in which the present invention is applied to an image processing device, it goes without saying that the present invention can be similarly applied to other data processing devices or others.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an example;
It goes without saying that the present invention is not limited only to the embodiments described here. Therefore, the present invention can be implemented with various changes without departing from the spirit of the invention.
For example, the number of memories used is two, A and B in this embodiment, but the number can be three or four, and the arithmetic circuit 206 provided in the data control unit 200 is Alternatively, the data calculation section 300 can be simply configured with a multiplexer, or the random read registers RR0 to RR in the memories A and B can be removed.
15 can also be replaced with a bus driver,
Other changes are also easy. However, all of these and other modifications and changes are included within the scope of the claims of the present application.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing one embodiment of the present invention applied to an image processing device, FIG. 2 is a block configuration diagram showing one embodiment of the address control section, and FIG. 3 is the same as shown in FIG. FIG. 4 is a block diagram showing an embodiment of the data control section; FIGS. 5 and 6 are diagrams for explaining the operation of the data control section shown in FIG. 4. 7 is a schematic block configuration diagram showing one embodiment of the memory, FIG. 8 is an operation time chart of the memory shown in FIG. 7, and FIG. 9 is a diagram of the data calculation section, video detection section, and color conversion section. Block configuration diagram, Figure 10,
FIG. 11 is a diagram for explaining the configuration shown in FIG. 9. 10...CPU, 11...Parameter data signal, 12...External data signal, 13...Pattern start signal, 14...Sequential write start signal, 15...Write data selection signal, 16...Read data selection Signal, 20...CCD scanner, 30
...Magnetic disk, 50...TV camera, 51...
... Output data signal of TV camera, 60 ... DA converter, 70 ... CRT monitor, 100 ... Address control section, 101 ... Pattern timing control circuit, 102 ... Pattern address control circuit, 10
3...A memory sequential read control circuit, 1
04...B memory sequential read control circuit,
105...Sequential write control circuit, 11
0, 111, 114, 115...address signal,
112, 113...Wait signal, 116...Address enable signal, 117...Pattern end signal, 118...Pattern busy signal, 119...
... sequential write mode signal, 120 ... control signal bus, 200 ... data control section, 201,
205, 207...selection circuit, 202, 204...
...Register, 206...Arithmetic circuit, 210...Write data signal, 300...Data calculation section, 30
1,302...Selection circuit, 303,304...Data conversion circuit, 310,311...Video signal,
400... selection section, 500... video detection section, 5
01, 502, 503... Comparison circuit, 504...
Priority order circuit, 511-512... Comparison circuit, 5
21-523...Enable signal, 600...Color conversion unit, 601, 602, 603...Color conversion circuit, 610...Color bus, A, B...Memory A, memory B, a, b...Memory A , B sequential data signals, a', b'...random data signals of memories A and B, M0 to M15...memories,
D1, D2...decoder, G1...gate circuit,
WR0 to WR15...Write data register, SR0
~SR15...Sequential read data register, RR0-RR15...Random read data register, ADD...Address signal, SRBA...Sequential read block address signal,
RRBA...Sequential write, random read/write block address signal, WDS...Write data signal, WDSS...Write data set signal,
TVW...Sequential write designation signal, WE...
...Write enable signal, SRDS...Sequential read data set signal, RRDS...Random read data set signal, S0-S15...Sequential read block selection signal, R0-R15...
Random read block selection signal, SW0 to SW1
5...Sequential write data set signal, W
0 to W15...Write signal.

Claims (1)

[Scope of Claims] 1. A plurality of independent image memories capable of simultaneously outputting first data and second data;
an address control unit that generates a plurality of independent sets of addresses for these image memories; and inputs the first data from the plurality of sets of image memories and external data from an external device, and performs calculation and selection processing on them. An image memory control device, comprising: a data control unit that outputs to the plurality of sets of image memories, and outputs the second data to a monitor. 2. multiple sets of independent image memories capable of simultaneously outputting first data and second data;
an address control unit that generates a plurality of independent sets of addresses for these image memories; and inputs the first data from the plurality of sets of image memories and external data from an external device, and performs calculation and selection processing on them. a data control unit that outputs to the plurality of sets of image memories, and a data calculation unit that inputs the second data from the plurality of sets of image memories and data from the television camera, performs calculation and selection processing on them, and outputs them. and a selection unit that selectively outputs the output of the data calculation unit and the output of the data control unit,
An image memory control device, wherein the second data is output to a monitor via the data calculation section.