JP3093359B2 - Line buffering processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line buffering circuit used in an image processing apparatus or the like.

[0002]

2. Description of the Related Art For example, when a smoothing filter process shown in FIG. 2 is performed on a raster-scanned serial image data sequence in real time, a one-line delay circuit (see FIG. 31a, 31
b) That is, a line buffering processing circuit is required in the configuration. In FIG. 3, reference numerals 32a to 32f denote one-pixel delay elements, and reference numeral 33 denotes an arithmetic circuit for performing a weighted average operation according to the filter coefficient shown in FIG. Conventionally, a line buffering processing circuit for accumulating and delaying one line of image data is realized with a configuration as shown in FIG. In FIG. 4, reference numeral 41 denotes a counter for generating an address signal for a memory, and reference numeral 42 denotes a RAM having a capacity capable of storing one line of an image data sequence.
(Random access memory) 43 is a three-state memory for controlling input data during a write cycle.
A buffer 44 is a flip-flop that strobes read data output from the SRAM 42 during a read cycle. FIG. 5 is a diagram showing an example of the timing of the image signal handled here. It is assumed that data of one pixel is input in synchronization with the image clock, image data of one line is input in synchronization with the line synchronization signal, and image data of one page is input in synchronization with the page synchronization signal. Accordingly, the circuit shown in FIG. 4 performs the line buffering process at the timing shown in FIG. Here, for the sake of explanation, a timing chart in a case where there are seven image data in one line is shown. Input data is input line by line in synchronization with the image clock (CLK) and the line synchronization signal (LSYN). The counter operates in synchronization with the CLK using the line synchronization signal as a count operation enable signal. The input data is output on the data bus by the write signal WR, and is simultaneously written into the memory using the counter output as an address.

The data written in the memory is read out by the RD signal at the time of the next line processing, and is strobed to a flip-flop. By sequentially performing the above processing for each line, input data delayed by one line can be obtained as output data.

[0004]

However, depending on the contents of the processing, it may be necessary to perform a delay processing with n pixels less than one line. For example, in the binarization processing circuit based on the error diffusion method shown in FIG. 14, when performing the error distribution processing according to the matrix shown in FIG. is necessary. Here, in FIG.
Reference numerals 41a to 41e denote one-pixel delay elements for delaying input image data by one pixel, reference numerals 142a to 142d denote adders for adding a quantization error generated by binarization to neighboring pixels, and reference numeral 143 denotes three pixels from one line. A line buffer 144 for performing a small delay process is a binarization circuit 144 for binarizing multi-valued data of a target pixel including a binarization error of a peripheral pixel, and 145 is a quantization error generated when the target pixel is binarized. Is an error distribution circuit that computes a value that distributes the quantization error to peripheral pixels.

FIG. 7 shows a configuration of a line buffer for realizing such a circuit. As shown in FIG. 7, a method of performing a delay process with n pixels less than one line by using the read address signal obtained by adding n to the read address signal in one clock is considered. In FIG. 7, 71 is a counter for generating an address signal for the memory, 72 is an adder for adding n to the counter output, 73 is a selector, which selects the addition result during a read cycle, and outputs the output of the counter 71 during a write cycle. Select a result. Reference numeral 74 denotes an RA having a capacity capable of storing one line of an image data sequence.
M (random access memory), 75 is a three-state buffer for controlling input data in a write cycle, and 76 is a flip-flop for strobeing read data output from the SRAM in a read cycle. FIG. 8 shows a timing chart when n = 2. Input data is input line by line in synchronization with the image clock (CLK) and the line synchronization signal (LSYN). The counter operates in synchronization with the CLK using the line synchronization signal as a count operation enable signal. Input data is output on a data bus by a write signal WR,
Simultaneously written to memory. As the counter output, the addition output from the adder 72 is selected in the read cycle by the selection signal R / W, and the counter 71 is selected in the write cycle.
Output from is selected. The data written in the memory is stored in the RD using the adder output as an address during the next line processing.
The signal is read out and strobed into a flip-flop. By sequentially performing the above processing on each line, an input signal delayed by two pixels from one line can be obtained as output data.

However, in this method, the address output is delayed by the selector, and furthermore, the addition processing of the address signal must be performed within one clock. For example, when processing an image of A3 size and 400 DPI, the address width is 13 bits. In the line buffer processing with many (necessary) operations, there is a problem that the processing of the adder takes time, the output of the address is delayed, and the operation speed is reduced.

As a second method, as shown in FIG. 9, the result of delaying the counter output by n clocks by flip-flop and the counter output are respectively written in the write address,
A method of selecting a read address can be considered. FIG.
In the figure, 91 is a counter for generating an address signal for the memory, 92 is n flip-flops for delaying the counter output by n clocks, 93 is a selector, which selects the addition result in a read cycle, and outputs the counter output result in a write cycle. select. Reference numeral 94 denotes a RAM (random access memory) having a capacity capable of storing one line of an image data string, 95 a three-state buffer for controlling input data in a write cycle, and 96 an output from the SRAM in a read cycle. This is a flip-flop that strobes the read data obtained. FIG. 10 shows a timing chart when n = 2. Input data is input line by line in synchronization with the image clock (CLK) and the line synchronization signal (LSYN). The counter operates in synchronization with the CLK using the line synchronization signal as a count operation enable signal. The input data is output on the data bus by the write signal WR and is simultaneously written to the memory. The counter output is the selection signal R /
W selects a result delayed by n clocks in a write cycle and a counter output in a read cycle. The data written in the memory is read out by the RD signal at the time of the next line processing and is strobed to the flip-flop. By sequentially performing the above processing on each line, an input signal delayed by two pixels from one line can be obtained as output data.

However, also in this case, there is a problem that the address output is delayed by the selector and the operating speed is reduced, and the number of registers for delaying the address increases as n increases, and the circuit scale increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has no reduction in operation speed, and furthermore, suppresses an increase in circuit scale and performs a line buffering process for delaying data of n pixels less than one line. It is intended to provide a circuit.

[0010]

In order to achieve the above object, a line buffering processing circuit according to the present invention is a line buffering processing circuit for delaying a raster-scanned serial image data sequence by n pixels less than one line. , Holds input image data temporarily and writes to memory
A buffer that outputs image data on a data bus in accordance with a signal, a counter that can set an initial value that outputs an address signal, and an adder that adds the value n to an output value from the counter. A first register that strobes the addition result from the adder with a line synchronization signal, and an address signal from the counter from the buffer.
Writing and writing of the image data output onto the data bus
A random access memory for controlling reading of the written image data;
A second register that strobes the output data of the memory; the counter has a register value strobed in the first register set as a counter initial value for each line synchronization signal; It operates in synchronization with an input clock to control writing of image data to the random access memory and reading addresses of image data from the random access memory, and the counter further controls the random access memory.
For writing one line of image data to access memory
After outputting the address signal of the random access
・ Read out one line of image data written in the memory
For this reason, the write address signal is more
It is characterized in that an address signal having a dress value larger by n is output .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing one embodiment of a line buffering processing circuit according to the present invention. This line buffering processing circuit is applied to the line buffer 143 of FIG. An adder 11 adds n to the counter output. A flip-flop 12 strobes the addition result at the falling edge of the line synchronization signal. 1
Reference numeral 3 denotes a counter which operates in synchronization with the image clock using the strobe result as an initial value. Reference numeral 14 denotes a RAM having a capacity capable of storing one line of an image data sequence.
(Random access memory), 15 is a three-state memory for controlling input data during a write cycle.
A buffer 16 is a flip-flop that strobes read data output from the SRAM during a read cycle.

Next, the operation of this embodiment will be described with reference to FIG. The image data is, as described above, an image synchronization signal (C
LK) and a line synchronization signal (LSYN). Here, a case where the number of pixels in one line is 7 will be described for the sake of explanation. Counter 1
Numeral 3 designates LSYN as a count enable signal and an initial value load signal, thereby setting the output of the flip-flop 12 to an initial value in a period where LSYN is invalid, and initializing the set value in a valid period. Count up as a value. If n = 2 and the flip-flop output of the first line is 0, the adder outputs 2 during the line. The flip-flop 12 strobes the adder output at the falling edge of LSYN, and the counter is set to an initial value = 2. At the time of processing the second line, the counter counts up as an initial value of 2 and operates similarly with an initial value of 4 on the third line. Hereinafter, the counter operates with a value obtained by accumulating 2 in line units as an initial value. The input data is the write signal WR
, And at the same time, is written into the memory using the counter output as an address. The data written in the memory is read out by the RD signal at the time of the next line processing and is strobed to the flip-flop 16. Since the address at the time of the next line processing is advanced by two clocks, the data written in the previous line is read out two pixels earlier, that is, a delay processing that is two pixels less than one line is performed.

According to the embodiment of the present invention, since the counter output is directly connected to the memory without passing through the selector, the memory is accessed at the same operation speed as the one-line delay line buffering circuit shown in FIG. Things are possible. Even when n is a large value, the circuit scale does not increase only by changing the added value.

[Other Embodiments] In the above-described embodiment, the case where one memory is used and the read operation and the write operation are executed by time division has been described. The present invention is not limited to this, and can be implemented in a so-called double-buffer configuration in which two memories are used and a read operation and a write operation are performed simultaneously for the purpose of high-speed operation. FIG. 12 shows an embodiment of the double buffer configuration. In FIG. 12, reference numeral 121 denotes an adder which adds n to the counter output. A flip-flop 122 strobes the addition result at the falling edge of the line synchronization signal. A counter 123 operates in synchronization with the image clock using the strobe result as an initial value. Reference numerals 124 and 125 denote RAMs (random access memories) each having a capacity capable of storing one line of image data strings, 126 and 127 three-state buffers for controlling input data during a run cycle, and 128 read data. Is selected from the outputs of the memory 1 and the memory 2, and 129 is a flip-flop that strobes the selected read data.

Next, the operation of this embodiment will be described with reference to FIG. The image data is, as described above, an image synchronization signal (C
LK) and a line synchronization signal (LSYN). Here, a case where the number of pixels in one line is 7 will be described for the sake of explanation. Counter 1
Numeral 21 gives LSYN as a count enable signal and an initial value load signal, and counts up the output of the flip-flop 122 as an initial value while LSYN is valid. If n = 2 and the flip-flop output of the first line is 0, the adder outputs 2 during the line. The flip-flop 122 strobes the output of the adder at the falling edge of LSYN, and the counter 123 counts up the processing of the second line as an initial value of 2. As described above, the counter operates with the value obtained by accumulating n in units of lines as the initial value. Input data is W when processing the first line
Writing to the memory 1 is performed by the R1 signal. During the second line processing, the data written from the memory 1 is read by the OE1. The selector 128 selects the memory output in the read state. That is, when OE1 is active, the output of the memory 1 is selected. Since the address at the time of processing the second line is advanced by two clocks by the processing of the address initial value, the data written in the first line is read two pixels earlier, that is, a delay of two pixels less than the first line. Processing is performed. The input data of the second line is written into the memory 2 by the WR2 signal simultaneously with the reading from the memory 1. With the above processing, the delay processing with n pixels less than one line can be realized with the same configuration in the processing of the double buffer configuration.

As in the previous embodiment, in this embodiment, since the counter output is directly connected to the memory without passing through the selector, the memory can be accessed at the same operation speed as the conventional one-line delay line buffer. It is.

As described above, when the present invention is applied to a double buffer circuit configured for high-speed operation, the effect becomes more effective.

Also, by using the line buffering processing circuit shown in FIGS. 1 and 12 in the circuit of the error diffusion method shown in FIG. 14, high-quality images can be obtained for both character and halftone images. Images can be obtained at high speed.

[0020]

As described above, according to the present invention, the operation speed is not reduced, and further, the circuit scale is increased, and
It becomes possible to realize a line buffering processing circuit that delays data of n pixels less than the line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a line buffering processing circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a matrix of a smoothing filter.

FIG. 3 is a diagram showing a configuration of a smoothing filter.

FIG. 4 is a diagram illustrating an example of a line buffering processing circuit that performs one-line delay processing.

FIG. 5 is a diagram showing the timing of an image signal.

FIG. 6 is a diagram showing a timing chart of a line buffering processing circuit that performs one-line delay processing.

FIG. 7 is a diagram showing a first example of a conventional line buffering processing circuit having n pixels less than one line.

FIG. 8 is a diagram showing a timing chart of a first line buffering processing circuit having n pixels less than one conventional line.

FIG. 9 is a diagram showing a second example of a conventional line buffering processing circuit having n pixels less than one line.

FIG. 10 is a diagram showing a timing chart of a second line buffering processing circuit having n pixels less than one conventional line.

FIG. 11 is a diagram showing a timing chart of a first line buffering processing circuit having n pixels less than one line according to the embodiment.

FIG. 12 is a diagram showing a second embodiment of the line buffering processing circuit according to the present embodiment, which has n pixels less than one line.

FIG. 13 is a diagram showing a timing chart of a second line buffering processing circuit having n pixels less than one line according to the embodiment.

FIG. 14 is a diagram showing a configuration example of a binarization processing circuit using an error diffusion method that requires a delay process that is n pixels less than one line.

FIG. 15 is a diagram showing an example of a diffusion matrix of the error diffusion method.

[Explanation of symbols]

 Reference Signs List 11 adder 12 flip-flop 13 counter 14 memory 15 three-state buffer 16 flip-flop

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 G06F 12/02 550

Claims (1)

(57) [Claims] 1. A line buffering processing circuit for delaying a raster-scanned serial image data string by n pixels less than one line, temporarily holding input image data and applying a write signal to a memory
A buffer for outputting image data to a data bus in response to the signal; a counter capable of setting an initial value for outputting an address signal; an adder for adding the value n to an output value from the counter; and an addition from the adder A first register for strobed the result by a line synchronization signal; and an buffer for storing an address signal from the counter.
And a random access memory for controlling writing and reading of written image data output to the data bus from the memory, and a second register for strobed the output data of the random access memory. In the counter, a register value strobed in the first register is set as a counter initial value for each line synchronization signal, and the counter operates in synchronization with an input clock of image data, and the random access and writing of the image data to the memory and the controls the reading address of the image data from the random access memory, further wherein the counter, the random access
Address for writing one line of image data to memory
After outputting the address signal, the random access
To read one line of image data written in
The address is more than the address signal for writing.
A line buffering processing circuit for outputting an address signal having a value larger by n .