JPH0527151B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing apparatus such as an image editing apparatus that reduces or enlarges binary dot matrix input image data and converts pixel density.

[Prior art]

An image editing device is a device that reduces or enlarges input image data;
When creating a workstation by combining CRT displays, a pixel density conversion device was required in addition to the image editing device (see Figure 1). In other words, although recent image editing devices have become capable of processing high-density data due to demands for improved image quality and increased capacity of semiconductor memory, the density of CRT displays is only about 4 dots/mm or 6 dots/mm. This is because it is a limit. The workstation shown in FIG. 1 is composed of a central processing unit (CPU) 1 connected to a common bus 6, an image memory 2, an enlargement/reduction device 3, a CRT density conversion device 4, and a CRT display 5. .

Techniques related to the above image processing include a density conversion device using a logical sum (see Japanese Patent Laid-Open No. 53-115124), and an enlargement/reduction device using thinning and duplication (see Japanese Patent Laid-Open No. 57-57080). However, even if these are simply combined, one device can reduce and
It is difficult to create a device that can satisfy the three functions of magnification and density conversion, and in the end the configuration as shown in FIG. 1 is inevitable. This is because when the conversion ratio is large, such as when converting from 12 dots/mm to 4 dots/mm, a method that simply thins out the dots will have the disadvantage of deteriorating image quality (e.g., disappearance of thin lines). This is because an enlargement/reduction device for image editing cannot be simply used for density conversion for CRT.

As described above, in the past, it was necessary to use independent devices as shown in FIG. 1, and it was impossible to realize the above three functions at low cost with a single device. Moreover, the expansion and
All reduction devices are expensive because they require high-speed processing.

〔the purpose〕

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an image processing device which has the functions of enlarging/reducing image data and converting pixel density in a single device, and which can be realized at low cost.

〔composition〕

The present invention will be described below based on illustrated embodiments.

FIG. 2 shows an outline of a workstation to which the present invention is applied. The same parts as in FIG. 1 are given the same reference numerals. In FIG. 2, numeral 7 indicates an enlargement/reduction/density conversion device according to the present invention. The detailed configuration of this device 7 is shown in FIG.

In FIG. 3, the basic configuration is as follows. Image data Di to be processed is stored in a first register (hereinafter referred to as input buffer register) 8 from the CPU 1 via a bus 6. The stored data is transmitted to the first clock pulse generating means (hereinafter referred to as master clock generating circuit) 9 and the second clock pulse generating means (hereinafter referred to as thinning clock pulse generating circuit).
Reading or writing is controlled by a first clock pulse (hereinafter referred to as master clock pulse) CKm and a second clock pulse (hereinafter referred to as clock inhibit signal) CKi from No. 10. Clock inhibit signal CKi
is magnification data indicating the ratio of enlargement/reduction/pixel density
It has a period thinned out by a specific number of pulses from master clock pulse CKm according to Dm.
The stored data from the input buffer register 8 is transferred bit by bit to a second register (hereinafter referred to as an output buffer register) 11 and written therein. When written to the output buffer register 11, the image is enlarged, reduced, and converted into pixel density by a counter and a logic gate, which will be described later.

The following detailed configuration and its operation will be explained.

Reduction When performing reduction, the “edit” input Edt of the OR gate 12 is set to ethics “1”, the “expansion” input Exp of the NAND gate 13 is set to “0”, and the “reduction” input Rdt of the NAND gate 14 is set to “1”. ”. Then, the output of OR gate 12 becomes "1", and D latch circuit 1
Since the CLR input of the D latch circuit 15 becomes "1", the Q output of the D latch circuit 15 always becomes "0". Therefore,
The B input of the OR gate 16 is always "0", and the data stored in the input buffer 8 is directly transferred to the output buffer 11 and stored therein. At this time,
Since the output of NAND gate 13 is "1", the output of AND gate 17 is synchronized with master clock CKm. Furthermore, since the output of the NAND gate 14 becomes the clock inhibit signal CKi, the output of the AND gate 18 is input to the output buffer address counter 19 as a clock thinned out from the master clock CKm according to the reduction magnification data Dm. . This clock causes input buffer registers 8 to 1 to
Of the image data output bit by bit, the data when the clock inhibit signal CKi is output is not input to the output buffer register 11, and the image data when it is not input is thinned out. In this way, one line of image data stored in the input buffer register 8 is output.
Output buffer register 11 contains reduction magnification data.
One line of reduced data is obtained by appropriately thinning out the image data according to Dm.

Enlargement When enlarging, the "enlargement" input Exp of the NAND gate 13 is set to "1" and the "reduction" input Rdt of the NAND gate 14 is set to "0". Then, AND
The output of gate 17 is given to input buffer address register 20 as clock inhibit signal CKi.
The output of AND gate 18 is the master clock CKm
It is given to the output buffer address register 19 as the output buffer address register 19. Then, at the time when the clock inhibit signal is output, the same data as the image data one bit before is input to the output buffer register 11 in duplicate. As a result, one line of enlarged data is obtained in the output buffer register 11. Note that the thinning ratio of the clock prohibition signal CKm follows the enlargement magnification data Dm.

Pixel Density Conversion Next, the case of performing pixel density conversion for CRT will be described. As an example, we will discuss the case of converting 12 dots/mm to 6 dots/mm. To begin with the conclusion, in this case, one pixel can be created by calculating the logical sum of adjacent vertical and horizontal 2×2 dots of the original image data.

First, one line of image data is transferred by the CPU 1 via the bus 6 and stored in the input buffer 8. And “edit” input of OR gate 12
Edt is “0”, NAND gate 13 “enlarge” input
Exp is “0”, NAND gate 14 “reduction” input
If Rdt is “1” and the first line is
“New line” input N of AND gate 21 is “1”
shall be. In addition, in this case, the clock inhibit signal CKi
is a signal obtained by dividing the master clock CKm by 1/2, and this fact is specified by the magnification data Dm. When the first dot is output from the input buffer 8, the clock inhibit signal CKi is “0”.
Since the AND gate 18 outputs the same clock pulse as the master clock CKm, the output buffer 11 inputs the data of the first dot and outputs the master clock pulse CKm to the D input of the D latch circuit 15. However, since the CLR input of the D latch circuit 15 is "1", the Q output is "0", so the output of the OR gate 16 (input to the output buffer 11) is still the data of the first dot. equal.

At the next master clock pulse CKm, the clock inhibit signal is “1”, so the output buffer 1
Address 1 is not updated. Further, since the CLR input of the D latch circuit 15 is "0", the data of the first dot is outputted to the Q output. Therefore, the output of the OR gate 16 is the first dot and the second dot.
The logical sum of the dots results in data, which is stored in the output buffer register 11. By repeating the above operation, the output buffer register 11 is finally filled with 1 with a logical sum for every 2 dots.
Data for each line will be obtained.

In the case of the second line, by setting the "new line" input N of the AND gate 21 to "0",
The data resulting from the logical sum of every two dots on the first line is sequentially output dot by dot to the Q output of the D latch circuit 15. Therefore, the data obtained by calculating the logical sum of every two dots on the second line and the logical sum of the two dots on the first line are sequentially stored in the output buffer.
After finishing line processing, 12 dots/mm to 6
Image data of the first line converted to dots/mm can be obtained. By repeating this process two lines at a time, density conversion of the entire image is completed.

In the above explanation, processing in the sub-scanning direction (vertical direction of the page), for example, processing decisions such as outputting the same line twice in the case of enlargement processing, do not need to be particularly fast, so they are not controlled by the CPU 1. Ru.

〔effect〕

As described above, according to the present invention, enlargement and
It is not necessary to combine the reduction device and the density conversion device individually, and it is possible to provide an image processing device that has a single device configuration and can perform the above three functions without impairing high speed.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an example of a workstation that combines a conventional enlargement/reduction device and a CRT density conversion device, and FIG. 2 is a schematic block diagram showing an example of a workstation using an image processing device according to the present invention. 3 are block diagrams showing an embodiment of an image processing apparatus according to the present invention. 7... Enlargement/reduction/density conversion device, 8... Input buffer register, 9... Master clock pulse generation circuit, 10... Thinning clock pulse generation circuit, 11... Output buffer register, 16...
OR gate, CKm...master clock pulse,
CKi...Clock inhibit signal, Exp...Expansion input,
Rdt...reduction input, Edt...editing input, E...
New line input.

Claims (1)

[Claims] 1. A first clock pulse generating means for generating a first clock pulse having a fixed period; and a second clock pulse generating means for generating a second clock pulse having a period thinned out by a specified number of pulses from the first clock pulse. a first register storing input image data; and a first register storing input image data;
The input image data stored in the register is 1
A second register stores output image data read out bit by bit and written in synchronization with the first or second clock pulse, and a logical sum signal of each output of the first and second registers. and an OR means for outputting data read bit by bit from the input image data stored in the first register in synchronization with the first clock pulse, and outputting the data bit by bit from the input image data stored in the first register in synchronization with the second clock 2
The input image data is reduced by writing to the register of the second clock pulse, and the data read bit by bit from the input image data stored in the first register in synchronization with the second clock pulse is read out bit by bit from the input image data stored in the first register. 1 from the input image data stored in the first register in synchronization with the first clock pulse. Data obtained by calculating the logical sum of first data read bit by bit and second data read bit by bit from the output image data stored in the second register in synchronization with the second clock pulse. The image processing apparatus is characterized in that the pixel density conversion of the input image data is performed by writing the input image data into the second register again in synchronization with the second clock pulse.