JPH0528398B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to an image memory write/read control device, and particularly to a CRT display device, which transfers image data from a linear generator (DDA) to a frame memory and writes the image data. The present invention relates to an image memory write/read control device for reading and writing to an image memory.

Prior Art FIG. 6 is a schematic block diagram of a conventional raster scan type graphic display device.
This figure is a diagram for explaining the operation of filling the frame memory 8 with data by the DDA 7 shown in FIG. 6.

First, with reference to FIGS. 6 and 7, an outline of a conventional raster scan type graphic display device and writing and reading of image data into and from a frame memory will be described. In FIG. 6, data is provided from a host computer 1 to a graphic data management section 3 via a transmission line and a host interface 2. In FIG. The graphic data management section 3 receives data from the host computer 1, arranges the data so that it can be displayed as a graphic, and stores it in a segment buffer (not shown). The data analysis unit 4 extracts the contents of the segment buffer, analyzes the information, and performs vector calculation processing based on the starting point coordinates and the ending point coordinates. The coordinate transformation clip section 5 multiplies the data by a necessary matrix when enlarging, reducing, rotating, or translating the figure. Also,
When a part of a figure on a CRT display screen is surrounded by a frame, the figure that protrudes from the frame is clipped.

When filling a figure, the DDA control filling section 6 generates line segments decomposed into inner lines from the coordinates of the vertices of each vector, and thereby obtains filling data. DDA7 is a straight line generator that generates a straight line, and DDA control filling section 6
Based on the data from , intermediate coordinates of the vector connecting the starting point and the ending point are calculated, and the calculation results are developed in the frame memory 8 to form a straight line. The frame memory 8 stores each dot on a straight line generated by the DDA 7. The data stored in the frame memory 8 is stored in the video control unit 9.
is given to , is converted into an analog signal by a D/A converter, and based on a color conversion table,
The signal is converted into a video signal and provided to the color monitor 10. As a result, the color monitor 10 has
Graphics based on data output from the host computer 1 are displayed.

Problems to be Solved by the Invention By the way, when filling in a figure based on the data from the DDA control filling unit 6,
When the DDA 7 develops image data in the frame memory 8, as shown in FIG. In this case, four dots are filled in every memory cycle of the frame memory 8. Generally, the memory cycle of the frame memory 8 is slower than the speed of the DDA 7.
Therefore, DDA7 develops data alternately to DDA buffers 31 and 32, and
The above-mentioned speed difference is alleviated by expanding data into the frame memory 8 every 2 seconds. However, if you want to fill the shape even faster,
For each multiple dot to increase the speed of DDA7
One possible method is to expand the data of the DDA 7, but no matter how fast the data is written to the DDA buffers 31 and 32, while the data is being expanded to the frame memory 8, the DDA 7 cannot output the next data. You will not be able to do so and will have to wait for that amount of time. For this reason, there is a drawback that it takes a long time to develop data in the frame memory 8.

Means for Solving the Problems Therefore, the main purpose of this invention is to
An object of the present invention is to provide an image memory write/read control device which can reduce waiting time and develop fill-in image data in a frame memory at high speed.

This invention includes a linear generator that outputs image data along with its address signal for each predetermined number of dots, a plurality of temporary storage means that temporarily stores the image data and its address signal sequentially output from the linear generator, and a plurality of It is composed of a block memory provided corresponding to each temporary storage means.

Operation In this invention, the linear generator sequentially stores image data and its address signal in each temporary storage means for each predetermined number of dots, and each block memory stores the image data and its address signal in each temporary storage means, respectively. The corresponding image data is stored in the designated storage area in a predetermined memory cycle.
Therefore, when the linear generator outputs the next image data, each block memory has finished writing the image data, so the linear generator outputs the next image data. You no longer have to wait until the end of the day, and you can eliminate waiting time.

Embodiments The present invention will be explained in more detail below along with embodiments shown in the drawings.

FIG. 1 is a schematic block diagram of one embodiment of the present invention. First, the configuration of an embodiment of the present invention will be described with reference to FIG. In FIG. 1, the frame memory consists of four A block memories 2
1 to D block memory 24. Then, an address/data latch 2 is provided corresponding to each of the block memories 21 to 24.
5 to 28 are provided. These addresses/
Data latches 25 to 28 are connected to address bus 29.
and DDA buffer 3 via data bus 30.
Connected to 1 and 32. DDA Batsuhua 31,3
2 is included in DDA7 shown in Figure 3 above,
It stores the filling data output from the DDA filling section 6 and its address signal. two
DDA buffers 31 and 32 are provided by
This is to perform high-speed processing by writing the data from the DDA filling section 6 into one side and simultaneously reading out the data written into the other side. Address bus 29 has
ROM38 is connected. This ROM 38 specifies any one of the A block memory 21 to the D block memory 24.

The image data written in the four memory blocks 21 to 24 is read out by an address control circuit 35 and a read/write control circuit 36. For this purpose, the block memories 21 to 24 are connected to an address control circuit 35 via an address bus 33 and a data bus 34, and the read/write control circuit 36 is connected to the block memories 21 to 24 via a control line 37. Ru.

FIGS. 2 and 3 are diagrams for explaining the operation of an embodiment of the present invention, and FIG. 4 is a diagram showing the structure of an address signal. FIG. 5 is a diagram showing another example of filling.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 1 to 4. First, the operation of generating an arbitrary straight line vector will be explained. DDA buffers 31 and 32 output address signals along with image data. As shown in FIGS. 4a and 4b, the address signal includes X coordinate data and Y coordinate data in order to designate a predetermined address in the A block memory 21 to D block memory 24. The X coordinate data includes the X of A block memory 21 to D block memory 24.
It includes a block designation bit for designating a block in the direction, and an intra-block designation bit for designating the X direction of the 4×4 storage area in each block. Similarly, the Y coordinate data includes a block specification bit for specifying a block in the Y direction,
It includes an intra-block specification bit for specifying the Y direction of the 4×4 storage area within the block.

To explain more specifically, when writing image data as shown in FIG. 2 into the A block memory 21 to the D block memory 24, first
Buffer 31 designates A block memory 21 and outputs an address signal for writing four dots in address A1 shown in FIG. 2 and image data representing the four dots. ROM38 is
Based on the address signal output from DDA buffer 31, A block memory 21 and address/data latch 25 are selected. Then, the address/data latch 25 temporarily stores the image data and address signal output from the DDA buffer 31. At this time, the time required to output the image data and address signal from the DDA buffer 31 is, for example, 60 nsec.

Subsequently, the DDA buffer 32 outputs the image data and an address signal in order to write the image data to the address D2 shown in FIG. ROM3
8 designates the D block memory 24 based on the address signal output from the DDA buffer 32.

On the other hand, the address/data latch 25 specifies the address A1 in the A block memory 21 and writes the image data based on the fact that the image data and address signal to be written to the address A1 are temporarily stored. In this case, a memory cycle of 240 nsec is required to write 4×4 image data. Also,
To finish outputting 4 dots of image data to be written to address D2 to the DDA buffer 32, the DDA 7 requires 60 ns to output 1 dot, so it takes 240 ns to output all 4 dots of image data. It takes. Therefore, DDA7 transfers the image data at address D2 to DDA buffer 32.
When the output is finished, the A block memory 21
This means that the writing of image data of 4 dots at address A1 has definitely been completed.

After the DDA buffer 32 outputs the image data at address D2, the DDA buffer 31 outputs the image data at address A2. Then, ROM3
8 specifies the A block memory 21 again, and the corresponding address/data latch 25 temporarily stores the image data and the address signal of address A2. Then, based on the address signal, one dot of image data is written to address A2.

As mentioned above, for example, the A block memory 21
After writing the image data to the DDA, 4-dot image data is written to either the other B block memory 22 or the D block memory 24, and then the image data is written to the A block memory 21 again. The buffers 31 and 32 can output image data at the DDA speed without waiting for the end of writing image data to the respective addresses of the A block memory 21 to the D block memory 24.

Next, filling of the figure expanded by the DDA control filling section 6 will be explained. DDA
The buffer 31 is 16 at address A1 shown in Figure 3b.
The data of all the dots and their address signals are output to the address/data latch 25. The time required for the data and address signal to be output from the DDA buffer 31 to the address/data latch 25 is, for example, 60 nsec. Subsequently, the DDA buffer 32 outputs all 16 dot data of address B1 and its address signal to the address/data latch 26. At this time, the DDA buffer 31 has the third buffer from the DDA7 shown in FIG.
Data and address signals for all 16 dots of address C1 shown in FIG. b are written. The time required for this is also 60 nsec, for example. And D.D.A.
Buffer 31 outputs all 16 dot data and address signals of address C1 to address/data latch 27. At this time, the address D1 output from the DDA7 is stored in the DDA buffer 32.
All 16 dots of data and address signals are written. The time required for this is, for example, 60nsec
It is. In this way, the addresses A1 to D1 output from the DDA buffers 31 and 32
data and address signals are temporarily stored in address data latches 25-28, respectively.
Note that the time required for the DDA buffers 31 and 32 to output the data and address signals of each address A1 to D1 is 60 nsec.

The address data latch 25 specifies a predetermined address in the A block memory 21 based on the temporarily stored data and the address signal, and simultaneously writes the data. The image data indicated by address A1 is composed of 4 dots x 4 dots, and a memory cycle of 240 nsec is required to write the data to the A block memory 21 indicated by address A1. Therefore, when the data and address signal of address D1 are output from the data buffer 32, the address A of the A block memory 21 is
This means that writing of data to 1 has been completed.
After outputting the data at address D1 and the address signal, the data at address A2 is output from the DDA buffer 31, or at this time, since the expansion of the data to address A1 of the A block memory 21 has been completed, the DDA7 is Next address A2
There is no need to wait for the data to be output,
You can eliminate waiting time.

Similarly, after 240 nsec after the DDA buffer 32 outputs the data at address B1 of the B block memory 22, the B block memory 22 has finished expanding the data to address B1, so the DDA buffer 32 is forced to wait. without getting caught,
Data can be immediately output to address B2 of B block memory 22. Thereafter, in the same manner, data is output from the DDA buffers 31 and 32 in the order of address C2 of the C block memory 23, address D2 of the D block memory 24, and address A3 of the A block memory 21, and expanded to each block memory.

As described above, fill-in image data and address signals for each 4×4 dot are temporarily stored in the address/data latches 25 to 28 in the A-block memory 21 to D-block memory 24, which are made up of frame memories, and each block memory is By expanding the data to predetermined addresses 21 to 24, the DDA 6 is not affected by the memory cycles of the A block memories 21 to D block memories 24, and can expand filled image data without waiting time. That is, if the memory cycle of the block memory is smaller than the DDA speed x the number of block memories, the DDA 6 can develop the filled image data into each block memory without waiting time.

In the above explanation, for example, for 4×4 DDA buffers 31 and 32, all 16 dots are A at once.
Block memory 21 to D block memory 24
Although the case of writing in the area has been described, it is not necessarily necessary, and filling may be performed in a dot configuration as shown in FIG. 5, for example. That is,
As shown in FIG. 5, the dots may be filled in 8 dots at a time or 4 dots at a time.

Effects of the Invention As described above, according to the present invention, a plurality of block memories and a temporary storage means are provided corresponding to each block memory, and image data is sequentially stored in address signals for each predetermined number of dots from a linear generator. Each block memory stores the corresponding image data in a storage area designated by the address signal stored in the corresponding temporary storage means in a predetermined memory cycle. Therefore, when the linear generator outputs the next image data, each block memory has finished writing data, so the image data can be expanded to each block memory without waiting time for DDA. Therefore, DDA can expand image data into block memory at high speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of one embodiment of the present invention. FIGS. 2 and 3 are diagrams for explaining the operation of an embodiment of the present invention. Figure 4 shows
FIG. 3 is a diagram for explaining address signals. FIG. 5 is a diagram showing another example of filling in figures. FIG. 6 is a schematic block diagram of a conventional raster scan type graphic display device. FIG. 7 is a diagram for explaining the operation of filling the frame memory with data by the DDA shown in FIG. 6. In the figure, 6 is the DDA control filling part, 7
is DDA, 21 to 24 are block memories, 2
5 to 28 are address/data latches, 29,
33 is an address bus, 30 and 34 are data buses,
31 and 32 are DDA buffers, 35 is an address control circuit, 36 is a read/write control circuit, and 38 is a ROM.
shows.

Claims (1)

[Claims] 1. Writing and reading image data in an image memory in order to display an image in an area that can be displayed as a dot in a first direction and a second direction perpendicular to the first direction. An image memory write/read control device for controlling an image memory, comprising: a linear generator that outputs the image data along with its address signal for each predetermined number of dots; a plurality of temporary storage means for temporarily storing; and a plurality of temporary storage means provided corresponding to the plurality of temporary storage means;
When the storage area corresponding to the displayable area is divided into a plurality of blocks, each block memory includes a divided storage area, and the linear generator converts the image data and its address signal into the predetermined dots. The image data is sequentially stored in the plurality of temporary storage means for each block memory, and each block memory stores the corresponding image data in a storage area designated by an address signal stored in the corresponding temporary storage means. Image memory read/write control device.