JPH0465582B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a scaling circuit for digital binary image data.

Prior Art When an operator edits character information input from a keyboard or image data from a scanner, etc. to create a single piece of text, it may be necessary to enlarge or reduce the image data for overall balance, etc. There is.

Image data can be enlarged or reduced by using software to enlarge or reduce the contents of a memory for storing image data, but this method is very time consuming. Therefore, efforts are being made to shorten the processing time for enlarging and reducing by implementing the enlarging and reducing functions using hardware.

For example, when enlarging the image twice, send the raw data of a digital binary image as shown in Figure 1a to the scaling circuit, sample the data from the same pixel in one line in the main scanning direction twice, and In the scanning direction, by outputting the same line twice, pixel data enlarged twice as shown in FIG. 2 is obtained. In addition, when reducing the size to 1/2, send the digital binary image data as shown in Figure 1a to the scaling circuit, sample the data of one line in the main scanning direction every other pixel, and in the sub-scanning direction, The above operation is executed every other line, and data on other lines is discarded.
The scaling process is performed in this way, but currently,
As resolution increases, the amount of data tends to increase, and high-speed ICs are used to deal with delays in processing time due to the increase in the amount of data. However, there are limits to this as well.

Purpose It is an object of the present invention to provide an image data scaling circuit that improves the drawbacks of the prior art as described above and performs high-speed scaling processing using the characteristics of image data.

Configuration The configuration of the present invention will be explained below using one example.

FIG. 2 is a block diagram of an imaging system having a variable magnification circuit.

Image data as a black and white binary image enters the system via a bus 8 from an input device 5 such as a scanner. The image data is developed on a bitmap memory 3 for image data. When editing this image data and other files (consisting of graphic data, character code data, etc.), if the image data needs to be scaled (enlarged or reduced), the scale can be changed using the scale circuit. However, the editing result including the scaling process is outputted to the display 4 and the output device 6 such as a printer. These series of processes are performed by CPU 1 using system memory 2 to
Control via.

Next, normal scaling processing will be explained.

FIG. 3 is a diagram showing an example of a variable magnification circuit to which the present invention is applied. 8 is a bus in the system, 9 is an input data line buffer, 10 is a controller, 1
1 is an output data line buffer. here,
The number of bits in the input data line buffer 9 and output data line buffer 11 for one line in the main scanning direction of the image data sent into the system corresponds to the number of bits in the bus 8 or an integral multiple thereof. There is.

First, the CPU 1 notifies the controller 10 of the scaling factor and the amount of data for one line in the main scanning direction after scaling. Then, when the image data is sent from the system to the variable magnification circuit, the controller 1
0 controls the address and read/write of the input data line buffer 9 and the output data line buffer 11 in accordance with the above magnification ratio.

FIG. 4 shows the control timing. FIG. 4a shows the control timing when enlarging the image twice. That is, when writing the image data (raw data) sent to the input data line buffer 9 to the output data line buffer 11, one of the input data line buffers 9
Data line buffer 1 outputs data for bits
By writing over two bits of 1, the raw data of the input data line buffer 9 is sampled twice, thereby expanding it twice in the main scanning direction. Enlargement in the sub-scanning direction is performed by writing the enlarged data into the output data line buffer 11 twice.

FIG. 4b shows the control timing when reducing the size to 1/2. In this case, by writing every other bit of data in the input data line buffer 9 to the output data line buffer 11 and sampling the data in the input data line buffer 9 every other bit, the data can be halved in the main scanning direction. Reduce to.
For reduction in the sub-scanning direction, raw data on the second line in the main scanning direction is discarded, and a similar reduction operation is performed on the raw data on the third line.

By the way, one line of image data in the main scanning direction has a considerable amount of uniform level data due to its nature, and the smaller the variable magnification block, the more data with uniform level. On the other hand, for uniform level data, the pattern does not change even after scaling. Therefore, for uniform-level image data, the scaling processing time can be shortened by eliminating scaling processing and immediately returning the data to the system.

FIG. 5 is a diagram showing an example of a uniform level detection circuit. Parallel input data according to the number of bits on bus 8 (“1” indicates black, “0” indicates white)
is input to the J input of the flip-flop 13 via the OR circuit 12, and the flip-flop 13 is strobed with a strobe pulse STB.The Q output of the flip-flop 13 can be used to determine whether the input data is at a uniform level of white ("0"). That is, if the Q output of the flip-flop 13 is "0", it means that all white is at a uniform level, and if it is "1", it is not a white uniform level. Similarly, the uniform level of black (“1”) also applies to parallel input data.
Input to NAND circuit 14, flip-flop 1
5's J input is strobed with a strobe pulse STB, and if the Q output is "0", it can be determined that all black is present.

Once the uniform level has been determined in this way, the controller 10 need not perform any scaling processing, and only need to return data at the same level as the input data to the system in an amount corresponding to the scaling factor.

FIG. 6 is a block diagram of an image data scaling circuit according to an embodiment of the present invention, and FIG. 7 is a flowchart thereof.

The difference from the conventional technology is the uniform level detection circuit (all white detection section: OR circuit 12 and flip-flop 13, all black detection section: NAND circuit 14 and flip-flop 15), and all white generation circuit 1.
6 and an all-black generating circuit 17 are provided.

Below, the image data scaling process by this circuit will be explained in the sixth section.
This will be explained based on FIG. 7 and FIG.

First, the controller 10 sends a signal to clear the flip-flops 13 and 15 for uniform level detection.
Clear by CLR. Eventually, the CPU 1 notifies the controller 10 of the magnification ratio 701.
The CPU 1 also notifies the controller 10 of the amount of data for one line in the main scanning direction according to the magnification ratio (702).

Next, data for one line in the main scanning direction is sent to the input data line buffer 9 (703). Before actual scaling processing, in order to determine whether the image data is uniform or not, the outputs of the OR circuit 12 and the NAND circuit 14 are input to flip-flops 13 and 15, respectively, using a strobe pulse STB (704). Based on the output Q of the flip-flop 13 and the flip-flop 15, it is determined whether one line of data in the main scanning direction sent to the input data line buffer 9 is uniform or not.
5. That is, if the output Q of the flip-flop 13 is "0", it means that the above data is all white, and the output Q of the flip-flop 15 is "0".
If so, it indicates that the color is all black. If the determination result is all white or all black, the controller 10 notifies the CPU 1 via the bus 8 of the end of the scaling process for one line, and also sends the all white generator 16 or The all-black generator 17 generates all-white or all-black data in an amount corresponding to the magnification ratio, and returns this to the system in synchronization with the reading timing of the CPU 1 (706).

As a result of the determination, if the data for one line in the main scanning direction is not at a uniform level, the controller 10 performs normal scaling processing on the input data line buffer 9 and the output data line buffer 11 (707). Data is stored in the output data line buffer 11. After that, the controller 10 notifies the CPU 1 that the scaling process for one line has been completed.
Selection 1 returns the variable magnification data to the system in accordance with the read timing of CPU 1 708 .

The above operations are performed for each line selected in accordance with the magnification ratio.

In the above explanation, uniform level detection was performed for each line in the main scanning direction, but it is also possible to divide the variable magnification area into multiple blocks and perform uniform level detection on all data in that area at once. It is possible.

Effects As explained above, according to the present invention, the image data sent to the scaling circuit includes a lot of uniform level image data, and the pattern of this uniform level image data remains unchanged before and after scaling. Taking advantage of the characteristic that only the amount of data changes after scaling, it is determined whether the scaled data is at a uniform level when it is sent to the scaling circuit, and if it is at a uniform level, it is By omitting the magnification process and immediately returning uniform level data to the system in an amount corresponding to the magnification ratio, it is possible to speed up the magnification process.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an image of image data scaling processing, FIG. 2 is a block diagram of an image system to which the present invention is applied, and FIG. 3 is a diagram showing an example of a scaling circuit to which the present invention is applied. FIG. 4 is a diagram showing the control timing of FIG. 3, FIG. 5 is a diagram showing a uniform level detection circuit according to an embodiment of the present invention, and FIG. 6 is a diagram showing an entire block diagram of a variable power circuit according to an embodiment of the present invention. 7 is a flowchart of FIG. 6. 8...Bus, 9...Input data line buffer, 1
0... Controller, 11... Output data line buffer, 12... OR circuit, 13, 15... Flip-flop, 14... NAND circuit.

Claims (1)

[Claims] 1. In a scaling circuit that receives scaling factor information and data amount information after scaling, and performs scaling processing on digital binary image data based on these scaling factor information and data amount information, the digital binary image data means for detecting whether or not is at a uniform level; and when the detection result by the means is at a uniform level, the scaling process by the scaling circuit is omitted, and the data at the level is immediately converted into a scaling result by the amount of data. A variable magnification circuit characterized in that it is provided with means for outputting.