KR100438161B1 - scanning apparatus - Google Patents

Abstract

A scanning device is disclosed. The clock generator generates a trigger signal and a counter signal. The scanning unit reads the image of the original at a predetermined resolution in synchronization with the trigger signal and the counter signal and outputs the image data. The mode selector sets a resolution reduction rate for reducing image data of the original input from the scanning unit, and outputs a resolution reduction ratio setting signal. The CPU receives the resolution reduction ratio setting signal from the mode selection unit, outputs the resolution control data corresponding thereto, and outputs a direct memory access recognition (DMA_ACK) signal in response to the input direct memory access request (DMA_REQ) signal. The resolution controller stores the input resolution control data and outputs a direct memory access request (DMA_REQ) signal to the CPU during the scanning operation of the scan unit. The buffer selectively stores the image data input from the scanning unit in accordance with the direct memory access request (DMA_REQ) signal and the direct memory access recognition (DMA_ACK) signal, and outputs it temporarily. According to such a scanning device, the resolution of the image data can be controlled using only the general-purpose storage element and the logic circuit element without using the dedicated image processor.

Description

Scanning apparatus

The present invention relates to a scanning device, and more particularly, in a general scanner system, the image data of a constant resolution inputted from a scanning unit can be obtained by using a general storage device and a simple logic device without using an exclusive image processor (ASIC). It relates to a scanning device that can be controlled.

The scanner device is widely used in office equipment for various purposes such as copying machines, fax machines, scanner systems, etc., and in particular, all of these functions are essential for a composite device in which multiple functions are combined.

A resolution control apparatus for image data according to the prior art will be briefly described with reference to FIG.

1 is a block diagram schematically showing the configuration of an apparatus for controlling resolution of image data according to the prior art.

As shown, the central processing unit 110 controls all the components as a whole, and the clock generator 100 controls various clock signals according to the control signals of the controller 110 and the image of the CDC 102. Output to processor 112. The CD 102 outputs an analog image signal obtained by reading the original image in synchronization with the input clock signal to the ADC 104. The ADC 104 converts an input analog image signal into a digital signal and outputs it to the image processor 112. The motor driver 108 drives the step motor 106 according to the control signal of the central processing unit. The step motor 106 feeds the document at low speed when scanning at high resolution according to the control signal of the central processing unit 110, and feeds the document at high speed when scanning at low resolution. The image processor 112 outputs a direct memory access request (DMA_REQ) signal to the central processing unit 110 in synchronization with the clock signal input from the clock generation unit 100, and in response thereto, inputs from the central processing unit 110. The image data input from the ADC 104 is input in synchronization with the direct memory access recognition (DMA_ACK) signal, which is processed by the enlargement and reduction and output. The page memory 114 stores image data output from the image processor 112 and outputs the image data to the outside according to a control signal of the central processing unit 110.

As described above, the resolution control apparatus of the image data according to the prior art requires a separate dedicated image processor (ASIC), it is not easy to change the design, and requires a step motor with a large operating area to change the vertical resolution. There was a problem.

In order to solve the above problems, an object of the present invention is to provide a scanning apparatus that can control the resolution of image data by using a step motor having a narrow operating area and using only general-purpose storage elements and logic elements.

1 is a block diagram schematically showing the configuration of a scanning apparatus according to the prior art,

2 is a block diagram schematically showing the configuration of a scanning device according to the present invention;

3 is a block diagram illustrating in detail the configuration of the resolution control unit shown in FIG. 2;

4 is a block diagram illustrating in detail the configuration of the horizontal resolution controller and the vertical resolution controller shown in FIG.

FIG. 5 is a timing diagram of signals input and output to the resolution controller shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

200: clock generator 202: CD (CCD)

204: ADC 206: step motor

208: motor drive unit 210: central processing unit

212: mode selection unit 214: resolution control unit

216: buffer 218: page memory

220: image data bus 222: system data bus

224 System Address Bus

A scanning device according to the present invention for achieving the above object, the clock generating unit for generating a horizontal trigger signal, a horizontal counter signal, a vertical trigger signal and a vertical counter signal, and the image of the original in synchronization with the clock signal of the clock generator; A scanning apparatus having a scanning unit for reading at a predetermined resolution and outputting image data, wherein the scanning unit is configured to set a resolution reduction rate when the image data outputted from the scanning unit is reduced as a key input and output a corresponding resolution reduction ratio setting signal. A mode selection unit; A central processing unit which receives the resolution reduction rate setting signal and outputs corresponding resolution control data and outputs a direct memory access recognition (DMA_ACK) signal in response to the input direct memory access request (DMA_REQ) signal; A resolution control unit which receives and stores the resolution control data and outputs a direct memory access request (DMA_REQ) signal based on a clock signal input from the clock generator and the stored resolution control data; In response to the direct memory access request (DMA_REQ) signal, the image data outputted from the scan unit is selectively received and temporarily stored in synchronization with the received direct memory access request (DMA_REQ) signal. And a buffer for outputting the stored image data.

The resolution control unit stores the resolution control data input from the central processing unit to correspond to the horizontal counter signal based on a control signal input from the central processing unit, and corresponds to the horizontal counter signal when the horizontal counter signal is input. A horizontal resolution control unit for outputting a horizontal mask signal latching resolution control data in synchronization with the horizontal trigger signal; Based on the control signal input from the central processing unit, the resolution control data input from the central processing unit is stored so as to correspond to the vertical counter signal, and when the vertical counter signal is input, the resolution control data corresponding thereto is stored. A vertical resolution controller for outputting a vertical mask signal latched in synchronization with the vertical trigger signal; And an end gate which combines the horizontal mask signal, the vertical mask signal, and the horizontal trigger signal and outputs the result as a direct memory access request (DMA_REQ) signal.

Preferably, the horizontal resolution control unit receives and outputs an address signal input from the central processing unit corresponding to the horizontal counter signal when a write operation control signal is input from the central processing unit, and reads from the central processing unit. A first mux for receiving and outputting the horizontal counter signal from the clock generator when a control signal is input; Receives and outputs the resolution control data input from the CPU when the write operation control signal is input from the CPU, and receives the stored resolution control data when the read operation control signal is input from the CPU. A second mux for outputting; Storing resolution control data output from the second mux based on an address signal output from the first mux upon inputting a write operation control signal from the central processing unit, and inputting a read operation control signal from the central processing unit An SRAM for reading out the resolution control data stored at an address corresponding to a horizontal counter signal output from the first mux and outputting the resolution control data to the second mux; And a first flip-flop that receives the resolution control data output from the second mux and outputs a horizontal mask signal latched in synchronization with the horizontal trigger signal.

Preferably, the vertical resolution control unit receives and outputs an address signal input from the central processing unit corresponding to the vertical counter signal when the write operation control signal is input from the central processing unit, and controls the read operation from the central processing unit. A third mux for receiving and outputting the vertical counter signal from the clock generator when a signal is input; Receives and outputs the resolution control data input from the CPU when the write operation control signal is input from the CPU, and receives the stored resolution control data when the read operation control signal is input from the CPU. A fourth mux to output; When inputting the write operation control signal of the central processing unit, the resolution control data output from the fourth mux is stored based on the address signal output from the third mux, and the read operation control signal of the central processing unit is stored. An SRAM for reading out the resolution control data stored at an address corresponding to a vertical counter signal output from the third mux at the time of input and outputting the resolution control data to the fourth mux; And a second flip-flop that receives the resolution control data output from the fourth mux and outputs a vertical mask signal latched in synchronization with the vertical trigger signal.

Hereinafter, with reference to the accompanying drawings a preferred embodiment of the present invention will be described in detail.

2 is a block diagram schematically showing the configuration of an apparatus for controlling the resolution of image data according to the present invention.

As shown, the clock generator 200 outputs a horizontal trigger signal, a horizontal counter signal, a vertical trigger signal, and a vertical counter signal.

The scanning units 202 to 206 read an original image at a predetermined fixed resolution in synchronization with various clock signals of the clock generation unit and output the image data as image data. At this time, the required operating area of the step motor 206 constituting the scanning units 202-208 is very narrow. That is, the step motor 206 constituting the scanning units 202 to 208 of the present invention does not need to change the stepping speed of the step motor 206 for changing the vertical resolution, so that the step motor 206 operates at a fixed speed. to be.

The mode selector 212 sets the resolution reduction rate when the image data output from the scanning units 202 to 208 is reduced to a key input at a desired ratio, and sets a corresponding resolution reduction ratio setting signal to the central processing unit ( 210). As a preferred embodiment, the operation of the present invention will be described with respect to the case where the fixed resolution of the scanning units 202 to 208 is set to 600 DPI and the resolution reduction rate is set to 33% so that the resolution of the finally output image data is set to 200 DPI. .

The central processing unit 210 receives the resolution reduction ratio setting signal (33%) applied from the mode selection unit 212, and the ratio of the resolution reduction ratio and the number of bits in the '1' state to the total number of bits of the resolution control data to be output. This repetitive data in the same predetermined bit unit is output to the resolution control unit 214 as resolution control data. That is, the resolution control data is repetitive data in units of 3 bits and is data of a type such as '1, 0, 0 ..... 1, 0, 0'. The CPU 210 outputs the direct memory access recognition (DMA_ACK) signal to the buffer 216 in response to the direct memory access request (DMA_REQ) signal input from the resolution controller 214.

The resolution controller 214 receives and stores the resolution control data input from the central processing unit 210, and then directly requests a memory access request (DMA_REQ) based on the clock signal input from the clock generator 200 and the stored resolution control data. Signal is output to the central processing unit 210.

The buffer 216 selectively receives image data output from the scanning units 202 to 208 in synchronization with the direct memory access request (DMA_REQ) signal, and temporarily stores the image data in response to the direct memory access recognition (DMA_ACK) signal. In synchronization, the stored image data is output to the page memory 218.

An operation of the resolution controller 214 will be described in detail with reference to FIG. 3.

3 is a block diagram illustrating in detail the configuration of the resolution control unit shown in FIG. 2.

As shown, the resolution controller 214 includes a horizontal resolution controller 214a, a vertical resolution controller 214b, and an end gate 214c.

The horizontal resolution controller 214a stores the resolution control data input from the CPU 210 in correspondence with the horizontal counter signal according to the write / read control signal SELECT input from the CPU 210. Also, the horizontal resolution controller 214a reads the resolution control data corresponding to the horizontal counter signal input from the clock generator 200 according to the write / read control signal SELECT input from the central processing unit 210. It latches in synchronization with the horizontal trigger signal and outputs it as a horizontal mask signal.

The vertical resolution control unit 214b stores the resolution control data input from the central processing unit 210 so as to correspond to the vertical counter signal according to the write / read control signal SELECT input from the central processing unit 210. Also, the vertical resolution controller 214b reads the resolution control data corresponding to the vertical counter signal input from the clock generator 200 according to the write / read control signal SELECT input from the central processing unit 210. It latches in synchronization with the vertical trigger signal and outputs it as a vertical mask signal.

The end gate 214c receives the horizontal mask signal output from the horizontal resolution controller 214a, the vertical mask signal output from the vertical resolution controller 214b, and the horizontal trigger signal output from the clock generator 200, respectively. And output as a direct memory access request (DMA_REQ) signal.

The configuration and operation of the horizontal resolution controller 214a and the vertical resolution controller 214b will be described in detail with reference to FIG. 4.

4 is a block diagram illustrating in detail the configuration of the horizontal resolution controller 214a and the vertical resolution controller 214b shown in FIG. 3.

Although the configuration and operation of the horizontal resolution controller 214a and the vertical resolution controller 214b are the same as shown, the signals input and output to the horizontal resolution controller 214a are horizontal trigger signals, horizontal counter signals, and horizontal mask signals. The signals input and output to the vertical resolution control unit 214b are a vertical trigger signal, a vertical counter signal, and a vertical mask signal.

The horizontal resolution controller 214a includes a first mux 402, a second mux 404, an SRAM 406, and a flip-flop 408.

When the write operation control signal (SELECT = '0') is input from the central processing unit 210, the first mux 402 receives an address signal input from the central processing unit 210 corresponding to the horizontal counter signal. Output to SRAM (406), and when the read operation control signal (SELECT = '1') from the central processing unit 210 receives the horizontal counter signal from the clock generator 200 receives the SRAM (SRAM) 406).

When the write operation control signal (SELECT = '0') is input from the central processing unit 210, the second mux 404 receives the resolution control data input from the central processing unit 210 and receives an SRAM. 406 and, when a read operation control signal (SELECT = '1') is input from the central processing unit 210, receives the resolution control data from the SRAM 406 to the flip-flop 408. Output

When the write operation control signal (SELECT = '0') is input from the central processing unit 210, the SRAM 406 based on the address signal output from the first mux 402 may be used. When the resolution control data outputted from the controller is stored and a read operation control signal (SELECT = '1') is input from the central processing unit 210, it is stored at an address corresponding to the horizontal counter signal output from the first mux 402. The resolution control data is read and output to the second mux 404.

The flip-flop 408 receives the resolution control data output from the second mux 402, latches it in synchronization with the horizontal trigger signal input from the clock generator 200, and outputs it as a horizontal mask signal.

That is, when the resolution control data input from the central processing unit 210 is '1,0,0,1,0,0,1,0,0 ... 1,0,0', the scanning unit The resolution control data '1' corresponds to the first pixel data, the '0' corresponds to the second pixel data, and the third pixel data corresponds to the pixel data of one line of image data outputted from (202 to 208). 0 'corresponds. Accordingly, the horizontal resolution control unit 214a is configured such that when the scanning units 202 to 208 perform a scanning operation, the horizontal resolution controller 214a omits two out of three pixel data of each line output from the scanning units 202 to 208. Output the mask signal.

The operation of the vertical resolution controller 214b is the same as the operation of the horizontal resolution controller 214a.

That is, when the resolution control data input from the central processing unit 210 is '1,0,0,1,0,0,1,0,0 ... 1,0,0', the scanning unit For each line of image data output from (202 to 208), the resolution control data '1' corresponds to the first line, '0' corresponds to the second line, and '0' corresponds to the third line. Therefore, the vertical resolution control unit 214Ba outputs a horizontal mask signal that causes each of the lines outputted from the scan units 202 to 208 to drop two out of three lines when the scan units 202 to 208 perform a scanning operation. Output

When the fixed resolutions of the scan units 202 to 208 are set to 600 DPI and the resolution reduction ratio is set to 33%, the resolution of the finally output image data is set to 200 DPI. The relationship is briefly described with reference to FIG.

FIG. 5 is a timing diagram of signals input and output to the resolution controller 214 shown in FIG. 3.

While the vertical counter signal counters the vertical trigger signal three times, the vertical mask signal occurs once, while the horizontal counter signal counters the horizontal trigger signal three times, and the horizontal mask signal occurs once, and the vertical mask The DMA_REQ is generated by combining the signal and the horizontal mask signal, and the / DMA_ACK signal generated in response to the signal is output to the buffer 216.

Therefore, the buffer 216 inputs and stores only one line of the image data output from the scanning units 202 to 208 by missing two lines for every three lines, but stores three pixels of the input one pixel. Missing two pixels as a unit, and inputting only one pixel temporarily saves and outputs. As a result, the buffer 216 selectively receives 600DPI resolution image data output from the scan units 202 to 208 and outputs the image data having 200DPI resolution.

According to the scanning device according to the present invention, the horizontal and vertical resolution of the image data can be controlled using only general-purpose storage elements and logic elements, and there is an advantage that a step motor having a narrow operating area can be used.

Claims (5)

A clock generation unit for generating a horizontal trigger signal, a horizontal counter signal, a vertical trigger signal and a vertical counter signal, and a scanning unit for reading an image of a document at a predetermined resolution and outputting the image data in synchronization with a clock signal of the clock generation unit. In the scanning device, A mode selection unit for setting a resolution reduction rate for reducing the image data output from the scan unit as a key input and outputting a resolution reduction ratio setting signal corresponding thereto; A central processing unit which receives the resolution reduction rate setting signal and outputs corresponding resolution control data and outputs a direct memory access recognition (DMA_ACK) signal in response to the input direct memory access request (DMA_REQ) signal; A resolution control unit which receives and stores the resolution control data and outputs a direct memory access request (DMA_REQ) signal based on a clock signal input from the clock generator and the stored resolution control data; In response to the direct memory access request (DMA_REQ) signal, the image data outputted from the scan unit is selectively received and temporarily stored in synchronization with the received direct memory access request (DMA_REQ) signal. And a buffer for outputting the stored image data. 2. The method of claim 1, wherein the resolution control data output from the central processing unit comprises a predetermined bit unit in which the ratio of the number of bits in the '1' state to the total number of bits of the resolution control data to be output is equal to the resolution reduction rate. Scanning apparatus, characterized in that the repetitive data. The method of claim 1, wherein the resolution control unit Based on the control signal input from the CPU, the resolution control data input from the CPU is stored so as to correspond to the horizontal counter signal, and the resolution control data corresponding to the horizontal counter signal is stored when the horizontal counter signal is input. A horizontal resolution controller which outputs a horizontal mask signal latched in synchronization with the horizontal trigger signal; Based on the control signal input from the central processing unit, the resolution control data input from the central processing unit is stored so as to correspond to the vertical counter signal, and when the vertical counter signal is input, the resolution control data corresponding thereto is stored. A vertical resolution controller for outputting a vertical mask signal latched in synchronization with the vertical trigger signal; And an end gate which combines the horizontal mask signal, the vertical mask signal, and the horizontal trigger signal as a direct memory access request (DMA_REQ) signal. The method of claim 3, wherein the horizontal resolution control unit When the write operation control signal is input from the central processing unit, the clock signal is inputted and output from the central processing unit corresponding to the horizontal counter signal, and the clock is input when the read operation control signal is input from the central processing unit. A first mux for receiving and outputting the horizontal counter signal from a generator; Receives and outputs the resolution control data input from the CPU when the write operation control signal is input from the CPU, and receives the stored resolution control data when the read operation control signal is input from the CPU. A second mux for outputting; Storing resolution control data output from the second mux based on an address signal output from the first mux upon inputting a write operation control signal from the central processing unit, and inputting a read operation control signal from the central processing unit An SRAM for reading out the resolution control data stored at an address corresponding to a horizontal counter signal output from the first mux and outputting the resolution control data to the second mux; And a first flip-flop that receives the resolution control data output from the second mux and outputs a horizontal mask signal latched in synchronization with the horizontal trigger signal. The method of claim 3, wherein the vertical resolution control unit When the write operation control signal is input from the central processing unit, the clock signal is inputted and output from the central processing unit corresponding to the vertical counter signal, and the clock is input when the read operation control signal is input from the central processing unit. A third mux for receiving and outputting the vertical counter signal from a generator; Receives and outputs the resolution control data input from the CPU when the write operation control signal is input from the CPU, and receives the stored resolution control data when the read operation control signal is input from the CPU. A fourth mux to output; When inputting the write operation control signal of the central processing unit, the resolution control data output from the fourth mux is stored based on the address signal output from the third mux, and the read operation control signal of the central processing unit is stored. An SRAM for reading out the resolution control data stored at an address corresponding to a vertical counter signal output from the third mux at the time of input and outputting the resolution control data to the fourth mux; And a second flip-flop that receives the resolution control data output from the fourth mux and outputs a vertical mask signal latched in synchronization with the vertical trigger signal.