JPH06311337A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain an equipment by which an outside of an area is copied as an erected image by applying mirror image processing only to the inside of the area without limit of a position and number of areas designated by a marker. CONSTITUTION:A picture data generating circuit 30 generates picture data and a marker data signal in the unit of a predetermined picture element and an area recognition circuit 50 discriminates whether a read picture element is resident in a closed loop or at the outside of the closed loop designated by a marker based on a marker data signal. A correction/filter circuit 60 applies correction and filter processing to a picture data signal from the data generating circuit 30 and a mirror image circuit 100 applies mirror image processing to a picture signal via the correction/filter circuit 60. An edit processing circuit 70 applies processing such as color conversion or magnification reduction to an output picture data signal of the mirror image circuit to provide an output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a facsimile machine for copying machines, and more particularly, it scans a document optically to read image information, and makes a mirror image of the inside of a region designated on the document by a marker or the like. The present invention relates to an image processing device that performs edit processing for outputting the outside as a normal image.

[0002]

2. Description of the Related Art As a conventional apparatus for processing an image as a mirror image, an apparatus which temporarily stores the image in a page memory and reads it in the reverse order to that when the image is stored to obtain a mirror image (Japanese Patent Laid-Open No. 52-2 / 52-2).
No. 2830, JP-A-56-27128, and JP-A-64-62971), the image data is temporarily stored in the line memory for one line, and the reading operation is performed in the reverse order from the storing operation. There has been proposed one that obtains a mirror image by repeating a page (Japanese Patent Laid-Open No. 61-23190). However, although these conventional apparatuses can obtain a mirror image of the entire original, a copy cannot be obtained in which only a partial area of the original is a mirror image and the other area is a normal image. Also,
As an apparatus for obtaining a mirror image of a partial area of a document, the position and size of the mirror image are calculated in advance by an area designating unit such as a digitizer, and the read address of the line memory storing the image data is controlled via the CPU. Japanese Patent Laid-Open No. 63-215165 proposes a mirror image of a part of an original by operating an address counter.

However, in recent years, the demand for the function of editing and processing a part of the original has increased, and at the same time, the designation of the region by the marker has become popular because of the demand for simplification of the designation method for the region. The above-mentioned JP-A-63-215165.
The technique disclosed in Japanese Patent Laid-Open Publication No. 2003-242242 is such that the position and size of the mirror image are calculated in advance by an area designating means such as a digitizer, and cannot address the area designation by a marker. The reason is that it is difficult to calculate the position and size of the mirror image in advance when the area is designated by the marker. As a method of recognizing the designated area by the marker, a method of once performing a pre-scan at the time of copying to detect the position and size of the designated area by the marker (Japanese Patent Laid-Open No. 2-2857).
No. 69 and Japanese Patent Application Laid-Open No. 3-54969), these methods can detect the position and size of only one area.

[0004]

Provisionally, the method for detecting the position and size of a designated area by the above-mentioned marker is improved so that the position and size of a plurality of marker areas can be detected. JP-A-63-215165 Even if the technique described in the publication is used to obtain mirror images of a plurality of regions of a document, the following problems remain. First, in the means for detecting the position and size of the marker area, and also in the mirror image processing circuit, hardware such as a register must be prepared in advance according to the number of areas specified by the marker.
This means that there is a restriction on the specified area by the marker.
Furthermore, in order to enable a large number of areas, the scale of the hardware is increased and the cost is increased accordingly.

The second is the problem of processing time. In Japanese Patent Laid-Open No. 63-215165, when there are a plurality of areas in the sub-scanning direction or when the range of the mirror image in the scanning line changes, various registers are reset through the CPU. However, in general, there are certain timing restrictions for changing the settings of the various registers of the image processing circuit, and the time during which the settings of the various registers can be changed in one scanning line is about several μsec to several tens μsec. It is actually difficult for the CPU to monitor the scan line during scanning and change the settings of several registers during the short time in terms of the processing capability of the CPU, and especially for high-speed image processing. Is impossible. If the image processing speed is slow, there is a possibility that it can be realized by using a CPU with high processing capacity, but it will be expensive as an image processing apparatus.

An object of the present invention is to eliminate the need to calculate the position and size of a region in advance by prescanning for a plurality of regions designated by a marker, and to limit the number and position of marker regions. It is an object of the present invention to provide a device capable of performing mirror image processing only inside the area and copying the outside of the area with a normal image. Another object of the present invention is to provide an inexpensive image processing apparatus which does not involve the CPU during scanning for mirror image processing. Furthermore, an object of the present invention is to provide a cheaper image processing apparatus by enabling a mirror image processing on a large number of areas, but by slightly limiting the number of marker areas.

[0007]

According to the present invention, a document is optically scanned to read image information, a unit for generating image data from the read image information in a predetermined pixel unit, and a document by a marker or the like. Image processing for dividing the inside and outside of the area specified above and generating area data representing the area in synchronization with image data, and performing edit processing on the inside or outside of the area In the apparatus, for each scanning line, the memory that stores the input image data and area data in a predetermined pixel unit, and for each scanning line, determine the image data to be mirrored based on the area data, Means to determine the write or read address of the memory and mirror image processing only inside the specified area for multiple areas specified by markers etc. on the document Means for, an image processing apparatus having a.

The present invention further includes a second memory for storing and calculating, for each pixel, an address of the first memory in which image data and area data to be output are stored, and the second memory. Of the first memory and a means for determining the read address of the first memory. The present invention also provides the second memory for storing an address of a change point of area data input in synchronization with the image data when writing the image data in the first memory.
Memory, write and read control means for the second memory, and means for reading a change point stored in the second memory to determine a read address of the first memory when reading image data. An image processing apparatus having a.

[0009]

FIG. 1 shows the basic structure of a scanning system in an image processing apparatus. This is provided with an openable platen cover 14 on the platen 12 on which a document 13 is placed, while a light source 15 and a light guide member 16 including a SELFOC lens and a one-dimensional image sensor 10 such as a CCD are provided below the platen cover 14. Are arranged, and these together form a scanning unit. Then, the scanning unit moves in parallel in the direction of the arrow in FIG. 1, and in the process of optically scanning the original document 13, the original document 13 is scanned based on the cell-based detection signal output from the image sensor 10 and corresponding to the received light amount. Image information in a predetermined pixel unit corresponding to a grayscale image, a line drawing, a character, and the like drawn in is generated. Next, FIG. 2 shows the basic configuration of the entire image processing apparatus.

The CPU 20 controls the image processing apparatus, and a ROM 21 for storing data such as a control program and a RAM 22 used for control are connected to the CPU via a CPU bus. A motor 17 for translating the scanning unit shown in FIG. 1 is connected to the CPU 20 via a motor driver circuit 18 for driving the motor 17. Further, a user interface unit 23 such as a console panel or a display device is connected to the CPU 20. Further, the CPU bus has an image data generation circuit 30,
The area recognition circuit 50, the correction / filter circuit 60, the mirror image circuit 100, the edit processing circuit 70, and the output interface circuit 80 are connected. The image data generation circuit 30 is a circuit that generates an image data signal and a marker data signal in a predetermined pixel unit based on the detection signal output from the image sensor 10. If this image processing device
If image processing of N colors (N is 2 or more) is performed, the image sensor 10 is a full color sensor, and the image data generation circuit 30 outputs an image data signal to which color information is added. become. Therefore, the image data signal referred to here includes density information and color information of the image. In addition, the present image processing apparatus has N colors (N
2) or more) and different editing processes may be performed with the markers, and the number of marker data signals is not limited to one.

Based on the marker data signal, the area recognition circuit 50 determines whether the read pixel is inside or outside the closed loop designated on the original by the marker, or inside or outside the rectangular area circumscribing the marker. Of the marker area and outputs the result as an area data signal in a predetermined pixel unit. Regarding the method of determining whether the area is inside or outside the rectangular area circumscribing the marker in the area recognition circuit 50, for example, when the marker is designated on the original as shown in FIG. The area is determined as follows. Further, the number of marker data signals is N (N is 2
(More than this number), N or more N area data signals will be output. The correction / filter circuit 60 is a circuit that performs various corrections and filter processes on the image data signal from the image data generation circuit. The mirror image circuit 100 is a circuit that performs mirror image processing on the image data signal that has passed through the correction / filter circuit 60. The edit processing circuit 70 is a circuit that performs edit processing such as color conversion and enlargement / reduction on the image data signal that has passed through the mirror image circuit 100. In the correction / filter circuit 60, the mirror image circuit 100, and the editing / processing circuit 70, the CPU 20 particularly designates a region for performing various processes, and only the designated region is designated based on a region data signal from the region recognition circuit 50. In addition, it has a function of performing predetermined correction / filter processing, mirror image processing, and editing processing.

The image data signal that has passed through the editing / processing circuit 70 as described above is supplied to a specific image forming apparatus through the interface circuit 80. The image forming apparatus includes a printer 90, an image transmitter / receiver 91, a computer 92, and the like. When the printer 90 is connected, a digital copying machine is configured as a whole, and when the image transceiver 91 is connected, a facsimile is configured as a whole. When connected to the computer 92, a system mode is also possible in which image data is stored in the auxiliary storage device of the computer 92 and the image data is used in various terminal devices. FIG. 4 shows an internal configuration of the mirror image circuit 100. The specific operation of the mirror image circuit 100 will be described below.

In addition to the image data signal VDT IN and the area data signal ARDT IN, the page sync signal PSYNC is sent to the mirror image circuit.
IN, video valid signal VVAD IN, video clock signal
Correction / filter circuit 6 for each VCLK timing signal
Enable signal AREN that is input from 0 and indicates whether to perform mirror image processing on the area specified by the marker
B is set by the CPU 20. The video clock signal defines the timing for the image data signal and the area data signal, and the image data signal and the area data signal change at the rising edge of the video clock signal. The video valid signal represents the effective range of the image data signal and the area data signal in one scanning line of the image sensor 10, and changes at the trailing edge of the video clock signal. The page sync signal represents the effective range of the scan line in the process of performing optical scanning by the image sensor 10, and changes at the trailing edge of the video valid signal.

In the embodiment of the mirror image processing apparatus shown below, 1
Since two lines of processing time are required for writing and reading line image data, there are two image data processing units 102 and 103 for even lines and odd lines. The internal configurations of these two image data processing units may be exactly the same, and the control signal from the reference signal generation unit 101 allows the output data to be obtained alternately. The specific configuration of the reference signal generation unit 101 is as shown in FIG. In the reference signal generation unit 101, as shown in (3) and (4) of FIG. 9, even-numbered (0, 2, 4, ...) Lines are written to the image data processing unit for even-numbered lines and odd-numbered lines are written. (1,
WRITE LI so that the third line is read
Generates NE1 signal and READ LINE 1 signal. As shown in (4) and (5) of FIG. 9, the odd-numbered (1, 3, 5, ...) Lines are written to the image data processing unit for odd-numbered lines,
A WRITE LINE 2 signal and a READ LINE 2 signal are generated so that even-numbered (2, 4, 6, ...) Lines are read.

Therefore, as shown in (8) and (9) of FIG. 9, writing and reading operations are alternately performed by these two image data processing units, and the MPX 104 of FIG. The output data is switched to the edit processing circuit 7 in the subsequent stage.
Output to 0. When the input of the S terminal is H, the MPX 104 outputs the input of the B terminal, and the input of the S terminal is L.
In the case of, the input of the A terminal is output. M
The OUT SEL signal connected to the S terminal of the PX 104 is generated in the reference signal generation unit 101 so that it becomes H on the odd line. In the reference signal generation unit 101, the AN
The area data signals ARDT IN and ARENB are output by the D gate 105.
The AND of is used to generate an AR IN signal that represents the area in which mirror image processing is actually performed. That is, the image in the range where the AR IN signal is H should be mirrored and output.

Since the mirror image processing has a processing delay of one line, the PSYNC IN signal input by the LAT 107 is latched at the falling edge of the VVAD IN signal so that the page sync signal passed to the circuit at the subsequent stage is also delayed by one line. PSYNC OUT
Output a signal. The reference address counter 106 is VVAD.
The pixel number of each pixel counted from the rising edge of the IN signal is given, and this number becomes the reference address STDADR of each pixel in one line. The clear signal of the reference address counter is generated by ORing the PSYNC IN signal and the PSYNC OUT signal and the VVAD IN signal by the OR gate 116 and the AND date 117. FIG. 6 shows the internal configuration of the image data processing units 102 and 103. Image data memory 120, pixel address memory 121, image data memory address generation unit 122, pixel address memory data address generation unit 123, and read / write control unit 12
7 are interconnected as shown in FIG.

The image data memory 120 is a memory for storing image data signals and area data signals for one line. The pixel address memory 121 is a memory for storing the address of the image data memory 120 in which the pixel to be output is stored. Image data memory address generator 1
Reference numeral 22 is an address generator of the image data memory 120. The pixel address memory data address generation unit 123 is a generation unit of data to be written in the pixel address memory 121 and a read / write address. Read / write controller 1
Reference numeral 27 is a read / write controller of the image data memory 120 and the pixel address memory 121. In the operation of the image data processing unit, the writing operation and the reading operation for the image data memory 120 and the pixel address memory 121 are alternately repeated for each line. The image data processing unit will be described below in accordance with the writing operation and the reading operation. First, the writing operation will be described.

FIG. 10 is a timing chart of each signal during the write operation. In the case of a line that performs a write operation, the WR LINE signal goes high (hereinafter referred to as H), and valid image data is input from the next rising edge of the VCLK signal, as shown in Fig. 10 (3). From the reference signal generation unit 101, FIG.
The reference address is input as shown in (5). L in FIG.
Write signal VAM of pixel address memory by AT128
WRLINE becomes H as shown in Fig. 10 (6). The read line signal VAM RDLINE of the pixel address memory and the read line signal VDM RDLINE of the image data memory 120 remain at a low level (hereinafter referred to as L). FIG. 7 shows a specific configuration of the address generator 122 of the image data memory. VDMRDL
Since the INE signal, that is, the S terminal of the MPX 149 is L, the input of the A terminal is selected, and the reference address STDADR becomes the address of the image data memory 120. That is, the input image data and the area data signal are stored in the image data memory 120 as they are in the input order.

FIG. 8 shows a specific configuration of the data address generator 123 of the pixel address memory. Since the VAM WRLINE signal is H, it passes through BUF154 and the standard address STDA
DR becomes the write data VAM DT to the pixel address memory 121. Address VA of pixel address memory 121 at that time
In M ADR, since the VAM WRLINE signal is H, that is, the S terminal of the MPX 153 is H, the input of the B terminal is selected. The output of the MPX 152, which is the input of the B terminal, becomes the output of the LAT 151 when the AR IN signal is H, and becomes the reference address STDADR when the ARIN signal is L. LAT151
The output of holds the reference address when the AR IN signal rises. For example, as shown in (4) of FIG. 10, the pixel address memory 121 when an AR IN signal in which the third pixel to the sixth pixel and the tenth pixel to the twelfth pixel of the input pixels are H is input. The address is
It becomes like (8). That is, since the AR IN signal is L from the 0th pixel to the 2nd pixel, the reference address is selected, and the address of the pixel address memory 121 is “0”.
It becomes "1" and "2". Since the write clock signal VAM WRCLK to the pixel address memory 121 is given as shown in (7) of FIG.
Similarly, "0" and "1" are assigned to the addresses "1" and "2".
The data of "2" will be written.

At the 3rd pixel, after the reference address becomes "3", the AR IN signal becomes H, so the output of the LAT 151 becomes "3", and thereafter the address of the pixel address memory 121 becomes "3" until the 6th pixel. Is held. That is, the same 3
Since the data of "3", "4", "5", and "6" is overwritten in the pixel, the data of "6" is finally written in the third pixel. Further, nothing is written in the 4th to 6th pixels. From the 7th pixel to the 9th pixel,
Since the AR IN signal becomes L, the reference address is selected again and “7”, “8” and “9” follow. AR again at the 10th pixel
Since the IN signal becomes H, "10" continues to the 12th pixel as well as the 3rd pixel, and from the 13th pixel where the AR IN signal becomes L, "13", "14" ...
And continues.

Next, the read operation of the pixel data memory 120 and the pixel address memory 121 will be described, but the data written in the pixel address memory 121 in the example described in the write operation will be described. FIG. 11 is a timing chart during the read operation. In the case of the line for which the read operation is performed, the RD LINE signal becomes H, and the reference address is input from the next rising edge of the VCLK signal as shown in (3) of FIG. In the read operation, the write line signal VAM WRLINE of the pixel address memory is L. The read line signal VAM RDLINE of the pixel address memory and the read line signal VDM RDLINE of the pixel data memory become H as shown in (4) and (5) of FIG. In the read line, the pixel address memory 121 is first read. Since the VAM WRLINE signal is L,
In MPX153, the input of the A terminal is selected, and the reference address becomes the address of the pixel address memory 121. As shown in (7) of FIG. 11, since the read clock VAM RDCLK of the pixel address memory 121 is given, the data read from the pixel address memory becomes as shown in (8) of FIG.
Further, the BUF 154 has high impedance.

The data read from the pixel address memory passes through the BUF 140 of FIG. 7 and is input to the LAT 142. The LAT 142 latches the data read from the pixel address memory 121 at the rising edge of the AND signal of VCLK and the inverted output of the LAT 145. The output of the LAT 145 is L at the rising edge of the RD LINE signal. Therefore, the LAT 142 latches the data read from the pixel address memory at the rising edge of VCLK and becomes as shown in (9) of FIG. This is CM
It becomes the input of the B terminal of P144. The CMP 144 outputs H when the input of the A terminal is smaller than the input of the B terminal. On the other hand, L which is the input of the A terminal of the CMP 144
The output of AT143 is as shown in (6) of FIG. 11 because the reference address is latched by VCLK.

As described in the writing operation, the data from the 0th pixel to the 2nd pixel of the pixel address memory 121 is
They are "0", "1" and "2". Therefore, since the output of the LAT 142 and the output of the LAT 143 are the same, the output of the CMP 144 remains L, and the output of the LAT 145 latching the output of the CMP 144 by the inversion of VCLK is also L.
The output of LAT 146, which is the output of LAT 145 latched with VCLK, is also L. In MPX148, since the S terminal is L,
The output of the LAT 142 which is the input of the A terminal is selected.
Since the VDM RDLINE signal is H, the MPX149 selects the input of the B terminal, and the output of the MPX148 becomes the address of the image data memory 120. That is, 2 from the 0th pixel
Up to the pixel, the address of the image data memory 120 is "0""1""2".

Since the data of the third pixel of the pixel address memory 121 is "6", the output of the CMP 144 becomes H and the output of the LAT 145 becomes as shown in (8) of FIG.
While this signal is H, that is, until the reference address becomes "6", CLOCK of LAT142 becomes L, so LAT1
The output of 42 holds "6". The output of LAT146 that latches the output of LAT145 with VCLK is (11) in FIG.
become that way. When the output of LAT146 becomes H, MP
In X148, the input of the B terminal, that is, the output of the DEC147 is selected. DEC147 is MP at the rising edge of VCLK
It latches the output of X148 minus one. MPX148 when the output of LAT146 becomes H
Output was "6", so "5""4""3"
And the output of DEC147 changes. The output of the DEC147 is as shown in (12) of FIG.

When the reference address is "7" and the data of the 7th pixel of the pixel address memory 121 is being read, the output of the CMP 144 is L, so VC
The output of LAT142 changes to "7" at the rising edge of LK. At this time, the output of the LAT 146 also changes to L. Therefore, in the MPX 148, the LAT 14 which is the input of the A terminal
The output “7” of 2 is selected. After that, it changes to “8” and “9” up to the 9th pixel of the pixel address memory 121.
The data of the 10th pixel of the pixel address memory 121 is “1.
2 ". Therefore, as in the case of the third pixel to the sixth pixel, the image data memory 1 of the tenth pixel to the twelfth pixel
The address of 20 changes to "12""11""10". Further, after the 13th pixel, the operation changes to "13", "14" ... Like the operation in the case of the 7th pixel to the 9th pixel.

Therefore, the address of the pixel data memory 121 is as shown in (14) of FIG. On the other hand, since the image data memory read clock VDM RDCLK is given as shown in (13) of FIG. 11, the read data from the image data memory 120 becomes as shown in (16) of FIG. That is, from the 3rd pixel to 6
The image data of the pixel and the image data of the 10th to 12th pixels are in reverse order, which shows that a mirror image can be obtained only for the region where the AR IN signal is H. Note that FIG.
Comparing (3) of 1 with (16) of FIG. 11, it can be seen that there is a processing delay of two pixels due to the read operation of the pixel address memory 121 and the image data memory 120. Therefore, the VVAD OUT signal passed to the subsequent circuit is also adjusted by the reference signal generation unit 101 so as to be delayed by two pixels as shown in (17) of FIG.

From the above description of the mirror image circuit, it can be seen that there is no limit to the number of marker areas. Further, even if the resolution or the number of pixels in one line is changed, it does not significantly affect the configuration of the mirror image processing of the present case, and the image data memory 120 and the pixel address memory are adjusted in accordance with the resolution and the number of pixels in one line. It is only necessary to determine the memory capacity of 121, the reference address counter 106, and the data width of each LAT. Next, an output example in the case where the mirror image processing is performed on the document as shown in (1) of FIG. 12 will be described. In the manuscript shown in (1) of FIG. 12, it is assumed that three areas are designated by the markers and the function is set to perform the mirror image processing in these areas. In the marker signal, the area recognition circuit 50 recognizes a rectangular area circumscribing the marker, and area data as shown in (2) of FIG. 12 is input to the mirror image circuit.

Further, in order to simplify the explanation, FIG.
As shown in (2), the pixel position of each marker in the main scanning direction is the pixel position of the first marker area surrounding the "character DHLP" by "1.
50 to 194 ", the pixel position of the second marker area enclosing the" character F "is" 60 to 104 ", and the pixel position of the third marker area enclosing the" character MNOR "is" 15 to 144 ".
And Further, the operation will be described in the range from to in the sub-scanning direction. First, in the range of, that is, from the leading edge of the document to the first marker area, as shown in FIG.
Since the AR IN signal indicating the area to be mirror-imaged is L over the entire image area, the addresses of the pixels to be read out are in the order in which they were input, and the mirror-image is not performed. In the range (1), that is, the range in which the first marker area exists, the AR IN signal becomes H in the range from the 150th pixel to the 194th pixel as shown in FIG. Therefore, as described above, the read addresses of the 150th to 194th pixels of the image data memory 120 are “194” and “19”.
Since "3" ... "151" and "150" are obtained, it can be seen that only the image in this range is mirror-imaged.

In the range of, that is, the range in which the first marker area and the second marker area exist, as shown in FIG.
The AR IN signal becomes H in the range from the 60th pixel to the 104th pixel and from the 150th pixel to the 194th pixel. As described above, even if there are a plurality of areas in one line, the mirror image processing can be performed on each of the areas. That is, the image memory 12 of the 60th pixel to the 104th pixel
The read address of 0 is "104", "103" ... "6".
1 ”and“ 60 ”, and the read addresses of the 150th to 194th pixels of the image memory 120 are“ 194 ”and“ 19 ”.
3 ”...“ 151 ”and“ 150 ”. The operation in the range of is exactly the same as the operation in the range of. The operation in the range of is different in the range where the AR IN signal becomes H, but
It is similar to the operation in the range of.

The operation in the range (1) is the same as the operation in the range (2), although the range in which the AR IN signal becomes H is different.
The operation in the range of is exactly the same as the operation in the range of. From the above description, it can be seen that the output like (3) in FIG. 12 is finally obtained. Next, a second embodiment will be described in which the same effect can be obtained with a pixel address memory having a smaller capacity by limiting the number of regions to be mirror-image processed to some extent. If the number of regions is limited to some extent, it is not necessary to make the pixel address memory correspond to all pixels as in the first embodiment described above, and the pixel address of the changing point of the region may be stored in the memory. For example, if the image processing apparatus has a resolution of 16 pixels / mm and is capable of reading up to the short side (297 mm) of an A3 document, the number of pixels in one line is about 5000 pixels. In the above-described embodiment, 13 bits × Two 5000 word memories are required as pixel address memory. However, in the second embodiment, under the same resolution condition,
If the number of regions to be mirror-imaged is 16, only two 26-bit x 16-word memories will be needed as pixel address memory.
A large cost reduction is possible. The number of areas is 16
However, the number of regions that overlap in the main scanning direction is up to 16, and there is no limit to the sub scanning.

Also in the second embodiment, the mirror image circuit 100
The internal structure of is similar to that of the first embodiment and is as shown in FIG. The reference signal generation unit 101 is exactly the same. The image data processing unit in the second embodiment will be described below. The internal structure of the image data processing units 102 and 103 is shown in FIG. The image data processing unit comprises an image data memory 120, an image address memory 121, an address generation unit 122 of the image data memory, data to be written in the image address memory and a read / write address generation unit 123, and a read / write control unit 127. . The image data memory 120 is a memory that stores an image data signal and a region data signal for one line. Image address memory 12
Reference numeral 1 is a memory for storing the rising pixel address and the falling pixel address of the mirror image area. The image address memory 121 has a memory configuration in which a rising address is stored in High data and a falling address is stored in Low data, as shown in FIG.

In the operation of the image data processing unit, the writing operation and the reading operation to the image data memory 120 and the pixel address memory 121 are alternately repeated for each line. Hereinafter, the image data processing unit will be described according to the writing operation and the reading operation as in the first embodiment. First, the writing operation will be described. FIG. 18 is a timing chart of each signal during the write operation. WR LIN for lines that perform write operations
The E signal becomes H, and as shown in (3) of FIG.
Valid image data is input from the rising edge of the LK signal,
A reference address is input from the reference signal generation unit 101 as shown in (5) of FIG. According to the LAT128 shown in FIG. 6, the write signal VAM WRLINE of the pixel address memory is shown in FIG.
It becomes H like (6). The read line signal VAM RDLINE of the pixel address memory and the read line signal VDM RDLINE of the image data memory 120 remain L.

FIG. 16 shows a specific configuration of the address generation unit 122 of the image data memory. Since the VDM RDLINE signal, that is, the S terminal of the MPX 149 is L, the input of the A terminal is selected and the reference address STDADR becomes the address of the image data memory 120. That is, the input image data and the area data signal are stored in the image data memory 120 as they are in the input order. FIG. 17 shows a specific configuration of the data address generation unit 123 of the pixel address memory. Since the VAM WRLINE signal is H, it passes through the BUF 161 and the reference address is the Lo of the pixel address memory 121.
w Data VAM DT (L) with the reference address latched by the AR IN signal is the High data of the pixel address memory 121.
Written to VAM DT (H). However, the write clock VAM WRCLK of the pixel address memory 121 is given only while the AR IN signal is H.

For example, suppose that there is an input in which the AR IN signals from the third pixel to the sixth pixel and from the tenth pixel to the twelfth pixel of the input pixels become H as shown in (4) of FIG. VAM WR
UP counter CN of FIG. 17 when the LINE signal rises
The output of T151 and the output of LAT153 are "0".
That is, since the input of the S terminal is H in MPX159,
The output of the LAT 153 which is the input of the B terminal is selected, and the write address value of the pixel address memory 121 is “0”. However, from the 0th pixel to the 2nd pixel, since the AR IN signal is L, the write clock VAMWRCLK of the pixel address memory remains H, and writing is not performed. At the 3rd pixel, after the reference address becomes "3", the AR IN signal becomes H, so the output of the LAT 160 becomes "3", and the 3rd to 6th pixels are as shown in FIG.
Since VAM WRCLK is given as in (9), "3" is written in VAM DT (H) and "3" is written in VAM DT (L) at the third pixel.

On the other hand, the CNT 151 is AR IN at the third pixel.
When the signal rises, it becomes "1", but the output of LAT153 is held at "0" until the 7th pixel where the AR IN signal falls, so the write address of the pixel address memory remains "0". Is. That is, at the 4th pixel, VAM DT
(H) is overwritten with "3", VAM DT (L) is overwritten with "4", and at the 5th pixel, VAM DT (H) is overwritten with "3" and VAM DT (L) is overwritten with "5". In the eyes, VAM DT (H) is "3", VAM DT
“6” is overwritten on (L). At the 7th pixel, AR I
Since the N signal becomes L, the output of the LAT 153 becomes "1", but since VAM WRCLK is not supplied, the pixel address memory is not written. As a result, as the data of the address "0" of the pixel address memory 121, "3" is written in the H data and "6" is written in the L data.

Thereafter, even if the AR IN signal becomes H in the third area and the fourth area, the rising pixel address and the falling pixel address of the area are similarly stored in the pixel address memory 121. Address "2", "3"
It is obvious that the data is written in each area, but in order to simplify the description, the description will be continued assuming that there are two areas as shown in FIG. That is, CN at the fall of WR LINE
The output of the LAT 152 that latches the output of T151 becomes "2". The output of this LAT152 is the next WRLINE
Is held until the trailing edge of, so that "2" is held during the next read line. Next, the read operation of the image data memory 120 and the pixel address memory 121 will be described using the example described in the write operation.
FIG. 19 is a timing chart of each signal during the read operation. In the case of the line for which the read operation is performed, the RD LINE signal becomes H, and the reference address is input from the next rising edge of the VCLK signal as shown in (3) of FIG. In the read operation, the write line signal VAM WRLINE of the pixel address memory is L. The read line signal VAM RDLINE of the pixel address memory and the read line signal VDM RDLINE of the image data memory are shown in FIG.
It becomes H like (4) and (5) of 9.

In the read line, the pixel address memory 121 is first read. Since VAM WRLINE is L, BUF161 in FIG. 17 has high impedance. In the MPX 159, the input of the A terminal is selected and the output of the CNT 156 becomes the address of the pixel address memory 121. The output of this CNT156 is VAM RDLINE
It is "0" at the rising edge of the signal. FIG. 19
Since the read clock VAM RDCLK is given to the pixel address memory 121 as shown in (7), the pixel address memory 121 outputs “3” for VAM DT (H) and “6” for VAM DT (L).
Is read. The read data is the BU of FIG.
Input to LAT142 through F141, and next VCLK
The output of the LAT 142 becomes "3" at DT (H) and "6" at DT (L) at the rising edge of. At this time, since the output of the LAT 143 latching the reference address with VCLK is “0”, the output of the CMP 145 becomes L. On the other hand, VAM RD
At the time of rising of the LINE signal, LAT158 of FIG.
The DT ENB signal which is the output of is LOW, but the output of CNT156, that is, the input of the A terminal of CMP157 is "0", LA
Since the output of T152, that is, the input of the B terminal is "2", the output of CMP157 is H. Therefore, the next VC
The rising DT ENB signal of the LK signal becomes H as shown in (9) of FIG. Therefore, the output of AND146 in FIG.
It is L as shown in (12) of FIG.

Since the VDM RDLINE signal is H, MPX1
At 49, the input of the B terminal, that is, the output of the MPX 148 becomes the address of the image data memory 120. The MPX 148 uses the output of the AND 146 to output the LAT 143 and the DE.
The output of C147 is switched. That is, since the output of the AND 146 is L when the VDM RDLINE signal becomes H, the input of the A terminal in the MPX 148, that is, the LAT 14
3 is selected and the address of the image data memory 120 becomes "0". The output of LAT143 is "1"
Since the output of the AND 146 does not change even if it advances to "2", the address of the image data memory 120 is also "1""2".
And proceed. When the output of LAT143 becomes "3", CMP
Since the output of 145 becomes H and the output of AND 146 also becomes H, the MPX 148 changes so that the output of the DEC 147 is selected as the address of the image data memory. D
Since the output of AND146 is input to the LOAD terminal, EC147 outputs the DT of LAT142 which is LOAD data.
The output of (L), that is, "6" is the output of the DEC147. The DEC 147 is a decrement counter that decrements the LOAD data by -1 at the rising edge of VCLK. Therefore, it changes to "5""4""3" by the next VCLK, which becomes the address of the image data memory 120.

As shown in (13) of FIG. 19, when the reference address becomes "6", the output of the CMP 154 of FIG. 17 rises to H, and as shown in (14) of FIG. The output of the LAT 155 also becomes H at the rising edge. Therefore, L
When the output of AT143 becomes "6", CNT151
Is incremented by 1 and the address of the pixel address memory 121 becomes "1", so that the read data from the pixel address memory becomes "10" for H data and "12" for L data. At the next rise of VCLK, the output of LAT142
DT (H) becomes "10" and DT (L) becomes "12". The output of the LAT 143 at this time is "7" as shown in (6) of FIG. 19, and the output of the CMP 145 becomes L, so AND
The output of 146 becomes L, the input of the A terminal is selected again in the MPX 148, and the address of the image data memory 120 becomes "7".

After that, the output of the LAT 143 is "8" or "9".
During this period, the address of the image data memory 120 is “8” and “9” as it is.
The fact that it becomes 2 ”,“ 11 ”, and“ 10 ”is similar to the operation of the 0th pixel to the 6th pixel. The output of LAT143 is "1.
When the output of the CNT 156 becomes “2” at the time of becoming “2”, the output of the CMP 157 becomes L. Therefore, next VCLK
Since the DT ENB signal becomes L from the rising edge of, that is, the time when the output of LAT143 becomes "13", AND14
The output of 6 also becomes L, the output of LAT 143 is selected as the address of the image data memory 120, and “13” and “14” are selected.
... and proceed. From the above, the image data memory 1
The address of 20 is as shown in (17) of FIG. 19, and it can be seen that the same result as in the case of the first embodiment is obtained. If there is not one mirror image area in the write operation unlike the above example, the output of the LAT 152 is "0".
Therefore, the output of CMP157 is always L
Since the output of the AND 146 is always L, the output of the normal image is obtained, and there is no problem in the operation.

In the present embodiment, as shown in FIG. 5, the area signal has been described as an example of one, but if the image processing apparatus concerned performs different editing processing with markers of N colors (N is 2 or more). If there is something to do, N or more than N area data signals will be input, but the enable signal corresponding to the area data signal is set from the CPU, and each AN
The AR IN signal may be generated by taking D and ORing them. In the second embodiment, an example of an inexpensive mirror image processing circuit is shown by limiting the number of areas in the main scanning direction. In this embodiment, although the error processing circuit for the case where the limit of the number of areas is exceeded is not shown, the circuit for counting the number of areas in FIG. In that case, it is also effective to add a circuit for stopping the operation such as writing to the pixel address memory 121 or counting the number of areas.

Further, in this embodiment, as shown in FIG. 2, the mirror image processing circuit 100 is arranged between the correction / filter circuit 60 and the editing processing circuit 70. However, the mirror image processing circuit 100 is edited. It may be placed in the circuit 70 and the order of processing with other editing processing may be exchanged.

[0043]

As described above, according to the first embodiment, since the image data to be mirror-imaged is determined for each scanning line, a plurality of regions designated by the markers are prescanned. It is possible to provide a device that does not require the calculation of the position and size of the area in advance, and that does not limit the number or position of the marker areas, performs mirror image processing only inside the area, and can copy the outside of the area with a normal image. . Further, regarding the mirror image processing, the CPU does not intervene during scanning, and an inexpensive image processing apparatus can be provided.
Further, according to the second embodiment, by limiting the number of regions in the main scanning direction to be mirror-image processed to some extent, it is possible to perform the mirror-image processing only on the inside of a large number of regions at a low cost, and the normal image outside the regions. It is possible to provide a device capable of copying with. Even if you say to limit the area, there is no limit in the sub-scanning direction,
The limited number in the main scanning direction also depends on the setting of the memory capacity and the like, and substantially the same effect as that of the first embodiment can be obtained.

[Brief description of drawings]

FIG. 1 shows a basic structure of a scanning system in an image processing apparatus.

FIG. 2 shows a basic configuration of the entire image processing apparatus.

FIG. 3 shows an example of region recognition.

FIG. 4 shows an internal configuration of a mirror image circuit.

FIG. 5 shows a specific circuit configuration of a reference signal generation unit.

FIG. 6 shows a specific circuit configuration of an image data processing unit.

FIG. 7 shows a specific circuit configuration of an address generation unit of the image data memory.

FIG. 8 shows a specific circuit configuration of a data address generation unit of a pixel address memory.

FIG. 9 shows the timing of each signal of the reference signal generator.

FIG. 10 shows the timing of each signal during a write operation.

FIG. 11 shows the timing of each signal during a read operation.

FIG. 12 shows an output example when a mirror image process is performed.

13 shows a signal state in the example of FIG.

FIG. 14 shows a memory configuration of a pixel address memory in the second embodiment.

FIG. 15 shows a specific circuit configuration of an image data processing unit in the second embodiment.

FIG. 16 shows a specific circuit configuration of an address generator of the image data memory in the second embodiment.

FIG. 17 shows a specific circuit configuration of a data address generation unit of the pixel address memory according to the second embodiment.

FIG. 18 shows the timing of each signal during a write operation in the second embodiment.

FIG. 19 shows the timing of each signal during a read operation in the second embodiment.

Claims (3)

[Claims] 1. A means for optically scanning an original to read image information, a means for generating image data in a predetermined pixel unit from the read image information, and an area designated on the original by a marker or the like. In an image processing device that divides the inside and the outside and that generates area data that represents the area in synchronization with image data, and that performs editing processing on the inside or outside of the area, for each scanning line, A memory that stores the input image data and area data in predetermined pixel units, and image data to be mirrored based on the area data is determined for each scanning line, and the write or read address of the memory is set. For the means to determine and the multiple areas specified by the marker etc. on the manuscript,
An image processing apparatus comprising means for performing mirror image processing only inside a designated area and outputting a normal image outside the designated area. 2. A second memory for storing and calculating, for each pixel, an address of the first memory in which image data and area data to be output are stored, and writing in the second memory. The image processing apparatus according to claim 1, further comprising a read control unit and a unit that determines a read address of the first memory. 3. A second memory for storing an address of a change point of area data input in synchronization with the image data when the image data is written in the first memory, and the second memory. Write and read control means and read means for reading change points stored in the second memory to determine a read address of the first memory at the time of reading image data. 1. The image processing device according to 1.