GB2288946A

GB2288946A - Image enlargement/reduction method

Info

Publication number: GB2288946A
Application number: GB9508860A
Authority: GB
Inventors: Hyang-Su Oh
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1994-04-30
Filing date: 1995-05-01
Publication date: 1995-11-01
Also published as: GB9508756D0; FR2719404A1; GB2288945B; GB2288945A; DE19508994A1; DE19508994B4; KR0120570B1; GB9508860D0; FR2719404B1; JPH07302331A; JP3694544B2; KR950029980A

Description

2288946 1 METHOD FOR ENLARGEMENT/REDUCTION OF IMAGE DATA IN DIGITAL IMAGE

PROCESSING SYSTEM AND CIRCUIT ADOPTING THE SAME The present invention relates to a method f or enlargement /reduction of image data in a digital image processing system, and more particularly, to a method for enlargement/reduction of input image data according to an arbitrary enlargement and reduction rate designated by a user.

In this document, "enlargement /reduction" means a change in scale of a document, which may be enlargement, reduction, or either; and need not be the same in all directions (i.e. may be anamorphic).

Generally, digital image processing systems (for example, digital copiers or facsimiles that converts an image into an electrical signal and process the result by employing a photoelectric device (i.e., an image sensor such as a charge-coupled device)), require a function for enlarging or reducing the original size image, in other words, a rate- converting function or the enlargement/ reduction function. In order to satisfy such a requirement, the enlargement/reduction function is realized in a conventional method in which a regulated copy ratio (e.g., zooming), even in 196 steps for standard-sized documents, is made possible.

is 2 A f irst technique applied for the conventional enlargement and reduction operations as above is illustrated in FIG. 1. Here, the pulse rate of an input (write) clock is controlled to correspond to a zooming ratio when image data is written into an image memory (for example, a line memory for storing the image data in units of one line of the main scanning direction) by employing a sync signal associated with the image data, or the pulse rate of an output (read) clock is controlled to correspond to a zooming ratio when the image data is read out from the image memory. In other words, when an image is to be doubled in size, the image data input at the image sync signal rate is written into an image memory and the same image data is read out from the image memory for two image sync signal pulses, to thereby output an image whose size is twice the original.

On the other hand, when an image is to be halved in size, alternating image data is written into the image memory every two image sync signal pulses and the image is read out f rom the image memory at the image sync signal rate, to thereby output an image whose size is half the original. (A more detailed method is disclosed in Japanese Laidopen Publication No. sho59-39158.) Enlargement (11501 reproduction) and reduction 3 (85t reproduction) operations performed according to the above technique are exemplified in the following Tables 1 and 2, respectively, where P is a value used in connection with zooming ratio, K is an integer value and R is the zooming ratio.

4 < TABLE 1 number of data data data number of input pixels value P+R value P value K output pixels 1 1.15 0.00 1 1 2 1.30 0.15 1 2 3 1.45 0.30 1 3 4 1.60 0.45 1 4 1.75 0.60 1 5 6 1.90 0.75 1 6 7 2.05 0.90 2 7,8 8 1.20 0.05 1 9 9 1.35 0.20 1 10 1.50 0.35 1 11 11 1.65 0.50 1 12 12 1.80 0.65 1 13 13 1.95 0.80 1 14 14 2.10 0.95 2 15,16 is 1.25 0.10 1 17 16 1.40 0.25 1 18 17 1.55 0.40 1 19 18 1.70 0.55 1 20 19 1.85 0.70 1 21 2.00 0.85 2 22,23 21 1.15 0.00 1 24 22 1.30 0.15 1 25 23 1.45 0.30 1 26 < Table 2 > is number of data data data number of input pixels value P+R value P value K output pixels 1 0.85 0.00 0 2 1.70 0.85 1 1 3 1.55 0.70 1 2 4 1.40 0.55 1 3 1.25 0.40 1 4 6 1.10 0.25 1 5 7 0.95 0.10 0 8 1.80 0.95 1 6 9 1.65 0.80 1 7 1.50 0.65 1 8 11 1.35 0.50 1 9 12 1.20 0.35 1 10 13 1.05 0.20 1 11 14 0.90 0.05 0 1.75 0.90 1 12 16 1.60 0.75 1 13 17 1.45 0.60 1 14 18 1.30 0.45 1 15 19 1.15 0.30 1 16 1.00 0.15 1 17 21 0.85 0.00 0 22 1.70 0.85 1 23 1.55 0.70 1 19 6 In the above tables, a zooming ratio (R) is sequentially accumulated to the number of input pixels, and the zooming ratio (R) is accumulated again with respect to the down of the decimal place of the accumulated values, and an integer portion (K) of the accumulated values is examined.

In the operation state of Table 1, the zooming ratio (R) is 1. 15. Here, if the examined integer portion (K) is above two, the next pixel data value is added to the input pixel data value, to thereby perform an enlargement corresponding to the zooming ratio (R).

In the operation state of table 2, the zooming ratio (R) is 0. 85. Here, if the examined integer portion (K) is less than one, the pixel data is not output and the next pixel data value is output, to thereby perform an reduction corresponding to the zooming ratio (R).

However, the circuit for implementing such an enlargement/reduction method is very complicated, and controlling the timing for high-speed processing is difficult. In addition, the circuit is costly and the range of the enlargement/reduct ion ratio cannot be easily extended or otherwise modified.

Another conventional technique is disclosed in Japanese Laid-open Publication No. hei2-132963, which 7 is is shown in FIG. 2A to FIG. 2D. Referring to FIG. 2A, reference numerals 25 and 26 denote FIFO memories A and B each having a capacity of one line of the main scanning direction, for example, 4752 pixels (16pels/mm x 297mm; i.e., length of A4-sized paper). As shown in FIG. 2B, a memory write operation is performed when write enable signals /AWE and /BWE are low, and a memory read operation is performed when read enable signals /ARE and /BRE are low. In addition, the output of FIFO A is at a high impedance state when its read enable signal (/ARE) is high, and the output of FIFO B is at a high impedance state when its read enable signal (/BRE) is high. Thus, the respective outputs of FIFO A and FIFO B are output in a wired-OR state (DOUT). In FIFO memories 25 and 26, an internal pointer proceeds in accordance with a write address counter 30 and a read address counter 31 which are operated by write clock WCK and read clock RCK, respectively, as shown in FIG. 2C. Therefore, the input image data is reduced when with the sync signal V= of the image data (Din) which is divided down by a rate multiplier (RMP1) 27 is applied to the write clock port of write address counter 30 and the sync signal V= which is similarly divided down by a rate multiplier (RMP2) 28 is applied to the read clock port of read address counter 31. Conversely, the input is 8 image is enlarged if the applied clock signals are reversed. Thus, FIF0s A and B alternately perform read and write operations. Meanwhile, a write address counter 30 and a read address counter 31 of FIFO memories 25 and 26 are structured such that counting is performed by a clock for the section where enable signals (WE and RE) are low, and are initialized (reset) upon a logic "low" state of a reset signal RST. For example, as shown in FIG. 2D, after an RST pulse (the inverted sync signal /HSYNC of main direction scanning) is input, pixel data from pixel nl to pixel ni+m is written during the logic,low,, state of the write enable signals of FIF0s A and B (/AWE and /BWE). Then, pixel data from pixel n2 to pixel n2+ m is read out during the logic "low" state of the read enable signals (/ARE and /BRE). As a result, the write data becomes the read data, as shown 2D.

The above-described method controls an output sync signal of image data at the point of reading/writing the image data from/to a line memory so as to perform enlargement or reduction which can be achieved stably in 10- . units. However, the circuitry for achieving such an enlargement/ reduction operation (i.e., 1-0. units) is quite complex. Further, in order to perform enlargement and reduction over a greater range of zooming ratios (beyond, say, 25% to 400R1), 9 the hardware needs to be physically altered.

Accordingly, it is an object of the present invention to provide an improved method for the enlargement/reduction method of image data in a digital image processing system.

It is another object of the present invention to provide a circuit suitable for realizing the above method.

To accomplish the above object, there is provided an image data enlargement/reduction method in a digital image processing system for promptly outputting image data of the desired reproduction or reduction rate with reference to data stored in a look-up-table (LUT) which may have a small capacity, whenever a user changes a zooming ratio. It comprises a LUT where a small quantity of data for use in enlargement/reduction is stored and a memory for use in enlargement/reduction, and which enlarges/reduces input image data in accordance with a user-designated zooming ratio. The method comprises the steps of: (a) dividing the user-designated zooming ratio by one and calculating the quotient and remainder thereof; (b) reducing image data with reference to the data stored in the LUT, if the quotient calculated in the step (a) is less than one; (c) enlarging image data with reference to the data stored in the LUT, if the quotient calculated in the step (a) is greater than one and the remainder thereof is not zero; (d) performing a simple enlargement process, if the quotient calculated in the step (a) is greater than one and the remainder thereof is zero; and (e) writing the enlargement/reduction data calculated via the steps (a) to (d) into the memory.

Corresponding apparatus is also provided. The apparatus may be an enlargement/reduction circuit for enlarging and reducing image data input to a digital image processing system and outputting an image corresponding to a user-designated zooming ratio, the circuit comprising: a first memory for storing an LUT for use in enlargement/reduct ion; a microprocessor for calculating enlargement/reduction data corresponding to the zooming ratio, using the LUT stored in the first memory; a second memory for temporarily storing, in the course of calculating the enlargement/reduct ion data by the microprocessor, the enlargement/reduction data of the LUT and enlargement/reduction data for an amount of one line calculated from the microprocessor; first and second line memories for storing the input image data to be enlarged/ reduced, in units of one scanned line, respectively; a third memory for performing enlargement/reduction by employing the enlargement/reduction data stored in the second 11 memory; a first counter for counting a sync signal of the image data in order to write the one scanned line units of the image data, into predetermined addresses of the first and second line memories; a second counter for counting the sync signal of the image data in order to output the data of the third memory as addresses of the first and second line memories, so that data can be written into the third memory by the microprocessor and so that enlargement /reduction can be performed with respect to the user-designated zooming ratio during a scanning operation; and a frequency divider for f requency- dividing a line sync signal such that the read and write operations of the first and second line memories can be performed alternately.

The above objects and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:

FIG.1 illustrates the concept of a conventional image data enlargement/reduction method; FIG. 2A to FIG. 2D illustrate conventional image data enlargement/reduction circuits and the operational waveforms thereof; FIG. 3 illustrates the concept of image data enlargement and reduction according to an embodiment is 12 of the present invention; FIG. 4 is an image data enlargement /reduction processing circuit according to an embodiment of the present invention; FIG. SA to FIG. SK are operational waveforms of various parts of the circuit shown in FIG. 4; FIG. 6A shows an LUT f or use in reduction, and FIG. 6B shows enlargement data calculated using the LUT.

FIG. 7 is a flowchart showing the image data enlargement /reduction method of the present invention; FIG. 8 is a flowchart showing the standard enlargement/reduction process with respect to FIG. 7; FIG. 9 is a flowchart showing the reduction process of FIG. 7, with reference to the LUT; FIG. 10 is a flowchart showing the enlargement process of FIG. 7, with reference to the LUT; and FIG. 11 is a flowchart showing a simplified enlargement process with respect to FIG. 7.

FIG. 3 illustrates the concept of image data enlargement and reduction for use in a digital image processing system, according to the present invention. Referring to FIG. 3, it can be seen that, in the present embodiment, the line memory write data is the same regardless of zooming ratio, but the read data is 1 13 controlled according to the zooming ratio, in contrast to the image data enlargement/reduction technique of FIG. I.

FIG. 4 is an image data enlargement/ reduction circuit for use in a digital image processing system, according to the present invention. The circuit of FIG. 4 basically includes enlargement/reduction data calculating means for calculating enlargement /reduction data to be processed during a real copy operation by recognizing a zooming ratio defined by a user, and enlargement/reduction processing means for performing enlargement/reduction by employing the enlargement /reduction data calculated by the enlargement/reduction data calculating means.

The enlargement/reduction data calculating means comprises a first memory, for example, a ROM 102, for storing an enlargement/ reduction LUT, a microprocessor 101 for calculating enlargement/reduction data by employing data of the LUT stored in ROM 102, and a second memory, for example, a RAM 103, for temporarily storing the LUT data for use in enlargement/reduction operations and the enlargement/reduction data calculated by microprocessor 101.

Meanwhile, the enlargement /reduction processing means comprises first and second line memories 601 and 602 for storing image data in units of one line in the 14 main scanning direction in which, f or example,the number of pixels is 4752pels/line by assuming a resolution of 400 Dots per Inch (DPI) (16pels/mm) and A4-sized paper (length: 297mm), a third memory, for example, a zoom P-AM 603, for performing enlargement /reduction by using enlargement /reduction data stored in RAM 103, a first counter, for example, a write address counter 604, for counting a sync signal WCLK) of the image data so that one line of image data in the main scanning direction, i.e., the image data output direction from a charge-coupled device, can be written into a predetermined address of first and second line memories 601 and 602, a second counter, for example, a zoom address counter 605, for counting the image data sync signal (VCLK) in order to output data of zoom RAM 603 as an address of first and second line memories 601 and 602 so that data can be written into zoom RAM 103 by microprocessor 101 or enlargement /reduction can be performed with respect to a predetermined zooming ratio during a scanning operation, and a frequency divider, for example, a D flip-flop 615, for dividing the frequency of a line sync signal so that the read/write operations of first and second line memories 601 and 602 can be performed alternately.

The enlargement/reduction processing means is is further comprises first buffer means, for example, buffers 607, 608, 609 and 610, which serve as a path f or designating a write and read-out address into first and second memories 601 and 602, second buffer means, for example, buffers 611 and 613, which serve as a path for writing image data to be enlarged/reduced into first and second line memories 601 and 602, third buffer means, for example, buffers 612 and 614, which serve as a path for outputting the enlarged/ reduced image data read out from first and second line memories 601 and 602, and fourth buffer means, for example, buffer 606, which serve as a path for enabling microprocessor 101 to read/write the data of zoom RAM 603.

In addition, the enlargement /reduction processing means further comprises first to fifth inverters 616 to 620, first to fourth AND gates 621 to 624, and first and second OR gates 625 and 626.

FIG. SA to FIG. SK illustrate the waveforms of various parts of the circuit shown in FIG. 4. FIG. SA illustrates a scan signal applied to first, second, fourth and fifth inverters 616, 617, 619 and 620 and to the clear port of D flip-flop 615. FIG. 5B illustrates a line sync signal (/LSYNC) applied to second AND gate 622, the clock port of D flip-flop 615 and the clear port of write address counter 604. FIG.

is 16 SC illustrates an enable signal output f rom the Q port of D flip-flop 615. FIG. SD illustrates an inverted enable signal output from the /Q port of D flip-flip 615. FIG. SE illustrates an image data enable signal (/VDEN) applied to third inverter 618. FIG. SF illustrates an inverted sync signal (/WLK) applied to first and second OR gates 625 and 626, third AND gate 623, and the clock port of write address counter 604. FIG. 5G illustrates image data DIN input to be enlarged or reduced. FIG. 5H illustrates the zoom RAM address clear signal (/CS1CLR) applied to second AND gate 622. FIG. 51 illustrates zoom RAM selecting signal (ICS1) applied to f irst and third AND gates 621 and 623. FIG. W illustrates the zoom RAM read signal (/CS1RD) applied to a terminal DIR of buffer 606, the output (read) enable port of zoom RAM 603, and fourth AND gate 624. FIG. 5K illustrates the zoom RAM write signal (/CS1WR) applied to the write enable port of zoom RAM 603.

FIG. 6A shows an embodiment of a LUT for use in enlargement/reduction for the case where the zooming ratio is 85%. FIG. 6B shows part of the enlargement/reduction data calculated by the microprocessor 101 for the case where the zooming ratio is 185%.

PIG. 7 is a flowchart for explaining the image is 17 data enlargement /reduction processing method according to the present embodiment, for use in a digital image processing system. Step 10 is a standard enlargement/reduct ion processing step for performing a standard enlargement /reduction with respect to image data which is input when an initial operation is executed. Step 40 is an enlargement /reduction ratio dividing step, performed if the zooming ratio is set by a user, for calculating the quotient and remainder by dividing the changed rate by 1. Steps 50 and 60 are for performing a reduction with reference to data stored in an LUT, if the quotient calculated in steps and 40 is less than one. Steps 50, 70 and 80 are first enlargement steps for performing an enlargement with reference to data stored in an LUT, if the quotient calculated in step 40 is larger than one and the remainder calculated in step 70 is not zero.

Steps 50, 70 and 90 are second enlargement steps for performing a simple enlargement, if the quotient calculated in step 40 is larger than zero and the remainder calculated in step 70 is zero. Step 100 is a data writing step for writing enlargement/reduction data calculated via steps 10 to 90 into a memory for use in enlargement /reproduction. Steps 110 and 120 are data verifying steps for verifying if enlargement /reduction data which is read is same as is is original data and then performing a scan operation.

An operation of circuit of the present invention can be explained with reference to FIG. 3 to FIG. 11.

First, the basic concept of enlargement/ reduction of the present invention can be explained with reference to FIG. 3, as follows. When image data is written into a line memory, as shown in reduction (b) and enlargement (c) of FIG. 3, the writing operation is performed by the sync signal (VCLK) of an input image signal. Then, the image data is enlarged/reduced in the line memory.

Ref erring to FIG. 4, a LUT for realizing the enlargement /reduction in 19k units is stored in ROM 102, and microprocessor 101 reads the LUT stored in ROM 102 to RAM 103 so as to calculate enlargement /reduction data corresponding to the rate selected by a user. Then, the calculated enlargement/reduction data is stored in a predetermined area of RAM 103. That is, microprocessor 101 reads out the LUT data from ROM 102 only when the zooming ratio selected by a user needs a reference from LUT, and stores the result into RAM 103. Here, 100 bytes is sufficient for the area of RAM 103 where the LUT is stored.

Assuming a resolution of 400DPI, the maximum number of pixels for one scanned line is 4,752.

is 19 Therefore, when enlargement/reduction data corresponding to 4,752 pixels is generated by microprocessor 101 and RAM 103, enlargement/reduction data is read out from RAM 103 and written into zoom RAM 603. At this time, microprocessor 101 does not perform random accessing of the enlargement/reduction data in zoom RAM 603 by employing an address bus, but accesses zoom RAM 603 using an address generated from zoom address counter 605 by a predetermined address allocated in each area of a memory. In addition, enlargement /reduction data can be written and read out from microprocessor 101 via buffer 606.

The above-described operations can be performed when the scan signal of FIG. SA is low, which corresponds to a zoom data download section. Here, /MCLR (FIG. SH) is a signal for aligning an address at zero when data is read/written from/into zoom RAM 603. In addition, ICS1 (FIG. SI) and /CS1RD (FIG. SJ) are low to read out data from zoom RAM 603, and CS1 (FIG. SI) and /CS1WR (FIG. SK) are low to write data into zoom RAM 603. When enlargement /reduction data is written into zoom RAM 603, all preparation for enlargement/reduction is completed. When the scan signal of FIG. SA is low, image data is not output and first and second line memories 601 and 602 are disabled.

When the scan signal of FIG. SA is high, the enable signal shown in FIG. SC is also high and the inverted enable signal shown in FIG. SD is low, by the trailing edge of the f irst pulse of the line sync signal (/LSYNC) of FIG. 5B. Then, when the image data enable signal (/VDEN) shown in FIG. SE goes low, image data is output by one pixel unit in accordance with the inverted sync signal (/WLK) shown in FIG. SF.

At this time, since buffers 608 and 612 are enabled, enlargement /reduction data output f rom zoom RAM 603 via buffer 608 is provided as an address to first line memory 601. First line memory 601 operates at an image data read-out mode in which the enlarged/reduced image data corresponding to the address output via buffer 612. Here, as an address value of first line memory 601, an output value of zoom address counter 605 which performs counting upon being reset by the line sync signal of FIG. 5B and triggered by the inverted sync signal /VCLK of FIG. SF. In addition, buffers 609 and 613 are enabled so that an output value of write address counter 604 is applied to an address of second line memory 602 and second line memory 602 operates in an image data write mode in which image data is synchronized with the inverted sync signal /VCLK of FIG. SF and input to second line memory 602. The above-described operation 21 corresponds to the state 1 of FIG. SG.

In the meantime, if the second pulse of line sync signal /LSYNC shown in FIG. 5B is input, the enable signal of FIG. SC is low and the inverted enable signal of FIG. SD is high. Accordingly, conversely with respect to the state 1, buffers 607 and 611 are enabled and an output value of write address counter 604 is applied to an address of first line memory 601.

As a result, f irst line memory 601 operates in an image data write mode in which image data is synchronized with the inverted sync signal /VCLK of FIG. SF and input to first line memory 601. Then, buffers 610 and 614 are enabled and enlargement /reduction data output from zoom RAM 603 is applied as an address. As a result, second line memory 602 operates in an image data read-out mode in which the enlarged/reduced data is output via buffer 614. The above-described operation corresponds to the state 2 of FIG. SG.

First and second line memories 601 and 602 alternately perform the states 1 and 2 by the line sync signal /LSYNC of FIG. 5B which is input continuously. When an entire scanning operation is completed, the scan signal of FIG. SA is low so as to prepare for performing enlargement/ reduction and other functions.

is 22 An enlargement/reduction method by using an LUT can be explained with reference to FIG. 7 to FIG. 11, as follows.

Referring to FIG. 7, a standard enlargement/ reduction (100'-';) is performed in step 10 as shown in FIG. 8, and it is determined whether the user specifies a zooming ratio in step 20. If a scan start command is given without setting the zooming ratio in step 20, enlargement /reduction data is written into zoom RAM 603 (step 100). Meanwhile, if step 20 results in a new zooming ratio, the zooming ratio is divided by one hundred (step 40) and it is determined whether the quotient is greater than one (step 50).

If the quotient is less than one in step 50, reduction is performed with reference to LUT as shown in FIG. 9 (step 60). If the quotient is greater than one in step 50, it is determined whether the remainder is zero (step 70).

If the remainder is not zero in step 70, an enlargement is performed with reference to an LUT as shown in FIG. 10 (step 80). If the remainder is zero, a simple enlargement is performed as shown in FIG. 11 (step 90).

If enlargement/reduction data is arranged after performing step 90, the enlargement/reduction data is written into zoom RAM 603 (step 100). Then, the data 23 written into zoom RAM 604 is read-out and it is verified whether the read- out data matches the original data (step 110). When the verification is completed, a scan operation is performed (step 120).

A standard enlargement /reduction can be explained with reference to FIG. 81 as follows. Enlargement /reduction data storing area TEMP in RAM 103 is allocated reference address Z-ADD, and reference data VALUE for calculating enlargement/ reduction data is set as zero (step 12) Then, the VALUE is written into Z-ADD (step 14) and then, Z-ADD (the address count) and VALUE are each incremented by one (step 16).

In step 18, the maximum number of pixels END-AD in units of one scanning line in the main scanning direction and Z-ADD are compared. If Z-ADD is smaller than END-AD, the step 18 returns to step 14, and if Z-ADD is larger than END-AD, the process is finished.

A reduction process having an LUT as a reference can be explained with reference to FIG. 9, as follows. Referring to FIG. 9, data corresponding to the zooming ratio designated by a user (among enlargement/reduction data stored in the LUT) is read out, and converted the read-out data into data in oneline units according to a reduction rate, thereby outputting data for performing a reduction.

is 24 Real address L-DATA of the LUT stored in ROM 102 is calculated by employing the remainder calculated by step 40 of FIG. 7 (step 61). An enlargement /reduction data storing area TEMP in RAM 103 is established in (e.g. assigned address pointer) Z-ADD, and the remainder calculated by step 40 of FIG. 7 is stored in LP-WT (step 62).

In step 63, the value of the data stored in address L-DATA of the LUT is written from L DATA (calculated in step 61) to Z-ADD. Then, L-DATA and ZADD are each increased by one (step 64).

In step 65, LP-WT is decreased by one and the result is compared with zero (step 66). 1 f LP-WT value is not zero, the process returns to step 63, and if LP-CNT is zero, the data is extended by as much as the maximum number of pixels of one line in the main scan direction corresponding to a reduction rate (step 67). Thus, the operation is finished.

An enlargement process having an LUT as a reference can be explained with reference to FIG. 10, as follows. Referring to FIG. 10, data corresponding to the zooming ratio designated by a user (among enlargement/reduction data stored in the LUT) is read out, and converted the read-out data into onescanning-line data units according to an enlargement rate, thereby outputting data for performing an enlargement.

The real address (L-DATA) of the LUT stored in ROM 102 is calculated by employing the remainder calculated in step 40 of FIG. 7 (step 811). Then, an enlargement/reduction data restoring area (TEMPO) in RAM 103 isestablished in (e.g. allocated address) Z-ADD, and a reference data (VALUE) for calculating enlargement/ reduction data is set to zero. Then, the remainder calculated in step 40 of FIG. 7 is stored in LP-CNT, and temporary area (TEMP1) of RAM 103 where the corresponding LUT data of ROM 102 is established in L-ADD (step 812).

In step 813, the L-DATA calculated in step 811 is written into L-ADD, and L-DATA and L-ADD are each increased by one (step 814).

In step 815, LP-WT is decreased by one and the result is compared with zero (step 816). If LP-CNT is not zero, the process returns to step 813 so as to repeat the process until the LP-WT value reaches zero. If LP-WT is zero, the quotient calculated in step 40 of FIG. 7 is established in LP-WT and TEMP1 is established in L-ADD (step 817).

In step 818, VALUE is written into Z-ADD and Z-ADD is increased by one (step 819), and LP-WT is decreased by one (step 820) so as to determine whether the LP-WT is zero (step 821). If LP-WT is not zero, 26 the process returns to step 818, and if LP-WT is zero, the quotient calculated in step 40 of FIG. 7 is stored again in LP-WT (step 822). Then, it is determined whether L ADD is equal to VALUE (step 823).

In step 824, if L ADD is not equal to VALUE, the process returns to step 818. If L-ADD is equal to VALUE, L-ADD is increased by one in order to read the next LUT data value (step 824). Then, VALUE is written into ZADD (step 825) and Z-ADD is increased by one (step 826). Then, it is determined whether the result of subtracting TEMP1 from the current L-ADD is equal to the remainder calculated in step 40 of FIG. 7 (step 827). If the result is different from the remainder, the process returns to step 818. If the result is equal to the remainder, the data is extended by as much as the maximum number of pixels of one line in the main scan direction corresponding to an enlargement rate, by employing the enlargement /reduction data produced thus far (step 828). Thus, the operation is finished.

A simple enlargement can be explained with reference to FIG. 11, as follows. An enlargement/ reduction data area (TEMP) in RAM 103 is established in Z-ADD, and reference data (VALUE) for calculating enlargement/reduction data is set to zero (step 91). Then, the quotient calculated in step 40 of FIG. 7 is 27 stored in LP-CNT (step 92). Then, VALUE is written into Z-ADD (step 93) and the Z-ADD is increased by one (step 94).

In step 95, LP_= is decreased by one and the result is compared with zero (step 96). Then, if the result is not zero, the process returns to step 93, and if the result is zero, VALUE is increased by one (step 97). Then, the maximum number of pixels END-AD in units of one scanning line of data in the main scan direction is compared with Z-ADD (step 98). If Z-ADD is smaller than END-AD, the process returns to step 93, and if Z-ADD is greater than END-AD, the process is finished.

The enlargement /reduction method explained with reference to the flowcharts shown in FIG. 7 to FIG. 11 can be explained with regards to 85% reduction and 185% enlargement, with reference to the LUT shown in FIG. 6A and FIG. 6B, as follows. Since LUT data from 1% to 99% is sequentially stored in the LUT, the start address where the LUT data corresponding to 85; is stored has to be calculated first. When calculating the address of the LUT is completed, 85 LUT data values are read from the LUT start address corresponding to 85% into enlargement/ reduction data storing area TEMP of RAM 103 and the read data is extended to reduction data for an amount equal to one 28 scanning line, since the reduction having an LUT as a reference shown in FIG. 9 employs the LUT data without change.

Meanwhile, in 185?1; enlargement, the LUT data corresponding to 85-. is read in an arbitrary area TEMP1 of RAM 103. Then, the simple enlargement shown in FIG. 11 is performed with respect to 100-. enlargement, and the enlargement having the LUT shown in FIG. 10 as a reference is performed with respect to 85-0k enlargement.

Thus, the enlargement/reduction data is supplied from the ROM 102 or the RAM 103 to the zoom RAM 603 via buffer 606, under control of microprocessor 101. That is, when enlargement /reduction data corresponding to 4,752 (the maximum number of pixels for one scanning line in the main scanning direction at a resolution of 400 DPI) according to the zooming ratio set by the user is generated by microprocessor 101 using the LUT stored in ROM 102 and is stored in RAM 103, enlargement/reduction data is read out from RAM 103 and written into zoom RAM 603 via buffer 606. Zoom address counter 605 is for counting the image data sync signal (VCLK) in order to output data of zoom RAM 603 as an address of f irst and second line memories 601 and 602 so that enlargement /reduction can be performed with respect to the predetermined zooming R 29 ratio during a scanning operation.

As described above, an image data enlargement/reduction and circuit of the present invention in a digital image processing system performs enlargement/reduction of image data by employing a small quantity of LUT data, to thereby correspond to a broad range of enlargement/reduction requests by a user and simplify a circuit structure.

In addition, enlargement/reduction data is calculated by a microprocessor, and zooming ratio can be easily extended in accordance with a software change.

In addition, a more stable enlargement/reduction can be performed since enlargement/reduction is performed via a RAM. Further, if the RAM is replaced by one having a rapid access time, enlargement/reduction can be easily applied for high speed processing.

Furthermore, enlargement/reduction data is calculated at every point where the zooming ratio is changed and written into the enlargement /reduction RAM. Then, the data is read again and verified so as to prevent a bad copy which may be caused by a malfunction (I/0 error) of a memory device. As a result, copy cost can be curtailed and an operation state of hardware can be checked, to thereby recognize an error state.

Claims

CLAIMS:

is 1. An image data enlargement/reduction method in a digital image processing system which comprises an LUT where a small quantity of data f or use in enlargement/reduction is stored and a memory for use in enlargement /reduction, and which enlarges /reduces input image data in accordance with a user-designated zooming ratio, the method comprising the steps of:

(a) dividing the user-designated zooming ratio by one hundred percent and calculating the quotient and remainder thereof; (b) reducing image data with reference to the data stored in the LUT, if the quotient calculated in said step (a) is less than one; (c) enlarging image data with reference to the data stored in the LUT, if the quotient calculated in said step (a) is greater than one and the remainder thereof is not zero; (d) performing a simple enlargement process, if the quotient calculated in said step (a) is greater than one and the remainder thereof is zero; and (e) writing the enlargement/reduction data calculated via said steps (a) to (d) into the memory.
2. An image data enlargement /reduction method 31 according to claim 1, wherein said LUT table stores data for enlargement and reduction operations corresponding to loi through 99% ratios in steps of Ili.
3. An image data enlargement/reduction method according to claim 1, further comprising the step of reading said written enlargement /reduction data and verifying whether the read data is the same as original data.
4. An image data enlargement/reduction method according to claim 1, wherein said reduction step reads out the data corresponding to the userdesignated zooming ratio among the enlargement/reduction data stored in said LUT, converts the read-out data into one scanning line of data corresponding to the reduction rate, and calculates enlargement/reduction data for a reduction process.
5. An image data enlargement/reduction method according to claim 1, wherein said first enlargement step reads out the data corresponding to the userdesignated zooming ratio among the enlargement/reduction data stored in said LUT, converts the read-out data into one scanning line of 32 data corresponding to the enlargement rate, and calculates enlargement/reduction data for an enlargement process.

is
6. An enlargement/reduction circuit for enlarging and reducing image data input to a digital image processing system and outputting an image corresponding to a user-designated zooming ratio, the circuit comprising:

a f irst memory f or storing an LUT f or use in enlargement/reduction; a microprocessor for calculating enlargement/reduction data corresponding to the zooming ratio, using the LUT stored in said f irst memory; a second memory for temporarily storing, in the course of calculating the enlargement /reduction data by said microprocessor, the enlargement /reduct ion data of said LUT and enlargement/reduct ion data f or an amount of one line calculated from said microprocessor; first and second line memories for storing the input image data to be enlarged/reduced, in units of one scanned line, respectively; a third memory for performing enlargement/reduction by employing the k 1 is 33 enlargement/reduction data stored in said second memory; a f irst counter for counting a sync signal of the image data in order to write said one scanned line units of the image data, into predetermined addresses of said first and second line memories; a second counter for counting the sync signal of the image data in order to output the data of said third memory as addresses of said first and second line memories, so that data can be written into said third memory by said microprocessor and so that enlargement /reduction can be performed with respect to said user-designated zooming ratio during a scanning operation; and a frequency divider for f requency- dividing a line sync signal such that the read and write operations of said first and second line memories are performed alternately.
7. An image data enlargement/reduction circuit according to claim 6, further comprising: a first buffer for designating a write and readout address into said first and second line memories; a second buffer for writing image data to be enlarged/reduced into said first and second line memories; 34 a third buffer for outputting the enlarged/reduced image data read out from said first and second line memories; and a fourth buffer for allowing said microprocessor to read/write the data of said third memory.
8. An image data enlargement/reduction circuit according to claim 6, wherein said LUT table stores data for enlargement and reduction operations corresponding to 1% through 99% ratios in steps of 1'-..

is
9. An image data enlargement/reduction circuit according to claim 6, which reads out the data corresponding to the user-designated zooming ratio among the enlargement /reduction data stored in said LUT, converts the read-out data into one scanning line of data according to the reduction rate, and calculates enlargement/reduction data for a reduction process.
10. An image data enlargement/reduction circuit according to claim 6, which reads out the data corresponding to the user-designated zooming ratio among the enlargement /reduction data stored in said LUT, converts the read-out data into one scanning line of data according to the enlargement rate, and calculates enlargement/reduction enlargement process.

data for an
11. An image data enlargement/reduction circuit according to claim 10, wherein said enlargement/reduction data for said enlargement process is calculated by a simple enlargement process and an enlargement process having said LUT as a reference.
12. An image scale changing circuit comprising at least one image memory; means f or reading image data into the image memory; and means f or reading image data out of the image memory; J n which said image data is read into the image memory in a first sequence and is read out of the image memory in a second sequence, the second sequence being different to the first sequence, the relationship between the first and second sequences corresponding to the degree of scale change, and in which there are provided means for determining at least one of the sequences in dependence upon the desired scale change.