JP2829930B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus that performs image data scaling processing.

[Prior Art] Conventionally, in this type of apparatus, a main scanning variable magnification method using a memory has been proposed.

[Problems to be Solved by the Invention] However, in the conventional image data enlarging process, mere enlargement of pixel data causes a rough tone, and in the image data reducing process, image quality is deteriorated due to lack of pixel data. I was

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object of the present invention is to provide an image processing apparatus which can easily store a characteristic portion of image data to be scaled and obtain a high-quality scaled image. Things. In particular, the present invention provides an image processing apparatus that obtains a reduced image at high speed by generating the scaling process in synchronization with the input of the image data to be reduced in addition to the above in the reduction process. is there.

[Means and Actions for Solving the Problems] To solve the problems, for example, an image processing apparatus of the present invention has the following configuration. That is, in an image processing device that performs image data reduction processing, input means for inputting image data in synchronization with a predetermined clock, and addition means for cumulatively adding a reciprocal of a set reduction rate in synchronization with the clock. Between the input pixel at the position indicated by the integer part of the addition result and the pixel adjacent to the input pixel, the pixel data at the position indicated by the value after the decimal point of the addition result is based on the two input pixel data sandwiching the position. And a storage means for storing the pixel data interpolated and generated by the interpolation means as pixel data of a reduced image in a predetermined memory.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic sectional view of the image processing apparatus of the embodiment.
In the figure, reference numeral 201 denotes an image reader, which electrically reads a document image and performs scaling processing of the read image data. A printer 203 prints image data sent from the image reader 201.

In the image reader 201, an original 204 is placed on an original platen glass 203, and the original is pressed by an original presser 200. Manuscript 204
Is illuminated by a lamp 205, and the reflected light is reflected by a mirror 20.
6,207 and 208.
Image on one.

When reading the original 204, the unit of the lamp 205 and the mirror 206 is mechanically scanned in the sub-scanning direction at a speed V, and the unit of the mirrors 207 and 208 is mechanically scanned in the sub-scanning direction at a speed of 1 / 2V, respectively. Thus, the variable-magnification reading in the sub-scanning direction is performed.

That is, assuming that the value of the scanning speed V at a reading magnification of 100% (1 ×) is V ₀ , the scanning speed V at a reading magnification of m% is (1)
It is obtained by the formula.

Further, the signal processing unit 216 performs a scaling process in the main scanning direction, and sends a resulting image signal to the printer 203.

In the printer 203, the laser driver 236 operates based on an image signal from the
ON / OFF drive. The laser light emitted from the semiconductor laser element 217 forms an image on the photosensitive drum 222 via the polygon mirror 218, the f-θ lens 219, and the mirrors 220 and 221. The image formed on the photosensitive drum 222 is developed by a known electrophotographic process and visualized. That is, the photosensitive drum 22
The electrostatic latent image on 2 is developed by the developing device 223 with toner.
On the other hand, paper is supplied from the paper cassette 224 or 225,
After the sheet is timed by the registration roller 226, a toner image is transferred on the photosensitive drum 222,
The image is further conveyed by the conveyance system 227 and output after the image is fixed in the fixing unit 228.

13 (A) to 13 (D) relate to a diagram for explaining an example of image processing of the embodiment, wherein FIG. 13 (A) is a manuscript image, FIG. 13 (B) is a reduced copy image, FIG. Double copy image, same figure (D)
Indicates examples of enlarged copy images.

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment. In the figure, reference numeral 301 denotes a CPU, which performs main control of the image processing apparatus. That is, first, the designated reading magnification m% from the operation unit 312 is input via the I / O controller 311, and the sub-scanning speed V is obtained from the equation (1) according to the magnification m%. And
Through the I / O controller 311 and the motor driver 313, the sub-scanning control of the motor 314 by the speed V is performed. Also, CPU30
Reference numeral 1 reads various control parameters from the ROM table 316 in accordance with the input designated magnification ratio m%, and provides them to the following main scanning scaling processing circuit.

That is, the image signal read by the CCD 211 is supplied to the amplifier (Amp) 3
The signal is amplified at 04 and converted to an 8-bit digital signal (multi-valued image data) from white (= 255) to black (= 0) by an A / D converter (A / D) 305. The character edge judging unit 306 extracts an edge portion such as a character or a line diagram from the multi-valued image data, and outputs the extracted 1-bit EDG data and the multi-valued image data (8 bits). The scaling unit 307 alternately writes and reads a pair of EDG data and multi-valued image data to and from the RAMs 309 and 310, and performs a main scanning scaling process described later together with the control of the address controller 302. In addition, magnification unit 307
Also performs interpolation processing of image data. The filter 310 performs a filtering process on the image data that has been subjected to the scaling process, and the output is input to the laser driver 236 to obtain an output image 315.

FIG. 3 is a block diagram of the magnification unit 307 of the embodiment. In the figure, the input of the scaling unit 307 is the character edge determination unit 3
8-bit image data and EDG data 1 sent from 06
The total number of bits is 9 bits, and the output of the scaling unit 307 is also 9 bits.

VSYNC is a synchronization signal in the sub-scanning direction, HSYNC is a synchronization signal in the main scanning direction, CLK is a pixel clock signal, and VE is a signal indicating an image effective section in the main scanning direction. FIG. 5 is a timing chart of these basic signals.

Reference numerals 401, 406, 407, and 408 denote 9-bit selectors. When the selection signal S is at logic 0 level, the A side input is selected and output. When the selection signal S is at logic 1 level, the B side input is selected and output.
Reference numerals 414 and 415 denote 1-bit selectors, respectively.
Is the same as above. 402, 403, and 405 are 9-bit D-type flip-flops (DFFs).
The input data is latched at the rise of the LK signal. An interpolator 404 performs linear interpolation between two consecutive image data (including EDG data) according to an interpolation rate α. An interpolation coefficient determiner 413 generates information of the interpolation rate α (= 0 to 15) according to the parameter information from the CPU 301 corresponding to the designated scaling factor m%. Similarly, the address controller 302 controls updating of an address. Further, 409 and 411 are bi-directional buffers, 410 and 416 are inverters, and 412 is a DFF constituting a 1-bit counter.

With this configuration, the DFF 412 is reset by the VSYNC signal and thereafter inverted by the HSYNC signal. That is, when the EVEN signal is at the logic 0 level, the CCD 211 reads an odd line of the document 204 and writes the read data to the RAM 309, and reads the stored data of the even line immediately before the document 204 from the RAM 310. When the EVEN signal is at the logic 1 level, the CCD 211 reads even lines of the document 204 and writes the read data to the RAM 310, and reads stored data of the odd lines just before the document 204 from the RAM 309. Corresponding.

The MOD signal is a signal sent by the CPU 301, and is a logical 1 level signal when the image is designated to be enlarged (m> 100) and a logical 0 level when the image is designated to be reduced or equalized (m ≦ 100).

That is, at the time of specifying the enlargement of the image, the image data read by the CCD 211 is supplied to the selector 408 via the selector 408.
The data is sequentially written to the AM 309 and, in the case of an even line, to the RAM 310 as they are. On the other hand, the image data written in the RAM 309 or 310 is expanded and read out according to the enlargement factor m% via the selector 407, and these are interpolated by the interpolator 404 and output from the selector 406.

When an image is to be reduced or the same size is designated, the image output data read by the CCD 211 is decimated in accordance with the reduction ratio m%, and the data is interpolated by the interpolator 404. In the case of an even-numbered line, the data is written in the RAM 310. On the other hand, the image data written in the RAM 309 or 310 is read out via the selector 407 and further output from the selector 406.

FIG. 4 is a block diagram of the interpolator 404 of the embodiment. In the figure, reference numerals 601 to 604 denote 8-bit selectors, each of which selectively outputs an A-side input when the selection signal S is at a logic 0 level, and selectively outputs a B-side input when the selection signal S is at a logic 1 level. Reference numerals 606 to 609 denote adders, which perform (A + B) / 2 operation on the 8-bit multi-valued image data of the input terminals A and B, and output 8-bit multi-valued image data. However, fractions less than 1 are discarded.

610 is an AND gate, and 611 is an OR gate. Reference numeral 612 denotes a 1-bit selector. When the selection input S = 0, the A side input is selected.
When S = 1, the B-side input is selected and output. 613 is also 1
It is a bit selector, and when the selection input S = 2, C
Select and output the side input.

In this configuration, the input image data is the immediately preceding image data A and the current image data B. Each of the image data A and B is an 8-bit multi-valued image data A1, B1
And 1-bit EDG data A2 and B2.

Selectors 601 to 604 for multi-valued image data A1 and B1,
Linear interpolation calculation is performed by the adders 606 to 609 and the interpolation rate α (= 0 to 15). If the circuit operation is expressed by a mathematical expression, the interpolation data Y1 can be obtained by the expression (2).

However, fractions less than 1 are discarded.

On the other hand, as for the EDG data A2 and B2, one of A2 and B2 is selected based on the AND of A2 and B2, the OR of A2 and B2, or the most significant bit (bit 3) of the interpolation rate α according to the iM signal sent by the CPU 301. In this case, three types of outputs are obtained. CPU301 is the current ED
When you want to change the magnification so that G data B2 = 0 is saved, iM =
0, previous EDG data A2 = 1 or current EDG data B2
Set iM = 1 when scaling to preserve = 1. If the user wants to enlarge the magnification close to the shape of the EDG data A2 or B2 before magnification, iM = 2 is set. That is, according to equation (2), when α is small (bit3 = 0), the interpolation data Y1 is A1
The selector 612 selects A2 because it reproduces a value close to, and reproduces a value close to B1 when α is large (bit3 = 1), so that the selector 612 selects B2.

FIG. 5 is a block diagram of the interpolation coefficient determiner 413 of the embodiment. In the figure, reference numeral 103 denotes a 4-bit down counter (DCNTR). When the load input terminal L is at the logical 1 level, the value R0 of the data input terminal D is loaded by the CLK signal. Counting is performed at each rising edge of the CLK signal during the level, and when the count output becomes 0, a logical 1 level is output to the carry output terminal RC. Reference numeral 104 denotes an adder (ADD), which calculates and outputs the sum (A + B) of the input terminals A and B, and outputs a signal at the terminal C0 when a carry-out of the 14th bit (= 8192) occurs.
The carry-out signal (C0) is output to Further 105-107
Is a 1-bit DFF, 108 is a 13-bit DFF, 109 is a NAND gate, 110 is an AND gate, 111 is a 13-bit AND gate, 113,
114 is an OR gate, and 115 to 117 are inverters.

Reference numeral 101 denotes a 4-bit register (R), and reference numeral 102 denotes a 13-bit register (R). A value corresponding to the designated magnification m% is set in advance by the CPU 301 in each of them.

If the specified magnification m% is the same size or reduced (m ≦ 100),
Magnification m%, value R0 set in register 101 and register 1
There is a relationship of equation (3) with the value R1 set to 02.

However, 0 ≦ R1 ≦ 8192 (3) In the equation (3), the content of R0 functions to determine a multiple of 8192 (the number of thresholds).
It functions to divide the sections such as 1-1 / 2, 1 / 2-1 / 3, 1 / 3-1 / 4 and so on. This function is implemented on the circuit by the DCNTR1
03, AND gate 110, DFF107, etc. Further, the content of R1 functions to supplement the fine magnification in each section.

Therefore, when performing copying at the same magnification or the reduction magnification of m%, the CPU 301 pre-calculates the formula (3) and sets the values R0 and R1 as shown in Table 1 in the registers R0 and R1, respectively.

Further, when the designated magnification m% is an enlargement (m> 100), there is a relation of the equation (4) between the magnification m% and the value R1 set in the register 102.

That is, since R0 is unnecessary, 0 is set in the register 101 so that the term of R0 in the equation (3) does not function on the circuit. Therefore, when copying at the magnification of m%,
The CPU 301 obtains R1 in advance by the equation (5) and sets it in the register 102.

FIG. 6 is a block diagram of the address controller 302 of the embodiment. In the figure, reference numerals 701 to 703 denote 13-bit counters, respectively. The counter 701 generates a read address of the CCD 211. That is, while VE = 0, it is reset, and while VE = 1, it counts up sequentially by each CLK signal to generate a continuous address of 0-8191.
The counter 702 has a write address (WR) of the RAM 309 or 310.
-ADD). That is, the counter 702 counts up only in the section where VE = 1 and WCN = 1. The counter 703 generates a read address (RD-ADD) for the RAM 309 or 310. That is, the counter 703 has VE = 1 and RCN = 1.
Count up only in the section of.

FIG. 7 is a block diagram of the filter circuit 310 of the embodiment. In the figure, reference numerals 901 and 902 denote 8-bit first-in first-out memories (FIFO), each of which gives a delay of one line to input multi-valued image data. Since these are connected in series, three lines of parallel data are obtained as a result. Furthermore, 904 ~ 906,908 ~
Reference numerals 910 and 912 denote 8-bit DFFs, respectively, which latch multivalued image data in synchronization with the CLK signal.

Now, as shown in FIG. 8, considering a 3 × 3 window around X _ij with X _ij as a pixel of interest, DFF 908 is (X _{i-1, j} ), DFF 905 is (X _{i, j-1} ), DFF 909 Is (X _{i, j} ),
The DFF 912 stores (X _{i, j + 1} ), and the DFF 910 stores (X _{i + 1, j} ).

Reference numeral 913 denotes an adder, which is a sum of four input terminals A to D (A +
B + C + D). Reference numeral 914 denotes a filter operation unit.
A smoothing filter operation of (A + 4B) / 8 is performed for the input terminals A and B. Substituting pixel data in the window to this, the smoothing operation output S0 for the pixel of interest X _ij is calculated by equation (6).

Reference numeral 915 denotes a filter operation unit which performs (8B-A) / 4 edge emphasis filter operation on the two input terminals A and B. When also shown in the calculation of the pixel data in the window, edge enhancement computation output E0 of the target pixel X _ij is calculated by equation (7).

Reference numeral 903 denotes a 1-bit FIFO which delays input EDG data by one line. Further, the pixel of interest X _{ij of the} multi-valued image data is transmitted via DFF907 and 911 of each one bit.
Is synchronized with the corresponding EDG data. Selector 9
In step 16, if EDG data = 0, the multi-valued image data is not the edge portion, so the smoothing operation output S0 side is selected and output. If EDG data = 1, the multi-valued image data is the edge portion, the edge enhancement operation output E0 side is selectively output. I do.

<Operation when Magnification m% is the Same Size or Reduction> FIG. 9 is an example operation timing chart for explaining the case where the designated magnification m% is the same size or reduction.

<< Writing operation >> In this case, the writing operation is to thin out the image data read by the CCD 211 according to the magnification m%, interpolate the data, and perform RAM interpolation.
This is the operation of writing to 09 or 310.

Now, since m ≦ 100, MOD = 0. For example, assuming that the designated magnification = 42%, R1 = 1 and R1 = 3121 are set according to Table 1.

As described above, first, an LCLR signal is generated in synchronization with the rise of VE, and DCO = 0 and DAB = 0.

In the next CLK signal, DCNTR = 0 (RC = 1) and ADE
= 1 is satisfied. As a result, WEN = 1, that is, writing of image data and increment of WR-ADD become possible. AB = 3121, which does not exceed 8192 (threshold), so that C0 = 0. Since DAB = 0, the interpolation rate α = 0, and the image data Y1 = A1 is stored in the RAM 309 or 310.
Is written to.

In the next CLK signal, WR-ADD = 1. DCNTR = 1
(RC = 0), and ADE = 1 is not satisfied. As a result, WEN = 0, that is, writing of image data and incrementing of WR-ADD become impossible. DAB holds 3121, resulting in AB = 3121, but this does not exceed 8192, so C0 = 0. Α = 6 by DAB = 3121.

In the next CLK signal, WR-ADD = 1 remains. Also DCN
TR = 0 (RC = 1), which satisfies AED = 1. Thereby, WEN = 1, that is, writing of image data and WR-ADD
Can be incremented. AB = 6242, but this does not exceed 8192, so C0 = 0. Further, since α = 6, the image data A1 of the CCD-ADD (1) and the image data B1 of the CCD-ADD (2) are Y1 = ｛10 × A1 + 6.
It is interpolated at the rate of × B1｝ / 16 and written to the RAM 309 or 310.

Proceed in the same manner, and for the second CLK signal, DCNTR =
0 (RC = 1), which satisfies ADE = 1. As a result, WEN = 1, that is, writing of image data and increment of WR-ADD become possible. AB = 1117, which once exceeded 8192, and C0 = 1.
Also, since α = 12, the image data A1 of CCD-ADD (3)
And image data B1 of CCD-ADD (4) is Y1 = ｛4 × A1 + 1
Interpolation is formed at a rate of 2 × B1｝ / 16, and is written to the RAM 309 or 310.

In the next CLK signal, WR-ADD = 3. DCNTR = 1
(RC = 0), and ADE = 1 is not satisfied. As a result, WEN = 0, that is, writing of image data and incrementing of WR-ADD become impossible. For DCO, C0
As a result of holding = 1, DCO = 1.

In the next CLK signal, since DCO = 1, the enable terminal E of DCNTR103 becomes 0, and the countdown cannot be performed. That is, DCNTR = 1 (RC = 0) remains. Therefore, ADE = 1
Not satisfied. As a result, WEN = 0, that is, writing of image data and incrementing of WR-ADD become impossible.
Also, AB = 1117 remains, which does not exceed 8192, so C0 = 0.

As described above, when DCO = 1, the increment of WR-ADD is blocked (decimated) by one pixel, and the above rough sections 1 to 1/2, 1/2 to 1/3, 1/3 to 1/4 Fine reduction / magnification / reduction within an equal space is properly performed.

As described above, WR- at a rate corresponding to the values of parameters R0 and R1
ADD proceeds, and image data Y1 having an appropriate density is interpolated and written to the RAM 309 or 310 at the timing of writing the image data. Comparing this with the progress of CCD-ADD for manuscript reading, the rate of thinning is approximately 3/7 (approximately 42
%).

<< Reading Operation >> In this case, the reading operation is an operation of sequentially reading out image data written to the RAM 309 or 310 after data interpolation and thinning according to the above-mentioned magnification m% and outputting the image data to the printer.

Now, since m ≦ 100, MOD = 0. Therefore, REN is always 1, and RD-ADD simply increases for each CLK signal, similarly to CCD-ADD. The image data thus read is output via the selector 406 in FIG.

When the designated magnification m% is reduced, there is a concern that EDG data may be missing. Therefore, in order to select the OR interpolation shown in FIG.
And

<Operation When Magnification m% is Enlarged> FIG. 10 is an example of an operation timing chart for explaining a case where the designated magnification m% is enlarged.

<< Writing Operation >> The writing operation in this case is an operation of sequentially writing the image data read by the CCD 211 into the RAM 309 or 310 as it is.

Now, since m> 100, MOD = 1. Therefore, WEN is always 1, and WR-ADD simply increases with every CLK signal as in CCD-ADD. Thus, the image data sent from the CCD 211 is transferred to the RAM 309 or 3 via the selector 408 shown in FIG.
It is sequentially written to 10.

<< Read Operation >> The read operation in this case is the above-described RAM 309 or 310
This is an operation of sequentially reading out image data written as it is, interpolating the data, and outputting the data to the printer.

Now, since m> 100, MOD = 1. For example, if the designated magnification is 142%, the settings are R0 = 0 and R1 = 5769.
Also, since R0 = 0, DCNTR = 0 (RC = 1) always.

As described above, first, an LCLR signal is generated in synchronization with the rise of VE, and DCO = 0 and DAB = 0.

In the next CLK signal, ADE = 1 is satisfied. This gives AB
= 5769, but this does not exceed 8192, so C0 = 0. Also, since REN = 0, RD-ADD = 0 remains, and the image data at address 0 of the RAM 309 or 310 is read.

In the next CLK signal, DAB holds 5769 and AB = 33
It becomes 46. Since this is once over 8192, C0
= 1. Further, since α = 11, the image data A1 of RD-ADD (0) and the image data B1 of RD-ADD (0) are expressed as Y1 =
It is interpolated and formed at a rate of {5 × A1 + 11 × B1} / 16 and output from the selector 406.

In the next CLK signal, as a result of DAB holding 3346, AB = 92
Becomes 3. Since this is again over 8192, C0 = 1. Also, since α = 6, RD-A
DD (0) image data A1 and RD-ADD (0) image data
B1 is interpolated and formed at a rate of Y1 = {10 × A1 + 6 × B1} / 16 and output from the selector 406. Also, at this point, D
As a result of CO holding 1, REN = 1, that is, RD-ADD can be incremented.

In the next CLK signal, RD-ADD = 1. DAB is 923
Holds, AB = 6692. Since this does not exceed 8192, C0 = 0. Further, since α = 1, the image data A1 of RD-ADD (0) and the image data B1 of RD-ADD (1) are interpolated and formed at a ratio of Y1 = {15 × A1 + 1 × B1} / 16, and the selector Output from 406. At this time, since DCO holds 1, REN = 1, that is,
RD-ADD can be incremented.

Thus, RD-ADD proceeds at a rate according to the value of R1,
At the output timing of each image data, the image data Y1 having an appropriate density is interpolated and output from the selector 406. Comparing this with the original progress of CCD-ADD, it can be seen that the expansion rate is about 142%.

When the designated magnification m% is enlarged, in order to preserve the shape of the original image by EDG data, iM =
Let it be 2.

FIG. 11 is a flowchart of the main control of the embodiment. In the figure, in step S1301, a scaling factor m% is input from the operation unit. In step S1302, the value of m is compared with 100 to determine whether the image is enlarged, reduced or equal in size.
In the case of enlargement, data for enlargement (V, MOD, R
0, R1 etc.). Step S1 when reducing or equalizing
At 304, data for reduction or equal magnification is set. Step 1
At 305, a copy operation is performed.

[Other Embodiments] In the above embodiment, linear interpolation is adopted, but the present invention is not limited to this. For example, sinc interpolation may be used.

FIG. 14 is a block diagram of a sinc interpolator according to another embodiment. In the figure, reference numerals 1401 to 1404 denote 8-bit DFFs, each of which delays image data by one pixel. 14
05 and 1406 are 4-bit DFFs, each of which gives a delay of one pixel to the interpolation coefficient α (which may be the same as in the above embodiment).
Reference numerals 1407 to 1410 denote look-up tables (LUTs). The values of the equations (8) to (11) are calculated in advance, and the ROM (LUT) is calculated.
Is stored in

a _-2 = b _-2 × γ a _-1 = b _-1 × γ a ₀ = b ₀ × γ a ₁ = b ₁ × γ (8) Further, 1411 to 1414 are multipliers, and 1415 is an adder.
Now, when the output of DFF1401~1404 each X _{t + 1,} X _t, and _{X t-1, X t-} 2, interpolated output y _t is determined by equation (12).

_{y t = a -2 · X t} -2 + a -1 · X t-1 + a 0 · X t + a 1 · X t + 1 (12) In the above embodiment, reducing the output of the interpolator 404 magnification m
Thinned out according to%, but not limited to this.

The input of the interpolator 404 may be thinned out according to the reduction ratio m%.

[Effects of the Invention] As described above, according to the present invention, a characteristic portion of image data to be scaled can be easily stored, and a high-quality scaled image can be obtained. In particular, in the reduction process, in addition to the above, by generating the scaling process in synchronization with the input of the image data to be reduced, a reduced image can be obtained at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of the image processing apparatus according to the embodiment, FIG. 2 is a schematic sectional view of the image processing apparatus according to the embodiment, FIG. 3 is a configuration diagram of a scaling unit 307 according to the embodiment, and FIG. FIG. 5 is a block diagram of an interpolator 413 of the embodiment, FIG. 6 is a block diagram of an address controller 302 of the embodiment, and FIG. 7 is a filter of the embodiment. FIG. 8 is a block diagram of the circuit 310, FIG. 8 is a diagram showing the relationship between the pixel of interest _Xij and the pixels in the surrounding 3 × 3 window, and FIG. 9 is a diagram showing the case where the designated magnification m% is the same or reduced. FIG. 10 is an example of an operation timing chart illustrating a case where the designated magnification m% is enlarged, FIG. 11 is a flow chart of a main control of the embodiment, and FIG. 12 is a diagram of a basic timing signal. Timing chart, FIGS. 13 (A)-(D) Diagram for explaining an image processing example of 施例, FIG. 14 is a block diagram of a sinc interpolator according to another embodiment. In the figure, 211 ... CCD, 236 ... Laser driver, 301 ... CP
U, 304: Amplifier (Amp), 305: A / D converter (A / D),
306: Character edge determination unit, 307: Magnification unit, 308: Fluid circuit, 309, 310 RAM, 311 I / O controller, 312 Operation unit, 313 Motor driver, 314
Motor, 316 ... ROM table.

──────────────────────────────────────────────────続 き Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/387-1/393 G06T 3/00

Claims (5)

(57) [Claims] 1. An image processing apparatus for reducing image data, comprising: input means for inputting image data in synchronization with a predetermined clock; and cumulative addition of a reciprocal of a set reduction ratio in synchronization with the clock. Adding means, between an input pixel at a position indicated by an integer part of the addition result and a pixel adjacent to the input pixel, pixel data at a position indicated by a value after the decimal point of the addition result, two input pixels sandwiching the position An image processing apparatus comprising: an interpolating unit that generates an interpolation based on data; and a storage unit that stores pixel data interpolated and generated by the interpolating unit in a predetermined memory as pixel data of a reduced image. 2. The apparatus according to claim 1, wherein said interpolation means generates the pixel data at the position indicated by the decimal point by linearly interpolating two input pixel data sandwiching the position. Image processing device. 3. An image processing apparatus for performing image data enlargement processing, comprising: input means for inputting image data in synchronization with a predetermined clock; and storage means for storing the input image data in a predetermined memory. Adding means for accumulatively adding the reciprocal of the enlargement ratio in synchronization with the clock; and reading out data from the memory for two pixels of a pixel at an address position indicated by an integer part of the addition result and a pixel adjacent to the pixel. Reading means; and interpolating means for interpolating and generating pixel data at a position indicated by a value less than the decimal point of the addition result between the two pixel data read by the reading means, based on the two pixel data sandwiching the position. Output means for outputting pixel data interpolated and generated by said interpolation means as pixel data of an enlarged image. 4. The image according to claim 3, wherein said interpolation means generates pixel data at the position indicated by the decimal point by linearly interpolating two input pixel data sandwiching the position. Processing equipment. 5. An image processing apparatus for performing image data reduction processing, comprising: input means for inputting image data in synchronization with a predetermined clock; and a first thinning interval indicating a basic thinning interval based on a reciprocal value of a set reduction ratio. Setting means for setting a second value for adjusting the thinning interval; and address generating means for updating the write address of the reduced image by counting the first value in synchronization with the clock. The second value is cumulatively added in synchronization with the clock. When the cumulative value exceeds a value corresponding to the distance between pixels of the input image, a carry signal is output, and the carry signal is transmitted to the address generating means. Adding means for outputting a signal for temporarily stopping, and adding by the adding means between two consecutive pixel data inputted at the timing of addition by the adding means Interpolated pixel generating means for generating interpolated pixel data at a position corresponding to a value; outputting interpolated pixel data by said interpolated pixel generating means to a predetermined memory as pixel data of a reduced image in accordance with an address position generated by said address generating means An image processing apparatus comprising: