JPH0364165A - Picture processing unit - Google Patents

Abstract

PURPOSE:To prevent the deterioration in a picture quality in the reduction processing by outputting a carry signal when a prescribed number is integrated and an addition output exceeds a threshold level and resulting that an input picture data is further taken as an object of interleave processing by one picture element. CONSTITUTION:A sub operation speed V is obtained in response to a designated read magnification m% to apply the sub operation control of a motor 314 depending on the speed V, a CPU 301 reads various control parameters from a ROM table 316 in response to the designated magnification m% and gives them to a main scanning magnification processing circuit 307. In the reduction processing of a picture data, a prescribed number is integrated and when the sum output exceeds a threshold level, a carry signal output, resulting that the input picture data is taken up as an object of interleave processing further by one picture element thereby applying proper interleaving in response to the reduction rate m%. Thus, a picture processing unit is obtained, in which no deterioration in the picture quality attended with the magnification is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that performs scaling processing on image data.

[Prior Art] Conventionally, a main scanning magnification method using a memory has been proposed for this type of device.

[Problems to be Solved by the Invention] However, in conventional image data enlargement processing, the gradation becomes rough due to the mere stretching of pixel data, and in image data reduction processing, image quality may deteriorate due to missing pixel data. Deterioration had occurred.

The present invention eliminates the drawbacks of the prior art described above, and its purpose is to provide an image processing device that does not cause deterioration in image quality due to scaling.

[Means and effects for solving the problem] In order to achieve the above object, the image processing device of the present invention performs image data reduction processing, and the image processing device performs cumulative addition of a predetermined number of data to obtain the addition output. The outline of the present invention is to include an addition means for outputting a carry signal when a threshold number is exceeded, and a thinning means for subjecting the input image data to further one-pixel thinning processing when the carry signal is outputted. do.

As a result, appropriate thinning is performed according to the reduction ratio.

Preferably, there is also a storage means for sequentially storing two or more consecutive input image data, and an interpolation method for sequentially forming interpolation data based on the image data of the storage means and using this as input image data of the thinning means. The outline is to further provide means.

Thereby, the output is reproduced by interpolated data.

Preferably, the interpolation means forms interpolated data at a rate corresponding to the addition output of the addition means. As a result, appropriate interpolation data is formed according to the reduction ratio.

Further, in order to achieve the above object, the image processing apparatus of the present invention includes a storage means for storing image data and a number based on the reciprocal of the enlargement magnification ratio. The outline of the present invention is to include an adding means for outputting a carry signal when the addition output exceeds a threshold number, and an updating means for updating the read address of the storage means when the carry signal is output. As a result, appropriate enlargement is performed according to the enlargement ratio.

Preferably, the apparatus further includes an interpolation means for forming interpolation data based on the image data read from the storage means and outputting the image data. Thereby, the output is reproduced by interpolated data.

Preferably, the interpolation means forms interpolated data at a rate corresponding to the addition output of the addition means. As a result, appropriate interpolation data is formed according to the enlargement ratio.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic cross-sectional view of the image processing device of the embodiment. In the figure, 201 is an image league, which electrically reads a document image and performs scaling processing on the read image data. A printer 203 prints image data sent from the image reader 201.

In the image reader 201, a document 204 is placed on a document table glass 203, and the document presser 200 is pressed against the document 204. An image of the original 204 is illuminated by a lamp 205, and the reflected light is guided by mirrors 206, 207 and 208, and is imaged on a CCD 211 via a lens 210.

When reading the original 204, the lamp 205 and mirror 2
Unit 06 has a speed V and mirrors 207 and 20
Units 8 are each mechanically scanned in the sub-scanning direction at a speed of 1/2V, and by making this scanning speed (2) variable, variable-magnification reading in the sub-scanning direction is performed.

That is, if the value of the scanning speed V when the reading magnification is 100% (same magnification) is vo, then the scanning speed V when the reading magnification is m% is (1
) can be found using the formula.

The signal processing unit 216 also performs magnification processing in the main scanning direction and sends the resulting image signal to the printer 203.

In the printer 203, the laser driver 236 drives the semiconductor laser element 217 ON10FF based on the image signal from the image reader 201. The laser beam emitted from the semiconductor laser element 217 passes through the polygon mirror 21
8. An image is formed on a photosensitive drum 222 via an f-θ lens 219 and mirrors 220 and 221. Photosensitive drum 222
The image formed thereon is developed and visualized using a known electrophotographic process. That is, the electrostatic latent image on the photosensitive drum 222 is developed with toner by the developing device 223. On the other hand, paper is supplied from the paper cassette 224 or 225, and after being timed by the registration rollers 226, the toner image is transferred onto the photosensitive drum 222, and further transported by the transport system 227, and then transferred to the fixing unit 228. After the image is fixed at , it is output.

13(A) to 13(D) are diagrams explaining an example of image processing in the embodiment, in which (A) is an original image, (B) is a reduced copy image, and (C) is an equivalent image. Double copy image, same figure (D)
1 and 2 respectively show examples of enlarged copy images.

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment. In the figure, a CPU 301 performs main control of the image processing apparatus. That is, first input the specified reading magnification m% from the operation unit 312 via the I10 controller 311,
The sub-scanning speed (■) is determined by equation (1) according to the magnification m%. Then, the sub-scanning control of the motor 314 is performed using the speed 2 via the I10 controller 311 and the motor driver 313. In addition, the CPU 301 inputs the specified magnification m.
%, various control parameters are read from the ROM table 316 and provided to the following main scanning magnification processing circuit.

That is, the image signal read by the CCD 211 is sent to the amplifier (A
mp) 304, and is amplified by an A/D converter (A/D) 30.
5, each signal is converted into an 8-bit digital signal (multivalued image data) ranging from white (=255) to black (=0). A character edge determination unit 306 extracts edge portions of characters, line drawings, etc. in multivalued image data, and outputs the extracted 1-bit EDG data and the multivalued image data (8 bits). The scaling unit 307 alternately writes and reads pairs of ED'G data and multivalued image data into and from the RAMs 309 and 310, and performs main scanning scaling processing, which will be described later, in conjunction with the control of the address controller 302. The scaling unit 307 also performs interpolation processing on image data. The filter 310 performs filter processing on the scaled image data, and its output is manually input to the laser driver 236 to obtain an output image 315.

FIG. 3 is a block diagram of the magnification changing section 307 of the embodiment. In the figure, the input to the scaling section 307 is a total of 9 bits consisting of 8 bits of multivalued image data sent from the character edge determining section 306 and 1 bit of EDG data, and the output of the scaling section 307 is also 9 bits.

VSYNC is a synchronization signal in the sub-scanning direction, H3YNC is a synchronization signal in the main-scanning direction, CLK is a pixel clock signal, and VE is a signal indicating an image valid section in the main-scanning direction. FIG. 5 is a timing chart of these basic signals.

Furthermore, 401, 406, 407, and 408 are 9-bit selectors, respectively, and when the selection signal S is at logic O level, A
Personal power is selected and output, and when the logic level is 1, B personal power is selected and output. Reference numerals 414 and 415 each indicate a 1-bit selector, and their relationship with the selection signal S is the same as described above. 40
2,403.degree. 405 are 9-bit D-type flip-flops (DFF), each of which latches input data at the rising edge of each CLK signal. An interpolator 404 performs linear interpolation between two consecutive image data (including EDG data) according to an interpolation rate α.

413 is an interpolation coefficient determiner, which determines the interpolation rate α according to the parameter information corresponding to the designated scaling factor m% from the CPU 301.
(=0 to 15) information is generated. Similarly, the update of the address in the address controller 302 is controlled. Further, 409, 411 are bidirectional buffers, 410, 41
6 is an inverter, and 412 is a DFF constituting a 1-bit counter.

Due to the configuration, the DFF 412 is reset by the VSYNCS signal and then inverted by the H6YNC signal. That is, when the EVEN signal is at the logic 0 level, the CCD 211 reads odd lines of the original 204, writes the read data to the RAM 309, and reads the stored data for the immediately preceding even line of the original 204 from the RAM 310. When the EVEN signal is at logic 1 level, the C0D 211 reads even lines of the original 204, writes the read data to the RAM 310, and reads the stored data for the odd line immediately before the original 204 from the RAM 309. handle.

The MOD signal is a signal sent by the CPL 1301, and is a logic 1 level signal when image enlargement is specified (m>100), and is a logic O level signal when image reduction or equal size is specified (m≦100).

That is, when specifying image enlargement, the image data read by the CCD 211 is transferred via the selector 408 to the RAM 309 for odd lines, and to the RAM 3 for even lines.
10, each one is sequentially written as is. On the other hand, the image data written in the RAM 309 or 310 is
The data is enlarged and read out via the selector 407 according to the magnification factor m%, interpolated with data by the interpolator 404, and output from the selector 406.

In addition, when specifying image reduction or same size, the image data read by the CCD 211 is thinned out according to the reduction magnification m%, data is interpolated by the interpolator 404, and the selector 4
08, the data is written to the RAM 309 when the line is an odd number, and to the RAM 310 when the line is an even number.

On the other hand, the image data written in the RAM 309 or 310 is read out via the selector 407 and further outputted from the selector 406.

FIG. 4 is a block diagram of the interpolator 404 of the embodiment. In the figure, 8-bit selectors 601 to 604 select and output A inputs when the selection signal S is at a logic 0 level, and select and output B inputs when the selection signal S is at a logic 1 level. 606 to 609 are adders, and input terminals A,
For each 8-bit multivalued image data of B, (A+B)/
2 is performed and 8-bit multivalued image data is output. However, numbers less than 1 are rounded down.

610 is an AND gate, and 61■ is an OR gate. 6
Reference numeral 12 denotes a 1-bit selector, which selects and outputs A inputs when S=O, and B inputs when S=1. 6
Reference numeral 13 designates a 1-bit selector, which selects and outputs the C side input when the selection force S=2.

In this configuration, the input image data is image data A at the previous point in time and image data B at the current point in time. Each image data A%B is 8-bit multivalued image data At, B, respectively.
l and 1 bit EDG data A2. I have been admonishing this since B2.

For multivalued image data Al and BL, selectors 601~
604, adders 606 to 609, and interpolation rate α (=0 to
15) performs linear interpolation calculation. If the circuit and operation are expressed mathematically, the interpolated data Y1 can be found by equation (2).

1 6 16 (2) However, numbers less than 1 are rounded down.

On the other hand, EDG data A2. For B2, CPU30
From the iM times signal sent by 1, AND of A2 and B2, OR1 of A2 and B2, or the most significant bit (bit 3) of interpolation rate α
Accordingly, three outputs are obtained when either A2 or 82 is selected. When the CPU 301 wants to change the magnification so as to save the current EDG data B2=0, it sets iM=o.

When changing the magnification to save the previous EDG data A2:1 or the current EDG data B2=1, i M =
Set to 1. Further, when it is desired to change the size to approximate the shape of the EDG data A2 or B2 before changing the size, set i M = 2. That is, according to equation (2), interpolated data Y1 is
When α is small (bit3=o), the selector 612 selects A2 because it reproduces a value close to A1, and when α is large (b
When it3=1), the selector 612 selects B2 because a value close to B1 is reproduced.

FIG. 5 is a block diagram of the interpolation coefficient determiner 413 of the embodiment. In the figure, 103 is a 4-bit down counter (DCNTR), and when its load input terminal is at logic 1 level, the value RO at the data input terminal is loaded by the CLK signal, and after that, the enable terminals are at logic 1 level. During the level, it counts down at each rising edge of the CLK signal, and when the count output becomes O, it outputs a logic 1 level to the carry output terminal RC.

104 is an adder (ADD) and has an input terminal A.

The sum of B (A+B) is calculated and output, and when the 14th bit (=8192) carries out, it is output to terminal C.
A carry-out signal (Co) is output to O. 10 more
5 to 107 are 1-bit DFFs, 108 is a 13-bit DFF, 109 is a NAND gate, 110 is an AND gate, 111 is a 13-bit AND gate, 113, 11
4 is an OR gate, and 115 to 117 are inverters.

Also, 101 is a 4-bit register (R), and 102 is 13
This is a bit register (R), and each register is preset by CPU3.
A value corresponding to the specified magnification m% is set from 01.

If the specified magnification m% is equal to or reduced (m≦100),
There is a relationship expressed by equation (3) between the magnification m%, the value RO set in the register 101, and the value R1 set in the register 102.

Set the values RO and R1.

Table 1 However, O≦R1≦8192 In formula (3), the contents of RO function to determine the multiple of 8192 (threshold number), and roughly 1 to 1/2 of the specified magnification m%, 1/2~1/3.1/3~1/4
It functions to separate sections such as. Note that this function is implemented by DCNTR 103 and AND gate 110 in Figure 5 on the circuit.
．． This is handled by DFF107 and others. Furthermore, the contents of R1 function to supplement the minute magnification within each section.

Therefore, when copying is performed at the same magnification or reduction magnification m%, the CPU 301 back-calculates equation (3) in advance and stores the specified magnification m% as shown in Table 1 in registers RO and R1, respectively. ), the magnification m% and register 102
There is a relationship expressed by equation (4) between the value R1 and the value set to R1.

That is, since RO is unnecessary, O is set in the register 102 so that the RO term in equation (3) does not function on the circuit. Therefore, when copying is performed at an enlargement ratio of m%, the CPU 301 calculates R1 in advance using equation (5) and sets it in the register 102.

m (5) FIG. 6 is a block diagram of the address controller 302 of the embodiment. In the figure, 701 to 703 are each 13-bit counters. Of these, counter 701 is CCD2
11 read addresses are generated. That is, while VE=0, it is reset, and while VE=1, it sequentially counts up by each CLK signal to generate consecutive addresses from 0 to 8191. Also, the counter 702 is stored in the RAM 30.
A write address (WR-ADD) of 9 or 310 is generated. That is, counter 702 has VE=1 and WCN
Count up only in the section where =1. Also counter 7
03 is the read address (RD
-ADD). That is, the counter 703 has VE=
1 and counts up only in the section where RCN=1.

FIG. 7 is a block diagram of the filter circuit 310 of the embodiment. In the figure, 8-bit first-in first-out memories (FIFO) 901 and 902 each provide a delay of one line to the input multivalued image data. Since these are connected in series, three lines of parallel data are obtained as a result. Furthermore, 90
4 to 906, 908 to 910, and 912 are 8-bit DFFs, each of which latches multivalued image data in synchronization with the CLK signal.

Now, as shown in Figure 8, if we consider XIJ as the pixel of interest and a 3x3 window around it, the DFF90g is (
X, -1,,) DFF905 is (XI, J-1)
DFF909 is (Xl, J) DFF912 is (Xl, J
), and DFF910 (Xl+1.J) are stored respectively.

913 is an adder, which calculates the sum of 4 input terminals A-D (A+
Take B+C+D). 914 is a filter calculation unit;
A smoothing filter calculation of (A+4B)/8 is performed for two input terminals A and B. By substituting the pixel data within the window into this, the smoothing calculation output SO for the pixel of interest Xlj is determined by equation (6).

(6) 915 is also a filter computing unit, and has two input terminals A,
For B, an edge enhancement filter calculation of (8B-A)/4 is performed. Similarly, when calculating the pixel data within the window, the edge enhancement calculation output EO for the pixel of interest XI is determined by equation (7).

(7) Also, 903 is a 1-bit FIFO, and the manual ED
A delay of one line is given to the G data. Further, the target pixel X1J of the multivalued image data and the corresponding EDG data are synchronized via DFFs 907 and 911 each having one bit.

In the selector 916, if EDG data = O, the multivalued image data is not an edge part, so the smoothing calculation output SO side is selected and output, and if EDG data = 1, the multivalued image data is an edge part, so the edge enhancement calculation output EO side is selected. Output.

Operation when the designated magnification m% is equal to or reduced> FIG. 9 is an exemplary operation timing chart illustrating a case where the designated magnification is equal to or reduced.

(Write Operation) The write operation in this case is an operation in which the image data read by the C0D 211 is thinned out according to the magnification m%, the data is interpolated, and the data is written to the RAM 309 or 310.

Now, since m≦100, MOD=O. For example, if the specified magnification = 42%, then from Table 1, RO = 1. R1=
The setting will be 3121.

As described above, the LCLR signal is first generated in synchronization with the rise of VE, and DCO=O and DAB=0.

In the next CLK signal, DCNTR=O (RC=1) and ADE=1 is satisfied. As a result, WEN=1,
That is, it becomes possible to write image data and increment WR-ADD.

Also, AB=3121, which is 8192 (threshold)
Since it does not exceed , C0=O. Also, since DAB=O, the interpolation rate α=0, and the image data Y1=A1 is written to the RAM 309 or 310.

In the next CLK signal, WR-ADD=1. Also D
CNTR=1 (RC=O), and ADH=1 is not satisfied. As a result, WEN=01, that is, writing of image data and incrementing of WR-ADD are disabled. Also, as a result of DAB holding 3121, AB=31
21, but this still does not exceed 8192, so C
0=0. Also, since DAB=3121, α=6.

In the next CLK signal, WR-ADD=1 remains. Also, DCNTR=C1 (RC=1), and ADE=
1 is satisfied. This allows WEN=l, that is, writing image data and incrementing WR-ADD. Again, AB=6242, which is still 81
Since it does not exceed 92, C0=O. Also, since α=6, image data A1 of CCD-ADD (1) and image data B1 of CCD-ADD (2) are Y1=
It is interpolated and formed at a rate of (10XA1+6XB1)/16 and written to the RAM 309 or 310.

Proceeding in the same manner, and at the second CLK signal, DCN
TR=O (RC=1) and ADH=1 is satisfied.

As a result, WEN=1°, that is, it becomes possible to write image data and increment WR-ADD. Also A
Since B=1171, which partially exceeds 8192, C0=1. Also, since α=12, the image data AI and CCD of C0D-ADD (3)
-ADD Image data B1 of (4) is Y1= (4X
Interpolated at the ratio of A1+12XB1)/16, RA
Written to M309 or 310.

For the next (7) CLK signal, W R-A DD = 3
4. :Become. Also, DCNTR=1 (RC=O), and ADH=1 is not satisfied. As a result, WEN=O1
That is, writing of image data and incrementing of WR-ADD become impossible. Also, for DCO, CO=
As a result of holding 1, DCO=1.

On the next CLK signal, because DCO=1, DCNT
Enable terminal E of R103 becomes O, and countdown cannot be performed. That is, DCNTR=1 (RC=O) remains. Therefore, ADH=1 is not satisfied. As a result, WEN=O1, that is, image data writing and WR-A
DD cannot be incremented. Also AB=117
Since it remains 1 and does not exceed 8192, C0
=O.

In this way, when DCO = 1, the increment of WR-ADD is blocked (thinned) by one pixel, and the above rough sections 1 to 1/2, 1/2 to 1/3, 1/3 to 1/4
Fine reduction and scaling within the same area is performed appropriately.

As described above, WR-ADD progresses at a rate according to the values of the parameters RO and R1, and at the timing of writing image data, image data Y1 of appropriate density is interpolated and written to the RAM 309 or 310. Comparing this with the progress status of C0D-ADD for document reading, it can be seen that the thinning ratio is approximately 3/7 (approximately 42%).

(Reading Operation) The reading operation in this case is an operation of sequentially reading the image data written in the RAM 309 or 310 through data interpolation and thinning according to the above-mentioned magnification m% and outputting it to the printer.

Now, since m≦100, MOD=O. Therefore, REN=1 always, and RD-ADD is CCD-AD
Like D, it simply increases for each CLK signal. The image data thus read out is output via the selector 406 in FIG. 3.

In addition, if the specified magnification m% is reduction, there is a concern that EDG data may be missing, so in order to select the OR interpolation shown in Figure 4, i
Let M = 1.

<Operation when magnification m% is enlargement> FIG. 10 is an exemplary operation timing chart illustrating a case where designated magnification m% is enlargement.

(Write Operation) The write operation in this case is an operation of sequentially writing the image data read by the C0D 211 into the RAM 309 or 310 as is.

Now, since m>100, MOD=1. Therefore, WEN=1 always, and WR-ADD is CCD-AD
Like D, it simply increases for each CLK signal. thus,
The image data sent from the C0D 211 side is sequentially written into the RAM 309 or 310 via the selector 408 in FIG.

(Reading Operation) The reading operation in this case is an operation of sequentially reading out the image data written as is in the RAM 309 or 310 described above, interpolating the data, and outputting the interpolated data to the printer.

Now, since m>100, MOD=1. For example, if the specified magnification = 142%, RO = 0, R1 = 576
9(7) setting. Also, since RO = 0, Luke is always D
CNTR=O (RC=1).

As described above, the LCLR signal is first generated in synchronization with the rise of VE, and DCO=O and DAB=0.

The next CLK signal satisfies ADH=1.

This results in AB=5769, which does not exceed 8192, so C0=O. Also, since REN=O, RD-ADD=O remains, and the image data at address O of the RAM 309 or 310 is being read.

In the next CLK signal, DAB holds 5769, resulting in AB=3346. Since this partially exceeds 8192, co=i. Also, since α=11, image data A1 and RD of RD-ADD(0)
-ADD (0) image data B1 is Y1= (5X
A1+I LXB 1) /16 is interpolated and output from the selector 406.

In the next CLK signal, DAB holds 3346, resulting in AB=923. Since this exceeds 8192 once again, C0=1. Also, since α=6, the image data A1 of the same < RD-ADD (0) and the image data B1 of RD-ADD (0) are Y1=
It is interpolated and formed at a ratio of (10XA1+6XB1)/16 and output from the selector 406. Also, at this point, as a result of DCO holding 1, REN=1, that is, R
D-ADD can be incremented.

In the next CLK signal, RD-ADD=1. Also D
As a result of AB holding 923, AB=6692.

Since this does not exceed 8192, C0=O. Also, since α=1, image data A1 of RD-ADD (0) and image data B1 of RD-ADD (1) are interpolated at a ratio of Y1 = (15XA1 + IXB1)/16 and output from the selector 406. Ru.

Also, since DCO holds l at this point, R
EN=1, ie RD-ADD increment is possible.

In this way, RD-ADD progresses at a rate according to the value of R1, and image data Y1 of appropriate density is interpolated and output from the selector 406 at the output timing of each image data. Comparing this with the progress status of the original C0D-ADD, it can be seen that the enlargement rate is approximately 142%.

In addition, when the specified magnification m% is enlargement, in order to preserve the shape of the original image using EDG data, i
Let M = 2.

FIG. 11 is a flowchart of the main control of the embodiment. In the figure, in step 51301, the magnification ratio m% is input from the operation unit. In step 51302, the value of m is set to 1.
00 to determine whether it is enlarged, reduced, or the same size. When enlarging, the data for enlarging (V, MOD, RO, R1, etc.) is -t='z in step S1303.

If the size is reduced or the same size, data for reduction or equal borrowing is set in step 51304. In step 51305, a copy operation is performed.

[Other Embodiments] Although linear interpolation is used in the above-mentioned flow, the present invention is not limited to this. For example, 5-inch interpolation may be used.

FIG. 14 is a block diagram of a 5-inch interpolator according to another embodiment. In the figure, 8-bit DFFs 1401 to 1404 each provide a delay of one pixel to the image data.

1405 and 1406 are 4-bit DFFs, which give a delay of one pixel to each interpolation coefficient α (which may be the same as in the above embodiment). Reference numerals 1407 to 1410 are look-up tables (LUTs) in which the values of equations (8) to (11) are calculated in advance and stored in the ROM (LUT).

a -, : b-, xγ a -, :: b-, xγ a a ” t) o Xγ a, = b, Xγ (8) However, 6 4 Furthermore, 1411 to l are adders. Now, When the outputs of are respectively Xt+ll, the interpolation output is yt:a-2"Xt-z + a O. z and (12)
It can be found by the formula.

+a-8・X,-.

10a + ・Xt+ (l 2) In the above embodiment, the output of the interpolator 404 is reduced by the reduction magnification m
It was thinned out according to the percentage, but it is not limited to this.

The input of the interpolator 404 may be thinned out according to the reduction magnification m%.

[Effects of the Invention] As described above, according to the present invention, there is no deterioration in image quality when changing the size of an image.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an image processing device according to an embodiment, FIG. 2 is a schematic sectional view of an image processing device according to an embodiment, FIG. 3 is a block configuration diagram of a variable magnification unit 307 according to an embodiment, and FIG. FIG. 5 is a block diagram of the interpolation coefficient determiner 413 of the embodiment. FIG. 6 is a block diagram of the address controller 302 of the embodiment. FIG. 7 is a block diagram of the address controller 302 of the embodiment. A block configuration diagram of the filter circuit 310. FIG. 8 is a diagram showing the relationship between the pixel of interest FIG. 10 is an example operation timing chart explaining the case where the specified magnification m% is enlargement. FIG. 11 is a flowchart of the main control of the embodiment. FIG. 12 is an example of the basic timing signal. Timing chart, FIGS. 13(A) to 13(D) are diagrams for explaining an example of image processing according to the embodiment, and FIG. 14 is a block diagram of a 5-inch interpolator according to another embodiment. In the figure, 211...CCD, 236...Laser driver, 301-CPU, 304-...Amplifier (Amp) 3
05-A/D converter (A/D), 306...Character edge determination section, 307...Scaling section, 308...Filter circuit, 309.310-RAM, 311...I1
0 controller, 312... operation unit, 313... motor driver, 314... motor, 316... RO
This is an M table. Figure 8 Figure 11 Figure 13 (A) Figure 13 (D)

Claims (6)

[Claims] (1) In an image processing device that performs image data reduction processing, an adding means that cumulatively adds a predetermined number and outputs a carry signal when the added output exceeds a threshold number; and the carry signal is output. An image processing apparatus characterized by comprising a thinning means for further subjecting input image data to one pixel thinning processing. (2) storage means for sequentially storing two or more consecutive input image data; and an interpolation means for sequentially forming interpolation data based on the image data in the storage means and using this as input image data for the thinning means. The image processing apparatus according to claim 1, further comprising: (3) The image processing apparatus according to claim 2, wherein the interpolation means forms interpolated data at a rate corresponding to the addition output of the addition means. (4) In an image processing device that performs enlargement processing of image data, a storage means for storing image data and a carry signal are generated when the addition output exceeds a threshold number by cumulatively adding a number based on the reciprocal of the enlargement magnification ratio. An image processing apparatus comprising: an adding means for outputting the carry signal; and an updating means for updating the read address of the storage means in response to the output of the carry signal. (5) The image processing apparatus according to claim 4, further comprising interpolation means for forming interpolation data based on the image data read from the storage means and outputting the image data. (6) The image processing apparatus according to claim 5, wherein the interpolation means forms interpolated data at a rate corresponding to the addition output of the addition means.