JP3003133B2 - Image outline extraction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital copying machine, a facsimile, and the like, in which an original is optically scanned while sequentially moving a scanning line, and image information is obtained in predetermined pixel units. An image processing apparatus comprising an image reading means for reading image data, and performing processing of image information sequentially read in pixel units by the image reading means.
The present invention relates to an image outline extracting device that extracts an outline of an image drawn on a document.

2. Description of the Related Art In an image processing apparatus such as a digital copying machine, an image drawn on a document can be variously converted and reproduced on a recording sheet. Then, functions such as image reproduction using only the outline (white characters or the like) or image reproduction by adding the extracted outline to the original image (thickening the image) have been realized. .

Here, in such an image processing apparatus, an image outline extracting apparatus for extracting an outline of an image drawn on a document is conventionally disclosed in, for example, JP-A-63-67872. There is something like that. This is because, in the process of optically scanning an original by an image sensor while sequentially moving a scanning line to obtain image data in a predetermined pixel unit, a level change of image data in a scanning direction in each scanning line is detected, and the change is detected. An outline drawing having a predetermined pixel width is generated starting from a point. That is, a line image is formed in the scanning direction (main scanning direction) of each scanning line from the changing point of the image data.

[Problems to be Solved by the Invention] As described above, in a conventional image outline extracting apparatus which detects a change point of image data only in the main scanning direction and forms a line image in the main scanning direction from the change point. If the edge portion of the image drawn on the original is parallel or nearly parallel to the scanning line, the outline at the parallel image edge is not extracted, or
The outline becomes thinner than other image edges.

This is because the change point of the image data is detected only in the direction along the scan line, so that the change point is not detected at the image edge parallel to this scan line. In addition, in a state where the image edge portion is not completely parallel to the scan line but close to the scan line, the movement pitch of the scan line is constant. It is because it becomes less.

Therefore, an object of the present invention is to provide an image outline extracting device that can appropriately extract an edge portion of an image drawn on a document as an outline.

[Means for Solving the Problems] As shown in FIG. 1, the present invention optically scans a document 1 while sequentially moving (S) a scanning line L to read image information in predetermined pixel units. Image reading means 2;
In an image outline extracting apparatus applied to an image processing apparatus for processing image information sequentially read in pixel units by the image reading means 2, a technical means for solving the above problem is shown in FIG. As shown in a), a main scanning direction edge detecting means 3 for detecting a boundary point between an image part I and a non-image part NI on each scanning line L based on image information read by the image reading means 2; A sub-scanning direction edge detecting means 4 for detecting a boundary point between the image portion I and the non-image portion NI at each pixel position in the moving direction (S) of the scanning line L based on the read image information; It is assumed that the apparatus includes an outline detection unit 3 and an outline generation unit 5 that generates an outline image having a predetermined pixel width from the boundary points detected by the sub-scanning direction edge detection unit 4.

In order to easily realize real-time processing synchronized with reading by performing processing in the same direction as the document scanning direction in the image reading means 2, as shown in FIG. Is a main scanning direction edge detecting means 3
The main scanning direction outline image means 5a for generating an outline image in the scanning direction (Sm) with respect to the boundary point detected by the sub-scanning direction edge detection means 4 It is also assumed that the apparatus includes a sub-scanning direction outline image generating means 5b for generating an outline image in the scanning line moving direction (Ss). According to the present invention, the outline drawing is generated in the reading scanning direction (Sm) and the scanning line moving direction (Ss), respectively. The outline drawing generated in the reading scanning direction (Sm) and the scanning line moving direction (Ss) are generated. In particular, in order to ensure continuity at the corners of the image with the drawn outline drawing, the sub-scanning outline drawing generation means 5b
The boundary point from the line drawing portion to the non-line drawing portion at each pixel position in the scanning line movement direction (Ss) of the outline drawing generated in (3) is also targeted (claim 3).

Further, the sub-scanning direction edge detecting means 4 recognizes the non-image part NI as a boundary point at a change position from the image part I to the non-image part NI. Regarding the outline image generated by the outline image generation means 5a in the main scanning direction, if the outline image partial pixel is recognized as a boundary point, the image portion and the reading scanning direction (Sm In particular, from the viewpoint of preventing the generated outlines in the scanning line moving direction (Ss) from being shifted from each other in the generated outlines, the main scanning direction edge detecting means 3 particularly includes the target scanning line and the one scanning line before the target scanning line. Logical OR data on the image I and the non-image of the same pixel may be used as the target image information on the line of interest.

In addition, when an outline drawing in the scanning line moving direction is generated together with the movement of the scanning line by the image reading unit 2,
During the process, each pixel position (for example, 48
It is necessary to constantly monitor to what extent the outline is generated for about 00 dots), but in order to easily realize this, in particular, as shown in FIG. The scanning direction outline drawing generating means 5b is used when the boundary point is detected in the course of scanning the original by the line memory 5b-1 having a storage address corresponding to each pixel position on the scanning line L and the image reading means 2. Line memory 5b-1
And a pixel width setting means 5b-2 for setting a numerical value corresponding to the pixel width of the outline drawing to be generated at each storage address, and a numerical value is set in the line memory 5b-1 for each scanning line from the boundary point. A unit image generating means 5b-3 for generating a unit image for a pixel corresponding to an address, and a value of a corresponding address in the line memory 5b-1 when a unit image is generated by the unit image generating means 5b-3. Numerical value correcting means 5b-4 for correcting the pixel width so as to reduce by one line is provided (claims 1 and 2).

In order to generate an outline drawing with a well-balanced line width according to the size of an image (characters or the like) drawn on the original, the outline generation means 5 in FIG. It may have a line width setting means capable of changing and setting the pixel width.

FIG. 1A shows an image processing apparatus in which the image reading means 2 has a function of reading not only the presence / absence information of an image but also density information of multiple gradations. In the configuration shown in FIG. 5, the multi-gradation density information read by the image reading means 2 is converted into binary image information in which the image portion I and the non-image portion NI are distinguished based on a predetermined reference value. Information converting means, the target image information in the main scanning direction edge detecting means 3 and the sub-scanning direction edge detecting means 4 is used as binary image information from the binary image information converting means, and the outline generating means 5 The image processing apparatus may be provided with a density conversion unit that converts the outline image obtained from the image information into multi-gradation density information.

Further, in order to be able to arbitrarily determine the density of the outline drawing to be generated, in particular, the density conversion means may have density setting means capable of changing and setting density information of multi-gradation to be converted. Good.

[Operation] The image reading unit 2 optically scans the original 1 while sequentially moving the scanning line L to read image information in predetermined pixel units. The main scanning direction edge detecting means 3 detects a boundary point between the image portion I and the non-image portion NI on each scanning line L based on the read image information, and further detects a sub-point on the basis of the read image information. The scanning direction edge detecting means 4 detects a boundary point between the image portion I and the non-image portion NI at each pixel position in the moving direction (S) of the scanning line L. Then, the contour line generating means 5 generates a contour line image having a predetermined pixel width from the boundary points detected by the main scanning direction edge detecting means 3 and the sub-scanning direction edge detecting means 4.

In particular, when the outline drawing is generated in the same direction as the scanning direction, the main scanning direction outline drawing generating means 5a outputs the boundary point between the image portion I and the non-image portion NI detected by the main scanning direction edge detecting means 3. Then, an outline drawing is generated with a predetermined pixel width in the reading scanning direction (Sm) (see the crosses in FIG. 1D). Further, the sub-scanning direction outline image generating means 5b is moved in the scanning line moving direction (Ss) by a predetermined pixel width from the boundary point between the image part I and the non-image part NI detected by the sub-scanning direction edge detecting means. An outline drawing is generated (see a mark in FIG. 1 (d)). In this case, only the boundary point detected by the main scanning direction edge detecting means 3 and the sub-scanning edge detecting means 4 is used as a target only in the reading scanning direction (Sm).
When the outline drawing is generated in the scanning line moving direction (Ss), the outline drawing is not generated in a portion surrounded by a dashed line in FIG. 1D. Therefore, the sub-scanning outline drawing device 5b converts the outline drawing (x mark) generated by the main scanning direction outline drawing device 5a from the line drawing portion at each pixel position in the scanning line movement direction (Ss) to the non-line drawing. If a boundary point to a part is also targeted, the sub-scanning direction outline drawing generation means 5b generates a new outline drawing as indicated by a triangle in the area surrounded by the dashed line.

Also, as shown in FIG. 1 (c), when the sub-scanning outline drawing apparatus 5b particularly has a line memory 5b-1, etc., when a boundary point is detected in the course of scanning of the original by the image reading section 2. , The pixel width setting means 5b-2 is provided as shown in FIG.
As shown in the figure, a numerical value corresponding to the pixel width of the outline drawing to be generated is set at a storage address corresponding to each pixel position Cn, Cn + 1, Cn + 2,... On the scanning line of the line memory 5b-1. Then, the scanning lines Ln, Ln + 1, Ln from the boundary point
The unit image generating means 5b-3 generates a unit image (one symbol Δ) for a pixel corresponding to an address for which a numerical value is set in the line memory 5b-1 for +2,..., And this unit image is generated. Sometimes, the numerical value correcting means 5b-4 corrects the numerical value of the corresponding address in the line memory 5b-1 so that the pixel width is reduced by one line. The same processing is performed for the next scan line every time the correction is made, and the processing is repeated until the numerical value stored in the line memory 5b-1 becomes a value corresponding to the pixel width "0".

When the outline drawing of the image I drawn on the document 1 as described above is extracted, the extracted outline drawing is subjected to image processing, for example, the image is reproduced on a recording sheet as it is,
In addition, an image is reproduced in a state where the outline drawing is added to the original image, and a similar image reproduction is performed in a state where the outline drawing is processed.

When the target image is a character, if the outline drawing is reproduced as it is, a so-called outline character is formed. If the outline drawing is reproduced together with the original image, a so-called bold character is formed.

Examples Examples of the present invention will be described below in the order of the table of contents.

Table of contents I. Basic configuration II. Image input unit III. Color image information generation unit IV. Outline drawing generation unit V. Image formation unit VI. Summary I. Basic configuration The basic structure of the scanning system in the image processing device is, for example, As shown in FIG.

An openable / closable platen cover 14 is provided above a platen 12 on which a document 13 is placed, and a light guide member 16 including a light source 15 and a selfoc lens and a one-dimensional image sensor such as a CCD are provided below the platen cover 14. 10 are arranged, and these constitute a scanning unit together. The scanning unit performs a parallel movement (in the direction of the arrow in the figure) to perform an optical scan of the document 13, and, based on a detection signal in units of cells corresponding to the amount of received light output from the image sensor 10, the scanning unit 13 The image information of a predetermined pixel unit corresponding to the grayscale image, the diagram, the character, and the like drawn in FIG.

Next, the basic configuration of the entire image processing apparatus is, for example,
As shown in FIG.

This example is an image processing apparatus that presupposes two-color image processing, for example, black (main color) and red (sub-color) image formation.

In FIG. 3, reference numeral 10 denotes a full-color sensor for optically scanning an original image (corresponding to the image sensor in FIG. 2);
Numeral 20 converts read signals sequentially output from the full-color sensor 10 in a time-division manner in cell units into color component data (green: G, blue: G, red: R) in predetermined pixel units and outputs them in parallel. The full-color sensor 10 and the sensor interface circuit 20 constitute an image input unit. Reference numeral 50 denotes a color image information generation circuit that generates density information and color information as image information from each color component data (GBR) from the sensor interface circuit 20 in pixel units. And a sub color flag SCF corresponding to the sub color “red” and a main color flag MCF corresponding to the main color “black” as the color information. 70 is a correction / filter circuit that performs various corrections and filter processing on the density information D and color information (SCF, MCF) from the color image information generation circuit 50, and 100 is density data D and An editing / processing circuit for performing processing such as editing, processing, such as enlargement, reduction, and color inversion, on color information (SCF, MCF). An outline drawing extraction unit is configured in the editing / processing circuit 100. .

As described above, the correction / filter circuit 70 and the editing /
The density data D and color information (SCF, MCF) that have been subjected to various processes in the processing circuit 100 are supplied to specific image forming equipment via the interface circuit 180. This image forming device is a laser printer that performs two-color reproduction.
182, an image transceiver 184, etc., and further, density data D and color information are provided to a computer 186, stored in an auxiliary storage device (magnetic disk device, etc.) of the computer 186, and stored in various terminal devices. A system configuration using information is also possible. When the laser printer 182 is connected, a two-color copying machine is configured as a whole, and when the image transceiver 184 is connected, a facsimile is configured as a whole.

II. Original Image Input Unit This image input unit and the color information generation unit described in the following section III are integrated to realize an image reading unit which is a component of the present invention.

The full-color sensor 10 includes, for example, five CCD sensor chips 10 (1) to 10 (5) having a predetermined dot density (16 dots / mm) as shown in FIG. It is a so-called staggered arrangement and integrated with each other. Each CCD sensor chip 10
As shown in FIG. 5, (1) to (5) show green G, blue B, and red R filters (gelatin filters) for each light receiving surface of each cell (photoelectric conversion element) that is obliquely partitioned. Etc.) are provided in order. The adjacent green filter cell 11g, blue filter cell 11b, and red filter cell 11r form a set and receive light from each cell (corresponding to the document reflectance).
Is processed as a signal for one pixel P.

The sensor interface circuit 20 basically aligns the color component signals (G, B, R) based on the output signals from the staggered CCD sensor chips 10 (1) to 10 (5) into one line. Correction function, each color component signal (G, B, R) processed serially as a signal from each cell of the CCD sensor chip
Is converted into a parallel signal for each pixel P, a correction function for a shift in the detection position of each color component signal (G, B, R) in one pixel P, and the like.

The circuit shown in FIG. 6 is a circuit for realizing the function of aligning the outputs from the staggered CCD sensor chips into one line.

In the figure, each CCD sensor chip 10 (1) to 10
Signals serially output from (5) in units of cells are sequentially transmitted to the A / D conversion circuit 22 via the amplification circuits 21 (1) to 21 (5).
(1) to (22) are input. Each A / D conversion circuit 22
In (1) to (5), the sensor output signal in each cell according to the light receiving amount is output as, for example, 8-bit data. At the subsequent stage of each of the A / D conversion circuits 22 (1) to 22 (5), latch circuits 23 (1) to 23 (5) for timing adjustment are provided. With respect to the CCD sensor chips 10 (2) and 10 (4), which are arranged in front of the other CCD sensor chips with respect to the other CCD sensor chips, the latch circuits 23 (2) and 23 (4) are provided first. First-come first-served FIFO memories 24 and 25 are provided. The FIFO memories 24 and 25 delay the output timing of the color component signals for the CCD sensor chips 10 (2) and 10 (4) by delaying the other CCD sensor chips 10 (1), 10 (3), 10 This is for adjusting the output timing of the same line signal for the system (5). Therefore, while the write timing is determined to be a predetermined timing, the read timing (delay amount) is determined by the CCD sensor chips 10 (2) and 10 (4).
Is determined based on the distance (for example, 62.5 μm) between the scanning line of the other CCD sensor chip and the scanning speed of the full-color sensor 10. For example, when the scanning speed is different according to the magnification of the image to be formed, the readout timing is controlled according to the magnification. As described above, when the read timing is made variable by the magnification or the like, the FI is assumed to be the slowest in the read timing.
The capacity of the FO memories 24 and 25 is determined (the memory capacity corresponds to the allowable delay amount). Latch circuits 26 (2) and 26 (4) are provided at the subsequent stage of each of the FIFO memories 24 and 25, while the CCD sensor chips 10 (1), 10 (3) and 10 (5) are provided with the above-mentioned latch circuits. The next latch circuit 26 (1), 26 (3), 26 (5) is directly connected to the subsequent stage of 23 (1), 23 (3), 23 (5), and the preceding CCD via FIFO 24, 25 is connected. Sensor chip
The color component signals of the 10 (2) and 10 (4) systems and the color component signals of the other sensor chips are stored in the respective latches 26 (1) to 26 (26).
In (6), they are aligned as those of the same scanning line, and are transferred to the subsequent stage at a predetermined timing. Each latch circuit 26
Looking at (1) to 26 (5), color component signals correspond to G → B → R → G → B → R → corresponding to the cell arrangement of each CCD sensor chip.
The data is serially transferred in the order of...

The circuit shown in FIG. 7 is a circuit for realizing the function of converting each color component signal serially transferred in the system of each CCD sensor chip into a parallel signal in pixel units as described above.

In the figure, each of the CCD sensor chips 10 (1) to 10 (10)
Serial-parallel conversion circuit 30 (1) to (5)
30 (5) are provided. Each of the serial / parallel conversion circuits 30 (i) (i = 1,..., 5) is a latch circuit 31g, to which the color component signals (G, B, R) serially transferred as described above are input in parallel. Each of the latch circuits 31b and 31r is such that 31g is synchronized with a clock signal (G clock) which becomes active when the color component signal G (green) is transferred, and 31b is active when the color component signal B (blue) is transferred. Is synchronized with the clock signal (B clock), and 31r is the color component signal R
Each color component signal is latched in synchronization with a clock (R clock) that becomes active at the time of transfer of (red). Further, at the subsequent stage of each of the latch circuits 31g, 31b, 31r, there is provided a tri-state latch circuit 32g, 32b, 32r for latching again for each pixel in order to adjust the transfer timing, and each tri-state latch 32g, 32b , 32r, the latch data (color component signal) of the preceding stage is simultaneously re-latched at the falling timing of the R clock. Further, the tri-state latch circuits 32g and 32g
The drive of b / 32r is controlled by the enable signal (i) (i = 1,..., 5).

A memory circuit 34 and a timing control circuit 36 for controlling writing and reading of the memory circuit 34 are provided at a stage subsequent to the serial / parallel conversion circuits 30 (1) to 30 (5). The memory circuit 34 has a dedicated memory for each color component (G, B, R). When writing each color component to the memory, the enable signal is changed from (1) to (2) to (3).
By switching the active state in the order of (4) → (5) and controlling the write address according to a predetermined rule, one memory is stored in the memory for each color component (G, B, R).
The data of the line is arranged in a quasi-order.
Then, by reading out the data of each color component from each dedicated memory sequentially in parallel, the color component data of each pixel is sequentially transferred from one end of one line to the subsequent stage.

It should be noted that the resolution is converted at the boundary of the memory circuit 34 by the difference between the write timing and the read timing in the timing control circuit 36. For example, a timing control circuit so that the resolution in the system after the memory circuit 34 is 400 SPI
Reference numeral 36 controls the read timing.

The circuit diagram shown in FIG. 8 shows each color component (G, B,
R) is a circuit that realizes a correction function for the deviation of the detection position.

As shown in FIG. 5, since the reading position of each color component G, B, R is spatially shifted within one pixel due to the structure of the full color sensor 10, the signal from each cell is processed as it is as a color component signal. Then, there occurs a problem that another color pixel is generated at a boundary portion of the black image, that is, a so-called ghost occurs. Therefore, in order to prevent such a ghost or the like, this correction circuit makes the reading positions of the respective color components apparently coincide with each other. Specifically, in the arrangement of each cell shown in FIG. 9, when the pixel Pn is focused on, the reading position of each color component is corrected to be virtually the position of the cell Gn. The correction method is based on the method of correcting adjacent pixels Pn−
In consideration of 1, the weighted average is set so that the reading position of each color component becomes the position of the cell Gn. That is, Gn = Gn (1) Bn = (Bn-1 + 2Bn) / 3 (2) Rn = (2Rn-1 + Rn) / 3 (3) Each color component data (Gn, Bn, Rn) is obtained. Like that.

As a circuit for realizing the above operation, there is a circuit shown in FIG. 8, for example.

The color component data output for each pixel in the circuit shown in FIG. 7 is input to the correction circuit in parallel. Then, regarding the system of the G component, the latch circuit 38g
For the system of the B component, a subsequent latch circuit 41 and a shifter 42 for shifting the data latched by the latch circuit 38b by 1 bit are provided at the subsequent stage of the latch circuit 38b, and the latch data of the latch circuit 41 and the shifter 42 are provided. An adder 43 for adding the shift data at 42 and a look-up table (ROM) 44 for taking the result of addition at the adder 43 as an address input and outputting 1/3 thereof are provided. For the system of the R component, a next latch circuit 45 and a shifter 46 for shifting the data latched by the latch circuit 45 by 1 bit are provided at the subsequent stage of the latch circuit 38r.
There is provided an adder 47 for adding the latch data of r and the shift data in the shifter 46, and a lookup table (ROM) 48 for taking the addition result of the adder 47 as an address input and outputting 1/3 thereof as described above. . With such a configuration, the above-described equation (1) is realized in the G component system, and shifting by one bit means a double operation. Therefore, in the B component system, the above equation (2) and the R component In the system, the above equation (3) is realized.

The above is the basic configuration of the image input unit composed of the full-color sensor 10 and the sensor interface circuit 20. When the original is scanned by the full-color sensor 10, the color component data ( G, B, R) are sequentially output.

Each color component signal that has been processed by the image input unit as described above is transferred to a color image information generation unit described below through a process such as shading correction that is generally performed.

III. Color Image Information Generating Unit FIG. 10 shows a specific structure of the color image information generating circuit 50 in FIG.

In the figure, a subtraction circuit 51 for inputting G component data and R component data of the color component data transferred from the sensor interface circuit 20 in pixel units and calculating a difference (R−G) between them, and B component data And a subtraction circuit 52 for inputting the R component data and calculating the difference (R−B). The result of the subtraction by each of the subtraction circuits 51 and 52 is input in parallel to the address end of the lookup table 53. The look-up table 53 outputs the product (H × C) of the saturation C and the hue H of the pixel and the color discrimination based on each of the subtraction results. The reading is performed in units of 8 bits.
For example, as a result of the upper 5 bits being (H × C), the lower 3 bits are allocated to the color determination output.

The contents of the look-up table 53 are determined, for example, as follows.

As shown in FIG. 11, the vertical axis represents the difference (RG) between the red (R) color component and the green (G) color component, and the red (R) color component and the blue (B) color component. When a color space with the difference (R−B) as the horizontal axis is set, an arbitrary color is specified by the distance r from the origin 0 and the rotation angle θ. The distance r is a factor mainly determining the saturation C. In the color space, the closer to the origin 0, the closer to the achromatic color. The rotation angle θ is a factor mainly determining the hue H. For example, "red""magenta"
“Blue”, “cyan”, “green”, and “yellow” are distributed at positions surrounded by broken lines in FIG. 11 in the color space.

From the relationship described above, (RG) data and (R-
B) The distance r from the origin obtained from the data in accordance with r = {(RG) ² + (RB) ² } ^1/2 and the same as (RG)
A color determination is made at a position in the color space specified by the rotation angle θ obtained from the data and the (RB) data according to θ = tan ⁻¹ {(RG) / (RB)}. You.

In addition, the saturation C is a relationship between the distance r from the origin and the saturation C determined from the (RG) data and the (RB) data by the above equation, for example, as shown in FIG. It is determined according to the relationship shown. In FIG. 12, when the distance r becomes smaller than the predetermined value r ₀ , the color becomes achromatic and the saturation C becomes “0”.
Becomes

Further, the hue H is a relationship between the rotation angle θ and the hue H determined by the above formula from the (RG) data and the (RB) data, for example, a relationship as experimentally determined as shown in FIG. Is required in accordance with In FIG. 13, the rotation angle θ is a predetermined value θ.
When it is smaller than ₀ , the hue H is forcibly set to "0".

As described above, since the color discrimination result, the saturation C and the hue H are both obtained based on the (RG) data and the (RB) data, the (RG) from each of the subtraction circuits 51 and 5 is obtained. Look-up table using RB and (RB) as address inputs
Reference numeral 53 is configured to realize the above-described processing such as calculation and determination, and to output the color discrimination and the product (C × H) of the saturation C and the hue H. Then, as described above, the value of (C × H) is represented by 5 bits, and the color determination result is represented by 3 bits. It is expressed as shown in Table 1 above.

FIG. 12 and FIG.
The relationship shown in FIG. 13 is determined variously depending on the ability related to color separation required of the system.

In FIG. 10, each of the color component data input in parallel on a pixel-by-pixel basis is a multiplication circuit 54 in which the G component data is 0.6 times larger.
, And the B component data is input to the multiplication circuit 55 of 0.1 times,
The R component data is input to a multiplication circuit 56 of 0.3 times. The multiplication results of the multiplication circuits 54, 55, and 56 are respectively input to an addition circuit 57, and the addition result VV = 0.6G + 0.3R + 0.1B of the addition circuit 57 is transferred to the subsequent stage as brightness data of the pixel. .

The brightness data V is generated based on the G component data of the color component data GBR, taking into account the values of the B component data and the R component data. This is because the spectral sensitivity curve of the G component signal in the image sensor (full color sensor 10) has characteristics close to the human luminous efficiency curve. Each coefficient (multiplied value in each multiplication circuit) in the expression for determining the brightness V is finally determined by the spectral sensitivity characteristics of the image sensor, the spectral distribution of the exposure lamp, and the like.

Since the spectral sensitivity characteristic of the G component signal is close to the human relative luminous efficiency characteristic as described above, it is also possible to use only the G component data as the brightness data V according to the capability required for the system. It is.

The output (H × C) relating to saturation and hue from the look-up table 53, the color discrimination data and the brightness data V from the adder circuit 57 become the address input of the next look-up table 58, and the look-up table 58 It has a function of outputting color density data Dc corresponding to the input. Specifically, it outputs color density data Dc determined according to Dc = K × C × H × V for each of the above inputs. Where K
Is a coefficient different depending on the color determination data. The coefficient K is used to match the lightness level between the chromatic color and the achromatic color because the chromatic color and the achromatic color seem brighter, and is determined experimentally in advance in accordance with each discrimination color. Is set to a value within a range of, for example, about 1.1 to 1.3.

The color discrimination output (3 bits) from the look-up table 53 and the color selection data set in the latch circuit 60 are input to the coincidence circuit 59. The output of signal 59 rises to H level. The color selection data is set in the latch circuit 60 based on an operation input by an operator or a setting input by a dip switch or the like. Become. The output of the matching circuit 59 functions as a sub color flag SCF (color information) indicating whether or not the color is a sub color (for example, red) set for color selection.
This is an output selection signal (SEL) of the selection circuits 61 and 62. The selection circuit 61 has a function of switching between the brightness data V and “0” data according to the state of the selection signal. In this case, the brightness data V is output. The selection circuit 62 has a function of switching between the color density data Dc from the look-up table 58 and the data from the selection circuit 61 according to the state of the selection signal.
When the level is at the level, the color density data Dc is output, and when the selection signal is at the L level, the data from the selection circuit 61 is output. The output bit of the selection circuit 61 is directly input to the OR circuit 63, and functions as a main color flag MCF (color information) indicating whether or not the output of the OR circuit 63 is a main color (for example, black). While the selection circuit 6
The output of 2 is transferred to the subsequent stage as density data.

In the color image information generating circuit as described above, in the main color (black) area of the original, the output of the matching circuit 59 is at L level, and the brightness data V from the adding circuit 57 is directly used as the selecting circuits 61 and 62. Are transferred to the subsequent stage as density data D. At this time, since the brightness data V is not “0”, the main color flag MCF becomes H level, and the matching circuit 59
Is low, the sub color flag SCF
Becomes the L level (the main color area Em in FIG. 14).
reference). In the sub-color area (for example, red) of the original, the output of the matching circuit 59 becomes H level, and the color density data from the lookup table 58 is transferred to the subsequent stage as density data D via the selection circuit 62. You. At this time,
Since the output of the selection circuit 61 is "0", the main color flag MCF goes low, and the output of the coincidence circuit 59 goes high, so that the sub color flag SCF goes high (see FIG. 14). See color area Es). Further, in the background area (density “0”) of the original, the output of the selection circuit 61 is “0” and the output of the matching circuit 59 is also at L level, so that the density data D is “0” and Color flag MF
Both C and sub-color flag SCF are at L level (14th
(See the background area En in the figure). Each of the arithmetic circuits is driven synchronously on a pixel-by-pixel basis under the control of a timing control circuit (not shown). The density data D and the color flags (MSF, SMF) are converted into data of the same pixel as the following data. The data is sequentially transferred to the correction / filter circuit 70 of the stage.

Thus, the density data D and the color flag (MCF, SCF)
Correction and filter circuit transferred in pairs for each pixel
In 70, the dot determined to be the sub-color (red) at the boundary between the main color (black) and the background (white) due to correction processing, for example, chromatic aberration of the reading optical system, bias of the color sensitivity of the full-color sensor 10, and the like. Correction processing such as ghost correction to prevent the appearance of ghosts, and filter processing such as MTF correction for emphasizing high frequencies and various filter processing such as high frequency cut correction to prevent moiré Is performed.

IV. Outline Drawing Generation Unit The outline drawing generation unit embodies the main scanning direction edge detection unit, the sub-scanning direction edge detection unit, and the outline generation unit, which are constituent elements of the present invention.

FIG. 15 shows a binarizing circuit, which embodies a binary image information converting means which is a specific component of the present invention.

In the figure, reference numeral 101 compares the density data D of 256-tone expression (multi-tone expression) from the color image information generation circuit 50 via the correction / filter circuit 70 with a predetermined binarization level as described above. The comparison circuit 101 has a function of converting the density data D of the multi-tone expression into binary image data. Similarly, the main color flag MCF and the sub color flag SCF from the color image information generation circuit 50 are input to the respective AND gates 102 and 103 which are gate-controlled by the binarized image data, respectively. The output is a new main color flag MCF, and the output of the AND gate 103 is a new sub color flag SCF.

With such a configuration, the main color flag MCF and the sub color flag SCF corresponding to the density data D of multi-tone expression
For example, as shown in FIG. 16, binary image data and a new main color flag MCF and sub color flag SCF
Are converted respectively. That is, the image data rises when the density data D becomes higher than the binarization level (image portion), and the new main color flag MCF and the new sub color flag SCF rise when the image data rises. When the image data falls (the non-easy portion), the flag is forcibly turned down.

Further, the image data (n), main color flag MCF (n), and sub color flag SCF (n) obtained for each scanning line Ln as described above are provided to a FIFO memory 104 of a first-in first-out system. In the scanning process, the image data (n-1), the main color flag MCF (n-1), and the sub color flag SCF (n
-1) can be obtained from the FIFO memory 104.

The overall configuration of the outline extraction circuit is, for example, as shown in FIG.

Image data (n) on the line of interest output from the binarization circuit is input to one end of a two-input AND gate 112,
Image data (n-1) at the same pixel position one line before is input to the other input terminal of the AND gate 112 by the inverter 113.
You are typing through. The image data (n-1) one line before is input to one end of another two-input AND gate 115, and the image data (n) on the line of interest is input to the other input end of the AND gate 115. It is input via the inverter 114. And each of the above-mentioned AND gates 112 and 115
Is input to the OR gate 116. Here, where the image data changes from the L level to the H level at the boundary point where the non-image portion changes to the image portion in the sub-scanning direction, (image data (n-1) = L, image data (n) = H ), While the output of the AND gate 112 goes to the H level, and where the image data changes from the H level to the L level at the boundary point where the image portion changes from the image portion to the non-image portion in the same sub-scanning direction (image data (n− 1) = H,
Image data (n) = L), and the output of AND gate 115 is H
Level. Therefore, the output of the AND gate 112 is a detection signal of a boundary point where the non-image portion changes from the image portion to the image portion, and the output of the AND gate 115 is a detection signal of a boundary point where the image portion changes from the image portion to the non-image portion. The output of the OR gate 116 that is the logical sum becomes the final image edge detection signal in the sub-scanning direction at each pixel position.

Further, the image data (n) on the target scanning line and 1
Image data (n-1) at the same pixel position before the line is input to the OR gate 111, and the output of the OR gate 111 is input to the main scanning direction outer shape detection circuit 120 as new image data. The reason why the main scanning direction outer shape detection circuit 120 processes the logical sum (OR gate 111) of the image data (n) and the image data (n-1) one line before as new image data will be described later.

The specific configuration of the main scanning direction outer shape detection circuit 120 is, for example, as shown in FIG.

In the figure, reference numerals 121 and 131 denote counters for counting a video clock signal (v.CLOCK) serving as an image reading timing signal, and each of the counters 121 and 123 is a load signal (L).
Initial data is set during the period when D) is at the L level, and the carry C output is started when the total count value from the initial data reaches the maximum value (for example, 255). The external line width data from the CPU is input to each of the counters 121 and 123 as initial data D, the image data is input as it is as a load signal of the counter 121, and an inverted signal of the image data via the inverter 122 is input to the counter 121 and 123. Input as 123 load signal. Here, the contour line width data is input by the operator by operating a numeric keypad or the like on the console panel. Specifically, when the operator inputs the pixel width w of the contour line to be extracted, the contour line width data X is calculated according to X = 256 + 1-w, and the calculation result X is provided from the CPU to each of the counters 121 and 123. In this case, the settable pixel width w is 2 dots or more (the maximum set pixel width is, for example, 129 dots).

124 is a quadruple latch circuit for latching the carry C output from each of the counters 121 and 123 in parallel in synchronization with the video clock signal (V.CLOCK). 125 is set at the rising edge of the image data. A flip-flop 126 is reset at the falling edge of the output (the carry C output of the counter 121). The flip-flop 126 is set at the falling edge of the image data, and is reset at the falling edge of the output of the inverting circuit 146 (the carry C output of the counter 123). The data terminals of the flip-flops 125 and 126 are always fixed at H level. Then, the output Q of each of the flip-flops 125 and 126 is input to the OR gate 127, and the output of the OR gate 127 becomes a main scanning direction outer shape detection signal.

In the main scanning direction outer shape detection circuit 120 having such a configuration,
For example, in the processing when a setting input of a pixel width w = 3 pixels is made, the signal states of the respective parts are as shown in FIG.

First, in the course of scanning of the original, the outline width data X = 256 + 1-3 = 254 is added to the counter 121 at the fall of the previous image data.
Are set as initial data. In this state, when the image data rises, the output Q of the flip-flop 125 rises to the H level at the same time. At this time, the external line width data 254 is set in other counters 123 as initial data. Thereafter, when the counter 121 counts one video clock (V.CLOCK) in the scanning process (count value 256> 255), the carry output C rises. At the next rising timing of the video clock (V.CLOCK), carry output C falls to L level, and output 2Q of latch circuit 124 rises to H level. Next video clock (V.CLOCK)
The output 2Q of the latch circuit 124 becomes L at the rising timing of
The output 4Q of the latch circuit 124 rises, and the output of the inversion circuit 145 falls to the L level. As a result, the flip-flop 125 is reset, and the output Q of the flip-flop 125 falls to the L level. Since then
This state is maintained while the image data maintains the H level in the process of scanning the image portion. When the scanning reaches the boundary point between the image portion and the non-image portion and the image data falls, the output Q of the flip-flop 126 rises to the H level at the same time. Thereafter, as in the case described above, when the counter 123 counts one video clock (V.CLOCK) during the scanning process (count value 256> 255), the carry output C rises. At the next rising timing of the video clock (V.CLOCK), carry output C falls to L level, and output 1Q of latch circuit 124 rises to H level. At the rising edge of the next video clock (V.CLOCK), the latch circuit 1
24, the output 1Q falls to the L level, the output 3Q of the latch circuit 124 rises, and the output of the inversion circuit 146 falls to the L level. Thereby, flip-flop 126 is reset, and its output falls to H level.

As a result of the processing as described above, the flip-flops 125 and 12
The external shape signal in the main scanning direction, which is the logical sum of the outputs Q of 6, is 3 clocks from the rising edge of the image data and 3
It is at the H level during the clock. In other words, the scanning direction outer shape signal has a width of three pixels in the scanning direction from a change point (rising edge of image data) from the non-image portion to the image portion,
From the point of change from the image portion to the non-image portion (fall of the image data), an external line having a width of three pixels is represented in the scanning direction.

Further, in FIG. 17, the main scanning direction outer shape detection circuit is used.
The outer scanning signal from the main scanning direction 120 and the image edge detection signal in the sub-scanning direction from the OR gate 116 are respectively OR gates 12.
Enter in 8. As a result, the output of the OR gate 128 becomes a signal that rises at the edges of the image in the main scanning direction and the sub-scanning direction.

On the other hand, reference numeral 129 denotes a FIFO (first-in first-out) line memory having a storage address corresponding to each pixel position of the scanning line. In the line memory 129, for example, the upper 7 bits (up to 127) of the 8-bit data line are assigned to numerical data relating to the line width, the least significant bit is assigned to the flag data, and the video clock (V.CLOCK) is read / read.
A write clock (RCK / WCK) and a video valid signal (V.VAD) representing a valid one scanning line become a read / write enable signal (RE / WE), and read / write control is performed based on each signal. It has become. 13
0 is a selection circuit, and the selection circuit 130 outputs the outline line width data X set as the outline line width to be extracted in the sub-scanning direction.
8-bit data (A) composed of (7 bits) and an edge detection flag (1 bit) described later, and 8-bit data (7 bits relating to line width and 1 bit of flag data) from the line memory 129 (B ) Is selectively output (Y). Specifically, when the selection signal S is at the H level, the A input side is input, and when the selection signal S is at the L level,
At the level, the B input side is selected. The output signal of the OR gate 128 rising at the image edge portion in the main scanning direction and the sub-scanning direction is the selection signal S of the selection circuit 130. The contour line width data X in the sub-scanning direction is calculated according to X = 128 + 1w when the operator specifies the pixel width w (operation input), and is supplied to the selection circuit 130.

Reference numeral 131 denotes an addition circuit. The addition circuit 131 receives 7-bit data regarding the line width from the selection circuit 130 as an A input, and obtains the output bits of the OR gate 128 through an inverter 132 and an AND gate 133. The A + B operation (Σ) is performed by using “1” or “0” data as B input. Here, the 7-bit data relating to the line width read from the line memory 129 is ORed with each bit by the OR circuit 134, and this OR signal is used as a page sync signal (PAGE SYN) indicating one read cycle.
The signal is a control signal of the AND gate 133 in the preceding stage of the B input of the adding circuit 131 via the AND gate 135 which is gate-controlled by C). The operation result (Σ) of the addition circuit 131 is fed back to the line memory 129 together with the paired flag data from the selection circuit 130.

Further, the output signal of the OR gate 128 rising at the image edge portion in the main scanning direction and the sub-scanning direction becomes the control signal of the AND gate 138 and the inverter 1
The inverted signal via 37 is a control signal for the AND gate 139. The edge detection flag is input to the AND gate 138 which is gate-controlled in this way, the flag data from the line memory 129 is input to the AND gate 139, and the output signals of the AND gates 138 and 139 are input to the OR gate 140, respectively. ing. This or gate 1
The output signal of the AND gate 142 becomes a control signal of the AND gate 142, and its inverted signal becomes the control signal of the AND gate 143.The output signal of the AND gate 135 and the output signal of the OR gate 128 are transmitted through the OR gate 136. Are input to the AND gates 142 and 143 in parallel. The output of the AND gate 142 is an SC outline signal indicating an outline represented by a sub color (red), and the output of the AND gate 143 is an MC outline signal indicating an outline represented by a main color (black). ing.

 The above-described edge detection flag will be described.

Since the image processing apparatus handles data of two colors (main color and sub color), when an edge of an image is detected, the color of that part is expressed as an edge detection flag. A specific circuit for generating the flag is, for example, as shown in FIG.

In FIG. 20, in the sub-scanning direction, a detection signal (a sub-scanning L → H) of a boundary point changing from a non-image portion to an image portion is provided.
Detection), specifically, an AND gate 151 to which the output of the AND gate 112 in FIG. 17 and the new sub color Bragg SCF which becomes the output of the AND gate 103 in FIG. A detection signal (sub-scan H → L) of a boundary point changing to an image portion, specifically,
Each of the AND gates 115 receives an output of the AND gate 115 in FIG. 17 and a new main color flag MCF serving as an output of the AND gate 102 in FIG.
Output signals 51 and 152 are input to the OR gate 153. Here, the output of the AND gate 151 is the color flag of the pixel at the boundary point that has changed from the non-image portion to the image portion. In the process of reading the image, the change from the non-image portion to the image portion changes the pixel of the image portion. Since it can be determined when reading, the sub color flag SC of the read pixel (n) is read.
F (n) is used as it is as the color flag of the pixel (n) at the boundary point. On the other hand, the output of the AND gate 152 is a color flag of the pixel at the boundary point that has changed from the image part to the non-image part. In this case, the change from the image part to the non-image part reads the pixel of the non-image part. The sub color flag SCF (n-1) of the pixel (n-1) one line before the read pixel (n) is set as the color flag of the pixel (n) at the boundary point. . Or gate
The output signal of 153 is input to an AND gate 155, which is gate-controlled by an inverted signal of the above-described main scanning direction outer shape signal (main scanning direction outer shape detection circuit 120) by the inverter 154.

On the other hand, in the main scanning direction, an outer shape signal generated from a boundary point changing from a non-image portion to an image portion (main scanning L →
H detection), specifically, the flip-flop in FIG.
125 outputs to the clock terminal (CLK)
F is the flip-flop 1 input to the data terminal (D)
56 and an external signal (main scanning H → H → H) generated from a boundary point changing from an image portion to a non-image portion in the main scanning direction.
L detection), specifically, the flip-flop in FIG.
126 output to clock terminal (CLK), sub color flag SC
F is the flip-flop 1 input to the data terminal (D)
The output Q of the flip-flop 156 and the outline signal (main scanning L → H detection) are supplied to the AND gate 157, and the output of the flip-flop 158 and the outline signal (main scanning H → L) are output to the AND gate 157.
Detection) are input to the AND gate 159, respectively. Here, in the main scanning direction outline detection circuit 120 that generates each outline signal, the image data of the scanning line is
Since the logical sum of the image data of the same position pixel before the line is handled as actual image data, the sub color flag SCF input to each of the flip-flops 156 and 158 is similarly set to the sub color flag of the scan line and the sub color flag SCF. The logical sum of the sub-color flags of the same position pixels before the line is treated as the actual sub-color flag SCF. Also, in the case of the main scanning direction, similarly to the case of the sub-scanning, when changing from the non-image portion to the image portion, the sub-color flag SCF (m) of the pixel (m) to be read at the time of detection is used as it is. Conversely, when changing from the image portion to the non-image portion, the sub color flag SCF (m-1) of the pixel (m-1) one pixel before the read pixel (m) at the time of detection is used as the color flag. It is a color flag for the outline. The output of each AND gate 157, 159 is OR gate 160
Further, the output of the OR gate 160 is input to the OR gate 161 together with the output from the AND gate 155 on the sub-scanning side. The output of the OR gate 161 is a final edge detection flag. When the edge detection flag is at the H level, it indicates the sub color, and when it is at the L level, it indicates the main color.

Next, the process of extracting the outline will be described in detail using a rectangular image as shown in FIG. 21 (a) as an example.

In this rectangular image, the left shaded portion is the main color (black), and the right halftone dot portion is the sub color (red). For simplicity, each scan line is assumed to have a 17-dot (pixel) configuration, and each pixel position (1
17) are stored in advance as initial values at addresses corresponding to the above. The outline width w set and input by the operator is w = 2 pixels.

In the process in which the full-color sensor 10 performs optical scanning by sequentially moving the scanning lines as L1, L2, L3,.
Since there is no image between L3 and L3, the image data corresponding to each read pixel maintains the L level. Further, between the scanning lines L4 to LR, as shown in "image data""MCF""SCF" in FIG.
As the image data rises up to the clock,
The main color flag MCF is at the H level between 4 and 9 clocks, and the sub color flag SCF is continuously at the H level between 10 and 13 clocks. Further, since there is no image again after the scanning line L9, the image data, the main color flag MCF, and the sub color flag SCF each fall and maintain the L level.

In the above scanning process, the signal waveform of each part in each scanning line is as shown in FIG.

Between the scanning lines L1 to L3, since there is no image, both the main scanning direction outer shape signal from the main scanning direction outer shape detection circuit 120 and the image edge detection signal in the sub-scanning direction from the OR gate 116 maintain the L level, Line memory
From 129, the initial value "0" is read out in synchronization with the video clock, and the "0" data is fed back as it is and written into the line memory 129 again. Therefore, MC external signal, S
Both the C external signals are kept at the L level.

Further, in the scanning line L4, the external signal (a) in the main scanning direction is equivalent to two clocks (set pixel width) from the fourth clock at which the non-image portion changes to the image portion, and from the reverse image portion to the non-image portion. From the 14th clock that changes to the H level for each of two clocks (the same pixel width) (similar to the external signal in the main scanning direction in FIG. 19).
Then, the image edge detection signal (b) in the sub-scanning direction from the OR gate 116 rises to the H level from 13 clocks to 4 clocks that change from the non-image portion to the image portion from the scanning lines L3 to L4. . In this state, the image edge detection signal (b) in the sub-scanning direction becomes H level (sub-scanning L → H) from 4 clocks to 13 clocks, particularly from 10 clocks when the sub color flag SCF becomes H level. Up to the 13th clock, the output of the AND gate 151 in FIG. 20 is at the H level, and the edge detection flag (c) rises to the H level. At the next 14th clock, the external signal (a) in the main scanning direction goes to the H level (main scanning H → L).
8 is set, and the subsequent AND gate 159 maintains the same H level state while the outer shape signal in the main scanning direction is at the H level, and the flag (c) at the time of edge detection continues from the above 13 clocks to 15 clocks (2 more). H level state is maintained.

On the other hand, during the period from 4 clocks to 15 clocks when either the external signal (a) in the main scanning direction or the image edge signal (b) in the sub scanning direction is at the H level, the output of the OR gate 128 in FIG. Level. Then
During that time, the selection circuit 130 selects and outputs the A side, and the B input of the addition circuit 131 is fixed to “0”. Therefore, from the 4th clock to the 15th clock, the outline line width data X = 128 + 1-2 = 127 is set at an address corresponding to the pixel positions (4) to (16) of the line memory 129 in synchronization with the video clock.
(W = 2) and the edge detection flag (c) are sequentially written as 8-bit data. The line memory 12
"0" data is written into addresses corresponding to the other nine pixel positions (1) to (3) and (16) to (17) (the same applies hereinafter). In the process of writing data to the line memory 129 in synchronization with the video clock as described above, the above OR gate is used for 4 to 9 clocks.
Since the flag (c) at the time of edge detection becomes L level when the output of the gate 128 is H level, the AND gates 138, 13
9 are both at L level, and the output of the subsequent AND gate 143 is at H level. That is, the MC external signal (d) rises to the H level. From the 10th clock to the 15th clock, since the output of the OR gate 128 is also at the H level and the edge detection flag (c) is at the H level, the AND gate 138 is at the H level and the subsequent AND gate The output of 142 goes high and the output of AND gate 143 goes low. That is, the MC external signal (d) rises to the L level, while the SC external signal (e) rises to the H level.

In the scanning line L5 subsequent to the scanning line L4, the external shape signal (a) in the main scanning direction is changed from the non-image portion to the image portion from 4 clocks to 5 clocks, and from the image portion to the non-image signal as in the case of the scanning line L4. The two pixels from 14 clocks to 15 clocks, which change to the section, are at the H level, but the image edge detection signal (b) in the sub-scanning direction from the OR gate 116 is the scanning line L4 to L5.
Since the image does not change until, the signal becomes L level at all clock timings. The edge detection flag (c) is set to the 20th in the sub-scanning direction when the image edge detection signal (b) in the sub-scanning direction becomes L level.
Since the output of the AND gate 155 in the figure maintains the L level, the L level is maintained until the 13th clock, and the same level occurs between the 14th clock and the 15th clock due to the H level state of the external signal in the main scanning direction. The state becomes the H level.

In the scanning line L5 in the above-described state, the output of the OR gate 128 is at the H level from 4 clocks to 5 clocks when the outer shape signal (a) in the main scanning direction is at the H level. Then, the MC outline signal (d) becomes H level, and the outline line width data X = 127 and the flag information “0” are again stored in the address corresponding to the pixel positions (4) and (5) of the line memory 129 in the 8-bit data. It is written as When the external signal (a) in the main scanning direction is L
Since the output of the OR gate 128 becomes L level from the 6th clock to the 13th clock which becomes the level, the AND gate 138 is output.
Becomes low level, and the output of the AND gate 139 outputs the flag data (L
Depending on the data written during the four scans), the state becomes L level up to 9 clocks and H level up to 13 clocks from 10 clocks. Further, at this time, the output of the OR gate 134 becomes H level due to the outline line width data 127 (data written at the time of L4 scanning) simultaneously read from the line memory 129, and the output of the AND gate 135 and the output of the OR gate 136 become H level. Becomes As a result, the MC external signal (d) from the AND gate 143 maintains the H level state from 6 clocks when the read flag data is at the L level to 9 clocks, and 10 clocks when the flag data is at the H level. From 13 to 13 clocks, the MC external signal (d) falls to the L level, and conversely, the SC external signal (e) from the AND gate 142 is at the H level. On the other hand, OR gate 128
The external line width data 127 read from the line memory 129 during the period from the 6th clock to the 13th clock when the output becomes L level is added with "1" (B input = 1) by the adding circuit 131, and 127 + 1 = 128, That is, "0" (expressed in 7 bits) is written to the address corresponding to the pixel positions (6) to (13). At this time, the read flag data is written to the line memory 129 together with the corresponding outline line width data “0”.

Further, during the period from the 14th clock to the 15th clock, the output of the OR gate 128 rises to the H level again and the flag (c) at the time of edge detection becomes the H level. Maintain the state of the level. At this time, the selection circuit 130 is switched to the A side, and the external line width data X = 127 set at the address corresponding to the pixel positions (14) and (15) of the line memory 129 and the edge detection flag “1” are set. Is written as 8-bit data.

Next, when the scanning line shifts to L6, the outer shape signal (a) in the main scanning direction, the image edge signal (b) in the sub-scanning direction, and the edge detection flag (c) are in the same state as in the case of the scanning line L5.

In this state, from 4 clocks to 5 clocks when the main scanning direction outer shape signal (a) is at the H level, the MC outer shape signal (d) is at the H level as in the case of the scanning lines L4 and L5, and the pixel position of the line memory 129 is set. The outline line width data X = 127 and the flag data “0” are written as 8-bit data at the addresses corresponding to (4) and (5). And
From the 6th clock to the 13th clock when the outer shape signal (a) in the main scanning direction is at the L level, the OR gate 128 is at the L level and the outer shape width data read from the line memory 129 is “0” (written during L5 scanning). OR gate with embedded data)
The output of 134 goes low, and the output of AND gate 135 and the output of OR gate 136 go low. As a result, both the MC external signal (d) and the SC external signal (e) become L level. At this time, since the output of the AND gate 135 is at the L level, the B input of the adding circuit 131 becomes “0”, and the outline line width data “0” read from the line memory 129 is written to the same address as it is.

Further, from the 14th clock to the 15th clock, the output of the OR gate 128 is at the H level and the SC external signal (e) is at the H level as in the case of the scanning line L5. At this time, the selection circuit 130 is switched to the A side, and the external line width data X = 127 set at the address corresponding to the pixel positions (14) and (15) of the line memory 129 and the edge detection flag “1” are set. Is written as 8-bit data.

Thereafter, the same processing as that of the scanning line L6 is repeated in the scanning lines L7 and L8.

Further, when the scanning line shifts to L9, no image exists in this scanning line, but the main scanning direction outer shape detection circuit
Since 120 processes the logical sum data with the image data of the previous line, the outer shape signal (a) in the main scanning direction is also changed from 4 clocks to 5 clocks in the scanning line L9 in the same manner as described above. H level during the period and between 14 and 15 clocks. Then, the image edge detection signal (b) in the sub-scanning direction from the OR gate 116 rises to the H level for 13 clocks from 4 clocks that change from the image portion to the non-image portion from the scan lines L8 to L9. As described above, the outer shape signal (a) in the main scanning direction and the image detection signal (b) in the sub scanning direction are the same as the state of the scanning line L4.
FIG. 20 shows the change from the image edge detection signal (b) in the sub-scanning direction (sub-scanning H → L) and the change in the main scanning direction outer shape signal (a) (main scanning H → L) from 10 clocks to 13 clocks. Since each output of the AND gate 159 is at H level from the 14th to 15th clocks of the AND gate 152, the edge detection flag (c) is also set to the scanning line.
As in the case of L4, the sub-color flag SCF is at the H level from 10 clocks when it rises to the H level to 15 clocks.

In such a state, the MC external signal (d) and the SC external signal (e) are at the H level from 4 clocks to 9 clocks as in the case of the scan line L4, and the SC external signal (E) is at H level from the subsequent 10 clocks to 15 clocks. At this time, the line memory 129 stores the pixel positions (4) to (4) to 15 clocks in which either the main scanning direction outer shape signal (a) or the sub-scanning direction image edge signal (b) becomes H level.
The external line width data X =
127 is written, flag data “0” is stored in the address corresponding to the pixel position (4) to (9), and flag data is stored in the address corresponding to the subsequent pixel position (10) to (15). “1” is written in pairs with the above-mentioned outline line width data.

In the scanning line L10 following the scanning line L9,
Since there is no image and the logical sum data of the image data and the previous line L9 is also "0", both the main scanning direction outer shape signal (a) and the sub scanning direction image edge detection signal (b) are both present. As a result, the L level is held, and as a result, the edge detection flag (c) also holds the L level. In such a state, from the 4th clock to the 9th clock, the external line width data read from the line memory 129 is X = 127 (data written at the time of the L9 scan), and the output of the OR gate 134 is at the H level. Further, while the outputs of the AND gate 135 and the OR gate 136 become H level, the flag data which is simultaneously read out in pairs is "0" (data written at the time of the L9 scan).
Since the output of 139 becomes L level, the AND gate 143
Is in the H level state. Also,
From the next 10 clocks to 15 clocks, the line memory 12
Similarly, the outline line width data read from 9 is 127, but since the flag data corresponding thereto becomes "1", the output of the AND gate 139 becomes H level. The signal (e) becomes H level. In the process of reading the line memory 129, if the outer line width data is "0" (pixel positions (1) to (3) and (16) to (1
7)) as it is, the data "0" is fed back and written again at the address corresponding to the same pixel position. On the other hand, when the outer line width data is 127, the outputs of the AND gates 135 and 133 become H level. Since the B input of the adder 131 becomes "1", 127 + 1 = 128, that is, "0" data is written into the addresses corresponding to the same pixel positions (4) to (15). As for the flag data, the read data is fed back as it is, and is written in the original address as a pair with the external line width data.

In the following scanning line L11, the main scanning direction outer shape signal (a), the sub-scanning direction image edge detection signal (b),
Both the edge detection flag (c) and the L level are held. Since the outline line width data stored in the line memory 129 by the processing in the previous scanning line L10 is "0" at all pixel positions (1) to (17) of one line, the MC outline signal Both (d) and the SC outline signal maintain the state of L level. Then, in the subsequent scan lines, the state becomes the same as that of the scan line L11, and the MC outer shape signal and the SC outer shape signal are thereafter kept at the L level.

With the above processing, the MC external signal (d) and the SC external signal (e) shown for each scanning line in FIG. 22 are obtained.
When this is displayed as an image, as shown in FIG. 21 (b), the left side from the pixel position (9) is the main color (MC: black, shaded portion), and the right side from the pixel position (10) is the sub color (SC: red). ,
A rectangular outline image having a line width of 2 pixels (a halftone dot portion), that is, an outline image.

In the above process, the main scanning direction outer shape signal (a) becomes H level even though no image actually exists on the scanning line L9, as described above, because the image data (n ) And the image data (n−1) at the same pixel position one line before, as the new image data, the outline extraction processing in the main scanning direction (main scanning direction outline detection circuit 120) is performed. It is.
This is because the outline in the sub-scanning direction is generated with a width of a predetermined pixel after the outline signal (a) in the main scanning direction or the image edge detection signal (b) in the sub-scanning direction falls to L level. This is because the completely falling scan lines of the external signal (a) in the main scanning direction and the image edge detection signal (b) in the sub-scanning direction are aligned. Thereby, for example, as shown in FIG. 21 (b), the outlines in the sub-scanning direction from pixel positions (4) to (13) in the scanning lines L9 and L10 and the pixel positions (14) and (15) are the same. The outlines are aligned. Conversely, when the image data handled as described above is not logical sum data, the scanning line where the main scanning direction outer shape signal (a) completely falls is L9, and is 1 more than the image edge detection signal (b) in the sub scanning direction. Since the line becomes earlier, the pixel position (14) (15) of the scanning line L10 in FIG. 21 (b)
No contour image is generated, and the contour line is lost.

The outer shape signal of the image generated by the processing described above, that is, the MC outer shape signal for the main color and the SC outer shape signal for the sub color are basically binary image data. Before being transferred to the image forming unit, it is converted into multi-valued image data.

The circuit for this multi-value processing is, for example, as shown in FIG.

In the figure, reference numeral 172 denotes a selection circuit.
72 is “0” data (A) and set density data (8
(B: 256 gradations) and (B) are selectively output (Y). When the selection signal input S is at H level, the set density data (B) is output. When the selection signal input S is at L level. Sometimes, "0" data (A) is selectively output. The set density data is used by an operator to specify desired density data by operating a numeric keypad or the like provided on the console panel, and the set density data corresponding to the operating input is transferred from the CPU. In addition, M
The SC external signal is input to the OR gate 171 as the C external signal, and the output signal from the OR gate 171 is supplied to the selection circuit 1
There are 72 selection signals S. Further, reference numeral 173 is also a selection circuit. This selection circuit 173 selects one of the read density data D (A) directly input from the color image information generation circuit 50 and the output data (B) of the selection circuit 172. When the selection signal input S is at H level, the data (B) from the selection circuit 172 is selected, and when the selection signal input S is at L level, the read density data (A) is selected. Output. A white / original switching signal from the CPU, which is H level when the white image is output (see FIG. 21 (b)) and is low when the original image is output (see FIG. 21 (a)), is a selection circuit. 1
73 are the selection signals S.

According to such a multilevel conversion circuit, when the white / original switching signal is at the H level (white mode),
As shown in FIG. 24, when the logical sum signal (output of the OR gate 171) of the MC external signal and the SC external signal indicating the external line of the image becomes H level, the set density data DN becomes the same logic indicating the non-image part. When the sum signal is at the L level, "0" data is output as final density data via the selection circuits 172 and 173, respectively.

When the white / original switching signal is at the L level (original mode), the density data read from the color image information generation circuit 50 is output as final density data as it is. That is, the white image generation function is prohibited and the normal image processing is performed.

The color flag paired with the density data obtained by the above multi-value conversion is the main color flag as it is with the MC external signal.
The MCF and SC outline signals are sequentially transferred as they are as the sub color flag SCF.

V. Image Forming Unit As described above, the density data and the pair of color flags (MCF, SCF) that have undergone the processing in the correction / filter circuit 70 and the various processings such as the outline extraction in the editing / processing circuit 100 are The data is transferred to an image forming device such as a laser printer 182 and an image transceiver 184 such as a facsimile via the interface circuit 180. The processing in the image forming apparatus will be described below by taking, for example, the laser printer 182 as an example. In this case, a copying machine (digital copying machine) is configured as a whole.

The basic configuration of the laser printer 182 that forms a two-color image based on the density data D and the color flag is, for example, as shown in FIG. The two-color image forming laser printer shown here uses an electrophotographic system, and realizes main color black image forming and sub-color red image forming in one image forming cycle. It is a pass 2 color (1P2C) type copier.

In FIG. 25, a charger 301, a developing device 302 for a sub-color (red), a developing device 303 for a main color (black), a corotron 308 before transfer, and a cleaning device to execute an image forming process around the photosensitive drum 300. The devices 306 are arranged, and the sub-color exposure position Ps is set immediately before the sub-color developing device 302, and the main color exposure position Pm is set immediately before the main-color developing device 303. Regarding the exposure system, the irradiation light from the image writing laser diode 251 for the main color is
Polygon mirror 254 and f-θ lens 2 rotating at a constant speed
55, it is set to reach the exposure position Pm of the main color via the optical system such as the reflection mirrors 257 and 258, and the irradiation light from the image writing laser diode 250 for the sub-color is similarly set on the polygon mirror 254 and the f-θ lens 255 And a reflector
It is set to reach the sub-color exposure position Ps via an optical system such as 256. Further, a transfer corotron 304 and a recording sheet peeling detack 305 are arranged at a transfer position around the photosensitive drum 300, and at this position, the red toner image formed on the photosensitive drum 300 by each of the developing machines 302 and 303 described above. The black toner image and the black toner image are collectively transferred to a recording sheet 310 conveyed from a paper feeding system. Then, the recording sheet 310 on which the image has been transferred is further discharged through, for example, a tray after the image is further fixed by the fixing unit 307.

On the other hand, the image writing laser diodes 250 and 251
Looking at the control system of

The density data Dm and the color flag CF are supplied for each pixel via the interface circuit 180 of the image processing system described above, and based on the color flag CF, the main color density data Dm (black density) and the sub color density data Ds A switching circuit 241 for separating (red density) is provided. In the above processing section, the color flag is composed of two bits of the main color flag MCF and the sub color flag SCF.
Can be changed by the interface circuit 180 into a 1-bit configuration for expressing the sub-color and the rest. In particular,
Only the sub-color flag SCF is the interface circuit 180
Is transferred to the subsequent stage. That is, the pixels in the background area are handled as being included in the main color area, and the color flag CF for controlling the switching circuit 241 is set to H
Level, and pixels in other areas are set to L level.

The specific configuration of the switching circuit 241 is, for example, as shown in FIG. That is, two selection circuits 261 and 262 are provided to select the output from the two input signals (A and B) according to the state of the color flag.
61 is input to the input terminal B and the input terminal A of the selection circuit 262, and "0" data is input to the input terminal A on the opposite side of the selection circuit 261 and the input terminal B on the opposite side of the selection circuit 262, respectively. are doing. The selection circuits 261 and 262 select the input signal on the A side by the control input of the L level and the input signal on the B side by the control input of the H level, respectively, and the color flag CF is the control input. The output of one selection circuit 261 is transferred to the subsequent stage as sub-color density data Ds, and the output of the other selection circuit 262 is transferred to the subsequent stage as main color density data Dm in pixel units. In the switching circuit 241 having such a configuration, the corresponding sub-color density Ds is transferred to the subsequent stage for the pixels in the sub-color area, while the corresponding main color area Ds is transferred to the pixels in the other areas (main color area and background area). The color density data Dm is transferred to the subsequent stage.

The main color density data Dm and the sub color density data Ds separated by the switching circuit 241 are as follows.
Enter 243.

Each screen generator 242,243 is 8 bits 2
Each of the density data Dm and Ds represented by 56 gradations via the switching circuit 241 is converted into a laser diode modulation code for each pixel. Specifically, it converts the density data D expressed by 256 gradations into the laser lighting area amount of each pixel. For example, as shown in FIG. The sub-pixels SP1 to SP3 are set, and the laser lighting area is determined by the number of divided pixels according to the density data D. This screen generator 24
The modulation codes output from 2,243 are set, for example, as shown in Table 2.

According to Table 2, for example, as shown in FIGS. 28 (a) to (d), four levels of density expression for each face are possible.

As described above, when converting the density data D of 256 gradations into a four-step code, the threshold value of each step is determined based on the color reproduction characteristics (development characteristics) of each color. It is set to reproduce. Therefore, different thresholds are set for the first screen generator 242 based on the color reproduction characteristics of the sub-color (red) and for the second screen generator 243 based on the color reproduction characteristics of the main color (black).

The sub-color modulation code SC from the first screen generator 242 is transmitted via a one-line FIFO memory (first-in first-out) 244, and the main color modulation code MC from the second screen generator 243 is transmitted via a cap memory 246. The signals are input to the corresponding first ROS control circuit 245 and second ROS control circuit 247, respectively. The above gap memory
246, as described above, the sub-color exposure position Ps and the main color exposure position Pm are separated from each other by the gap Gp on the photosensitive drum 300 due to the arrangement of the developing devices 302 and 303, so that the sub-color image and the main color image are separated. This is for delaying the transfer timing of the modulation code of the main color by an amount corresponding to the gap Gp in order to match the formation position. Accordingly, the timing of writing and reading of the gap memory 246 is determined by the gap Gp of each of the exposure positions Ps and Pm, the rotation speed of the photosensitive drum, and the like.

The first ROS control circuit 245 generates a laser modulation signal of a corresponding system based on the sub-color modulation code SC, and also generates a control signal for a servo motor 253 for rotating the polygon mirror 254. The second ROS control circuit 247 receives the synchronization signal from the first ROS control circuit 245 and generates a laser modulation signal of a corresponding system based on the main color modulation code MC. A motor driver 252 drives the polygon mirror servo motor 253 at a constant speed based on the control signal from the first ROS control circuit 245, and a laser driver based on a sub-color modulation signal from the first ROS control circuit 245. 248 turns on / off the image writing laser diode 250 for the sub-color,
On the basis of the main color modulation signal from the second ROS control circuit 247, the laser driver 249 turns on and off the image writing laser diode 251 for the main color.

The on / off control of the main-color image writing laser diode 251 and the sub-color image writing laser diode 250 as described above causes a potential state corresponding to each color on the photosensitive drum 300 uniformly charged by the charger 301. Are formed with respect to each of the electrostatic latent images, the developing unit 302 develops a red toner for the sub-color, and a black toner develops the developing unit 303 for the main color. Then, the red and black toner images formed on the photosensitive drum 300 are recorded on a recording sheet 310 supplied from a paper feeding system.
The recording sheet is transferred onto the recording sheet, and after the image is fixed, the recording sheet on which two colors are reproduced is discharged.

After the image outline extraction processing described in the above processing section, for example, when the image on the document becomes a rectangular image as shown in FIG. 21 (a), the above-described scanning section (see FIG. 2) (B) in real time in synchronism with the scanning in FIG. 3 (b), a half-color left-sided rectangular image with a main color black (diagonal line) and a right-hand side with a sub-color red (halftone dot) as shown in FIG. Is reproduced on the recording sheet.

In the above-described sub-color image formation, a latent image Z1 having an exposed portion as an image portion as shown in FIG. 29A is formed, and this latent image Z1 is
The toner image T1 of the sub-color (red) is formed by developing under the condition (1). In the main color image formation,
29 Latent image Z2 in which the non-exposed area becomes the image area as shown in FIG.
The latent image Z2 is developed by the developing device 303 under the second developing bias VB2 to form a main color (black) toner image T2. More specifically, the toner images T1 and T2 are batch-transferred on the recording sheet 310 by the transfer corotron 304 after the polarities thereof are made uniform by the pre-transfer corotron 308.

VI. Conclusion In the above embodiment, in the main scanning direction, the pixel (change point) that changes from the non-image portion to the image portion and the pixel (change point) that changes from the image portion to the non-image portion are set to the H level by the set pixel width. A main scanning direction outer shape signal that is in a rising state is generated, and in the sub-scanning direction, pixels that change from a non-image part to an image part (change points) and pixels that change from an image part to a non-image part (change points) Generates an image edge detection signal which rises. Then, when the external signal in the main scanning direction is in the H level state, an image is generated for each pixel in that state, thereby generating an external line in the main scanning direction. Also,
The state in which the image edge detection signal in the sub-scanning direction is at the H level, and the image edge detection signal and the image in the main scanning direction are generated only for a predetermined line width after the outer shape signal has fallen to the L level, so that the image is detected in the sub-scanning direction. Is generated.

In the main scanning direction, an outline image is generated downstream in the scanning direction from the boundary point between the image portion and the non-image portion, and in the sub-scanning direction, an outline image is generated downstream from the boundary point in the scanning line moving direction. Is generated. this is,
Since it is not necessary to perform the contour generation processing for the pixels of the line that has been read and scanned, the processing is particularly suitable for reproducing the contour in real time in synchronization with the scanning of the original document. I have. Instead of such processing, by securing the image data before the reading time using the memory for storing the image data, the scanning direction or the moving direction of the scanning line from the boundary point between the image part and the non-image part is determined. It is also possible to generate an outline image in the opposite direction.

The outline line width data X set in the line memory is calculated with respect to the pixel width w of the outline line by using X = 128 + 1-w, which is based on an algorithm of a later process. Therefore, it is of course possible to perform processing in accordance with an algorithm for simply setting the pixel width w and generating an outline image having the pixel width w. The pixel width of this outline may be fixed in advance, but can be variably set by an operator's operation input, so that the width is balanced with the size of the image on the document or a width that suits the user's preference. Is generated.

Further, in the above embodiment, a binary image is converted to multi-tone data, but this is not particularly necessary when a binary image is reproduced. However, in the above embodiment, since the image is originally read at 256 gradations, the multi-value processing is performed to match the normal read image reproduction processing. Since the multi-tone data can be variably set, the density can be reproduced according to the user's preference.

Although the above embodiment has been described with reference to a two-color reproduction copier as an example, it is needless to say that a copier for the purpose of reproducing a single color image, other image forming equipment, and further, a multi-color (full color) image reproduction. The application is also applicable to the image forming apparatus described above.

[Effects of the Invention] As described above, according to the present invention, an outline drawing is generated in a scanning direction for a boundary point between an image part and a non-image part detected in the scanning direction, and
In the sub-scanning direction, an outline drawing is generated in the scanning line moving direction with respect to the same boundary point, so that processing in step with reading of image information by the image reading means can be performed, and real-time synchronized with image reading can be performed. Processing is easily realized.

In addition, since the boundary point from the line drawing portion to the non-line drawing portion at each pixel position in the scanning line movement direction of the outline drawing generated in the scanning direction is also subjected to the outline generation in the scanning line movement direction, the scanning direction The outline drawing is formed in the scanning line moving direction from the boundary point of the generated outline drawing, and the continuity of the outline formed in the scanning direction and the scanning line moving direction becomes more complete.

[Brief description of the drawings]

1 (a), 1 (b) and 1 (c) are block diagrams showing the configuration of the present invention, and FIG. 1 (d) shows an example of the state of an outline formed by an image outline extracting apparatus according to the present invention. FIG. 2 is a diagram showing a structural example of a scanning system of an image processing apparatus to which the image outline extracting apparatus according to the present invention is applied. FIG. 3 is an image to which the image outline extracting apparatus according to the present invention is applied. FIG. 4 is a block diagram showing a basic configuration example of the processing apparatus, FIG. 4 is a diagram showing a structural example of a full-color sensor, FIG. 5 is a diagram showing an example of each cell arrangement of the full-color sensor, and FIGS. FIG. 9 is a circuit diagram showing an example of a cell configuration of a pixel unit, FIG. 10 is a circuit diagram showing an example of a configuration of a color image information generation circuit, and FIG. Fig. 12 shows the state of color discrimination. Fig. 12 shows the distance r from the origin and the saturation in the color space. Diagram showing the relationship between, FIG. 13 is a diagram showing a relationship between the angle θ and the hue H in the color space, Fig. 14 shows the correspondence between the density data and the color flag, 15
FIG. 17 is a diagram showing a configuration example of a binarization circuit for binarizing density data of 256 gradations. FIG. 16 is a diagram showing the state of binarized image data and color flags (MCF, SCF). FIG. 18 is a circuit diagram showing an example of the entire configuration of an outline detection circuit. FIG. 18 is a circuit diagram showing an example of the configuration of a main scanning direction outline detection circuit. FIG. 19 is a timing chart showing an operation state of the main scanning direction outline detection circuit. ,
FIG. 20 is a diagram showing a configuration example of an edge detection flag generation circuit, FIG. 21 is a diagram illustrating an original image drawn on a document and its outline image, and FIG. 22 is an outline line extraction 23 is a timing chart showing the operation state of the circuit, FIG.
The figure shows a configuration example of a conversion circuit that changes binary image data extracted as an outline drawing into multi-gradation image data.
24 is a diagram showing a state of conversion into multi-tone data, FIG. 25 is a diagram showing a configuration example of an electrophotographic two-color printer, and FIG. 26 is a configuration example of a circuit for separating density data by a color flag FIG. 27 is a diagram showing an example of a divided pixel constituting one pixel. FIG. 28 is a diagram showing an example of a relationship between a laser modulation code corresponding to density data and a laser lighting state. FIG. 4 is a diagram illustrating an example of development characteristics of a main color and a sub color. [Explanation of Signs] 1 Original 2 Image reading means 3 Edge detecting means in the main scanning direction 4 Edge detecting means in the sub-scanning direction 5 Outline generating means 5a ... Outline drawing generating means in the main scanning direction 5b: Sub-scanning direction outline image generation means 5b-1: Line memory 5b-2: Pixel width setting means 5b-3: Unit image generation means 5b-4: Numeric correction means 10: Full color sensor 20 ... Sensor interface circuit 50 ... Color image information generation circuit 70 ... Correction / filter circuit 100 ... Editing / processing circuit 180 ... Interface circuit 182 ... Laser printer 184 ... Image transceiver 186 ... Computer

Claims (3)

(57) [Claims] An image reading means (2) for optically scanning an original (1) while sequentially moving (S) a scanning line (L) to read image information in predetermined pixel units. An image processing apparatus for processing image information sequentially read in pixel units by means (2), wherein each of the scanning lines (L) based on the image information read by the image reading means (2). Main scanning direction edge detecting means (3) for detecting a boundary point between the image portion (I) and the non-image portion (NI); and each of the scanning line (L) moving directions (S) based on the read image information. A sub-scanning direction edge detecting means (4) for detecting a boundary point between an image part (I) and a non-image part (NI) at a pixel position; and a boundary point detected by a main scanning direction edge detecting means (3). Generate outline drawing in the scanning direction (Sm) for A sub-scanning outline drawing which generates an outline drawing in the scanning line moving direction (Ss) with respect to the boundary point detected by the main scanning direction outline drawing generating means (5a) and the sub-scanning direction edge detecting means (4). And a contour line generating means (5) comprising a generating means (5b), wherein the sub-scanning direction contour image generating means (5b) includes a storage address corresponding to each pixel position on the scanning line. And a line image to be generated at each storage address of the line memory (5b-1) when the boundary point is detected in the course of scanning the original by the image reading means (2). A pixel width setting means (5b-2) for setting a numerical value corresponding to the pixel width of a pixel corresponding to an address where a numerical value is set in the line memory (5b-1) for each scanning line from the boundary point. Nitsu Unit image generating means (5b-3) for generating a unit image, and a numerical value of a corresponding address in the line memory (5b-1) when the unit image is generated by the unit image generating means (5b-3) And a numerical value correcting means (5b-4) for correcting the image width to reduce the pixel width by one line. 2. The sub-scanning direction outline drawing generating means (5b).
Means that the boundary point from the line drawing portion to the non-line drawing portion at each pixel position in the scanning line moving direction (Ss) of the outline drawing generated by the main scanning direction outline drawing generating means (5a) is also targeted. 2. The image outline extracting apparatus according to claim 1, wherein: 3. An image reading means (2) for optically scanning a document (1) while sequentially moving (S) a scanning line (L) and reading image information in predetermined pixel units. An image processing apparatus for processing image information sequentially read in pixel units by the means (2), wherein each of the scanning lines (L) based on the image information read by the image reading means (2). A main scanning direction edge detecting means (3) for detecting a boundary point between the image portion (I) and the non-image portion (NI); and each of the scanning line (L) moving directions (S) based on the read image information. A sub-scanning direction edge detecting means (4) for detecting a boundary point between an image part (I) and a non-image part (NI) at a pixel position; and a boundary point detected by a main scanning direction edge detecting means (3). Generates outline drawing in the scanning direction (Sm) for A sub-scanning contour image generating unit generates a contour image in the scanning line moving direction (Ss) with respect to the boundary point detected by the main scanning direction contour image generating means (5a) and the sub-scanning direction edge detecting means (4). And a contour line generating means (5) comprising a generating means (5b), wherein the sub-scanning direction contour image generating means (5b) includes a main scanning direction contour image generating means (5a). An image outline extracting apparatus, which also targets a boundary point from a line drawing part to a non-line drawing part at each pixel position in a scanning line moving direction (Ss) of the generated outline drawing.