JP3213347B2 - Digital copier and contour mode processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital copying machine及beauty contour mode processing method having a contour mode.

[0002]

2. Description of the Related Art Conventionally, in a digital copying machine provided with a contour mode, an image signal obtained by reading a document is binarized using a fixed threshold value, edge extraction processing is performed, and a contour image is output. I have to.

[0003]

However, according to such a contour mode, even when the original has a continuous gradation like a photographic image, the recorded contour line crosses over a fixed threshold and the image signal is over. Only where the level of
The line density of the contour cannot be controlled.

Further, when processing an image having a continuous gradation, the signal of the image portion for which contour extraction is to be performed and the signal of the background image may not cross a fixed threshold level.
In some cases, a desired contour cannot be extracted.

[0005]

An image reading means for outputting a multivalued image signal having the number of gradations of the three or more gradations by reading the information, such as [means for solving the problems] document image, multi-output from the image reading means
Binarization processing means for binarizing the value image signal according to the gradation level; edge extraction processing means for performing edge extraction processing based on the binary image signal output from the binarization processing means; and image recording means for recording an image based on an image signal output from the edge extraction processing means, said multi-value image
The input level to the signal binarization processing means is divided into a plurality of sections.
Set the threshold value so that it can be divided
Binarized output level by alternately switching between 1 and 0
And conversion characteristic setting means for changing and setting the conversion characteristic of the binarization processing means .

[0006]

In addition to the image reading means, the binarization processing means, the edge extraction processing means and the image recording means, an input means for selecting and specifying the line density of the contour, and the input means for selecting and specifying the line density of the contour selected by the input means Conversion characteristic setting means for changing and setting the conversion characteristic of the binarization processing means, and binarization by the conversion characteristic setting means in accordance with the line density of the contour selected and designated according to the contour mode by the input means. The conversion characteristics of the processing means are changed and set, and output from the image reading means.
Divide a multi-level image signal into multiple sections according to the gray level
Set multiple thresholds as described above,
The output level is binarized to switch to 1,0 alternately, since to extract the edge image by the edge extraction means based on binary image signal, binarization once
And edge extraction processing, it is possible to select the line density of the contour line to be extracted and recorded , and appropriate contour processing can be performed even for a document image or the like having continuous gradation. In particular, since the number of section divisions corresponding to the gradation level at which the binarization level is changed also increases / decreases in accordance with the line density, even if the original image has a continuous gradation, an image portion to be contour extracted is desired. And the signal of the background image do not straddle the binarization level, and desirable contour extraction becomes possible.

[0007]

An embodiment of the present invention will be described with reference to the drawings. First, FIG. 2 shows an outline of a digital color copying machine as an example to which the present invention is applied, and FIG. 3 shows an outline of an electrical unit. As shown in FIG. 2, the digital color copying machine of this embodiment is roughly divided into a scanner unit (image reading means) 1 for reading a document and a printer unit (image recording means) 2 for recording an image on a recording sheet. You. Referring to the scanner unit 1, a document 4 placed on a platen (contact glass) 3 is exposed and illuminated by a fluorescent lamp 5. Manuscript 4
The reflected light from the camera enters a CCD 7 serving as a color image sensor via a lens array 6, and is converted into an image signal (color separation into R, G, and B) by photoelectric conversion. Here, the fluorescent lamp 5, the lens array 6, the CCD 7 and the like are mounted on the carriage 8, and the carriage driving motor 9
As a result, the carriage 8 moves from right to left, and the entire surface of the document 4 placed on the platen 3 is scanned. The image signal output from the CCD 7 is input to a laser diode (not shown) of the printer unit 2 after being subjected to various types of image processing by the image processing unit 10 and the like.

In the printer unit 2, Y, M, and Y emitted from a laser diode energized by an image signal are output.
The laser beams for C and BK are respectively reflected by the polygon mirror 11 and the like, and are imaged and irradiated on the respective drum-shaped photoconductors 14 via the fθ lens 12 and the mirror 13. Each polygon mirror 11 is fixed to a rotation shaft of the same polygon motor 15, and the polygon motor 15 rotates at a constant speed to drive the polygon mirror 11 to rotate. By the rotation of the polygon mirror 11, the laser beam is scanned in a direction perpendicular to the rotation direction (clockwise) of the photoconductor 14, that is, in a direction along the drum axis. Here, the surface of the photoreceptor 14 has been uniformly charged by the charging charger 16 connected to the negative voltage high voltage generator. Therefore, when the laser beam is irradiated, the charge on the surface of the photoconductor flows to the device ground of the drum main body due to the photoconductive phenomenon and disappears. Here, the laser diode is not turned on in the portion where the document density is high, and the laser diode is turned on in the portion where the document density is low. As a result, an electrostatic latent image corresponding to the density of the document is formed on the surface of the photoconductor 14. When this latent image is developed by the developing unit 17, a toner image corresponding to the image density is formed on the photoconductor 14.

On the other hand, the recording paper 19 stored in the paper feeding cassette 18 is fed out by a paper feeding operation of a paper feeding roller 20 and the like.
2 sent over. While the recording paper 19 conveyed on the transfer belt 22 passes under the photoreceptor 14, the toner image on the photoreceptor 14 is changed by the operation of the transfer charger 23.
Is transferred to After the transfer, the recording paper 19 is separated from the separation charger 2.
4 and is sent to the fixing unit 26,
Upon receiving the fixing, the sheet is discharged onto a sheet discharge tray 28 by a sheet discharge roller 27.

After the transfer, the toner remaining on the photoreceptor 14 is removed by a cleaning unit 29, and the toner adhering to the surface of the transfer belt 22 is removed by the cleaning unit 3.
0, and each is discharged to the waste bottle 31. Also,
The residual charge on the surface of the photoreceptor 14 is erased and erased by an erase lamp 32.

Referring to the electrical components, as shown in FIG. 3, together with the above-described scanner unit 1, printer unit 2, and image processing unit 10, an operation display unit for inputting and displaying various processing modes, etc. Input means) 3
3. A system control unit (conversion characteristic setting means) 3 which communicates with the control units in these units 1, 2, 33, and controls the entire copying machine and sets the image processing unit 10.
4 and the like. An external device 36 is connectable to the copying machine main body 35 having such an electrical unit, and is configured to be able to transmit and receive an image signal through communication between the copying machine main body 35 and the external device 36. ing.

It is assumed that the digital color copying machine of the present embodiment can read and write an A3-size original image and has a pixel density of 16 pixels / mm.

Hereinafter, the configuration and operation of each unit will be individually described. First, the scanner unit 1 will be described with reference to FIGS. FIG. 4 shows the electrical configuration of the scanner unit 1. The CCD 7 on which the reflected light of the original is incident is composed of five CCD color sensor chips 7a to 7e arranged in a staggered manner on a substrate. It is driven by an operation control clock output from the driver 51. Here, the output signal of the CCD color sensor chip 7a is amplified by the preamplifier circuit 52 and then input to the shading correction circuit 53. The shading correction circuit 53 is a circuit for performing correction for uneven illumination of the fluorescent lamp 5, uneven sensitivity of the light receiving element in the CCD, dark current, and the like. The output of the circuit is converted into an 8-bit digital signal by the A / D converter 54. Is done. A white level memory 55 and a dark current memory 56 are circuits for storing reading results of a white reference plate and a black reference plate which are scanned prior to a document portion, respectively.
The level of the image signal to be output is adjusted according to the outputs of 5, 56 to realize the above-described correction. Such an output signal processing circuit 57a is connected to another CCD color sensor chip 7
Similarly, the output signal processing circuits 57b to
57e.

Further, delay circuits 58b and 58d are connected to outputs of the output signal processing circuits 57b and 57d. These delay circuits 58b and 58d are circuits for delaying an input image signal, thereby correcting a shift d _{CCD in} the sub-scanning direction between the CCD color sensor chips 7a to 7e arranged in a staggered manner, and Are input to the RGB separation circuit 59 as image signals on the same line.

In the scanner unit 1 according to the present embodiment, the magnification in the sub-scanning direction is realized by changing the moving speed of the carriage 8, so that the required delay amount changes according to the magnification. That is, d _CCD x magnification / 100 /
There are 16 lines. On the other hand, the delay circuits 58b and 58d of the present embodiment have delay memories of the number of lines corresponding to the magnification, and control the number of lines to be delayed by the memory for reduction and equal magnification, and enlargement. In this example, the required delay amount is realized by prohibiting writing to the memory in line units and duplicating the reading. For this reason, even when enlargement is performed, the required capacity of the delay memory is the same as that of the same size.

Since the CCD color sensor chips 7a to 7e have a structure in which R, G, and B filters 60 are arranged in order as shown in FIG. 5, the output image signal is a state in which RGB signals are mixed. It has become. Therefore, the RG
The B separation circuit 59 integrates the image signals from the five CCD color sensor chips 7a to 7e sent in parallel into one, and separates these signals into respective colors. The image signal R thus integrated and separated is
s, Gs, and Bs are output to the image processing unit 10.

The scanner unit 1 is provided with a scanner control circuit 61 for controlling the entire unit. The scanner control circuit 61 includes a CPU 62, a ROM
63, a RAM 64, a microcomputer system including a serial I / O circuit 65, a parallel I / O circuit 66, and the like for communicating with the system control unit 34. Further, the parallel I / O circuit 66 inputs various sensor signals such as a home position (HP) sensor 67, outputs a signal for setting a delay amount for the delay circuits 58b and 58d, and outputs a signal to the carriage drive motor 9 and the like. This is for outputting a signal for controlling a drive circuit 68 for driving various loads such as the fluorescent lamp 5 and the like. That is, the scanner control circuit 61 operates according to the program stored in the ROM 63, and performs setting of each circuit and drive control of various loads in accordance with a command from the system control unit 34 and various sensor signals.

Reference numeral 69 denotes a reference clock generation circuit which outputs various synchronization signals based on the line synchronization signals SYNCs output from the image processing unit 10. Each of the circuits described above operates in synchronization with this signal.
Further, the reference clock generation circuit 69 converts the line synchronization signal and the pixel synchronization signal CKs in the scanner unit 1 into
The image is output to the image processing unit 10.

Next, the image processing section 10 will be described with reference to FIG. FIG. 6 shows the overall configuration of the image processing unit 10. In general, a main scanning magnification changing circuit 72 controlled according to an image synchronization signal S ₁₀ generated by a synchronization signal generation circuit 71, a processing circuit 73, a first filter processing circuit 74,
External I / F circuit 75, first γ conversion processing circuit 76, color correction circuit 77, UCR processing circuit 78, second γ conversion processing circuit 7
9, document size detection circuit 80, second filter processing circuit 8
1. Multi-value dither processing circuit 82 and delay processing circuit 83
It is connected to the output side of the RGB separation circuit 59 in order. Further, an area control circuit 84 is also provided. These components will be described in order.

First, the timing generator will be described with reference to FIGS. The synchronization signal generation circuit 71
Line synchronization signal SY output from printer unit 2
NCp and based on the setting of the control signal BUSo outputted from the system control unit 34, a circuit for generating a synchronous signal S ₁₀ in the image processing unit 10, configured as shown in FIG. 7, for example.

The clock generator 101 for generating a reference clock signal S ₁₁ is provided in the synchronization signal generating circuit 71, flip-flop 10 at its output side for generating a clock signal S ₁₂ that the reference clock signal S ₁₁ divided by 2
2 are connected. Meanwhile, the clock signal S ₁₂ synchronized with line sync signal SY to indicate the line synchronization signal SYNCp output from the printer unit 2 in FIG. 7
A waveform shaping circuit 103 for converting to NCs is provided. Also, the flip-flop 104 and OR gate 105 to produce a 2-fold cycle of the line synchronization signal S ₁₃ is connected. These signals S ₁₁ , S ₁₂ , SYNCs, and S ₁₃ are used as selectors 1 that constitute means for switching the image signal reception speed.
06, one of them is selectively output as the pixel synchronization signal S ₁₀₁ and the line synchronization signal S ₁₀₂ in the image processing unit 10. Therefore, the selector 106 supplies the control signal BUSo
Signal S ₁₄ set in the synchronization signal register 107 by
The selection operation is performed according to. In the present embodiment, it is possible to operate in two modes, a high-speed mode and a low-speed mode, by switching between a pixel synchronizing signal and a line synchronizing signal. In particular, the latter low-speed mode is capable of fixing OHP sheets and thick paper. Is selected when using recording paper that requires

Further, the counter 108 for counting the pixel sync signal S ₁₀₁ is cleared is provided in the line synchronizing signal S _102, the counter 108 outputs each comparator 1
09,110. To these comparators 109 and 110, a signal indicating the start point and an end point of the effective image area in the main scanning direction set in the synchronization signal register 107 are also input.
The output of the ND gate 111 becomes H level in the ineffective image range in the main scanning direction. Also, the NAND gate 11
1 of the output signal is output to the multi-level dither processing circuit 82 as the main scanning direction erase signal S _103.

The signals S ₁₅ and S ₁₆ set by the control signal BUSo are held in the flip-flop 112 in synchronization with the line synchronizing signal S ₁₀₂ , and are respectively provided as a frame synchronizing signal S ₁₀₄ and a sub-scanning direction erase signal S _105. Is output.

FIG. 9 is a timing chart showing such signal generation.

[0025] Returning to FIG. 6, output from the synchronizing signal generating circuit 71 the image synchronization signal S ₁₀ is input each circuit of the image processing unit 10, the scanner unit 1, the system control unit 34 or the like. Further, the image signals Rs, Gs, Bs and the synchronizing signal CLKs output from the scanner unit 1 are input to the main scanning direction scaling circuit 72.

This main scanning magnification change is shown in FIGS.
3 will be described. The main scanning scaling circuit 72 performs scaling processing in the main scanning direction on the image signals Rs, Gs, Bs, and the like.
It outputs processed image signals S _20R , S _20G , and S _20B , and the main scanning magnification changing circuit 72 is composed of independent processing circuits 72 _R , 72 _G , 72 _{B for} each color image signal. However, the configuration itself is the same, for example, as shown in FIG. Here, a circuit example for the image signal Rs will be described.

First, an input image signal Rs or the like is converted into a FIFO (first-in-first-out) memory 121, 1 serving as image storage means in accordance with a synchronization signal CLKs.
Written in 22. Here, the synchronization signal CLKs is shown in FIG.
Consisting pixel such as an image signal Rs synchronizing signal S ₂₁ and the line synchronization signal S ₂₂ as shown in. Also, the write gate circuit 12
Reference numeral 3 denotes a circuit for outputting a signal indicating the write start position at the end of the line set by the control signal BUSo, and this signal regulates the writing of image signals to the FIFO memories 121 and 122. The FIFO memories 121, 1
22 is, for example, μPD42505C manufactured by NEC Corporation.
And a device having a capacity capable of storing an image signal of one line or more, and a built-in address counter for writing / reading that can be controlled independently. These FIFO memories 1
The image signals written to the registers 21 and 122 are read by the line synchronization signal S ₁₀₂ output from the synchronization signal generation circuit 71 and the read clock S ₂₃₁ output from the scaling processing circuit 124, and written into the shift register 125. .

The flip-flop 126 inverts the output every time the line synchronization signal _S102 is input, and
Toggle control of writing / reading of the memories 121 and 122 is performed.

The shift register 125 outputs pixel signals S _{241 to} S _{244 of} four consecutive pixels, which are input to respective parts of the multiplying circuit 127. Each part of the multiplication circuit 127 by a factor determined for each respective sections as shown in Table 1 by a factor switching signal S ₂₃₃ output from the magnification processing circuit 124, and multiplication processing an input image signal, and outputs the result. The multiplication results of the respective units of the multiplication circuit 127 are input to the addition and shaping circuit 128, summed up, further processed for overflow and negative value, and output to the FIFO memory 129.

[0030]

[Table 1]

The shift register 125 and the multiplication circuit 1
27 and the addition shaping circuit 128, as shown in FIG.
It is provided to interpolate image signal values at virtual sampling points after scaling from image signals D _{1 to} D ₄ sampled by a CD. Further, the coefficients shown in Table 1 has been determined based on a sampling function, the choice of coefficients is determined by the distance between the virtual sampling point and the CCD image signal D ₂ [delta].

The writing into the FIFO memory 129 is controlled by a write clock S ₂₃₂ and line synchronization signal S ₁₀₂ that the variable magnification processing circuit 124 outputs a pixel synchronizing signal S ₁₀₁ that read that output from the synchronizing signal generating circuit 71 This is performed by the line synchronization signal _S102 . The output is input to the mask processing circuit 130. Mask processing circuit 1
Reference numeral 30 denotes a circuit for whitening the image signal in accordance with the mask signal _S234 output from the scaling processing circuit 124, and outputs a processed image signal _{S20R and the} like ( _S20G , _S20B ).

The magnification processing circuit 124 calculates the position of the above-mentioned virtual sampling point and outputs the read / write clock signals S ₂₃₁ and S ₂₃₂ , the coefficient switching signal S ₂₃₃ and the mask signal S ₂₃₄ . It is configured as shown in FIG. In the figure, reference numeral 131 denotes a circuit for outputting the reciprocal of the magnification. The reciprocal of the magnification is the sum of the output S ₃₀ of the magnification register 132, the cumulative change S _{31 in the} sub-scanning direction, and the cumulative change S _{32 in} the main scanning direction. Is output from the adder circuit 133. Here, the value set by the output S ₃₀ of the magnification register 132 control signals BUSO, area control circuit 84
_Is determined by the selection based on the area signal _S331 output from. Further, the accumulated variation amount S ₃₁ in the sub-scanning direction selects the decrement value set in the sub-scanning direction increases or decreases the register 134 by the control signal BUSo by the area signal S _332, the adder 135 and the flip-flop 136 it, line sync It is determined by performing cumulative addition every time the signal _S102 is input. The cumulative amount of change is cleared by the frame synchronizing signal S _104. Cumulative change amount S ₃₂ in the main scanning direction is selected by the area signal S ₃₃₃ to increase or decrease value set in the main scanning direction increases or decreases the register 137 by the control signal BUSO, the adder 138 and the flip-flop 139 it
Is determined by cumulative addition every time the clock output from the OR gate 140 is input. This accumulated change amount is cleared by the line synchronization signal _S102 .
The signal indicating the reciprocal of the magnification output from the reciprocal magnification output circuit 131 is an integer part signal S ₃₄₁ and a decimal part signal S
₃₄₂ and processed.

The integer part signal _S341 is input to the comparator 141, and it is determined whether or not the enlargement is performed (that is, whether or not the integer part is 0). That is, in the case of enlargement, the signal S ₃₅₁ is at the H level, the signal S ₃₅₂ is at the L level, and reduced (including the same magnification).
In the case of, the opposite is true.

Here, the operation in the case of enlargement will be described. In this case, since the output of NOR gate 142 will always be L level, the clock signal output from the write clock signal S ₂₃₂ and the OR gate 140 output from the OR gate 143 is equal to the pixel sync signal _{S 10.} This OR
Since the output of gate 140 controls the flip-flop 144, an adder 145, a selector 146 the flip-flop 144 performs cumulative addition of the fraction signal _{S 342} each time the pixel synchronization signal. The upper bits of the accumulated result output from the flip-flop 144, for example, 3 bits in the case of Table 1, are output as the coefficient switching signal _S233 . It should be noted that the selector 146 controls the line synchronization signal S
_{While 102} is being input (L level), the control signal BUS
Since the offset signal set in the offset register 145 is output by o, the output of the flip-flop 144 after releasing the line synchronization signal becomes equal to the offset signal. This offset signal is used to correct the difference in the center position between RGB caused by the color image sensor structure shown in FIG. That is, the offset signal set in the offset register 145 is different for each of the main scanning scaling circuits 72 _R , 72 _G and 72 _B.

On the other hand, the carry output signal of adder 145 is input to adder 146, and its output is
47 (the output of the NOR gate 142 is always at L level) and is input to the comparator 148. In the case of enlargement, the integer part signal _S341 is 0, so that the input of the comparator 148 becomes 1 only when a carry signal is generated in the adder 145, and becomes 0 in other cases. The comparator 148 outputs a signal of H level when the input is 1, and in this case, the output of the NOR gate 149 becomes L level, and the read clock signal S ₂₃₁ is output from the OR gate 150. In the case of enlargement, the signal S ₃₅₂
Is always at L level, the read clock is generated only when a carry signal is generated in adder 145.

Next, the operation in the case of reduction will be described. In this case, since the output of the NOR gate 149 is always at the H level, the read clock signal S ₂₃₁ output from the OR gate 150 becomes equal to the pixel synchronization signal S ₁₀ . When the flip-flop 151 is cleared by the line synchronization signal _S102 , the input of the comparator 152 becomes 1 or 0.
Therefore, the H level is output, and as a result, the output of the NOR gate 142 becomes the L level. Thus, immediately after the line synchronization signal changes to the H level, the integer part signal S ₃₄₁
Is stored in the flip-flop 151. On the other hand, the output of the flip-flop 151 is a decrement circuit 153,
The signal is again input to the flip-flop 151 via the selector 147, and this is repeated until the value of the flip-flop 151 is decremented to 1 and the output of the NOR gate 142 becomes L level.

On the other hand, when the output of the NOR gate 142 becomes L level, the OR gate 140 generates a clock, and the sum of the accumulated value of the decimal part and the reciprocals S ₃₄₁ and S ₂₄₂ stored in the flip-flop 144 is calculated by the flip-flop. Step 14
4,151. In the next cycle of the pixel synchronization signal S ₁₀ , the write clock S ₂₃₂ is output from the OR gate 143 by the operation of the flip-flop 153.

Next, the OR gate 150 has a counter 1
54 are connected. This counter 154 is cleared by the line synchronizing signal _S102 , and the read clock signal S
₁₀₁ is counted, and the output is input to the comparator 155. The effective image width register 156 is set by the control signal BUSo, and the write gate circuit 12
The number of effective image signals determined by the writing start position of the leading end of the line set to 3 and the effective range of the document in the main scanning direction (FIG.
1), and this output is also input to the comparator 155. Therefore, comparator 1
55 outputs an H level when the output of the counter 154 reaches the number of valid image signals, and inhibits the counting operation of the counter 157. This counter 157 has a line synchronization signal S
Is cleared at _102, and counts the write clock signal S ₁₀₁ that is input via the OR gate 158, the output of which is held in the flip-flop 159 before the counter 157 by the line synchronizing signal S ₁₀₂ is cleared. Counter 160 is cleared by the line synchronization signal S _102, and counts the pixel sync signal S _10, the output of which is input to the comparator 161. The output signal of the flip-flop 159 is also input to the comparator 161, and outputs a mask signal S ₂₃₄ for inhibiting whitening until the output of the counter 160 reaches the output value of the flip-flop 159.

As described above, the main scanning magnification changing circuit 72 of this embodiment is used.
According to the discrete switching of magnifications, the main scanning and continuous magnification change in the sub-scanning directions can be realized by control of setting a region signal S ₃₃ to the magnification inverse output circuit 131 by the control signal BUSO. Further, with the discontinuous switching of the magnification and the continuous magnification change in the sub-scanning direction, the effective image range in the main scanning direction after the scaling process changes for each line.
In this embodiment, the number of pixels written to the FIFO memory 129 is counted when reading from the FIFO memories 121 and 122 is within the effective image range, and the number of pixels exceeds the number of pixels when reading an image signal from the FIFO memory 129. The whitening of the image signal makes the erase control in the main scanning direction easy.

Referring back to FIG. 6, the image signals S _20R , S _20G , and S output from the main scanning scaling circuit 72 are output.
_20B is input to the processing circuit 73.

FIGS. 14 to 1 show the processing section.
This will be described with reference to FIG. The processing circuit 73 is a circuit that performs a shift process in the main scanning direction on the image signals S _20R , S _20G , and S _20B and outputs processed image signals S _35R , S _35G , and S _35B . It is configured as shown.

First, the image signals S _20R , S _20G , S _20B are input to the line buffer circuits 171 _R , 171 _G , 171 _B , respectively. Note that these line buffer circuits 17
1 _R , 171 _G , and 171 _B have the same configuration, and here, only the line buffer circuit 171 _R is shown in detail. Focusing on the line buffer circuit 171 _R, the image signal S _35R are input to the buffer 172, memory control circuit 17
3, control signals S _{361 having} different signal levels,
Is selectively output to the line memories 174 and 175 by S _362. For example, when the image signal is output to the line memory 174 when the control signal S ₃₆₁ is at the H level, the I / O terminal of the line memory 174 enters a high impedance state by the control signal S ₃₆₁ and is output from the memory control circuit 173. image signal S _20R is written in the line memory 174 by the address signal S ₃₇₁ and the write enable signal S _381. At this time, the control signal S ₃₆₂ is at the L level, and the address signal S ₃₇₂ is output from the line memory 175.
Is read out. Also, the selector 176
Are in a state where the image signal output from the line memory 175 is selected. On the other hand, when the control signal _S361 is at the L level, the image signal _S20R is written into the line buffer 175, and the selector 176 outputs the image signal read from the line buffer 175.

Here, the memory control circuit 173 is a circuit for outputting a control signal to the line buffer circuits 171 _R , 171 _G , 171 _B and the like, and is configured as shown in FIG. 14, for example. First, the counter 177 is normally cleared by the line synchronization signal S ₄₀ which is input via the selector 178, and counts the pixel sync signal S _41, the output is lower write address signal of the line memory 174, 175 Used as etc. Further, the up-down counter 179 is initialized by a control signal BUSo read start address to the line synchronizing signal S ₄₀ that is set by,
And counts the synchronous signal S _41, the output of which is used as the lower read address signal of the line memory 174, 175. The flip-flop 180 holds an up / down control signal input simultaneously with the read start address and an upper address signal of the line memories 174 and 175. The system control unit 34 realizes italic processing and mirror image processing by the read start address and the up / down control signal.

The flip-flop 181 controls a toggle control signal S for the line memories 174, 175 and the like.
₃₆₁ and _S362 are output from the selector 18
2, 183, lower address signal selection output, OR
Write enable signal S by gates 184 and 185
Used for the masks ₃₈₁ and _S382 .

Next, the up / down counter 179
Are also input to the comparators 186 and 187. To the other inputs of these comparators 186 and 187, signals S ₄₂ and S ₄₃ representing the start position and the end position of the effective image range in the main scanning direction set in the effective image range register 188 by the control signal BUSo are respectively input. Have been. Outputs of the comparators 186 and 187 are input to an OR gate 189. Therefore, the output signal S ₄₄ of the OR gate 189 indicates whether the lower read address of the line memory 174 and 175 is within the effective image range.

Referring again to the line buffer circuit 171 _R , the signal S ₃₉ is input to the gate terminal of the selector 176, whereby the line memory 174, 1
When the reading from 75 is within the effective image range, the selector 1
76 outputs an image signal from the line memory 174 or 175, and outputs a white (all bits H) image signal when out of the range.

The image signal output from the selector 176 is input to the selector 190 and the level detection circuit 191.

The level detection circuit 191 controls the control signal BUSo
Is a circuit that compares the image signal with the value set by (1). In this example, three types of values a, b, and c can be set, and these set values are each used to detect whether the image signal Di is smaller or not, and to detect coincidence between the upper bit Di 'of the image signal and the comparator. And the respective comparison results are output as signals S ₄₅₁ , S ₄₆₁ , and S ₄₇₁ .

Although the line buffer circuits 171 _R , 171 _G , and 171 _B have the same configuration as described above, the values a, b, and c of the level detection circuit 191 and the like can be set independently. Has become.

The signals S ₄₅ , S ₄₆ , S _{47 and the} like output from the line buffer circuits 171 _{R to} 171 _B are input to the OR gate 193 and the selector 194 in the shadow control circuit 192. The output of the OR gate 193 is H
At level (ie, when the image signal is far from white)
The shadow length register 19 set by the control signal BUSo
Signal representative of the length of the shadow output from 5 S ₄₈ and the signal S _471, select the S _472, S _473, when the output of OR gate 193 is at L level (i.e., when the image signal is close to white) The signals S ₄₉ and S ₅₀ output from the shadow area determination circuit 196 are selected and output to the line memory 197. The signal S ₅₁ that is output to the line memory 197 represents the length of the shadow, the signal S ₅₂ represents the color of the shadow.

[0052] Control of the line memory 197 is performed by a memory control circuit address signal S ₃₇₃ output from 173 and the write enable signal S _383, the data at the address designated by the address signal S ₃₇₃ is read, the shadow After being output to the area determination circuit 196, the selector 1
Data output from 94 is written to the same address. While data is being read from the line memory 197, the output of the selector 194 is in a high impedance state by the signal _S383 .

The shadow area determination circuit 196 is a circuit for determining a shadow area and the like, and is configured, for example, as shown in FIG. First, the signals S ₅₁ and S ₅₂ output from the line memory 197 are applied to the signal S ₅₁ by the flip-flop 198.
It is held by the falling _edge of ₃₈₃ . Flip-flop 19
Signal S ₅₃ representing the length of shadow 8 outputs the comparator 1
At 99, it is determined whether the length is 0. When the length is 0, the length is reduced.
And output to the flip-flop 201. The flip-flop 201 delays the signal output from the selector 200 and the signal _S54 indicating the length of the shadow output from the flip-flop 198 by one pixel, and outputs the delayed signal to the selector 194 shown in FIG. In addition, the comparator 199
Is not 0 and the signal S ₅₅
Is L level, it is determined that the region is a shadow region, and the selector 2
02 selects the signal S ₅₄ representing the color of a shadow flipflop 198 is outputted, and when the other it is output as the inverted signal S ₅₀ selects the signal (no color) of all bits L.

Referring again to FIG. 14, the signals S ₅₀₁ , S ₅₀₂ , and S ₅₀₃ output from the shadow area determination circuit 196 are N
The signals are input to OR gates 203, 204, and 205. The signals S _{461 to} S ₄₇₃ output from the line buffer circuits 171 _R , 171 _G , 171 _B are N
The signals are input to the AND gates 206 and 207, whereby a match between the color represented by the image signal and the set color is detected, and the result is input to the NOR gates 208 and 209.

On the other hand, the area signals S ₃₃₄ and S ₃₃₅ are selection signals for no processing / shadow processing / designated color / color conversion processing 1/2.
3, 204, 205, 208, and 209. That is, the NOR gates 203 to 205 output the area signal S _33.
When the shadowing process is selected according to, and the determination result of the shadow region for each color is true, an H-level signal is output and N
The OR gate 208 outputs an H level signal when the designated color / color conversion 1 is selected and the color represented by the image signal matches the set color (b or the like), and the NOR gate 209 outputs the designated color / color. When the conversion 2 is selected and the color represented by the image signal matches the set color (c or the like), an H-level signal is output.

The color selection circuits 211 _R , 211 _G , 211 _B have the NOR gates 203, 204, 205, 208,
The value corresponding to the output signal of the control signal BUSo
, The color selection circuit 211 has a value corresponding to the output signal of each NOR gate at H level, and the selectors 190 _R , 190 _G , 190 _B when the output of each NOR gate is at L level. _Are output as image signals S _35R , S _35G , and S _35B , respectively.

[0057] The pattern generating circuit 212 is a circuit for outputting in synchronization image signal of the image processing unit operation check pattern or the like to the image synchronization signal S _10, the control signal BUS
o, these patterns are selected, and at the same time, the image signal output from the pattern generation circuit 212 is
A setting is also made as to whether or not 90 _R , 190 _G , and 190 _B are to be selected.

Further, the image signal selection circuit 213 is a circuit for selecting an image signal stored in the line memory 174 or 175 and outputting it on the signal line BUSi. The selection of the image signal is performed by a control signal BUSo.

That is, the system control unit 34 switches the upper address signal to be set in the flip-flop 180 in FIG. 15 according to the position in the sub-scanning direction at the time of scanning of the original, whereby the image signals stored in the line memories 174 and 175 are switched. Do not rewrite. Then, changing the setting of the read control register 214, is output from the control signal by generating a line sync signal S ₄₁ and the pixel synchronization signal S ₄₂ from BUSo adjust the position of the main scanning direction, the line memories 174, 175, etc. An image signal is selected and captured by the image signal selection circuit 213.

As described above, in this embodiment, since the system control unit 34 can detect the color at a predetermined position of the document,
Level detection circuit 178 and color selection circuit 2 corresponding to the color of the document
11 and the like can be set.

Referring again to FIG. 6, the processing circuit 7
The image signals S _35R , S _35G , and S _35B output from 3 are the first.
The signal is input to the filter processing circuit 74.

The first filter processing section will be described with reference to FIG. The first filter processing circuit 74 _subjects the image signals S _35R , S _35G , and S _35B to two-dimensional filter processing of 3 lines × 5 pixels and processes the processed image signals S _55R , S _55G ,
This is a circuit that outputs _S55B . First filter processing circuit 7
4 is an independent processing circuit 74 _R , 74 _G ,
74 is constituted by _B, the individual is constructed as shown in FIG. 17.

First, the input image signal S ₃₅ is stored in the FIFO
The output is input to the memory 221, and the output is input to the FIFO memory 222. Further, the output of the image signal S ₃₅ and the FIFO memory 221 and 222 is inputted to each circuit block 223 a to 223 c. That is, the image signals of three consecutive lines are simultaneously input to the circuit block 223. Note that these circuit blocks 22
Since 3a to 223c all have the same structure, only the circuit block 223b shows the internal structure in the figure.

The circuit block 223b has a five-stage flip-flop 224a for holding image signals of five consecutive pixels.
To 224e, and image signals at positions symmetrical with respect to the center pixel of each line are added by adders 225 and 226. Further, the circuit block 223b outputs an image signal including the center pixel _S56b and the addition results _S57b and _S58b .

Of the three lines of image signals, the outputs of the circuit blocks 223a and 223c located at both ends are subjected to addition processing of the corresponding signals by adders 227, 228 and 229, and the image signals S ₅₉ , S ₆₀ , It is output as the S _61.

By the above processing, the sum of the image signals at the symmetric positions is obtained. Next, the weighting is equal image signal with each other (S _{57 b} and S _60, S _58b and S ₅₉₎ are added by the adder 230 and 231.

The filter coefficients of this filter circuit can be selected from two types of smoothing, four types of edge enhancement and through as shown in Table 2. Here, the selection from the two types of smoothing and the four types of edge enhancement is performed according to the control signal BUS.
It is determined by the output value of the coefficient selection register 232 written by o. Switching between smoothing / edge enhancement / through is controlled by area signals S ₃₃₆ and S ₃₃₇ .

[0068]

[Table 2]

Next, weighted addition is performed. In the smoothing process, the image signals S ₆₃ and S ₆₁ are weighted and added by the adder 433, and the multiplier 434 sets the coefficient selection register 2
32, the image signal _S62 is multiplied by a coefficient corresponding to the output signal _S641.
35. On the other hand, the multiplier 436 outputs the signal S
_The image signal S _{56 b} is multiplied by a coefficient corresponding to ₆₄₁ , and the result is added by the adder 437 to the output of the adder 435. Further, the result of the addition is subjected to a multiplication process corresponding to the signal S ₆₄₁ by the multiplier 438,
Output to 39.

On the other hand, in the edge enhancement processing, the image signals S ₆₂ ,
S ₆₃ is weighted and added by the adder 440, and the result is converted into a two's complement signal by the code conversion circuit 441. The multiplier 442 multiplies the image signal S _56b by a coefficient corresponding to the output signal S ₆₄₂ of the coefficient selection register 232,
The result is added to the sign conversion circuit 441 by the adder 443.
Is added together with the output of. Further, the output is multiplied by a coefficient according to the signal S ₆₄₂ by a multiplier 444 and output to the selector 439.

The area signal S ₃₃₆ is a switching signal for smoothing / edge enhancement, and the selector 439 selects the smoothed output of the multiplier 438 and the edge enhanced output of the multiplier 444 according to the signal S ₃₃₆ , and shapes the signal. Output to the circuit 445. The shaping circuit 445 is a circuit for processing the overflow and the negative value of the input signal.
Output to On the other hand, a pixel signal S _56b corresponding to the center of 5 × 3 pixels is input to the other input terminal of the selector 446, and the area signal S ₃₃₇ is used for switching between through / smoothing or edge emphasis. The output of the selector 446 is _supplied to the image signal S _55R via the flip-flop 447 _.
And so on.

[0072] As described above, switching of the smoothing / edge emphasis / through processing according to this circuit, can be controlled in real time by the area signal S _33. In the first filter processing circuit 74 shown in FIG.
32 settings can be made for each of the processing circuits 74 _R , 74 _G , and 74 _B.

Referring again to FIG. 6, the image signals S _55R , S _55G , and S ₅₅ output from the first filter processing circuit 74 are _displayed .
_55B is input to the external I / F 75.

FIGS. 18 to 20 show the I / F section.
This will be described with reference to FIG. The external I / F circuit 75 constitutes a receiving unit and a transmitting unit, and is a circuit for the image processing unit 10 and the external device 36 to exchange image signals.
It is configured as shown in FIG. Referring to FIG.
The image signals S _55R , S _55G , and S _55B are input to the selector 451, and when no image signal is sent from the external device 36, the image signals S _55R , S _55G , and S _55B are selected by the selector 451. _Are output as image signals S _65R , S _65G , and S _65B via the flip-flop 452.

When an image signal is input from the external device 36, the image signal sent from the external device 36 is input to the other input terminal of the selector 451. That is, the image signal S sent from the external device 36
₆₆₅ is written into the FIFO memory 456 or 457 serving as image storage means via the buffer 453, the selector 454, and the flip-flop 455. Here, these F
For controlling the writing to the IFO memories 456 and 457, the pixel synchronization signal S ₆₆₁ and the line synchronization signal S ₆₆₂ sent from the external device 36 or the synchronization signal dividing circuit 458
The pixel synchronization signal S ₆₇₈ output by the selector 459 is selected by the selector 459 and used. Also, FIFO memories 456, 4
57 is output from the synchronizing signal frequency dividing circuit 458 and the pixel synchronizing signal S selected by the selector 460 is output.
₆₇₅ and the line synchronization signal S ₆₇₆ , and the read image signal is input to the selector 451 via the flip-flop 461. The synchronous signal frequency dividing circuit 458 and the selectors 459 and 460 constitute a control means 462 for write / read control.

The selection of the image signal by the selector 451 is controlled by the selection signal S ₆₇₁ output from the synchronizing signal frequency dividing circuit 458, whereby the image signals S _55R and S _55G from the scanner unit 1 side are _obtained. , _S55B and the image signal _S665 from the external device 36 can be combined and output.

The external I / F circuit 75 can also output an image signal to the external device 36. In this case, an image signal S output from a first gamma
_70R , _S70G and _S70B are selected by the selector 454,
FIFO memory 456 via flip-flop 455
Or 457. Here, the FIFO memory 45
6, 457 is controlled by the synchronization signal dividing circuit 45.
8 and is performed by the pixel synchronization signal S ₆₇₇ and the line synchronization signal S ₆₇₈ selected by the selector 459. The reading from the FIFO memories 456 and 457 is performed by the pixel synchronization signal S ₆₆₁ sent from the external device 36.
And the line synchronizing signal S ₆₆₂ or the synchronizing signal dividing circuit 4
The image signal read out by the pixel synchronizing signal S ₆₇₆ output from the flip-flop 461 and the buffer 4
The data is transmitted to the external device 336 via 53.

The selection of the input / output of the buffer 453 and the selection control of the selector 454 and the selection of the selectors 459 and 460
Is controlled by the output signal of the input / output register 463 set by the control signal BUSo.

The frame synchronization signal S ₆₇₂ , line synchronization signal S _673, and pixel synchronization signal S ₆₇₄ output from the synchronization signal dividing circuit 458 are output to the external device 36 via the buffer 464. Reference numeral 36 denotes input / output of image signals based on these signals, or input / output of image signals based on the pixel synchronization signal S ₆₆₁ and the line synchronization signal S ₆₆₂ generated by the external device 36 from these signals.

The above-mentioned synchronizing signal frequency dividing circuit 458 comprises an image synchronizing signal S ₁₀ , an area signal S ₃₃₈ and image synchronizing signals S _{672 to} S ₆₇₈ based on the control signal BUSo, and a selector 4.
51 selection signal S ₆₇₁ , FIFO memories 456 and 457
_Is a circuit that outputs the toggle control signals S ₆₇₉ and S ₆₇₁₀ of FIG. The external I / O circuit 75 includes an external device 36
The image density is transmitted and received between the pixel density of the copying machine main body 35 (high-resolution mode) and half the pixel density (standard mode).
The synchronization signal dividing circuit 458 generates an image synchronization signal for the density conversion.

FIG. 19 shows an outline of the image synchronization signal in the high resolution mode, and FIG. 20 shows an outline of the image synchronization signal in the standard mode. As shown in FIG. 19, in the high resolution mode, the line synchronization signal S ₁₀₁₁ output from the synchronization signal generation circuit 71
And the pixel synchronization signal S ₁₀₁₀ is used as it is as the synchronization signal dividing circuit 4
58. Also, the toggle control signals _S679 , S
₆₇₁₀ is inverted every time the line synchronization signals S ₆₇₃ , S ₆₇₆ , and S ₆₇₈ are output, and switches read / write of the FIFO memories 456 and 457.

As shown in FIG. 20, in the standard mode, a signal obtained by _dividing the line synchronization signal S ₁₀₁₁ by two, the toggle control signals S ₆₇₉ and S ₆₇₁₀ inverted by this signal, and the pixel synchronization signal S ₁₀₁₀ being _divided by two. The signal divided by 4 is generated by the synchronization signal generation circuit 71, and the external device 36 supplies the line synchronization signal S _{673 divided} by 2 and the pixel synchronization signal S _{674 divided} by 4 to the external device 36.
Is output. When an image signal is input from the external device 36, a line synchronization signal that is not divided and a pixel synchronization signal that is divided by two are output to the selector 459. This allows
The image sent from the external device 36 is magnified twice and taken into the copying machine main body 35. When outputting an image signal to the external device 36, a line synchronization signal that is not divided and a pixel synchronization signal that is divided by two are output to the selector 459, and a line synchronization signal that is divided by two is output to the external device 36. The pixel synchronization signal divided by 4 is output. As a result, an image reduced to １ ／ is output to the external device 36.

As shown in FIG. 20, the signal obtained by dividing the frequency of the pixel synchronization signal S ₁₀₁₀ by 2 and 4 is cleared at the falling edge of the line synchronization signal divided by 2 so that the phase of the signal becomes constant. Is controlled so that

The direction of image signal transmission and reception between the image processing unit 10 and the external device 36 and switching between the high resolution / standard mode are determined by communication between the external device 36 and the system control unit 34. It is set by the system control unit 34. Further, the synthesis control of the image signals from the scanner unit 1 and the external device 36 is controlled by the area signal S.
₃₃₈ .

Referring again to FIG. 6, the image signals S _65R , S _65G , and S _65B output from the external I / F circuit 75 are input to the first γ conversion processing circuit.

The first γ conversion processing section will be described with reference to FIGS. 21 and 22. The first γ-conversion circuit 76 is provided according to the γ characteristics of the scanner unit 1 and the external device 36.
This circuit performs LUT (Look Up Table) conversion on the image signals S _65R , S _65G , and S _65B and outputs processed image signals S _70R , S _70G , and S _70B . The first gamma conversion circuit 76 of the digital color copying machine converts the image signal into an image signal proportional to the cube root of the reflectance as shown in the equation (1). That is, X is the reflectance conversion value of the input image signal, X 'is the output image signal value, H is the reflectance value of the input image signal at the background level, and the reflectance conversion value of the darkest part of the input image signal is H. Let S be the function for finding the cube root and cube ()

[0087]

(Equation 1)

The processing represented by the following equation is performed.

The first γ-conversion circuit 76 is constituted by independent processing circuits 76 _R , 76 _G , 76 _{B for} each image signal, and each circuit is constituted, for example, as shown in FIG. First, the image signal S _{65R and the} like and the area signal S ₃₃₉ are supplied to the RAM 47 via the flip-flop 471 and the selector 472.
3 is input to the address terminal. LUT data for converting the image signal is stored in the RAM 473 in advance, and an image signal S _{70 R} or the like corresponding to the address signal is output via the flip-flop 474.

The LU stored in the RAM 473
The T data is written to the RAM 473 by the control signal BUSo. That is, the system control unit 34
When writing data to 73, the control signal _S714 as shown in FIG. 22 is set to the L level and the control signal _S711 is output as one pulse. Thus, the output of the counter 475 is cleared and input to the RAM 473 as an address signal. Next, the system control unit 34 outputs predetermined data to the control signal S ₇₁₃ and then outputs one pulse of the control signal S ₇₁₂ . As a result, the first data is written into the RAM 473, and at the same time, the output of the counter 475 advances to prepare for writing the next data. By repeating this a predetermined number of times (n times), necessary data is written, and finally, the control signal _{S714 is set} to the H level to complete the writing.

[0091] Further, in the RAM473 are LUT data of a plurality of types of conversion characteristics is writable, it is real-time switching by domain signal S ₃₃₉ according to an instruction from the operation and display unit 33.

Referring again to FIG. 6, the image signals S _70R , S _70G , and S _70B output from the first γ conversion circuit 76 are input to the color correction circuit 77.

The color correction / BP processing section will be described with reference to FIGS. This color correction circuit 77 converts the input image signals S _70R , S _70G , and S _70B into image signals S _72BK , S _72BK in consideration of the unnecessary absorption components of the BK, M, Y, and C toners used in the printer unit 2. _72M , S _72Y ,
It is a circuit that converts it to _S72C and outputs it.
It can be expressed by the first-order product-sum operation of the equation (2).

[0094]

(Equation 2)

Here, R, G, and B are image signals S _70R , S
_70G, in response to _{S 70B, BK, M, Y} , C image signals S
_72BK, S _72M, S _72Y, corresponding to the S _72C.

The color correction circuit 77 is composed of independent processing circuits 77 _BK , 77 _M , 77 _Y , and 77 _C for each output image signal, one of which is configured as shown in FIG. 23, for example. I have.

First, the image signals S _70R , S _70G and S _70B are _supplied to the multiplier 4 via flip-flops 481 _R , 481 _G and 481 _B and flip-flops 482 _R , 482 _G and 482 _B.
83 _R , 483 _G and 483 _B. The outputs of the flip-flops 481 _R , 481 _G , and 481 _B are also input to the coefficient generation block 484. The coefficient generation block 484 includes multipliers 483 _R , 483 _G , and 483.
Coefficient signals S _73R to the other input terminal of the _B, S _73G, S
A circuit for outputting a _73B, the coefficient signal is output from the RAM486 _R, 486 _G, 486 _B serving as a coefficient switching means via a flip-flop _{485 R, 485 G, 485 B} . Here, the coefficient signals output by the RAMs 486 _R , 486 _G , and 486 _B are selected by the image signals S _70R , S _70G , S _70B and the area signal S ₃₃ . That is, the outputs of the flip-flops 481 _R , 481 _G , and 481 _B are input to the comparators 487 _R , 487 _G , and 487 _B. 488. The selector 488 selects and outputs the comparator output or the area signal S ₃₃₁₁ according to the area signal S ₃₃₁₀ .
The output of the RAM 486 _R , 48 is supplied as an address signal through a selector 489 together with the area signal S _3312.
6 _G and 486 _B , thereby selecting a coefficient. That is, the comparators 487 _R , 487 _G , 487 _B
And selectors 488 and 489, and RAM 486 _R , 4
Control means for 86 _G and 486 _B is constituted.

Incidentally, the comparators 487 _R , 48
The selection of the coefficients using the outputs of 7 _G and 487 _B is used only in the full-color mode, and in the mono-color mode, the selection of the coefficients is directly performed by the area signal S ₃₃ .

The RAMs 486 _R , 486 _G , 486 _B
And the coefficient stored in the RAM 490 are the control signals B
Written in advance by USo. That is, the system control unit 34 sets the control signal S ₇₁₅ to L level and outputs one pulse of the control signal S ₇₁₁ . As a result, the output of the counter 491 is cleared, and its lower bits are used as address signals for the RAMs 486 _R , 486 _G , 486 _B and R.
Output to AM490. The upper bit of the counter 491 is input to the decoder 492, and
92 selects the RAM 486 _R. Next, the system control unit 34 outputs predetermined data to the control signal S ₇₁₃ and then outputs one pulse of the control signal S ₇₁₂ . As a result, the first data is written into the RAM 486 _R , and at the same time, the counter 491 advances to prepare for writing the next data. The system control unit 34 repeats this,
The necessary data is written to the AM 486 _R , and this is repeated to write the necessary data to the RAM 486 _G , 486 _B, and the RAM 490. When this is also completed, the system control unit 34 sets the control signal _S715 to the H level, and ends the write operation.

On the other hand, multipliers 483 _R , 483 _G , 483 _B
Is output together with the output of the RAM 490 by an adder 491,
The signals are added by 492 and 493 and input to the shaping circuit 494. The shaping circuit 494 performs overflow and negative value processing on the addition result, and outputs the result to the flip-flop 49.
5 and output as an image signal S _72BK or the like.

It should be noted that the RAM 490 stores the constant term (a
_{14 to} a ₁₄ ), and the output value can be selected in real time by the area signal S ₃₃₁₃ .

Next, in the full-color mode, the color correction circuit 7
Coefficients a ₁₁ to a set to 7 _BK , 77 _M , 77 _Y , and 77 _C
44 will be described. The processing in the color correction circuit 77
Although expressed by a linear function as shown in equation (2), when performing full-color processing, the comparator 48 described above is used.
Switching of coefficients by 7 _R , 487 _G , 487 _B, etc. is also performed. As a result, the image signals R,
The color space formed by G and B is divided by a plane radially extending around an achromatic axis (R = G = B) for each region.
The optimal coefficients a _{11 to} a ₃₄ can be set.

[0103]

[Table 3]

The coefficients a ₁₁ to a actually set
_Reference numeral ₄₄ denotes six chromatic colors on the boundary surface of each area as shown in FIG. 24 and two achromatic image signals R and R common to each color space.
It is determined by the system control unit 34 based on G and B and the corresponding image signals BK, M, Y and C.

Referring again to FIG. 6, the color correction circuit 77
Image signals S _72BK , S _72M , S _72Y , S _72C from UCR
It is input to the processing circuit 78.

FIG. 25 shows the UCR / UCA processing unit.
This will be described with reference to FIG. UCR (Under Color Remova)
l) The processing circuit 78 is a circuit that corrects the image signals S _72M , S _72Y , and S _72C according to the image signal S _72BK obtained by the color correction circuit 77. Note that the image signals S _72BK , S _72M , S _72Y , and S _72C output from the color correction circuit 77 do not take into account the recording of black BK. This circuit is provided for the correction because the vividness of the output image is lost.
The UCR processing circuit 78 is an independent processing circuit 78 _BK , 7
8 _M , 78 _Y , and 78 _C.
One of 8 _M , 78 _Y , and 78 _C is configured as shown in FIG. 25, for example.

First, the image signal S _72BK and the image signal S _72M ,
S _72Y and S _72C are flip-flops 501 and 5, respectively.
02 as an address signal of the ROM 503. In the ROM 503, 2 as shown in the equations (3) and (4) is stored.
The results of the types of operations are stored in advance at predetermined addresses, and the results of the operations are read from the _{ROM 503} and output as image signals S _75M , S _75Y , S _75C, etc. via the selector 504 and the flip-flop 505. You. The area signal S ₃₃₁₄ is expressed by the following equation (3) or (4): X ′ = X−BK (3) (where X = M, Y, C) X ′ = u (BK) (X-BK) (4) (where u (BK) is a function of BK) is used to switch the operation, and the image signals S _72BK , S
It is input to the ROM 503 as in the case of _72M . In addition,
The processing based on equation (3) is a normal UCR processing, whereas the processing based on equation (4) is based on UCA (Under Color Addit).
ion).

The area signal S ₃₃₁₅ is used for selecting whether or not to perform the above-described processing. The processing circuit 78 _BK shown in Figure 6 in accordance with the delay of the image signal produced by the processing circuit _{78 M, 78 Y, 78 C} , is a circuit for the image signals S _75BK delay the image signal S _72Bk.

The image signals S _75BK , S _75M , S _75Y , and S _75C output from the UCR processing circuit 78 are input to the second γ conversion processing circuit 79.

The second γ conversion processing section will be described.
The second γ-conversion processing circuit 79 functions as a binarization processing unit, and according to the state of the printer unit 2 and a dither pattern selected by a multi-value dither processing circuit 82 described later.
Image signal _{S 75BK, S 75M, S 75Y} , the S _75C and LUT conversion, the processed image signal _{S 76BK, S 76M, S 76Y} , S 76C
Is a circuit that outputs. This second γ conversion processing circuit 79 is a processing circuit 79 _BK , 79 _M , 7 independent for each image signal.
9 _Y , 79 _C , and each circuit is configured in the same manner as in the case of the first γ conversion processing circuit 76 as shown in FIG. Therefore, although the details are omitted, writing of LUT data of a plurality of types of conversion characteristics and real-time switching by the area signal S ₃₃₁₆ are possible.

[0111] The 2γ converted output from the processing circuit 79 the image signal _{S 76BK, S 76M, S 76Y} , the upper 6 bits of the S _76C is input to the document size detection circuit 80.

FIG. 26 shows the document size detection processing section.
28 will be described with reference to FIG. The document size detection circuit 80 is a circuit for performing processing such as detecting the size and position of the document 4 placed on the platen 3 prior to the copying operation. The document size detection circuit 80 is composed of independent processing circuits 80 _BK , 80 _M , 80 _Y , and 80 _C , one of which is shown in FIG. 26.

[0113] First, the image signal _{S 76BK, S 76M, S 76Y} , S
_76C is connected to the selector 51 via the flip-flop 511.
2, input to the delay circuit 513 and the difference circuit 514. The delay circuit 513 is a circuit for delaying the input image signal by n pixels, and its output is also input to the difference circuit 514. The difference circuit 514 is a circuit that outputs the absolute value of the difference between the two input image signals. The output of the difference circuit 514 is input to the comparator 515, where it is compared with the threshold signal _S771 output from the document size register 516. That is, the comparator 515 is configured to output the H level if the absolute value of the difference between the image signals separated by n pixels is larger than the threshold signal S ₇₇₁ . In this circuit, the boundary between the original portion and the non-original portion (pressing plate) is detected based on the difference between the values of the image signals. It is treated as a boundary candidate with the non-document section.

The output of the comparator 515 is input to a shift register 517, and the comparison results for n pixels are put together and input to a main scanning direction determination circuit 518. The main scanning direction determination circuit 518 regards the input result of n pixels as being a candidate for a boundary between a document portion and a non-document portion if at least m (m ≦ n) pixels are at the H level. An H level signal is output. The output of the main scanning direction determination circuit 518 is input to the FIFO memory 519, and the determination results for n ′ lines are collected and input to the sub-scanning direction determination circuit 520. In the sub-scanning direction determination circuit 520, if at least the m ′ (m ′ ≦ n ′) line of the input determination results for the n ′ line is at the H level, the boundary between the original portion and the non-original portion is determined. The signal is regarded as a candidate and an L-level signal is output.

By the way, the original size detecting circuit 80 is not shown in FIG.
6, the minimum value x ₁ in the main scanning direction, the maximum value x ₂ , the minimum value y ₁ in the sub scanning direction at the boundary between the document 4 and the non-document portion,
This circuit detects the maximum value y _{2. In} FIG. 25, these values x ₁ , x ₂ , y ₁ , y ₂ are respectively set to the flip-flops 521 to 521.
524. That is, the counter 52
5, 526 respectively count the position in the main scanning direction and the position in the sub-scanning direction. For example, in the flip-flop 521, the output of the counter 525 is larger than the value held by the flip-flop 521, and the sub-scanning direction determination circuit 520 Is operated to hold the output value of the counter 525 when the output is at the L level. In the flip-flop 522, when the output of the counter 525 is smaller than the value held by the flip-flop 521,
Update the value of. Further, the flip-flop 524 holds the output of the counter 526 when the output of the sub-scanning direction determination circuit 520 first goes to the L level, and the flip-flop 523 holds the output each time the output of the sub-scanning direction determination circuit 520 goes to the L level. Holds the output of the counter 526. As a result, the counter 52 when the output of the sub-scanning direction determination circuit 520 finally becomes L level is output to the flip-flop 523.
6 is held.

The data held in the flip-flops 521 to 524 are selected by the output signals S ₇₇₂ and S _{773 of} the document size register 516 set by the control signal BUSo, and are selected via the signal line BUS via the selector 527.
output on i.

The circuit described above is the same as that of the frequency dividing circuit 52.
As shown in FIG. 28, the signal is operated by an image synchronization signal _S78 and a line synchronization signal _S79 which are _divided by four,
As a result, small dust adhering to the platen 3 is not detected as a boundary. In order to prevent the boundary between the platen 3 portion as shown in FIG. 27 from being determined as the boundary between the document 4 and the non-document portion (pressing plate), the region outside the platen 3 is defined by Depending on the setting, it is painted in the same color as the pressure plate.

The selector 512 has the flip-flop 51
In addition to the image signal output by the counter 1, the higher bits of the outputs of the counters 525 and 526 and the non-recorded data (= 0) are also input. Can be selected by the signal _S774 output from the document size register 516.

[0119] Again, paying attention to FIG. 6, the image signal S _80BK output from the document size detection circuit 80, S _80M,
S _80Y and S _80C are input to the second filter processing circuit 81.

The second filter processing section will be described with reference to FIGS. 29 and 30. Second filter processing circuit 8
1 functions as an edge extraction processing section, the image signal _{S 80BK, S 80M, S 80Y} , 2 of 3 lines × 5 pixels S _80C
This is a circuit that _performs a dimensional filter process and outputs processed image signals S _81BK , S _81M , S _81Y , and S _81C .
The second filter processing circuit 81 includes independent processing circuits 81 _BK , 81 _M , 81 _Y , and 81 _C for each image signal, and each processing circuit is configured as shown in FIG. 29, for example.

First, the input image signal S _80BK etc.
Input to the FO memory 541, and the output
It has been input to the O memory 542. Further, the image signal S
_{The outputs of the 80BK} and FIFO memories 541 and 542 are input to circuit blocks 543a to 543c, respectively. Therefore, these circuit blocks 543a to 543c are supplied with continuous three lines of image signals. Further, these circuit blocks 543a to 543c have the same structure, and only the circuit block 543b is shown in detail in FIG. The circuit block 543 has flip-flops 544 and 545 for holding image signals of two consecutive pixels, and outputs of the flip-flops 544 are multipliers 546 to 5.
49, and the output of the flip-flop 545 is input to the multiplier 550. In addition, these multipliers 54
Outputs of flip-flops 551 to 555 that hold temporary filter coefficients are connected to the other input terminals of 6 to 550. Outputs of the multipliers 550 and 546 are added to an adder 556.
, And the result is delayed by the flip-flop 557 and then added to the multiplier 54 by the adder 558.
7 is added. Further, the result is delayed by the flip-flop 559 and then added by the adder 560 to the output of the multiplier 548. Thereafter, delay and addition are repeated in the same manner using the flip-flop 561 and the adder 562, and the final result is
63. Note that this result is equal to the result of performing the filtering process of one line × 5 pixels.

The outputs of the block circuits 543a to 543c are added by adders 564 and 565 and input to a multiplier 567 via a flip-flop 566.
The other input terminal of the multiplier 567 has a flip-flop 5
The coefficients held at 68,569 are input,
These multiplication results are input to the shaping circuit 570. The true filter coefficient of this circuit is the flip-flop 56
8, 569 and a temporary filter coefficient (output of flip-flops 551 to 555, etc.).

The shaping circuit 571 has a flip-flop 570
Is a circuit that operates in two modes according to the output signal of The first mode is a mode in which a signal output from the multiplier 567 is subjected to overflow and negative value processing, and the second mode is a mode in which the absolute value of the signal output from the multiplier 567 is obtained and then overflow processing is performed. It is. Note that the latter mode is a mode used only when performing contour processing using the Laplacian filter shown in Table 4, and the former mode is used in normal filter processing.

The image signal output from the shaping circuit 571 is output as an image signal _S81BK or the like via a selector 572 and a flip-flop 573.

By the way, the other input terminal of the selector 572 is also _{supplied with an} image signal corresponding to the center of 5 × 3 pixels, and the switching is performed by the area signal S ₃₃₁₇ .
That is, in the present circuit, the result of performing the filter processing and the result (through) of not performing the filter processing can be switched in real time. Also,
The flip-flops 574a to 574e function to correct the delay caused by the filtering.

Also, flip-flops 551 to 555,
The data held in 568 to 570 and the like is the control signal BUS
written by o. That is, these flip-flop groups have a shift register structure. The system control unit 34 sets the control signal S ₇₁₆ to L level, then outputs predetermined data to the control signal S ₇₁₃ and outputs the control signal S ₇₁₂ for one pulse. Repeat output. As a result, the data is sequentially shifted, and finally the control signal _S716 is set to the H level to complete the setting.

As is clear from the above description, the present circuit can set an arbitrary filter coefficient. The system control unit 34 stores the filter coefficients as shown in Table 4, and selects and sets the filter coefficients according to an instruction from the operation display unit 33 and the like.

[0128]

[Table 4]

FIG. 30 is an explanatory diagram schematically showing various filter processing examples corresponding to various filter coefficients in Table 4.

Referring again to FIG. 6, the image signals S _81BK , S _81M , S 81 outputted from the second filter processing circuit 81 are _displayed .
_81Y, S _81C is inputted to the multilevel dither processing circuit 82.

This dither processing section is shown in FIGS.
This will be described with reference to FIG. The multi-level dither processing circuit 82 performs an 8-level dither process on the image signals S _81BK , S _81M , S _81Y , and S _81C , and processes the processed 3-bit image signals S _82BK , S _81BK .
_82M, S _82Y, a circuit for outputting the S _82C. The multi-level dither processing circuit 82 includes independent processing circuits 82 _BK , 82 _M , 82 _Y , and 82 _{C for} each image signal.
One of them is configured as shown in FIG. First, the image signal _{S81BK and the} like are input to the ROMs 581 and 582 as address signals via the flip-flop 580. The outputs of the counters 583 and 584 and the pattern selection register 58 are used as address signals of the ROM 581.
5, the output of the counters 586 and 587 and the PS output of the pattern selection register 588 are also input as address signals of the ROM 582. These ROMs 581 and 582 store results after multi-value dither processing determined by the values of image signals and counter output values, and the results are output from ROMs 581 and 582. Also, the pattern selection registers 585, 588
Is a signal for selecting one of the processing results of the two types of multi-valued dither patterns stored in the ROMs 581 and 582.

The counters 583 and 586 and the counters 584 and 587 are counted by the pixel synchronization signal S ₇₁₁ and the line synchronization signal S ₇₁₂ , respectively, and cleared by the line synchronization signal S ₇₁₂ and the frame synchronization signal S ₇₁₃ .
The counters 583, 584, 586, and 587 and the comparators 589 to 592 each form a pair of n-ary counters.
5,588 LP outputs.

The image signals output from the ROMs 581 and 582 are output as an image signal _{S82BK and the} like via the selector 593 and the flip-flop 594. Here, the area signal S ₃₃₁₈ is input to the selector 593, and this signal is supplied to the selector 593 by the pattern selection registers 585 and 588.
It is used to switch the narrowed dither pattern in real time. The main scanning direction erase signal output from the synchronizing signal generating circuit 71 S ₇₁₇ and the sub-scanning direction erase signal S ₇₁₈ is an OR gate 595, is inputted to the gate terminal of the selector 593 via a flip-flop 596, the signal Is used to output a white image signal regardless of the image signal _S82BK or the like. Also,
The setting of the pattern selection registers 585 and 588 is performed by the control signal BUS.

Table 5 shows an example of a multi-value dither pattern stored in the ROMs 581 and 582. Table 5
, Levels 1 to 7 indicate octalization level thresholds.
The ROM 581 stores image signals S _81BK , S _81M ,
Two patterns common to S _81Y and S _81C (a.
b. The processing result is stored in the ROM 58
2 stores two processing results: a pattern common to the image signals S _81BK , S _81M , S _81Y , and S _81C (c. Line type) and a pattern different for each image signal (d. Halftone type). . The pattern d for the image signals _S81M and _S81C uses a small threshold pattern repeatedly, and as a whole, 10 pixels ×
The dither pattern has 10 pixels.

[0135]

[Table 5]

FIG. 32 schematically shows a part thereof.
FIG. 11A shows the contents of the ROM 582 corresponding to the level 7 in 10 × 10 pixels for the image signal S _81M , and FIG. 11B shows the content of the ROM 582 in 10 × 10 pixels for the image signal S _81C . The contents of the corresponding ROM 582 are shown.

Referring again to FIG. 6, the image signals S _82BK , S _82M ,
S _82Y and S _82C are input to the delay processing circuit 83.

This delay processing section will be described with reference to FIGS. The delay processing circuit 83 is shown in FIG.
Corresponding as the origin of the photosensitive member 14 _BK for black BK as shown in the number of lines corresponding to the distance between the photosensitive member 14, the input image signal _{S 82BK, S 82M, S 82Y} , circuit for delaying S _82C , and the thereby, the image signal S _82BK at the same position on the recording paper 19, S _82M, S _82Y, images are superimposed by the S _82C. In this embodiment, the distance 1 between the photoconductors 14 is set to 110 mm.

FIG. 34 shows a configuration example of the delay processing circuit 83. The image signals S _82BK , S _82M , S _82Y , and S _82C are input to the separation selection circuit 601, one of which is selected and output as an image signal for BK recording. Image signals S _82BK , S
_82M, S _82Y, is used to record S _82C individually BK in separations mode to create a master for simple printing. The selection of the image signal is performed by the control signal BUSo.
In the normal operation mode, it is set so that the image signal _S82BK can be selected.

[0140] The image signal output from the separations selection circuit 601 and the image signal S _82M, S _82Y, S _82C is inputted to the selector 602. The selector 602 also receives an image signal and a selection signal output from the pattern generation circuit 603. Pattern generating circuit 603 is a circuit configured to synchronize the image signal and the like of a pattern for checking the operation delay line number adjustment pattern and delay processing circuit to an image synchronization signal S _10,
These patterns are selected by the control signal BUSo, and at the same time, whether the selector 602 selects the image signal output from the pattern generation circuit 603 is set.

The image signal selected by the selector 602 is input to the mask processing circuit 604. The mask processing circuit 604 individually whitens the input image signal in accordance with the setting of the control signal BUSo, and also sets the pixel synchronization signal S
Image signals S _83BK , S _83M , S _83Y , S _83C in synchronization with ₇₁₁
For example, in the above-described separation mode, the image signal for M, Y, and C recording is whitened and only BK is recorded.

The image signals S _83M , S _83Y and S _83C output from the mask processing circuit 604 are stored in RAM blocks 605-6.
08 is connected to the data input terminal. However, the image signals S _83M and S _83C are selectively connected to the data input terminal of the RAM block 608 via the selector 609.

Here, the role of the RAM block 608 will be described. In order to realize a delay circuit corresponding to the distance l between the respective photoconductors 14, the RAM blocks 605 to 60
8 is normally used in a delay mode as shown in FIG. That is, the RAM blocks 605 and 608 are for C,
RAM block 606 is a RAM block 607 for Y
Is used to delay the M image signal. On the other hand, the delay processing circuit 83 shown in FIG.
8 can also be used as a frame memory, in which case it operates in a frame memory mode as shown in FIG. That is, the RAM block 608 is diverted to storing the image signal for M, whereby the M, Y, C
And a frame memory with a surplus area of 220 mm × 297 mm (length in the main scanning direction) is realized. Therefore, the RAM blocks 605 and 606 are 220 × 297
× 16 × 16 = 16727040 ≒ the capacity of the image signal for 16 M pixels is stored in the RAM blocks 607 and 608 as 110
× 297 × 16 × 16 = 8363520/8 M pixels.

Referring again to FIG. 34, the memory control circuits 610 to 612 each output an address signal of the M, Y, C RAM block and a control signal such as a write enable signal. ~ 608
Has been entered. Note that the RAM block 608 includes
An address signal for M or C is selected and input by the selector 609 according to the above-described delay / frame memory mode.

Further, the memory control circuits 610 to 612
Control signal BUSo operation mode is determined by by the setting, and operates in synchronization with the image synchronization signal S _10, further reference to the signal S ₈₄ outputted by the combining control circuit 613 at the time of writing of the memory. Here, the synthesis control circuit 613
Is a circuit for controlling writing of a partial image signal when the RAM blocks 605 to 608 are used as a frame memory. The control at this time is performed based on the area signal S ₃₃₁₉ or the image signal S _82BK . In other modes, a signal fixed to the L level is output.

FIG. 36 shows a circuit configuration example of such a memory control circuit 612. First, the counter 614 that outputs a signal indicating a position in the main scanning direction is output from the line synchronization signal S _712.
And the pixel synchronization signal S ₇₁₁ is counted.
The output signal is input to comparators 615 and 616. The memory control register 617 has a control signal BUSo
37 is a circuit that outputs various control parameter signals S _85. For example, the parameter signal S ₈₅₁
, The parameter signal S ₈₅₂ represents the effective image width in the main scanning direction, and the parameter signal S ₈₅₃ represents the repeat width in the main scanning direction of the repeat processing in the memory mode. .

The other input terminal of the comparator 615 receives the parameter signal S ₈₅₁ , and the other input terminal of the comparator 616 receives the sum of the parameter signals S ₈₅₁ and S _{852 from} the adder 618. Therefore, OR gate 619 outputs a pixel synchronizing signal S ₈₆ when the position represented by the counter 614 is within the effective image area in the main scanning direction.

The counter 620 counts the pixel synchronization signal S ₈₆ output from the OR gate 619, and
1 is cleared by the line synchronization signal S ₇₁₂ or the like input via the control signal 1. Here, the output of the counter 620 is a RAM
This means an offset address in the main scanning direction in the block, and its output is input to the comparator 622 and the adder 623. The other input terminal of the comparator 622 receives the parameter signal S ₈₅₃ .
When the value of the counter 620 matches the value of the parameter signal S ₈₅₃ , the comparator 622 outputs an L-level signal,
This output is sent to the counter 6 via an AND gate 621.
Used to clear 20. That is, thereby, the repeat in the main scanning direction is realized. Note that the comparator 622
Is used only when the RAM blocks 605 to 608 are set to the frame memory mode to perform the repeat operation. In other modes, (signal S ₈₅₂ ) <(signal S ₈₅₃ ), so that no clear operation occurs.

The frequency dividing control circuit 624 controls the line synchronizing signal S as shown in FIG. 38 according to the setting by the control signal BUSo.
_This is a circuit that _{divides the} frequency of ₇₁₂ by two, and outputs the line synchronization signal S ₇₁₂ as it is in a normal operation.

The line synchronization signal S ₈₇ is counted, and AND
The counter 626 that is cleared by the frame memory synchronization signal _S88 or the like input from the system control unit 34 via the gate 625 is input to the comparator 627. The parameter signal S ₈₅₄ input to the other input terminal of the comparator 627 indicates the number of delay lines in the sub-scanning direction in the delay mode and the repeat width in the sub-scanning direction in the frame memory mode.
Every time the AND output value of the reaches the value of the parameter signal S ₈₇
Gate 625 outputs L level, and as a result, counter 626 is cleared, and thereafter this operation is repeated.

The flip-flop 628 is connected to the AND gate 6
25, each time the line synchronization signal _S87 is input, the adder 6 of the parameter signal _S853 representing the effective image width in the main scanning direction and the output value of the flip-flop 628
29 is output as a new value. This output means an offset address in the sub-scanning direction, and is added together with the offset address in the main scanning direction by the adder 629 to obtain a true address.

Here, the role of the frequency division control circuit 624 will be described. The frequency division control circuit 624 doubles the apparent memory capacity in the frame memory mode (440 times).
mm x 297 mm). That is, by dividing the line synchronization signal by two, the way in which the offset address advances in the sub-scanning direction is halved, whereby the image signal of the same line is continuously read twice, and the area is doubled. Also, when such an apparent memory capacity is doubled, the line synchronization signal is not divided by two when writing the image signal to the frame memory, but is reduced to し て in the sub-scanning direction. The image signal is being written. Thereby, the writing time to the memory is shortened, and the operability is improved.

As described above, the memory capacity for cyan C is 16 + 8 = 24 M pixels in the delay mode.
In the frame memory mode, the number is 16 M pixels. Therefore, the upper two bits (AD23, AD24) of the address signal are input to the decoder 630 and output to the RAM block as chip select signals (CS0 to CS2) in units of 8M pixels.

The OR gate 631 has the signal S ₈₄ input from the synthesis control circuit 613 and the line synchronization signal S ₈₇
And the pixel synchronization signal _S86 are input to the RAM block as a write enable signal. That is, in the RAM block, an image signal is written when the output of the OR gate 631 changes from H → L → H.

FIG. 39 shows a configuration example of the RAM block 607, and the operation timing thereof is shown in FIG. In FIG. 39, a RAM block 607 includes memory arrays 632 and 633 having a capacity of 8M pixels and a buffer 634, and the above-described chip select signal (CS0,
CS1) is used for selecting the memory arrays 632 and 633. In this circuit, when an address signal or the like is determined as shown in FIG. 40, the stored data is output from the corresponding I / O terminal of the RAM array.
Is latched by an output control circuit described later. Here, when the write enable signal falls, the RAM array enters a high impedance state, while the buffer 634 inputs the image signal Di to the RAM array. RAM
In the array, this image signal is stored at the rise of the write enable signal, and the image signal is rewritten. When the write enable signal does not become L level, the stored image signal is held as it is.

Note that the memory control circuits 610 and 611
The configuration is the same as that of the memory control circuit 612, and the description is omitted.

In the above description, the memory control circuit 6
Although 10 to 612 have been described as independent circuits, the parameter signals S set in the memory control register 617 and the like have been described.
Since ₈₅₁ to S ₈₅₃ is common to each circuit, circuits for outputting the offset address in the sub-scanning direction (from 625 to 62
9), an adder 623, a decoder 630, the parameter signal S _854, with the exception of the memory frame synchronizing signal S _88, it may be common.

Referring again to FIG. 34, the image signals output from the RAM blocks 605 to 608 are input to the output control circuit 635. The RAM block 608
Is output from the RAM by the operation of the buffers 636 and 637.
It is combined with either the output of block 605 or 607. That is, the memory mode register 638 controls the control signal B when the delay / frame memory mode is selected.
This register is set by USo, and the selector 609 selects the image signal, the address signal, and the like, and the buffers 636 and 637 according to the signal output from the register.
Operation is restricted. Further, the above-described image signal S
_{841 is} also input to the output control circuit 635.

[0159] in accordance with the output control circuit 635 synchronous signal S _10, and performs alignment in the main scanning direction of the input image signal, to whiten the image signal of the non-effective image range set by the control signal BUSO, FIG As shown in FIG. 6, the circuit outputs the image signals BKp, Mp, Yp, and Cp. The output control circuit 635 also outputs an image synchronization signal CLKp of the image processing unit 10 together with the image signal.

The area processing section will be described with reference to FIGS. 41 to 44. Area control circuit 84 is a circuit for outputting the domain signal S ₃₃ described above, configured as shown for example in FIG. 41. The area control circuit 84 shown in FIG. 41 performs switching control of a rectangular area as shown in FIG. 42. In order to realize the control of the rectangular area, control patterns are classified in line units. Are stored in the memory 651 in the form of the switching point coordinates xi in the main scanning direction and the area number signal ai as shown in FIG.

First, the output of the counter 652 that is cleared by the line synchronization signal S ₇₁₂ and counts the pixel synchronization signal S ₇₁₁ is output to the comparator 653 as a signal indicating the position in the main scanning direction. The switching point coordinate signal xi output from the RAM 651 is input to the other input terminal of the comparator 653, and when they match, the output of the comparator 653 becomes L level. This allows
The OR gate 654 outputs a clock signal to the counter 655, and the output of the counter 655 advances by one. The sum of the offset address signal Pj set by the control signal BUSo and the output of the counter 655 by the adder 656 is used as the address signal of the RAM 651. Therefore,
When the count position in the main scanning direction matches the switching point coordinates, the address signal of the RAM 651 advances by one, and the switching point coordinate signal xi and the area number signal ai output from the RAM 651 are updated. By repeating this, the area is switched in the main scanning direction.

The counter 655 is provided by the AND gate 65.
7 is cleared by the line synchronizing signal S ₇₁₂ inputted through the line 7. The offset address signal Pj is latched by the latch 659 by the line synchronization signal _S712 input via the AND gate 658, and the system control unit 34 sets the offset address signal as the processing proceeds in the sub-scanning direction. At a predetermined timing to control the area switching in the sub-scanning direction.

The area number signal ai output from the RAM 651 is input to the area processing register 660. The area processing register 660 is a circuit that outputs an area signal pattern in each area. A plurality of area signal patterns as shown in FIG. 44 are set in advance for each area number by the control signal BUSo. When a pattern is selected, the set area signal pattern is output.

The area signal pattern output from area processing register 660 is input to delay circuit 661,
Here, the delay is delayed by the same amount as the delay of the image signal in each image processing circuit. Thus, domain signal S ₃₃ which coincides with the delay of the image signal is output.

Next, the printer unit shown in FIG.
47 will be described with reference to FIG. FIG. 45 shows the electrical configuration of the printer unit 2. In the printer unit 2 of this embodiment, as shown in FIG. 46, the laser beams emitted from the laser diodes 701 _{BK to} 701 _C for the respective colors are scanned by the polygon mirror 11 and the like on the same axis. There are two scanning directions on the bodies 14 _{BK to} 14 _C. Therefore, as shown in the timing chart of FIG. 47, the sensors 702 _BK to 702 _C also output signals at different timings in order to detect the writing start timing of the laser beam.

In FIG. 45, the image signals BKp, Mp, Yp, Cp and the image synchronization signal CLKp output from the image processing section 10 are input to write control circuits 703 _{BK to} 703 _C. Note that these write control circuits 703 _BK
～703 _C is of a similar configuration, wherein the write control circuit 703 _C only shows the details. Focusing on the write control circuit 703 _C , the image signal Cp and the image synchronization signal CLKp are input to the three-line buffer circuit 704. The synchronous signal generating circuit 705 sensor 702 an image synchronization signal to be used in the write control circuit 703 _C
The three-line buffer circuit 704 writes the image signal Cp sent from the image processing unit 10 to the line memory based on the image synchronization signal CLKp, and generates a synchronization signal. The reading is performed according to the image synchronization signal output from.

As described above, the read start timing of the image signal differs depending on the write control circuits 703 _{BK to} 703 _C , and the read direction needs to be reversed depending on the circuit. Therefore, the three-line buffer circuit 7
04 has a memory for storing image signals for three lines,
As shown in FIG. 47, control is performed so that the memory for writing and the memory for reading do not overlap.

The image signal output from such a three-line buffer circuit 704 is input to a pulse width modulation circuit 706. The pulse width modulation circuit 706 converts the input image signal into a pulse signal having a width corresponding to the signal value, and outputs the pulse signal to a laser diode (LD) drive circuit 707. L
D drive circuit 707 drives the laser diode 701 _C based on the control signal outputted from the pulse signal and a power control circuit 708 which is input, to emit laser light. The monitor signal output from the laser diode 701 _C is inputted to the power control circuit 708, and feedback control of the LD drive circuit 707 so that the laser light intensity in the power control circuit 708 is constant.

When the low-speed mode is selected, the transmission speed of the image signal and the like output from the image processing unit 10 becomes に な る as shown in FIG. 47, but the reading speed from the line memory is constant. Performs double reading. However, the driving of the laser diode 701 _C is performed once to twice by control by the power control circuit 708.

[0170] Incidentally, the line synchronization signal SYNCp the write control circuit 703 _C is outputted to the image processing unit 10 as a line sync signal representative of the printer unit 2.

The printer unit 2 has a printer control circuit 709 which controls the entire unit and constitutes an image recording speed changing means. This printer control circuit 7
09 is a serial I / O circuit 713 and a parallel I / O circuit 7 for communicating with the system control unit 34, including the CPU 710, the ROM 711, and the RAM 712.
14 and the like. Here, the parallel I / O circuit 714 inputs various sensor signals such as the registration sensor 715, outputs setting signals to the write control circuits 703 _{BK to} 703 _C , inputs abnormal detection results, and outputs signals for controlling the drive circuit 716. And the like. Further, the drive circuit 716 includes a main motor 71 that rotationally drives the photoconductor 14 and the like, the transfer belt 22 and the like.
7, a circuit for driving and controlling various loads such as a polygon motor 15, a paper feed clutch 718, a fixing heater 719, and a high voltage power supply 720. That is, the printer control circuit 709 outputs the RO
It operates according to a program stored in M711 and performs setting of each circuit and drive control of various loads in accordance with a command from the system control unit 34 and various sensor signals. For example, when a low speed mode selection command is input by the system control unit 34, the printer control circuit 70
9 sets the write control circuits 703 _{BK to} 703 _C in the low speed mode as shown in FIG.
Control such as setting the drive circuit 716 so as to control the output of the high-voltage power supply 720 that performs the rotation speed and constant current control to 1/2.

The system control and operation display unit will be described with reference to FIG. System control unit 3
48 and the configuration of the operation display unit 33 are shown in FIG. As shown in FIG. 48, the system control unit 34 has a CPU
731, ROM732, RAM733, 732, 735
And the timer 736, the scanner unit 11, the printer unit 2, the operation display unit 33, and the external device 3.
6 is a microcomputer system including a serial I / O circuit 737, a parallel I / O circuit 738, an interrupt controller 739, and the like for communicating with each control circuit. Here, the parallel I / O circuit 738 is a control signal BUSo for setting the image processing unit 10 and the like.
And a circuit for capturing the detection result output from the image processing unit 10. A part of the output signal is input to the decoder 740, and the image processing unit 1
The selection signals S _{711 to} S _71n for the RAM or the like within 0 are output.
Further, the line synchronization signal _S102 of the image processing unit 10 is input to the interrupt controller 739, and the system control unit 34 manages the progress of the processing in the sub-scanning direction based on this signal. That is, the system control unit 34
It operates according to a program stored in the OM 732, and gives instructions to the scanner unit 1 and the printer unit 2 in response to a request from the operation display unit 33, and performs initial setting of the image processing unit 10. During the image processing, the progress of the processing in the sub-scanning direction is monitored, and the read start address and the up / down control signal of the processing circuit 73, the frame memory synchronization signal of the delay processing circuit 83, the area control Processing control is performed such as changing the setting of the offset address signal and the like of the circuit 84 as needed.

The RAMs 732 and 735 are provided with a battery
It is backed up and stores the results of adjustments made on the operation display unit and past operation modes even after the power switch is turned off. In particular, the RAM 735 is a detachable IC card, and can register / call an operation mode and the like for each user.

The operation display unit 33 includes a digitizer 741 for inputting a predetermined range, position, and the like on the document 4, a touch panel display 742 in which a display unit and an input unit are integrated, a numeric keypad 743, and a clear / stop key 74.
4. An operation display panel 748 having an OHP mode key 745, an interrupt key 746, a copy key 747, etc., and an operation display control circuit 749 for controlling the entire operation display unit.
And so on.

Here, the operation display control circuit 749 is a CPU
750, a ROM 751, a RAM 752, a serial I / O circuit 753 for communicating with the system control unit 34 and the digitizer 741, and an operation display panel 748.
Is a microcomputer system including a keyboard controller 754 for detecting an input in the, a display controller 755 for performing display control, and the like. The operation display control circuit 749 is RO
It operates according to the program stored in the M751, and displays a message or the like on the display unit to prompt the user to set an operation mode or the like, thereby performing processing control such as transmitting the set result to the system control unit 34. .

The operation will be described with reference to FIGS. 49 to 54. 49 to 53 show the touch panel
7 shows examples of various display screens of a display 742. First, when the power of the digital color copying machine is turned on, the operation display control circuit 749 is in an initial state, and displays a standard screen as shown in FIG. The display areas such as "Photo", "Text", and "Standard" on the right side of the screen are areas for selecting the image quality mode. A suitable character mode and a standard mode for both a photograph image and a character image are selected.

For example, when the "character" display portion is pressed and detected by the operation display control circuit 749, a screen in which the background of the "character" display portion is different as shown in FIG. 50 is displayed, and the display portion is pressed. Is notified to the operator, and requests the system control unit 34 to set the character mode. Also, when the “standard” or “photo” display portion is pressed, the same change of the display screen and the change of the system control unit 3 are performed.
4 is made.

In response to this, the system control unit 34 receives each circuit (the first filter processing circuit 7) of the image processing section 10.
4, each RAM 486 in the color correction circuit 77, each RAM in the second γ conversion circuit 79 (corresponding to each RAM 473 in the first γ conversion circuit 76), and each of the RAMs in the second filter processing circuit 81. Flip-flops 551-5
55, etc., the settings of the pattern selection registers 585, 588 in the multi-value dither processing circuit 82, the area processing register 660 in the area control circuit 84, and the RAM 651) are changed as necessary.

For example, when a request for the character mode is received, the coefficient selection register 232 in each processing circuit of the first filter processing circuit 74 is set, and the filter coefficients for edge enhancement of the processing circuits 74 _R and 74 _G are displayed. E1 in the processing circuit 7
The filter coefficient of the edge enhancement in _4G is set to E0 in Table 2. Generally, MTF characteristics of color-separated image signals obtained by scanning a document or the like are not equal. For this reason, in the color digital copying machine, when the character mode is selected, the filter coefficients E0 to E3 for edge enhancement as shown in Table 2 are appropriately selected for each image signal. As a result, even when a black thin line such as a black character is read, the levels of the image signals after the filter processing are uniform, and replacement with black BK toner is facilitated. In addition, the full-color coefficient for the character mode is set in the RAM 486 of each of the processing circuits 77 _{BK to} 77 _C of the color correction circuit 77, and the UCR processing circuit 78 executes the UCA processing.
A process in which no process is performed (formula (3)) is selected.

As shown in Table 3, the data used to determine the coefficient for the character mode is black BK in achromatic color.
Is larger than the values of M, Y, and C, and by the processing in the UCR processing circuit 78, the color near the achromatic color is processed to be recorded only by BK. In addition, the data for character mode is designed to reproduce chromatic colors with higher saturation compared to other modes,
Colored characters and the like are reproduced vividly.

In each processing circuit of the second filter processing circuit 81, a filter coefficient selected for each character mode is set, and a pattern selection register 585, 588 of each processing circuit of the multi-value dither processing circuit 82 is set. Is set with data for the character mode dither pattern.

The RAM (corresponding to 473) of each processing circuit of the second γ conversion circuit 79 performs processing such as setting LUT data for each color corresponding to the character mode dither pattern.

Further, the system control unit 34
The region control circuit 84 is configured to select the above-described setting, such as performing edge enhancement in the processing by the filter processing circuit 74.
The contents of the area processing register 660 and the RAM 651 are changed, and during the copy operation, the offset address signal Pj is output to the area control circuit 84 so that the above-described processing is executed.

The same applies when a request for the photograph mode or the standard mode is received, and the system control unit 34 performs setting and control according to the mode.

For example, when the photograph mode or the standard mode is requested, the coefficient selection register 232 of the first filter processing circuit 74 is set so that the smoothing process using the filter coefficients of S0 shown in Table 2 is performed. By this smoothing process, moire generated when a halftone image or the like is read is removed, and a good copy is obtained. In the case where the smoothing process is performed, the same filter coefficient is used in this embodiment because the influence of the difference in the MTF characteristics described above is reduced.

The RA of each processing circuit of the color correction circuit 77
In M486, the coefficient obtained from the data shown in Table 3 is set according to the selected mode, and the UCR processing circuit 78 selects the process for performing the UCA process (formula (4)). As shown in Table 3, in the data for the standard mode, the value of BK in the achromatic color is equal to the values of M, Y, and C, and by the processing in the UCR processing circuit 78, the achromatic color in the standard mode is obtained. Is recorded so as to be recorded only in black BK. On the other hand, in the data for the photograph mode, the recording amount of the BK is reduced, whereby smooth gradation reproduction is easily realized.

Each processing circuit of the second γ conversion circuit 79
Each processing circuit of the second filter processing circuit 81 and each processing circuit of the multi-value dither processing circuit 82 also perform setting according to each mode. In this embodiment, as shown in Table 5, there are two types of dither patterns for the standard mode. Normally, the standard 1 dither pattern is selected.

As described above, in the present color digital copying machine, the optimum image quality can be selected by changing the data set in the image processing unit 10 according to the selected image quality mode.

Further, in the present embodiment, the filter coefficient set in the second filter processing circuit 81 and the LUT data set in the second γ conversion circuit 79 in each of the above-described modes can be selected by the operator. This selection can be made by pressing the image quality adjustment key 756 on the operation display panel 748. That is, the operation display control circuit 74
9 detects the operation of the image quality adjustment key 756, displays a screen as shown in FIG. 50, and displays a sharp / soft adjustment mode for adjusting the filter coefficient and a color balance adjustment mode for adjusting the LUT data. Selection is allowed.

When the sharp / soft adjustment mode is selected, the operation display control circuit 749 displays a screen as shown in FIG. 51 so that the filter coefficient of the second filter processing circuit 81 in each image quality mode can be selected. Is done. As shown in FIG. 52, in this embodiment, 11 levels of filter coefficients can be selected for each image quality mode, and the operation display control circuit 749 outputs the selected result to the system control unit 34.
The system control unit 34 informs the RAM 7
34.

The correspondence between the filter coefficients shown in Table 4 and the adjustment results is as shown in FIG. That is, in the character mode, a filter coefficient is selected mainly for smoothing, and in the standard mode, a filter coefficient is selected mainly for edge enhancement. In the photo mode, a filter coefficient centering on the through is selected. Thus, in the character mode, moire generated by edge enhancement performed by the first filter processing circuit 74 can be reduced, and in the standard mode, blur caused by smoothing performed by the first filter processing circuit 74 can be corrected. Further, in the character mode and the standard mode, the filter coefficients on the edge emphasis side for one stage are used only for BK, whereby thin lines such as black characters are copied sharply.

When the color balance adjustment mode is selected, the operation display control circuit 749 displays a screen as shown in FIG. 53 so that the LUT data of the second γ conversion circuit 79 can be selected in each image quality mode. Is done. As shown in FIG. 53, adjustment of LUT data is performed for each image quality mode and each color.
17 levels for each shadow, middle and highlight (-8 to 0
8) can be adjusted, and the operation display control circuit 7
49 informs the system control unit 34 of the adjustment result. The system control unit 34 stores this adjustment result in RAM
734, and the second γ conversion circuit 7
9 to calculate the LUT data to be set in the RAM. That is,
The ROM 730 of the system control unit 34 includes FIG.
LUT data of 2, 4, 6, and 8 for shadow portion adjustment, middle portion adjustment, and highlight portion adjustment as shown in (a) to (c) are stored in advance, and the LUT data is adjusted according to the adjustment result. Read data, perform sign inversion / interpolation, etc.
The LUT data to be set in the RAM is calculated by adding the LUT data for density adjustment as shown in FIG.

Referring again to FIG. 49 to FIG. 53, the lower right part of the screen is an image density adjustment area. When the “dark” or “light” display portion is pressed, the density of the image to be printed becomes darker. Alternatively, it can be made thinner. That is, when the operation display control circuit 749 detects the above-mentioned operation, the operation display control circuit 749 changes the display of the scale portion and transmits the result to the system control unit 4. In response, the system control unit 34 changes the selection of the LUT data for density adjustment shown in FIG.
The data is recalculated and set in the RAM of the second γ conversion circuit 79.

As described above, in this embodiment, the filter coefficient set in the second filter processing circuit 81 and the LUT data set in the second γ conversion circuit 79 in each mode are
Since selection is possible, copying under optimal conditions becomes possible.

Next, the operation when the contour mode, which is a feature of this embodiment, is selected will be described. In the display state of the standard screen as shown in FIG. 49, when the operator presses the “create” display portion, the operation display control circuit 749
Detects this operation and displays a screen as shown in FIG. This allows the operator to select various create modes including the contour mode.

In this state, when the operator further presses the "outline" display portion, the operation display control circuit 749 detects this operation and displays a screen as shown in FIG. Thus, the operator can select the line width (thick, medium, and thin) and the line density (many, medium, and small) of the outline in the outline mode. That is, in the present embodiment, the line width and the line density of the contour image to be obtained can be arbitrarily selected in three steps, and the operation display control circuit 749 displays each selection display by the operator. The pressing of the portion is detected, and the background of the selection display portion is changed accordingly.

Here, selection of the contour mode is realized by the operator pressing the "end" display portion in the display state shown in FIG. That is, when this operation is detected, the operation display control circuit 749 displays a screen as shown in FIG. 57 and requests the system control unit 34 to set the contour mode including the selection information of the line width and the line density. I do.
Similarly, the release of the contour mode is realized by the operator pressing the “release” display portion. That is, when the operation display control circuit 749 detects this operation, it performs a display corresponding to the operation and requests the system control unit 34 to release the contour mode.

It should be noted that a display screen as shown in FIG.
When the “end” display portion is pressed, the operation display control circuit 74
Reference numeral 9 returns to the standard screen display state as shown in FIG.

Next, upon receiving a request for setting the contour mode from the operation display control circuit 749, the system control unit 3
Reference numeral 4 denotes each circuit (the first filter processing circuit 7) of the image processing unit 10.
4, each RAM 486 in the color correction circuit 77, each RAM in the second γ conversion circuit 79 (corresponding to each RAM 473 in the first γ conversion circuit 76), and each of the RAMs in the second filter processing circuit 81. Flip-flops 551-5
55, the area processing register 66 in the area control circuit 84
0 and RAM 651) are changed as necessary.

For example, the setting of each coefficient selection register 232 in the first filter processing circuit 74 is performed in accordance with the selected image quality mode, but the setting is different from the above-described normal case. That is, the filter coefficient of the smoothing process is set to S1 in Table 2 in the photograph mode, and is set to S0 in the standard mode. Further, a full-color coefficient for a character mode is set in each of 486 in the color correction circuit 77 irrespective of the image quality mode selection, and the UCR processing circuit 78 selects a process in which the UCA process is not performed.

Each RAM in the second γ-conversion circuit 79 has a configuration shown in FIG. 5 in accordance with the line density (high, medium, low) of the selected contour.
LUT data for binarization (0/255) processing as shown in 9 (a) to 9 (c) is set respectively. That is, as shown in the figure, the input image signal is divided into a plurality of sections as indicated by A to G according to the levels, and the binarization levels of the output image signals corresponding to these sections are alternately changed. It switches. The line density “small” corresponds to a normal binarization process, and for example, a line density equal to or higher than D is set as a binarization threshold. The line density “medium” is divided into levels B, D, and F, and those having a level equal to or higher than level B and equal to or lower than level D and equal to or higher than level F are set as binarization thresholds. The linear density “many” is level A,
The sections are divided into B, C, D, E, F, and G. Levels are equal to or higher than level A and are equal to or lower than level B.
As described above, the binarization threshold is set to the level F or less and the level G or more. Here, the section division is sequentially increased to a state in which the section length increases as the level increases, but each section has the same length.

The coefficients of the Laplacian filter shown in Table 4 are set in each of the flip-flops 551 to 555 in the second filter processing circuit 81 according to the line width of the selected contour.

Further, the system control unit 34 has an area processing register 660 in the area control circuit 84 and a RAM.
651 is changed so that the settings described above can be selected, and during the copy operation, the offset address signal Pj is output to the area control circuit 84 so that the above-described processing can be executed. When the outline mode and the character are selected, the first filter processing circuit 74
The setting and control of the area processing register 660 of the area control circuit 84 and the RAM 651 are performed so that the through processing is performed in the area control circuit 84.

As described above, in the present embodiment, the contour processing is realized by performing the binarization processing by the second γ conversion circuit 79 and then performing the Laplacian processing by the second filter processing circuit 81. Further, by selecting LUT data to be set in the second γ-conversion circuit 79 in accordance with the selection of the line density of the contour in the operation display unit 33 from the data as shown in FIGS. Has been realized.

This will now be described with reference to FIG. In FIG. 1, the output from the UCR processing circuit 78 is the same.
The multi-gradation image signal S _75M as shown in (a) is the L signal as shown in FIGS. 59 (a) to (c) set in the second γ conversion circuit 79.
In accordance with the UT data, the image signals are binarized into image signals _S76Ma , _S76Mb , and _S76Mc as shown in _FIGS . Thereafter, the edge portions of these signals are extracted by the Laplacian processing of the second filter processing circuit 81, and the signals are extracted as shown in FIG.
To (g), the edge image signals _S81Ma , _S81Mb , S
_{81 Mc} is output. Other image signals S _75BK, S _75Y, S _75C
The same applies to. As is apparent from FIG. 1, the extracted edge density is determined by the L set in the second γ conversion circuit 79.
Since it is changed by the UT data and the actual processing is performed two-dimensionally, selection of the line density of the contour image is realized. Therefore, when the contour mode processing is performed on a document image having continuous gradation, the line density of the contour can be selected, and the contour can be reproduced according to the image characteristics. In addition, since the number of sections can be increased by selecting the line density of the contour line, the signal of the image portion for which contour extraction is desired to be performed and the background image thereof even in the case of continuous gradation. The case where the signal does not straddle the threshold level can be reduced, and a desired contour can be extracted.

[0206]

As described above, according to the present invention, in addition to the image reading means, the binarization processing means, the edge extraction processing means and the image recording means, the input of the multi-valued image signal to the binarization processing means is achieved.
Set thresholds to divide force level into multiple sections
Then, the binarized output level corresponding to each section is alternately set to 1, 0.
Conversion characteristic setting means for changing and setting the conversion characteristic of the binarization processing means so as to switch and binarize the data, wherein the input means selects the conversion characteristic according to the line density of the contour selected and designated according to the contour mode by the input means. The conversion characteristic of the binarization processing means is changed and set by the conversion characteristic setting means, and
Output multi-valued image signal in multiple sections according to gray level
Multiple thresholds are set so that
The corresponding binarized output level is switched between 1, 0 alternately
Since the edge image is extracted by the edge extracting means based on the binarized image signal, once
And edge extraction processing, it is possible to select the line density of the contour line to be extracted and recorded. Even if the original image has continuous gradation, appropriate contour processing can be performed. Since the number of section divisions according to the gradation level for which the conversion process is changed also increases or decreases in accordance with the line density, even if the original image has a continuous gradation, the signal and the background of the image portion whose contour is to be extracted are desired. It is possible to reduce the case where the signal of the image does not cross the binarization level, and it is possible to extract a desired contour.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating contour processing according to an embodiment of the present invention.

FIG. 2 is a schematic front view showing the configuration of the entire color digital copying machine.

FIG. 3 is a block diagram showing an entire electrical control system.

FIG. 4 is a block diagram illustrating an electrical configuration of a scanner unit.

FIG. 5 is a diagram showing a filter arrangement of a color CCD.

FIG. 6 is a block diagram illustrating an electrical configuration of an image processing unit.

FIG. 7 is a block diagram of a synchronization signal generation circuit.

FIG. 8 is a timing chart showing the operation.

FIG. 9 is a timing chart showing the operation.

FIG. 10 is a block diagram of a main scanning magnification changing circuit.

FIG. 11 is a timing chart showing the operation.

FIG. 12 is an explanatory diagram showing an interpolation calculation process.

FIG. 13 is a block diagram of a scaling processing circuit.

FIG. 14 is a block diagram of a processing circuit.

FIG. 15 is a block diagram of a memory control circuit.

FIG. 16 is a block diagram of a shadow area determination circuit.

FIG. 17 is a block diagram of a first filter processing circuit.

FIG. 18 is a block diagram of an external I / F circuit.

FIG. 19 is a timing chart showing the operation of the external I / F circuit.

FIG. 20 is a timing chart showing the operation of the external I / F circuit.

FIG. 21 is a block diagram of a first γ conversion circuit.

FIG. 22 is a timing chart showing the operation.

FIG. 23 is a block diagram of a color correction circuit.

FIG. 24 is a schematic diagram showing a color space.

FIG. 25 is a block diagram of a UCR processing circuit.

FIG. 26 is a block diagram of a document size detection circuit.

FIG. 27 is a plan view illustrating an example of a document state.

FIG. 28 is a timing chart showing an operation.

FIG. 29 is a block diagram of a second filter processing circuit.

FIG. 30 is a schematic diagram illustrating an example of a filter process according to a filter coefficient.

FIG. 31 is a block diagram of a multi-level dither processing circuit.

FIG. 32 is an explanatory diagram illustrating an example of a dither pattern.

FIG. 33 is a simplified front view showing the arrangement of photoconductors.

FIG. 34 is a block diagram of a delay processing circuit.

FIG. 35 is a schematic diagram showing a memory capacity for delay processing.

FIG. 36 is a block diagram of a memory control circuit.

FIG. 37 is a timing chart showing the operation.

FIG. 38 is a timing chart showing the operation.

FIG. 39 is a block diagram of a RAM block.

FIG. 40 is a timing chart showing the operation.

FIG. 41 is a block diagram of a region control circuit.

FIG. 42 is an explanatory diagram showing units of area control.

FIG. 43 is a RAM map showing storage contents of a memory.

FIG. 44 is an explanatory diagram showing storage contents of an area processing register.

FIG. 45 is a block diagram of a printer unit.

FIG. 46 is a schematic plan view showing a planar arrangement of a scanning optical system.

FIG. 47 is a timing chart showing the operation.

FIG. 48 is a block diagram of a system control unit and an operation display unit.

FIG. 49 is a plan view showing a screen display example.

FIG. 50 is a plan view showing a screen display example.

FIG. 51 is a plan view showing a screen display example.

FIG. 52 is a plan view showing a screen display example.

FIG. 53 is a plan view showing a screen display example.

FIG. 54 is a diagram showing various characteristics.

FIG. 55 is a plan view showing a screen display example.

FIG. 56 is a plan view showing a screen display example.

FIG. 57 is a plan view showing a screen display example.

FIG. 58 is a plan view showing a screen display example.

FIG. 59 is an explanatory diagram showing LUT data contents according to the line density of a contour line.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image reading means 2 Image recording means 33 Input means 34 Conversion characteristic setting means 79 Binarization processing means 81 Edge extraction processing means

Claims (2)

(57) [Claims] And 1. A image reading means for outputting a multivalued image signal having the number of gradations of the three or more gradations by reading the information such as a document image, multi-level image signal output from the image reading means gradation Binarization processing means for binarizing according to the level;
An edge extraction processing means for performing an edge extraction process on the basis of the binary image signal outputted from the binarizing means, an image recording means for recording an image based on the image signal output from the edge extraction processing means, wherein Binary processing of multi-level image signal
Divide the input level to the
Set the threshold and set the binarized output level corresponding to each section.
The binarization processing is performed so as to alternately switch between 1,0 and binarize.
A conversion characteristic setting means for changing and setting the conversion characteristics of the physical means
Digital copier characterized by Rukoto provided. 2. The method according to claim 1, wherein the multi-gradation image signal is generated according to a gradation level.
From the binarization processing step for binarization and the binarization processing step
Performs edge extraction processing based on the output binary image signal.
An edge extraction processing step, wherein the binarization processing step
Sets the input level of the input multi-valued image signal to the gradation level.
Set threshold to divide into multiple sections according to
Then, the binarized output level corresponding to each section is alternately set to 1, 0.
Contour mode process how to <br/> and outputs a binary image signal to switch.