JP3169219B2 - Color image forming equipment - Google Patents

Description

The present invention relates to a color image forming apparatus such as a color copying machine or a color facsimile having a color copy mode.

[Conventional technology]

Scan the original to scan R (red), G (green), B
2. Description of the Related Art A color image forming apparatus that performs image processing such as shading correction and gamma correction on an image signal that has been color-separated (blue) or the like and records an image based on the image signal after the image processing is widely known. I have.

Then, in the course of image processing, a technique of performing filter processing after performing color correction processing (Japanese Patent Laid-Open No. 63-125554, etc.)
And Japanese Patent Laid-Open Publication No. 1-255380, for example, have proposed a technique in which black characters and the like are reproduced only by Bk (black) by performing color correction processing of full black and black.

[Problems to be solved by the invention]

By the way, in an image reading apparatus which scans a document and outputs an image signal which is color-separated into R, G, B, etc., when a halftone image is read, interference occurs between a reading pitch of the image reading apparatus and the halftone dot, and thus, R , G, B, etc., a different moire occurs for each image signal.

When color correction processing is performed on such an image signal to obtain an image signal for color separation recording such as C (cyan), M (magenta), Y (yellow), and Bk (black), interference between the image signals is obtained. Therefore, there is a disadvantage that moire is further amplified.

Therefore, when performing filter processing after color correction processing as in JP-A-63-125054, it is necessary to perform strong smoothing in order to remove moiré, and therefore, it is included in the image. On the other hand, there has been a problem that characters cannot be copied sharply.

In general, an image reading apparatus has different MTF characteristics for each image signal such as R, G, and B. Therefore, when an image such as a black character is read, the image signals of R, G, and B do not match, and the image is output as a colored image. Accordingly, when such an image signal is subjected to color correction processing to obtain an image signal for recording a color separation plane such as C, M, Y, Bk, etc., an image such as a black character is also colored.

That is, in the method disclosed in Japanese Patent Application Laid-Open No. 1-255380, full-black color correction processing is performed to reproduce black characters and the like using only Bk, but the above-mentioned problem of the MTF characteristic cannot be solved.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a color image forming apparatus with high image quality and high reliability, which solves the above-mentioned disadvantages of the prior art.

A more specific first object is to provide a color image forming apparatus having an image processing device capable of alleviating the above-mentioned problems caused by the image reading device and the color correction processing.

Further, a second object is to provide a color image forming apparatus capable of selecting appropriate image processing according to an image to be read.

A third object is to provide an MTF for the above-described image reading apparatus.
An object of the present invention is to provide a color image forming apparatus capable of preventing coloring of black characters and the like due to characteristics.

[Means for solving the problem]

The object is to scan an original, an image reading device that outputs an image signal that is separated into red, green, blue, and the like, an image processing device that processes an image signal output by the image reading device,
In a color image forming apparatus having an image recording apparatus for recording an image based on an image signal output from the image processing apparatus, a first filter means capable of setting an independent filter coefficient for each color-separated image signal; Applying a color correction process to the image signal that has been subjected to the spatial filter process by the first filter unit to obtain a cyan, magenta, yellow,
A color correction processing means for outputting an image signal for recording a color separation such as black, and a color correction processing means for converting the image signal into an image signal of cyan, magenta, yellow, black or the like, and then performing a filtering process in a plurality of processing modes. A second filter means for performing filter processing suitable for each processing mode by changing a filter coefficient of the plurality of processing modes. The plurality of processing modes include a processing mode for a character image, and the processing mode for a character image is This is attained by the first means in which the filter coefficient when selected is edge-emphasized and different filter coefficients are provided for each image signal.

[Action]

According to the first means, the image signal subjected to the spatial filter processing by the first filter means capable of setting an independent filter coefficient for each of the image signals color-separated by the image reading device is processed by the color correction processing means. After converting the image signals into cyan, magenta, yellow, and black image signals, the filter coefficients of the filter processing are changed according to a plurality of processing modes, whereby the filter processing suitable for each of the above processing modes is performed.
Is performed by the filter means. When a processing mode for a character image is selected from the plurality of processing modes, the filter coefficient is edge-emphasized, and a different filter coefficient is set for each image signal.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Overall Description) FIG. 14 shows an outline of the structure of a mechanical section of a digital color copying machine of a type embodying the present invention, and FIG. 15 shows an outline of the structure of an electrical section of the digital color copying machine of FIG.

Referring to FIG. 14, the mechanical unit of the copying machine is mainly divided into a scanner unit 1500 for reading an original and a printer unit 1502 for recording an image on a recording sheet.

Looking at the scanner unit 1500, the original 1400 is placed on a platen (contact glass) 1401 and is illuminated by a fluorescent lamp 1402. The reflected light from the original passes through a lens array 1403, and is a color image sensor CCD1.
The light is incident on 404, where it is converted into an image signal. Also,
The fluorescent light, lens array, CCD, etc. are mounted on the carriage 1405, and the carriage drive motor 14
06 moves the carriage from right to left and scans the entire surface of the document placed on the platen.

The image signal output from the CCD 1404 is subjected to various kinds of processing by the image processing unit 1501 and the like, and then is processed by the printer unit 15.
02 is input to an LD (laser diode) not shown.

Focusing attention on the printer unit 1502, the laser beams emitted from the LDs energized by the image signal are reflected by the polygon mirror 1407, respectively, and are reflected by the fθ lens 1408 and the mirror.
After passing through 1409, the photosensitive drum 1410 is irradiated with an image. The polygon mirror 1407 is fixed to the rotation shaft of the same polygon motor 1411, and the polygon motor 1411 rotates at a constant speed to rotate the polygon mirror 1407. Further, by the rotation of the polygon mirror 1407, the above-described laser light is scanned in a direction perpendicular to the rotation direction (clockwise) of the photosensitive drum 1410, that is, in a direction along the drum axis.

The surface of the photosensitive drum 1410 is uniformly charged by a charging charger 1412 connected to a negative voltage high voltage generator (not shown). When the surface of the photoreceptor is irradiated with the laser beam, the electric charge on the surface of the photoreceptor flows to the device ground of the drum main body due to a photoconductive phenomenon and disappears. Here, do not turn on the LD when the document density is high, and turn off the LD when the document density is low.
Lights up. As a result, an electrostatic latent image corresponding to the density of the document is formed on the surface of the photosensitive drum 1410. When this electrostatic latent image is developed by the developing unit 1413, a toner image corresponding to the image density is formed on the surface of the photoconductor.

On the other hand, the recording paper 1415 stored in the cassette 1414 is fed out by a paper feeding operation such as a paper feeding roller 1416 and is fed onto a transfer belt 1418 at a predetermined timing by a registration roller 1417. While the recording paper conveyed on the transfer belt 1418 passes under the photosensitive drum 1410, the toner image on the photosensitive drum 1410 is transferred to the recording paper by the action of the transfer charger 1419. The recording paper 1415 to which the toner has been transferred is separated from the transfer belt 1418 by the action of the separation charger 1420 and sent to the fixing unit 1421. The transferred toner is fixed to the recording paper 1415, and the recording paper to which the toner is fixed is attached.
1415 is discharged to the tray 1422.

The toner remaining on the surface of the photoreceptor even after the transfer is removed by the cleaning unit 1423, while the toner attached to the surface of the transfer belt 1418 is removed by the cleaning unit 1424 and discharged to the waste toner bottle 1425. Further, the residual charge on the surface of the photosensitive drum 1410 is extinguished by the charge removing lamp 1426 before being charged by the charging charger 1412.

Referring to FIG. 15, the electrical unit of the digital copying machine includes a scanner unit 1500 that outputs an image signal obtained by reading a document, an image processing unit 1501 that performs processing on the image signal, and outputs the processed image signal. A printer unit 1502 for performing image recording based on the information, an operation display unit 1504 for inputting and displaying various processing modes, and a communication unit with the control unit of each unit to control the entire copying machine. And a system control unit 1503 for performing settings and the like.

In addition, the external device 15
06 can be connected.
Communicates and exchanges image signals.

It is assumed that the digital color copying machine of the present embodiment can read and write an A3-size image, and the pixel density of the reading and writing is 16 pixels / mm.

<Scanner Unit> FIG. 16 (a) schematically shows the electrical components of the scanner unit 1500.

In FIG. 16 (a), the CC on which the reflected light of the original is incident
The D1404 is composed of five CCD color sensor chips 1404-1, 2,3,4,5 arranged in a staggered manner, and is driven by a clock for operation control output from a clock driver circuit 1600. Have been.

The output signal of the CCD color sensor chip 1404-1 is amplified by a preamplifier circuit 1601 and then input to a shading correction circuit 1602. The shading correction circuit 1602
This circuit corrects for uneven lighting of fluorescent lamps, uneven sensitivity of the light receiving element inside the CCD, dark current, etc., and its output is A / D
The signal is converted into an 8-bit digital signal by a converter 1603. A white level memory 1604 and a dark current memory 1605 are circuits for storing reading results of a white reference plate and a black reference plate which are scanned prior to a document portion, respectively. A shading correction circuit 1602 responds to outputs of these memory circuits. The level of the image signal to be output is adjusted to realize the above-described correction.

Also, the circuits 1606-2, 3, 4, 5 for processing the output signals of the CCD color sensor chips 1404-2, 3, 4, 5 are the circuits described above, that is, the preamplifier circuit 1601, the shading correction circuit 1602, It has the same configuration as the circuit 1606-1 including the memories 1604, 1605 and the like.

The delay circuits 167-1 and 2 are circuits for delaying an input image signal, and thus, the CCs arranged in a staggered manner are provided.
The displacement dccd of the D color sensor chip 1404 in the sub-scanning direction is corrected, and the signals 1608-1, 2, 3, 4, 5 become image signals on the same line on the document surface.

In this scanner unit, since the magnification in the sub-scanning direction is realized by changing the moving speed of the carriage 1405, the required amount of daylay varies with the magnification (dccd × magnification / 100 / 16 line). However, the delay circuits 167-1 and 2 in FIG. 16 (a) have a delay memory with the number of lines corresponding to the same magnification, and control the number of lines delayed by the memory in the reduction and equal magnification. As a result, in the case of enlargement, writing to the memory is prohibited on a line-by-line basis, and the required amount of delay is realized by duplicating the reading. For this reason, even when enlargement is performed, the required capacity of the delay memory is the same as that of the same size.

The color image sensors 1404-1, 2, 3, 4, and 5 have a structure in which R, G, and B filters are arranged in order as shown in FIG. 1,2,3,4,5
Is in a state where R, G, and B signals are mixed.
The R, G, and B separation circuit 1609 is a circuit that integrates the image signals 1408-1, 2, 3, 4, and 5 sent in parallel into one and separates these signals for each color. , And outputs the integrated and separated image signals Rs, Gs, and Bs to the image processing unit 1501.

Further, the scanner unit 1500 has a scanner control circuit 1610 for controlling the entire unit.

The scanner control circuit 1610 includes a CPU 1611, a ROM 1612, and a RAM 161.
3, a micro computer system including a serial I / O circuit 1614 and a parallel I / O circuit 1615 for communicating with the system control unit 1503. Also,
The parallel I / O circuit 1615 is a home position sensor 1616
Control of the drive circuit 1618 for driving various loads such as the carriage drive motor 1406 and the fluorescent lamp 1402. This is a circuit for outputting a signal 1619 and the like. That is, the scanner control circuit 1610 operates according to a program stored in the ROM 1612, and performs setting of each circuit and drive control of various loads in accordance with a command from the system control unit 1503 and various sensor signals.

Reference numeral 1620 denotes a reference clock generation circuit, which is an image processing unit 1501.
And outputs various synchronizing signals based on the line synchronizing signal SYNCs.

The circuits described above operate in synchronization with this signal. Further, the reference clock generation circuit is provided with a line synchronization signal and a pixel synchronization signal CLKs in the scanner unit.
Is output to the image processing unit 1501.

<Image Processing Unit> FIG. 1 shows a schematic configuration example of the image processing unit 1501.

In FIG. 1, the synchronization signal generation circuit 124 includes a line synchronization signal SYNCp output from the printer unit 1502 and a control signal BU output from the system control unit 1503.
This circuit generates an image synchronization signal 123 in the image processing unit 1501 based on the setting of So.

1) Timing generator FIG. 13 (a) shows a configuration example of the synchronization signal generation circuit 124, and FIGS. 13 (b) and 13 (c) show an outline of the image synchronization signal 123.

In FIG. 13 (a), a clock generator 1303 is a circuit for generating a reference clock signal 1304 in a synchronizing signal generating circuit. F / F1305 is the reference clock signal 1304
Is output as a clock signal 1306.

Line synchronization signal output from printer unit 1502
SYNCp is a line synchronizing signal synchronized with a clock signal 1306 as shown in FIG.
Converted to SYNCs. Further, a line synchronization signal 1310 having a double cycle is generated by the F / F 1308 and the OR gate 1309.

The selector 1311 outputs the pixel synchronizing signal 1300 and the line synchronizing signal 1301 in the image processing unit 1501, and the signal set in the synchronizing signal register 1312 by the control signal BUSo.
By 1313, a clock signal 1304 or 1306 and a line synchronization signal SYNCs or 1310 are selectively output. still,
This copier is capable of operating in two modes, high speed and low speed, by switching between the pixel synchronization signal and line synchronization signal, etc. In particular, the latter mode requires fixing properties for OHP sheets and thick paper. Is selected when the recording paper to be used is used.

The counter 1313 is cleared by the line synchronization signal 1301,
The pixel synchronization signal 1300 is counted, and its output is input to the comparators 1314 and 1315. Comparator 131
4, 1315, a signal indicating the start point and an end point of the effective image area in the main scanning direction set in the synchronization signal register 1312 are also input.
The output of 16 becomes H level in the non-effective image range in the main scanning direction. This output signal is output to the multi-level dither processing circuit 120 as the main scanning direction erase signal 1317.

Also, signals 1318 and 131 set by the control signal BUSo
9 is held in the F / F 1320 in synchronization with the line synchronization signal 1301, and is output as the frame synchronization signal 1302 and the sub-scanning direction erase signal 1321, respectively.

Referring again to FIG. 1, the image synchronizing signal 123 output from the synchronizing signal generating circuit 124 is output to the respective circuits of the image processing unit, the scanner unit 1500, and the system control unit 1503.
And so on. Further, the image signals Rs, Gs, Bs and the synchronization signal CLKs output from the scanner unit 1500 are input to the main scanning direction scaling circuit 100.

2) Main-scanning scaling The main-scanning scaling circuit 100 performs scaling processing in the main-scanning direction on the image signals Rs, Gs, and Bs, etc.
This is a circuit that outputs 1, 2, and 3. The main scanning magnification changing circuit 100 is composed of processing circuits 100-1, 2, and 3 which are independent for each image signal, and FIG. 2A shows a configuration example of each processing circuit.

In FIG. 2 (a), the input image signal Rs, etc.
The data is written to FIFO (first-in-first-out) memories 200-1 and 200-2 according to the synchronization signal CLKs. Here, the synchronization signal CLKs includes a pixel synchronization signal 201 such as an image signal Rs and a line synchronization signal 202 as shown in FIG. 2B. Further, the write gate circuit 203 controls the control signal BUS
This circuit outputs a signal that is set by o and indicates the write start position at the end of the line.
The writing of the image signal to the memory is restricted. In addition, FIFO memory
Reference numeral 200 denotes an element such as a μPD42505C (manufactured by NEC Corporation) having a capacity memory capable of storing an image signal for one line, and an address counter for writing and reading which can be controlled independently.

The image signals written in the FIFO memories 200-1 and 200-2 are read out by the line synchronizing signal 1301 output from the synchronizing signal generating circuit 124 and the read clock 208-1 output from the scaling control circuit 207, and are read by the shift register. Written to 206.

The output of the F / F 254 is inverted every time the line synchronization signal 1301 is input, and the writing / reading of the FIFO memories 200-1 and 200-2 is toggled.

From the shift register 206, an image signal 2 of four consecutive pixels
09-1, 2, 3, 4 are output, and the multipliers 210-1, 2, 3,
Entered in 4.

The multiplication circuits 210-1, 2, 3, and 4 are controlled by coefficients determined for each circuit by a coefficient switching signal 208-3 output from the scaling control circuit 207 (an example is shown in FIG. 2C). The input image signal is multiplied and the result is output.

The addition and shaping circuit 212 sums the outputs of the multiplication circuits 210-1, 2, 3, and 4, further performs overflow and negative value processing, and
Output to the FO memory 214.

The shift register 206, the multiplication circuits 210-1, 2, 3, and 4 and the addition shaping circuit 212 are provided with a CCD as shown in FIG.
It is provided to interpolate the image signal value at the virtual sampling point after scaling from the image signals D1, D2, D3, 4 sampled according to. The coefficients shown in FIG. 2 (c) are determined based on the sampling function, and the selection of the coefficients is determined by the distance δ between the virtual sampling point and the CCD image signal D2.

Writing to the FIFO memory 214 is performed by the write clock 208-2 output from the scaling control circuit 207 and the line synchronization signal 1301.
The reading is controlled by a synchronizing signal generation circuit.
The pixel synchronization signal 1300 and the line synchronization signal 1301 output by 124
It is performed by. The output is the mask processing circuit 25.
Entered in 3.

The mask processing circuit 253 is a circuit for whitening the image signal according to the mask signal 208-4 output from the scaling control circuit 207, and outputs the processed image signal 101-1 and the like.

The scaling control circuit 207 calculates the position of the virtual sampling point described above, and reads and writes the read and write clocks 208-.
FIG. 2D shows a circuit for outputting 1, 2, a coefficient switching signal 208-3 and a mask signal 208-4.

In FIG. 2D, reference numeral 209 denotes a circuit block diagram for outputting the reciprocal of the magnification. The reciprocal of the magnification is represented by the output 211 of the magnification register 210, the accumulated change amount 212 in the sub-scanning direction, and the accumulated amount in the main scanning direction. The sum of the change amounts 213 is output from the addition circuit 214.

Here, the output of the magnification register 210 is determined by selecting the value set by the control signal BUSo by the area signal 125-1 output from the area control circuit 126.

Further, the cumulative change amount 212 in the sub-scanning direction is the control signal BUSo
Thus, the increment / decrement value set in the sub-scanning direction increment / decrement register 215 is selected by the area signal 125-2, and it is cumulatively added by the adder 216 and the F / F 217 each time the line synchronization signal 1301 is input. It is decided by going. The accumulated change amount is cleared by the frame synchronization signal 1302.

As the cumulative change amount 213 in the main scanning direction, the increase / decrease value set in the main scanning direction increase / decrease register 218 is selected by the area signal 125-3 by the control signal BUSo, and is selected by the adder 219 and F / F2.
According to 20, it is determined by accumulative addition every time the clock output from the OR gate 227 is input. The accumulated change amount is cleared by the line synchronization signal 1301.

The signal indicating the reciprocal of the magnification output from the circuit block 209 is processed by being divided into an integer part 221-1 and a decimal part 221-2.

The integer part 221-1 is input to the comparator 223, and it is determined whether or not the enlargement is performed (that is, whether or not the integer part is 0). That is, the signal 224-1 becomes H and the signal 224-2 becomes L in the case of enlargement, and vice versa in the case of reduction (including the same magnification).

Here, the operation in the case of enlargement will be described.
Since the output of the R gate 225 is always L, the write clock 208-2 output from the OR gate 226 and the clock signal output from the OR gate 227 are equal to the pixel synchronization signal 1300.

Since the output of the OR gate 227 controls the F / F 228, the F / F 228 performs cumulative addition of the decimal part 221-2 every time a pixel synchronization signal is input, such as an adder 229 and a selector 240. The high-order bit (for example, 3 bits in the case of FIG. 2C) of the accumulated result (output of F / F 228) is a coefficient switching signal 208.
-3 is output. The selector 240 outputs the offset signal set in the offset register 241 by the control signal BUSo while the line synchronizing signal 1301 is being input (L level). The output of F228 is equal to the offset signal. This offset signal is used to correct the difference in the center position between R, G, and B caused by the structure of the color image sensor shown in FIG. 16 (b). That is, the offset signal set in the offset register 241 is transmitted to the processing circuit 101-
It is different every 1,2,3.

On the other hand, the carry output signal of the adder 229 is input to the adder 230, and its output is further supplied to the selector 231 (N
The output of OR 225 is always input to L) comparator 232.
Since the integer part 221-1 is 0 in the case of enlargement, the input to the comparator 232 becomes 1 only when the carry is generated in the adder 229, and becomes 0 in other cases.

The comparator 232 is a circuit that outputs H when the input is 1, and in this case, the output of the NOR gate 233 becomes L,
The OR gate 234 outputs a read clock 208-1. In the case of enlargement, the signal 224-2 is always at L level, so that a read clock is generated only when a carry occurs in the adder 229.

Next, the operation in the case of reduction will be described. NOR in this case
Since the output of the gate 233 is always H, the read clock 208-1 output from the OR gate 234 is
It is equal to 0.

When the F / F 235 is cleared by the line synchronization signal 1301, the input of the comparator 236 becomes 1 or 0, so that the comparator 236 outputs H, and as a result, the output of the NOR gate 225 becomes L. As a result, immediately after the line synchronization signal changes to H, the integer part 221-1 is stored in the F / F 235. On the other hand, F / F23
The output of 5 is again input to the F / F 235 via the decrement circuit 237 and the selector 231. This is repeated until the value of the F / F 235 is decremented to 1 and the output of the NOR gate 225 becomes L.

On the other hand, when the output of the NOR gate 225 becomes L, the OR gate 22
7 generates a clock, and the sum of the cumulative value of the decimal part and the reciprocal number 221-1, 2 of the magnification stored in the F / F 228 is stored in the F / F 228 and 235. In the next cycle of the pixel synchronization signal 1300, the write clock 208-2 is operated by the operation of the F / F 238.
Is output from the OR gate 226.

The counter 242 is cleared by the line synchronization signal 1301,
The read clock 208-1 is counted, and its output is input to the comparator 243. The effective image width register 244 is set by the control signal BUSo, and the number of effective image signals determined by the writing start position of the leading end of the line set in the writing gate circuit 203 and the effective range of the original in the main scanning direction [FIG. (See (b)). This output is also input to the comparator 243. Accordingly, the comparator 244 outputs H when the output of the counter 242 reaches the number of valid image signals, and inhibits the counting operation of the counter 245.

Here, the counter 245 is cleared by the line synchronizing signal 1301 and counts the write clock 208-2 input through the OR gate 246, and its output is before the counter 245 is cleared by the line synchronizing signal 1301. Is held in F / F247. The counter 248 is cleared by the line synchronizing signal 1301 and counts the pixel synchronizing signal 1300, and its output is input to the comparator 249. Comparator 249
The F / F247 output signal is also input to the counter 248.
The mask signal 208-4 for inhibiting whitening is output until the output of the F / F 247 reaches the output value of the F / F 247.

As described above, according to this circuit, discontinuous switching of the magnification and continuous magnification change in both the main scanning and sub-scanning directions are performed by the setting to the circuit block 209 by the control signal BUSo and the area signal 125. It can be realized by control. Also, the effective image range in the main scanning direction after magnification processing changes line by line due to discontinuous switching of magnification and continuous magnification change in the sub-scanning direction. Is within the effective image range, the number of pixels written to the FIFO memory 214 is counted, and when the number of pixels is exceeded when the image signal is read from the FIFO memory 214, the image signal is whitened. Control is easy.

Referring again to FIG. 1, the image signals 101-1, 2, and 3 output from the main scanning scaling circuit 100 are input to the processing circuit 102.

3) Processing unit The processing circuit 102 performs a shift process in the main scanning direction and the like on the image signals 101-1, 2, and 3 to process the processed image signal 103-
This is a circuit that outputs 1, 2, and 3. FIG. 3A shows a configuration example of the processing circuit 102.

In FIG. 3A, image signals 101-1, 2, and 3 are input to line buffer circuits 300-1, 2, and 3, respectively. Since the line buffer circuits 300-1, 2, and 3 have the same configuration, FIG. 3A shows details of only the line buffer circuit 300-1.

Paying attention to the line buffer circuit 300-1, the image signal 1
01-1 is input to the buffer 306, and is output from the memory control circuit 301 to the control signal 302- having a different signal level.
1 and 2 selectively output to the line memories 307-1 and 2-7.

For example, when the control signal 302-1 is at the H level and the image signal is output to the line memory 307-1, the line memory 3
The I / O terminal 07-1 is brought into a high impedance state by the control signal 302-1, and the address signal 303-1 and the write enable signal 304-1 output from the memory control circuit 305.
Thus, the image signal is written to the line memory 307-1. At this time, the control signal 302-2 is at the L level, and an image signal corresponding to the address signal 303-2 is read from the line memory 307-2. Also, selector 308
Selects the image signal output from the line memory 307-2.

On the other hand, when the control signal 302-1 is at the L level, the image signal 101-1 is written to the line buffer 307-2, and the selector 308 outputs the image signal read from the line buffer 302-1.

Here, the memory control circuit 310 has a line buffer circuit 3
FIG. 3 (b) shows a circuit for outputting control signals such as 00-1, 2, 3 and the like.

In FIG. 3B, the counter 309 is cleared by the line synchronization signal 311 normally input via the selector 310 and counts the pixel synchronization signal 312, and its output is the lower write address signal of the line memory 307. Used as etc. The up-down counter 313 is initialized by the line synchronization signal 311 to the read start address set by the control signal BUSo, counts the image synchronization signal 312, and its output is the lower read address of the line memory 307. Used as a signal. The F / F 314 holds an up / down control signal and an upper address signal of the line memory 317 which are input simultaneously with the read start address. The system control unit 1503 uses the read start address and the up / down control signal to
It implements italic processing and mirror image processing.

The F / F 315 outputs a control signal 302-1,2 for switching the toggle of the line memories 307-1,2 and the like, and this output is a selection output of the lower address signal by the selectors 316,317 and a write enable signal by the OR gates 318,319. Used for masks 304-1,2.

The output of the up / down counter 313 is also input to the comparators 320 and 321. Comparators 320, 321
Signals 323 and 324, which are set in the effective image range register 322 by the control signal BUSo and indicate the start position and end position of the effective image range in the main scanning direction, are input to the other input terminal of the other input terminal. Are input to the OR gate 325. Therefore, the output signal 305 of the OR gate 325 indicates whether the lower read address of the line memory 307 is within the valid image range.

Looking again at the line buffer circuit 300-1, the signal 3
05 is input to the gate terminal of the selector 308, so that when reading from the line memory is within the valid image range, the selector 308 outputs an image signal from the line memory, and when reading out of the range is white ( An image signal of all bits H) is output.

The image signal output from the selector 308 is supplied to the selector 309.
-1 and input to the level detection circuit 310.

The level comparison circuit 310 is a circuit that compares a value set by the control signal BUSo with an image signal. Level comparison circuit
Three types of values a, b, and c can be set in 310, and these set values are used to detect a match between a comparator that compares whether the image signal Di is smaller and a higher order Di ′ of the image signal. The signals are input to the two comparators, and the respective comparison results are output as signals 311-1 to 313-1.

Although the line buffer circuits 300-1, 2, and 3 have the same configuration as described above, the values a, b, and c of the level comparison circuit 310 and the like can be set independently.

Signal 31 output from line buffer circuit 300-1, 2, 3
1-1 and the like are input to the OR gate 327 and the selector 328 of the shadow control circuit 326. When the output of the OR gate 327 is at the H level (that is, when the image signal is separated from white), the selector 328 sets the shadow length register 33 by the control signal BUSo.
Signals 331 and 311-1 representing the length of the shadow output from 0 and 311-1,
Select 2, 3 and when the output of the OR gate is at L level (ie,
When the image signal is close to white), the signals 336 and 337 output from the shadow area determination circuit 335 are selected and output to the line memory 332. The signal 333 output to the line memory 332 indicates the length of the shadow, and the signal 334 indicates the color of the shadow.

The line memory 332 is controlled by the address signal 303-3 output from the memory control circuit 301 and the write enable signal 3
After the data at the address specified by the address signal 303-3 is read out and output to the shadow area determination circuit 335, the data output from the selector 328 is written to the same address. . While reading data from the line memory 332, the output of the selector 328 is in a high impedance state by the signal 304-3.

The shadow area determination circuit 335 is a circuit for determining a shadow area, and a detailed example thereof is shown in FIG. 3 (c).

In FIG. 3C, the signals 333 and 334 output from the line memory 332 are held by the F / F 338 at the falling edge of the signal 304-3.

It is determined by the comparator 339 whether or not the signal 350 indicating the length of the shadow output from the F / F 338 has a length of 0. When the length is 0, the signal is unchanged. And output to F / F342. F / F342
3A delays the signal output from the selector 341 and the signal 351 indicating the color of the shadow output from the F / F 338 by one pixel, and FIG.
To the selector 328.

When the length of the shadow determined by the comparator 339 is not 0 and the signal 329 is L, it is determined that the shadow area is present, and the selector 343 outputs a signal 3 representing the color of the shadow output from the F / F 338.
51 is selected, otherwise, a signal of all bits L (no color) is selected and output as an inverted signal 344.

Referring again to FIG. 3A, the shadow area determination circuit 335
Signals 344-1, 2, 3 output from the NOR gate 345-1, 2, 3
Is input to

The signals 312-1 and 313-1 output from the line buffer circuits 300-1, 2, and 3 are respectively connected to NAND gates 346 and
The result is input to the NOR gates 348 and 349. The result is input to the NOR gates 348 and 349.

On the other hand, the area signals 125-4 and 5 have no processing / shadow processing /
This is a selection signal for the designated color / color conversion processing 1/2, and the decoder 352
Are input to NOR345-1, 2, 3, and 348, 349 via the.

That is, the NOR gates 345-1, 2, and 3 output an H-level signal when the shadowing process is selected by the area signal 125 and the determination result of the shadow area for each color is true. When the designated color / color conversion 1 is selected and the color represented by the image signal matches the set color (b or the like), an H-level signal is output, and the NOR gate 349 selects the designated color / color conversion 2 Further, when the color represented by the image signal matches the set color (c or the like), an H-level signal is output.

The color selection circuits 346-1, 2, 3 have NOR gates 345-1, 2, 3, 3
The value corresponding to each of the 48,349 output signals is the control signal BUSo
The color selection circuit 346 outputs the corresponding value when the output signal of each NOR gate becomes H, and outputs the signals from the selectors 309-1, 2, and 3 when the output of each NOR gate is all L. , And output as image signals 103-1, 2, and 3.

The pattern generation circuit 347 is a circuit for outputting an image signal of an image processing unit operation check pattern or the like in synchronization with the image synchronization signal 123. These patterns are selected by the control signal BUSo, and the pattern generation is performed at the same time. Whether or not the selector 309-1, 2, 3 selects an image signal output from the circuit 347 is also set.

Further, the image signal selection circuit 348 includes a line memory 307-1.
Alternatively, select the image signal stored in 2 or the like and select the signal line BU
This is a circuit to output on Si.
Performed by So.

That is, the system control unit 1503 switches the upper address signal to be set in the F / F 314 in FIG. 3B according to the position in the sub-scanning direction at the time of scanning the original, and thereby the image signal stored in the line memory 307 or the like Not to be rewritten. After that, change the setting of the read control register 349,
Line synchronization signal 311 and pixel synchronization signal 312 from control signal BUSo
To adjust the position in the main scanning direction,
An image signal output from 307 or the like is selected and captured by the image signal selection circuit 348.

As described above, in this embodiment, since the system control unit 1503 can detect the color at a predetermined position of the document, the level detection circuit 310 and the color selection circuit 3 corresponding to the color of the document are provided.
It is also possible to set 46-1, 2, 3 etc.

Referring again to FIG. 1, the image signals 103-1, 2, and 3 output from the processing circuit 102 are output from the first filter processing circuit 104.
Is input to

4) First Filter Processing Unit The first filter processing circuit 104 performs a two-dimensional filter process of 3 lines × 5 pixels on the image signals 103-1, 2, and 3, and processes the processed image signals 105-1, 2, 2, This is a circuit that outputs 3. First
The filter processing circuit 104 includes independent processing circuits 104-1, 2, and 3 for each image signal, and each processing circuit has a configuration as shown in FIG.

In FIG. 4 (a), the input image signal 103-1
Are input to the FIFO memory 400, and the output is
It is input to the memory 401. Also, the image signal 103-1,
Outputs of the FIFO memories 400 and 401 are input to circuit blocks 402-1, 2, and 3, respectively. That is, the circuit block 40
The image signals of three consecutive lines are simultaneously input to 2-1, 2 and 3. Since the circuit blocks 402-1, 2, 3 have the same structure, FIG. 4 (a) shows details of only the block 402-2.

The circuit block 402-2 has F / Fs 403-1, 2, 3, 4, and 5 that hold image signals of five consecutive pixels. Image signals at positions symmetric with respect to the center pixel of each line are not included. , Adder
The addition processing is performed by 404 and 405. From the circuit block 402-2, the central pixel 406-2 and the addition processing circuit 40
7-2, 408-2 image signals are output. This is the same for the circuit blocks 402-1,3.

The outputs of the circuit blocks 402-1, 3 located at both ends of the three lines of image signals are subjected to addition processing of the corresponding signals by adders 409, 410, 411, and the image signals 412, 41
Output as 3,414.

By the above processing, the sum of the image signals at the symmetric positions is obtained. Next, image signals having the same weight (40
7-2 and 413, and 408-2 and 412) are added by adders 415 and 416.

The filter coefficient of this filter circuit is shown in FIG.
It is possible to select from two types of smoothing, four types of edge enhancement and through as shown in FIG. Here, the selection from the two types of smoothing and the four types of edge enhancement is determined by the output value of the coefficient selection register 415 written by the control signal BUSo. Switching between smoothing / edge enhancement / through is controlled by area signals 125-6,7.

 Next, weighted addition is performed.

In the smoothing process, the image signals 418 and 41 are added by the adder 419.
4 is weighted and added, and the multiplier 420
The image signal 417 is multiplied by a coefficient corresponding to the output signal 422-1 of 5, and these two results are added by an adder 421. On the other hand, the multiplier 423 multiplies the image signal 406-2 by a coefficient corresponding to the signal 422-1, and the result is added by the adder 424 to the output of the adder 421. Further, the result is subjected to a multiplication process according to the signal 422-1 by the multiplier 425 and output to the selector 426.

On the other hand, in the edge enhancement processing, the image signals 417 and 418 are weighted and added by an adder 427, and the result is converted into a two's complement signal by a code conversion circuit 428. Multiplier 429
Multiplies the image signal 406-2 by a coefficient corresponding to the output signal 422-2 of the coefficient selection register 415, and the result is
The signal is added together with the output of the code conversion circuit 428 by 30.
Further, the output is subjected to a multiplication process of a coefficient corresponding to the signal 422-2 by the multiplier 431 and output to the selector 426.

The area signal 125-6 is a switching signal for smoothing / edge enhancement, and the selector 426 responds to this signal by the multiplier 425.
Output (smoothing) or the output of the multiplier 431 (edge emphasis) is selected and output to the shaping circuit 432. Shaping circuit 432
Is a circuit for processing the overflow and the negative value of the input signal, and outputs the result to the selector 433.
On the other hand, an image signal 406-2 corresponding to the center of 5 × 3 pixels is input to the other input terminal of the selector 433, and the area signal 125-7 is used for switching between through / smoothing or edge emphasis. The output of the selector 433 is output as an image signal 105-1 and the like via the F / F 434.

As described above, according to the present circuit, the switching of the smoothing / edge enhancement / through processing can be controlled in real time by the area signal 125. In the first filter circuit 104 shown in FIG. 1, the setting of the coefficient selection register 415 can be performed for each of the processing circuits 104-1, 2, and 3.

Referring again to FIG. 1, the image signals 105-1, 2, and 3 output from the first filter circuit 104 are input to the external I / F processing circuit 106.

5) I / F Unit The external I / F circuit 106 is a circuit for exchanging image signals between the image processing unit 1501 and the external device 1506. FIG. 5A shows an example of the configuration.

Referring to FIG. 5A, the image signals 105-1, 2, and 3 are input to the selector 500. If no image signal is sent from an external device, the image signal is selected by the selector 500. , F / F 501, and output as image signals 107-1, 2, and 3.

When an image signal is input from the external device 1506, the image signal sent from the external device is input to the other input terminal of the selector 500.

That is, the image signal 127-5 sent from the external device
Is written to the toggle controlled FIFO memory 505-1 or 50-2 via the buffer 502, the selector 503, and the F / F 504. Here, writing control to the FIFO memory 505 is controlled by a pixel synchronization signal 127-1 sent from an external device.
And line sync signal 127-2 or sync signal divider 5
07 outputs the pixel synchronization signal 508-7 and the line synchronization signal 508
-8 is selected and used by the selector 509. Further, reading from the FIFO memory 505 is performed by the pixel synchronizing signal 509-5 and the line synchronizing signal 509-6 which are output from the synchronizing signal dividing circuit 507 and selected by the selector 510. The data is input to the selector 500 via the F / F 511.

The selection of the image signal by the selector 500 is controlled by a selection signal 508-1 output from the synchronization signal frequency dividing circuit 507, whereby the image signal 105-1, 2, 3 from the scanner unit 1500 and the external device are output. From the image signal 127-5.

Further, the external I / F circuit 106 can also output an image signal to an external device. In this case, a first γ conversion unit 108 described later
Are output by the selector 503 and written to the FIFO memory 505-1 or 50-2 via the F / F 504. Here, to control writing to the FIFO memory 505, the pixel synchronization signal 508-7 output from the synchronization signal dividing circuit 507 and selected by the selector 509 is used.
And the line synchronization signal 508-8. Also FIFO
Reading from the memory 505 is performed by the pixel synchronization signal 127-1 and the line synchronization signal 127-2 sent from the external device, or the pixel synchronization signal 509- output by the synchronization signal dividing circuit 507.
5 and the line synchronization signal 509-6, and the read image signal is transmitted to an external device via the F / F 511 and the buffer 502.

The selection of the input / output of the buffer 502 and the selection of the selector 503 and the selection of the selectors 509 and 510 are controlled by the control signal BUS.
This is performed by the output signal of the input / output register 512 set by o.

The frame synchronization signal 508-2, the line synchronization signal 508-3, and the pixel synchronization signal 508-4 output from the synchronization signal dividing circuit 507 are output to an external device via a buffer 513. The input / output of image signals based on these signals or the input / output of image signals based on the pixel synchronization signal 127-1 and the line synchronization signal 127-2 generated by an external device from these signals is performed.

The above-described synchronization signal dividing circuit 507 includes the image synchronization signal 123,
Based on the setting by the area signal 125-8 and the control signal BUBo, the image synchronization signal 508-2, 3, 4, 5, 6, 7, 8, the selection signal 500-1 of the selector 500 and the FIFO memory 505-1, 2 Is a circuit for outputting the toggle control signals 508-9 and 10 of FIG. This external I / F circuit
In the 106, image signals can be exchanged with external equipment in two ways: the pixel density of the copier body (high-resolution mode) and half the pixel density (standard mode).
The synchronization signal dividing circuit 507 generates an image synchronization signal for the density conversion. FIGS. 5B and 5C show the outline of the image synchronization signal in each mode.

As shown in FIG. 5B, in the high resolution mode, the line synchronizing signal 1301 and the pixel synchronizing signal 1300 output from the synchronizing signal generating circuit 124 are output from the synchronizing signal dividing circuit as they are. The toggle control signals 508-9, 10 are inverted every time the line synchronization signals 508-3, 6, 8 are output, and the
Switch read / write of 5-1 and 2.

In the standard mode, as shown in FIG. 5 (c), a signal obtained by dividing the line synchronization signal 1301 by 2, a toggle control signal 508-9,10 inverted by this signal, and a pixel synchronization signal 1300 divided by 2 and divided by 4 The frequency-divided signal is generated by the synchronization signal generation circuit 507, and the external device receives the frequency-divided line synchronization signal 508-3.
Then, a pixel synchronization signal 508-4 divided by 4 is output. When an image signal is input from an external device, the selector 509 outputs the line synchronization signal divided by two and the image signal divided by four, and the selector 510 outputs the line synchronization signal not divided by two and the pixel synchronization divided by two. A signal is output. As a result, the image sent from the external device is doubled and taken into the copying machine body. When an image signal is output to an external device, a line synchronization signal that is not frequency-divided and a pixel synchronization signal that is frequency-divided by 2 are output to the selector 509.
9 outputs a line synchronization signal divided by two and a pixel synchronization signal divided by four. As a result, an image reduced to 1/2 is output to the external device.

Also, as shown in FIG. 5 (c), the pixel synchronization signal 1300
The signal obtained by dividing the frequency by 2 and 4 is cleared at the falling edge of the line synchronization signal divided by 2 and is controlled so that the phase of the signal becomes constant.

The direction of image signal exchange between the image processing unit 1501 and the external device 1506 and switching between high resolution / standard mode described above are performed by the external device 1506 and the system control unit 15.
Determined by communication with the system control unit 1503
Is set by In addition, the synthesis control of the image signal from the scanner unit 1500 and the external device 1506
-8.

Referring again to FIG. 1, the image signals 107-1, 2, and 3 output from the external I / F circuit 106 are input to the first γ conversion processing circuit 108.

6) First γ-Conversion Processing Unit The first γ-conversion circuit 108 performs LUT processing on the image signals 107-1, 2, and 3 according to the γ characteristics of the scanner unit 1500 and the external device 1506.
(Look-up table) This is a circuit that performs conversion and outputs processed images 109-1, 2, and 3. The first γ conversion circuit of the present color copier converts the image signal into an image signal proportional to the 1/3 root of the reflectance as shown in the first equation.

Here, X is a reflectance conversion value of the input image signal,
X 'is an image signal value to be output, H is a reflectance conversion value at the background level of the input image signal, S is a reflectance conversion value of the darkest part of the input image signal, and cubt () is a function for calculating the 1/3 root. It is.

The first γ-conversion circuit 108 includes independent processing circuits 108-1, 2, and 3 for each image signal, and FIG. 6A shows a configuration example of each circuit.

Referring to FIG. 6A, the image signal 107-1 and the like and the area signal 125-9 are input to the address terminal of the RAM 602 via the F / F 600 and the selector 601. LUT data for converting the image signal is stored in the RAM 602 in advance, and the F / F 603
, An image signal 109-1 or the like corresponding to the address signal is output.

The LUT data stored in the RAM 602 is written to the RAM 602 by the control signal BUSo. That is, when the system control unit 1503 writes data to the RAM 602,
As shown in FIG. 6B, the control signal 1603-1 is set to L, and the control signal 1600 is output as one pulse. As a result, the output of the counter 604 is cleared, and the RAM 60 is used as an address signal.
Entered in 2. Next, the system control unit outputs predetermined data to the control signal 1602 and then sets the control signal 1601 to 1
Output pulse. As a result, the first data is written into the RAM 602, and at the same time, the output of the counter 604 advances to prepare for writing the next data. This is repeated a predetermined number of times (n
The necessary data is written by repeating the process twice), and finally, the control signal 1603-1 is set to H to complete the writing.

Further, the LUT data of a plurality of types of conversion characteristics can be written in the RAM 602, and the real-time switching by the area signal 125-9 can be performed according to the instruction from the operation / display unit 1504.

Referring again to FIG. 1, the image signals 109-1, 2, and 3 output from the first γ conversion circuit 108 are input to the color correction circuit 110.

7) Color correction / BP processing unit The color correction circuit 110 receives the input image signals 109-1, 2, 3
Are the Bk, M, and Bk used in the printer unit 1502.
Image signal 11 in consideration of unnecessary absorption components of Y and C toners
This is a circuit that converts the data into 1-1, 2, 3, and 4 and outputs the converted data. The processing content can be represented by the following equation.

However, R, G, and B are added to the image signals 109-1, 2, 3, and Bk, M,
Y and C correspond to the image signals 111-1, 2, 3, and 4, respectively.

The color correction circuit 110 includes independent processing circuits 110-1, 2, 3, and 4 for each output image signal. FIG. 7A shows a configuration example of each processing circuit.

Referring to FIG. 7 (a), the image signals 109-1, 2, 3 are F /
The signals are input to multipliers 702-1, 2, 3 via F700-1, 2, 3, and 701-1, 2, 3. The outputs of the F / Fs 700-1, 2, and 3 are also input to a coefficient generation block 703.

A coefficient generation block 703 and a circuit that outputs coefficient signals 704-1, 2, and 3 to the other input terminals of the multipliers 702-1, 2, and 3, respectively, and this coefficient signal is transmitted through the F / Fs 701-1, 2, and 3. Are output from the RAMs 706-1, 2, and 3. Here, the coefficient signals output from the RAMs 706-1, 2, and 3 are selected based on the image signals 109-1, 2, and 3 and the area signal 125. That is, the outputs of the F / Fs 700-1, 2, and 3 are input to the comparators 707-1, 2, and 3, and the outputs of the comparators 70-1, 2, and 3.
From 7, a signal corresponding to the magnitude relationship between the image signals is output and input to the selector 708. The selector 708 selects and outputs the output of the comparator 707 or the area signal 125-11 according to the area signal 125-10. The output is input to the RAMs 706-1, 2, and 3 as address signals via the selector 709 together with the area signal 125-12, whereby the coefficients are selected.

Note that the selection of coefficients using the outputs of the comparators 707-1, 2, 3 is used only in the full-color mode, and the coefficients are directly selected by the area signal 125 in the mono-color mode.

The coefficients stored in the RAMs 706-1, 2, 3, and 4 are written in advance by the control signal BUSo. That is, the system control unit 1503 sets the control signal 1603-2 to L and outputs one pulse of the control signal 1600. As a result, the output of the counter 710 is cleared, and its lower bits are output to the RAMs 706-1, 2, 3, and 4 as address signals. The upper bits of the counter 710 are input to the decoder 711, and the decoder 711 selects the RAM 706-1. Next, the system control unit outputs predetermined data to the control signal 1602 and then outputs one pulse of the control signal 1601. As a result, the first data is written into the RAM 706-1, and at the same time, the counter 710 advances to prepare for writing the next data. The system control unit repeats this, and
Write the necessary data to -1 and repeat this
Write necessary data to RAM706-2,3,4. When this is also completed, the system control unit sets the control signal 1603-2 to H, and the write operation ends.

On the other hand, the outputs of the multipliers 702-1, 2, 3 are added together with the output of the RAM 706-4 by the adders 712, 713, 714, and the shaping circuit 715 is added.
Is input to

The shaping circuit 715 processes the overflow and the negative value of the addition result, and outputs the result via the F / F 716 to the image signal 111-.
Output as 1 etc.

Note that the RAM 706-4 outputs a signal corresponding to the constant term (a14 to a44) of the first equation, and the output value is the area signal 125-1.
3 allows you to select in real time.

Next, in the full-color mode, the color correction circuits 110-1, 2, 3, 4
Will be described.

The processing in the color correction circuit 110 is represented by a first-order function as shown in the first equation. When performing full-color processing, coefficient switching by the comparators 707-1, 2, 3, and the like as described above is performed. Has also gone. As a result, FIG. 7 (b)
The optimal coefficients a11 to a34 are set for each area divided by a plane radially extending around the achromatic axis (R = G = B) in the color space formed by the image signals R, G, and B as shown in FIG. It can be set.

The coefficients a11 to a44 actually set include six chromatic colors on the boundary surface of each area and two achromatic image signals R and G common to each color space as shown in FIG. 7C. , B
And the corresponding image signals Bk, M, Y, and C, and are obtained from the system control unit 1503.

Referring again to FIG. 1, the image signals 111-1, 2, 3, and 4 output from the color correction circuit 110 are input to the UCR processing circuit 112.

8) UCR / UCA processing unit The UCR (Under Color Removal) circuit 112 is a color correction circuit 1
This is a circuit for correcting the image signals 111-2, 3, 4 (M, Y, C) according to the image signal 111-1 (Bk) obtained in step 10.
Note that the image signals 111-2, 3, and 4 output from the color correction circuit 110 of the present image processing unit are signals that do not take Bk recording into account. Since the vividness of the image is lost, this circuit is provided for the correction. The UCR circuit 112 includes independent processing circuits 112-1, 2, 3, and 4, and the processing circuit 112-
FIG. 8 shows configuration examples of 2, 3, and 4.

Referring to FIG. 8, image signals 111-1 and 111-2 are input as address signals of the ROM 802 via F / Fs 800 and 801 respectively. The results of the two types of calculations as shown in the equations (2) and (3) are stored in advance at a predetermined address in the ROM 802, and the results of the calculations are read out from the ROM 802 and are read via the selector 803 and F / F 804. It is output as an image signal 113-2 or the like.

The area signal 125-14 is used for switching the calculation according to the second or third equation, and is input to the ROM 802 in the same manner as the image signals 111-1 and 111-2. The processing according to the second equation is usually a UCR processing, whereas the processing according to the third equation is a UCA processing.
(Under Color Addition) is also considered.

The area signal 125-15 is used to select whether or not to perform the above-described processing.

 X ′ = X−Bk (3) where X = M, Y, and C.

X ′ = u (Bk) · (X−Bk) (4) where u (Bk) is a function of Bk, and X = M, Y, and C.

The processing circuit 112-1 shown in FIG.
Image signals 113-1, 2, 3, 4 output from the UCR processing circuit 112, which is a circuit for delaying the image signal 111-1, in accordance with the delay of the image signal generated in 12-2, 3, 4
Is input to the second gamma conversion processing circuit 114.

9) Second γ-Conversion Processing Unit The second γ-conversion processing circuit 114 generates image signals 113-1, 2, 3, and 3 according to the state of the printer unit 1503 and the dither pattern selected by the multi-value dither processing circuit 120 described later. 4 is a circuit that performs LUT conversion on 4 and outputs processed image signals 115-1, 2, 3, and 4. The second γ conversion circuit is composed of processing circuits 114-1, 2, 3, and 4 which are independent for each image signal, and each circuit is a circuit example of the first γ conversion circuit 108 shown in FIG. It has the same configuration as. Therefore, although detailed description is omitted, it is possible to write LUT data of a plurality of types of conversion characteristics and to switch in real time by the area signals 125-16.

The image signal 115− output from the second γ conversion processing circuit 114
The upper 6 bits of 1, 2, 3, and 4 are input to the document size detection circuit 116.

10) Document Size Detection Processing Unit The document size detection circuit 116 is a circuit for detecting the size and position of the document 1400 placed on the platen 1401 prior to the copying operation. The document size detection circuit 116 is composed of independent processing circuits 116-1, 2, 3, and 4, and a configuration example of each circuit is shown in FIG. 9 (a).

Referring to FIG. 9A, the input image signal 115
-1 and the like are connected to the selector 901 and the delay circuit 9 via the F / F 900.
18 and the difference circuit 902. The delay circuit 918 is a circuit for delaying the input image signal by n pixels, and its output is also input to the difference circuit 902. The difference circuit 902 is a circuit that outputs the absolute value of the difference between the two input image signals. The output of the difference circuit 902 is input to the comparator 903, where it is compared with the threshold signal 905-1 output from the document size register 904. That is, the absolute value of the difference between the image signals separated by n pixels is equal to the threshold signal 90.
If it is larger than 5-1, the comparator 903 is a circuit that outputs H. In this circuit, the boundary between the original portion and the non-original portion (press plate portion 1428) is to be detected based on the difference between the image signals. Accordingly, a pixel whose output of the comparator 903 is H is treated as a candidate for a boundary between a document portion and a non-document portion.

The output of the comparator 903 is input to the shift register 906, and the comparison results for n pixels are collected and input to the main scanning direction determination circuit 905. If at least m (m ≦ n) pixels among the input determination results for n pixels are H, the main scanning direction determination circuit 905 regards the input as a candidate for a boundary between a document portion and a non-document portion. , H level signals.

The output of the main scanning direction determination circuit 905 is input to a FIFO memory 906, where the determination results for n ′ lines are collected and input to the sub-scanning direction determination circuit 907. In the sub-scanning direction determination circuit 907, m ′ out of the determination results for the input n ′ lines
If (m'≤n ') line or more is H, it is regarded as a candidate for the boundary between the original portion and the non-original portion and an L level signal is output.

By the way, the original size detection circuit 116 is shown in FIG.
As shown in FIG. 9A, the minimum value x1, the maximum value x2 in the main scanning direction and the minimum value y1 and the maximum value y2 in the sub-scanning direction of the boundary between the document and the non-document portion are detected. , These values
It operates to hold x2, x1, y2, and y1 in F / Fs 908, 909, 910, and 911, respectively.

That is, the counters 912 and 913 count the position in the main scanning direction and the position in the sub scanning direction, respectively.
When the output of the counter 912 is larger than the value held by the F / F 908 and the output of the sub-scanning direction determination circuit 907 is L, the operation is performed to hold the output value of the counter 912.
In the F / F909, when the output of the counter 912 is smaller than the value held by the F / F909, the value of the F / F909 is updated. Further, the F / F 911 holds the output of the counter 913 when the output of the sub-scanning direction determination circuit first becomes L, and the F / F 910 holds the counter 913 every time the output of the sub-scanning direction determination circuit becomes L. Hold the output. As a result, the output of the counter 913 when the output finally becomes L in the sub-scanning direction determination circuit is held in the F / F 910.

The data held in the F / Fs 908, 909, 910, and 911 are selectively output on the signal line BUSi via the selector 914 by the output signals 905-2 and 905 of the document size register 904 set by the control signal BUSo. Is output.

The above-described circuit is divided into a ninth circuit by a frequency dividing circuit 915.
As shown in FIG. 7C, the operation is performed by the image synchronization signal 916 and the line synchronization signal 917 divided by four, so that small dust adhering to the platen 1401 is not detected as a boundary. . In order to prevent the boundary between the platen portions as shown in FIG. 9 (b) from being determined as the boundary between the original and the non-original portion (pressing plate), the region outside the platen is a color correction circuit 110 and an area control circuit 126. Is painted in the same color as the pressure plate.

In addition to the image signal output by the F / F 900, the selector 901 also receives the upper bits of the outputs of the counters 912 and 913 and the non-recording data (= 0). These signals are output to the image processing circuit and the printer unit at the subsequent stage. A signal 905 output from the document size register 904 as a test image signal 1502
-4 can be selected.

Referring again to FIG. 1, the image signals 117-1, 2, 3, and 4 output from the document size detection circuit 116 are input to the second filter processing circuit 118.

11) Second filter processing unit The second filter processing circuit 118 is configured to output the image signals 117-1, 2, 3, 4
Is a circuit that performs a two-dimensional filtering process of 3 lines × 5 pixels to output processed image signals 118-1, 2, 3, and 4.
The second filter processing circuit 118 includes independent processing circuits 118-1, 2, 3, and 4 for each image signal, and FIG. 10A shows a configuration example of each processing circuit.

Referring to FIG. 10 (a), the input image signal 117
-1 etc. are input to the FIFO memory 1000, and the output is
It is input to the FIFO memory 1001. Also, the image signal 117
-1, the outputs of the FIFO memories 1000 and 1001 are input to circuit blocks 1002-1, 2, and 3, respectively. Accordingly, three continuous lines of image signals are input to the circuit blocks 1002-1, 2, and 3. Since the circuit blocks 1002-1, 2, 3 have the same structure, FIG. 10 (a) shows details of only the circuit block 1002-2.

The circuit block 1002-2 has F / Fs 1003 and 1004 that hold image signals of two consecutive pixels. The output of the F / F 1003 is a multiplier 1006, 1007, 1008, and 1009, and the output of the F / F 1004 is a multiplier. 1005
Has been entered. Also, multipliers 1005, 1006, 1007, 1008,
The other input terminal of 1009 holds the temporary filter coefficient
Outputs of the F / Fs 1010, 1011, 1012, 1013, and 1014 are connected. The outputs of the multipliers 1005 and 1006 are added by the adder 1015, and the result is delayed by the F / F 1016 and then added to the adder 1
The output from the multiplier 1007 is added by 017. Further, the result is delayed by the F / F 1018 and then added to the output of the multiplier 1008 by the adder 1019. Hereinafter, the delay / addition is similarly repeated, and the final result is output from the F / F 1022. It should be noted that this result is equal to the result of performing the filtering process of 1 line × 5 pixels.

The outputs of the circuit blocks 1002-1, 2, and 3 are added by adders 1023 and 1024 and input to a multiplier 1026 via an F / F 1025. F / F1 is connected to the other input terminal of multiplier 1026.
The coefficients held in 027−1 and 2 are input, and the result of the multiplication is input to the shaping circuit 1028. The true filter coefficient of this circuit is expressed as the product of the coefficient held in F / F1027-1,2 and the temporary filter coefficient (output of F / F1010, 1011, 1013, 1014, etc.). .

The shaping circuit 1028 is a circuit that operates in two modes according to the output signal of the F / F 1033. The first mode is a multiplier
This is a mode in which the signal output from the multiplier 1026 is processed for overflow and negative values. The second mode is a mode in which the absolute value of the signal output from the multiplier 1026 is calculated and then the overflow is processed. Note that the latter mode is a mode used only when performing contour processing using a Laplacian filter as shown in c of FIG. 10B, and the former mode is used in normal filter processing.

The image signal output from the shaping circuit 1028 is output as an image signal 119-1 and the like via the selector 1029 and the F / F 1030. By the way, the other input terminal of the selector 1029 also receives an image signal corresponding to the center of 5 × 3 pixels.
The switching is performed by the area signal 125-17. That is, in the present circuit, the result of performing the filter processing and the result (through) of not performing the filter processing can be switched and output in real time. The F / Fs 1031-1, 2, 3, 4, and 5 have a function of correcting a delay caused by the filter processing.

Also, F / F1010,1011,1012,1013,1014,1027-1,1027-
The data held in 2, 1029 and the like are written by the control signal BUSo. That is, these F / F groups have a shift register structure. The system control unit 1503 sets the control signal 1603-3 to L, outputs predetermined data to the control signal 1602, and outputs the control signal 1601 for one pulse. Repeat outputting. By this. The data is sequentially shifted, and finally the setting is completed by setting the control signal 1603-3 to H.

In addition, as is clear from the above description, the present circuit can set an arbitrary filter coefficient. still,
The system control unit 1503 stores a filter coefficient as shown in FIG.
The filter coefficient is selected and set according to an instruction from the user.

Referring again to FIG. 1, the second filter processing circuit 118
The image signals 119-1, 2, 3, and 4 output from are input to the multi-value dither processing circuit 120.

12) Dither processing section The multi-value dither processing circuit 120 performs 8-value dither processing on the image signals 119-1, 2, 3, and 4, and outputs the processed 3-bit image signals 121-1, 2, 3, 3 respectively. , 4 are output. The multi-value dither processing circuit 120 includes independent processing circuits 120-1, 2, 3, and 4 for each image signal, and FIG. 11 (a) shows a configuration example of each processing circuit.

Referring to FIG. 11 (a), the image signals 119-1, etc.
The address signal is input to the ROMs 1101 and 1102 via the / F1100. Also, the outputs of the counters 1103 and 1104 and the pattern selection register 1111-
1 is also input, and the outputs of the counters 1105 and 1106 and the PS output of the pattern selection register 1111-2 are also input as the address signal of the ROM 1102.

ROMs 1101 and 1102 store results after multi-value dither processing determined by image signal values and counter output values, respectively, and the results are output from ROMs 1101 and 1102. Also, the P output from the pattern selection registers 1111-1 and 111-2 is
The S signal is a signal for selecting one of the processing results of the two types of multi-valued dither patterns stored in the ROMs 1101 and 1102.

The counters 1103 and 1105, and 1104 and 1106 are counted by the pixel synchronization signal 1300 and the line synchronization signal 1301, respectively, and cleared by the line synchronization signal 1301 and the frame synchronization signal 1302, respectively. Also, counters 1103, 1104, 1105, 110
6 and the comparators 1107, 1108, 1109, and 1110 form a pair of n-ary counters, respectively, and their periods are determined by the LP outputs of the pattern selection registers 1111-1 and 111-2.

The image signals output from the ROMs 1101 and 1102 are output as image signals 120-1 and the like via the selector 1112 and the F / F 1113. Here, the selector 1112 supplies the area signal 125-18
This signal is input to the pattern selection register 11
The dither pattern narrowed down to two by 11-1 and 2 is used to switch in real time. The main scanning direction erase signal 1317 and the sub-scanning direction erase signal 1321 output from the synchronization signal generation circuit 124 are
The signal is input to the gate terminal of the selector 1112 via the F / F 1116, and this signal is used to output a white image signal regardless of the image signal 119-1 or the like.

The settings in the pattern selection registers 1111-1 and 2
This is performed by the control signal BUSo.

FIG. 11B shows an example of a large-scale multi-valued dither pattern stored in the ROMs 1101 and 1102.

In FIG. 11 (b), levels 1,2,3,4,5,6,7 represent threshold values of the octalization level.

As shown in the figure, the ROM 1101 stores image signals 119-1, 2, 3, 4
The processing results of two common patterns (a. Halftone type, b. All lines type) are stored in the ROM 1102, and the image signals 119-1, 1.2, and
Two processing results are stored: a pattern common to 3 and 4 (c. Line type) and a different pattern (d. Halftone type) for each image signal. As the pattern d for the image signals 119-2 and 4-4, a small threshold pattern as shown in the figure is used repeatedly, and a dither pattern of 10 pixels × 10 pixels is obtained as a whole.

Focusing again on FIG. 1, the image signals 121-1, 2, 3, and 4 output from the multi-value dither processing circuit 120 are
Is input to

13) Delay processing section As shown in FIG. 18A, the delay processing circuit 122 receives the image signals 121 corresponding to the number of lines corresponding to the distance from the corresponding photosensitive drum with the Bk photosensitive drum as the origin. −2,
This is a circuit for delaying 3, 4 so that images based on the image signals 121-1, 2, 3, 4 are superimposed on the same position on the recording paper.
FIG. 18 (b) shows a configuration example of the delay processing circuit 122. still,
The distance between adjacent photosensitive drums in this copier is 110m
m.

Referring to FIG. 18 (b), the image signals 121-1, 2, 3, and 4 are input to the separation selection circuit 1800. Separation version selection circuit 1800
Is a circuit for selecting one of the input image signals and outputting it as an image signal for Bk recording.
It is used in the separation mode in which the masters for simple printing are created by recording 3 and 4 individually in Bk. Selection of image signal is control signal
BUSo, and is set to select the image signal 121-1 in the normal operation mode.

Image signal and image signal 12 output by separation selection circuit 1800
1-2, 3, and 4 are input to the selector 1801. Also, the selector
The image signal and the selection signal output from the pattern generation circuit 1802 are also input to 1801. The pattern generation circuit 1802 is a circuit that outputs an image signal of a pattern for adjusting the number of delay lines or a pattern for checking the operation of the delay processing circuit in synchronization with the image synchronization signal 123, and these patterns are selected by the control signal BUSo. At the same time, whether or not the selector 1801 selects the image signal output from the pattern generation circuit 1802 is set.

The image signal selected by the selector 1801 is input to the mask processing circuit 1803. The mask processing circuit 1803 individually whitens the input image signal according to the setting of the control signal BUSo, and synchronizes the image signal with the pixel synchronization signal 1300.
1804 is a circuit that outputs 1, 2, 3, 4; for example, in the above-described separation mode, the image signals for M, Y,
It operates so that only k is recorded.

The image signal 1804-2 output from the mask processing circuit 1803,
Reference numerals 3 and 4 are connected to the data input terminals of the RAM blocks 1805, 1806, 1807 and 1808. However, the image signals 1804-2 and 18
04-4 is selectively connected to a data input terminal of a RAM block 1808 via a selector 1809.

Here, the role of the RAM block 1808 will be described. In order to realize the above-described delay processing corresponding to the distance between the photosensitive drums, the RAM blocks 1805, 1806, 1807, and 1808 are usually
18 It is used in the delay mode shown in FIG. That is, RAM blocks 1805 and 1808 are RAM blocks 18 for C.
06 is used for delaying the image signal for Y, and RAM block 1807 is used for delaying the image signal for M.

On the other hand, in the delay processing circuit shown in FIG. 18B, the RAM blocks 1805, 1806, 1807, and 1808 can be used as a frame memory. In this case, as shown in FIG. Operate in frame memory mode. That is, RAM
The block 1808 is diverted to the storage of the image signal for M, thereby realizing a frame memory having the same memory capacity of M, Y, and C and having an area of about 220 mm × 297 mm (length in the main scanning direction).

Therefore, RAM blocks 1805 and 1806 are 220 × 297 × 16 × 16 =
16727040 を The capacity of the image signal for 16M pixels is stored in the RAM block.
1807 and 1808 have a capacity of 110 × 297 × 16 × 16 = 8363520 / 8M pixels.

Referring again to FIG. 18 (b), the memory control circuit 18
Reference numerals 10,1811,1812 denote circuits for outputting the address signals of the M, Y, and C RAM blocks and control signals such as write enable, respectively, and outputs the RAM blocks 1805, 1806, 1807, and 1807, respectively.
Entered in 1808. The RAM block 1808 has M
And C address signals and the like are selected and input by the selector 1809 in accordance with the above-described delay / frame memory mode.

Also, the memory control circuits 1810, 1811 and 1812 control the control signal BU.
The operation mode is determined by the setting by So, and the operation is performed in synchronization with the image synchronization signal 123.
Are referenced when writing to the memory. Here, the synthesis control circuit 1813 has the RAM blocks 1805, 18
A circuit which controls writing of a partial image signal when 06, 1807, and 1808 are used as a frame memory. The control at this time is performed based on the area signal 125-19 or the image signal 121-1. In other modes, a signal fixed to L is output.

Next, a detailed configuration example of the memory control circuit 1812 will be described with reference to FIG. In FIG. 18 (d), a counter 1814 that outputs a signal indicating the position in the main scanning direction is cleared by the line synchronization signal 1301 and counts the pixel synchronization signal 1300, and the output signal is a comparator 1815 and 1816.
Has been entered.

The memory control register 1817 is a circuit which is set by a control signal BUSo and outputs various control parameter signals 1818. For example, the parameter signal 1818-1 is an effective image in the main scanning direction as shown in FIG. The start position, the parameter signal 1818-2 represents the effective image width in the main scanning direction, and the parameter signal 1818-3 represents the repeat width in the main scanning direction of the repeat processing in the memory mode.

The other input terminal of the comparator 1815 receives the parameter signal 1818-1, and the other input terminal of the comparator 1816 receives the sum of the parameter signals 1818-1 and 1818-2. Accordingly, the OR gate 1819 outputs the pixel synchronization signal when the position indicated by the counter 1814 is within the effective image area in the main scanning direction.
Outputs 1829.

The counter 1820 counts the pixel synchronization signal 1829 output from the OR gate 1819 and is cleared by the line synchronization signal 1301 or the like input via the AND gate 1821.
Here, the output of the counter 1820 means an offset address in the main scanning direction in the RAM block, and the output is input to the comparator 1822 and the adder 1823.

A parameter signal 1818-3 is input to the other input terminal of the comparator 1822. The comparator 1822 outputs L when the value of the counter 1820 matches the value of the parameter signal 1818-3, and this output is used for clearing the counter 1820 via the AND gate 1821. That is, thereby, the repeat in the main scanning direction is realized. Note that the comparator 1822
The clear operation of the counter 1820 by the RAM block 1805,
It is used only when the repeat processing is performed by setting 1806, 1807, 1808 to the frame memory mode. In other modes, (value of signal 1818-2) <(value of signal 1818-3), so that it is cleared. No action occurs.

The frequency dividing control circuit 1833 divides the line synchronizing signal 1301 by 2 according to the setting by the control signal BUSo as shown in FIG. 18 (h), and in a normal operation, the line synchronizing signal 1301
Is output as is.

A counter that counts the line synchronization signal 1834 and is cleared by the frame memory synchronization signal 1904 or the like input from the system control unit 1503 via the AND gate 1824.
The output of 1825 is input to the comparator 1826. The parameter signal 1818-4 input to the other input terminal of the comparator 1826 indicates the number of delay lines in the sub-scanning direction in the delay mode and the repeat width in the sub-scanning direction in the frame memory mode. Each time reaches the value of the parameter signal 1824, the AND gate 1824 outputs L, as a result, the counter 1825 is cleared, and thereafter, this operation is repeated.

The F / F 1827 is cleared by the output of the AND gate 1824, and every time the line synchronization signal 1834 is input, the sum of the parameter signal 1818-3 representing the effective image width in the main scanning direction and the output value of the F / F 1827 is provided. Is output as a new value. This output means an offset address in the sub-scanning direction,
An adder 1823 is added together with the offset address in the main scanning direction to obtain a true address.

Here, the role of the frequency division control circuit 1833 will be described. The frequency division control circuit 1833 has a function of doubling the apparent memory capacity in the frame memory mode (440 mm × 297 mm). That is, by dividing the line synchronization signal by two, the way the offset address advances in the sub-scanning direction is halved, whereby the image signal of the same line is read twice consecutively, and the area is reduced. Is doubled. Even when the apparent memory capacity is doubled as described above, when writing the image signal to the frame memory, the line synchronization signal is not divided by two, and is reduced to half in the sub-scanning direction. To write image signals. As a result, the writing time to the memory is shortened, and the operability is improved.

As described above, the memory capacity for cyan is 16 + 8 = 24 M pixels in the day-lay mode, and 16 M pixels in the frame memory mode. Therefore, the upper two bits (AD23, 24) of the address signal are input to the decoder 1835 and output to the RAM block as chip select signals (CS0, 1, 2) in units of 8M pixels.

The OR gate 1831 receives the signal 1830, the inverted signal of the line synchronization signal 1834, and the pixel synchronization signal 1829 input from the synthesis control circuit, and outputs the output to the RAM block as a write enable signal. . That is, R
In the AM block, an image signal is written when the output of the OR gate 1831 changes from H → L → H.

FIG. 18 (f) shows an example of a schematic configuration of the RAM block 1807.
FIG. 8 (g) shows the operation. In FIG. 18 (f), R
The AM block 1807 is a memory array 183 with a capacity of 8M pixels.
6, 1837 and a buffer 1838, and the above-mentioned chip select signals (CS0, 1) are used for selecting the memory arrays 1836, 1837.

In this circuit, as shown in FIG. 18 (g), when an address signal or the like is determined, the stored data is output from the I / O terminal of the corresponding RAM array, and this data is output to an output control circuit 1832 described later. It is latched. Here, when the write enable signal falls, the RAM array enters a high impedance state, while the image signal Di is input to the RAM array by the buffer 1838. The RAM array stores this image signal at the rise of the write enable signal,
The image signal is rewritten. When the write enable signal does not become L, the stored image signal is held as it is.

Note that the memory control circuits 1810 and 1811 are
Since the configuration is the same as that of 2, the description is omitted.

In the above description, the memory control circuits 1810, 1811 and 1812
Has been described as an independent circuit, but since the parameter signals 1818-1, 2, and 3 set in the memory control register 1817 and the like are common to each circuit, an offset address in the sub-scanning direction is output. Circuit (1824,1825,1826,1827,182
8), adder 1823, decoder 1835, parameter signal 1818
-4, the memory frame synchronization signal 1904 may be common except for the signal.

Referring again to FIG. 18 (b), the RAM blocks 1805,
The image signals output from 1806, 1807, 1808 are input to the output control circuit 1832. The output of the RAM block 1808 is output from the RAM block 1805 or the RAM block 1808 by the operation of the buffers 1833 and 1834.
Has been with either of the 1807 outputs. That is, the memory mode register 1839 is a register set by the control signal BUSo when selecting the above-described delay / frame memory mode. The signal output from the memory mode register 1839 controls the image signal, the address signal, and the like by the selector 1809. Selection and operation of the buffers 1833, 1834 are controlled. The image signal 1804-1 described above is also input to the output control circuit 1832.

The output control circuit 1832 aligns the input image signal in the main scanning direction in accordance with the image synchronization signal 123, whitens the image signal in the non-effective image range set by the control signal BUSo, and As shown in the figure, the image signals BKp, M
It is a circuit that outputs as p, Yp, and Cp. The output control circuit 1832 also outputs an image synchronization signal CLKp of the image processing unit 1301 together with the image signal.

14) Area processing unit The area control circuit 126 is a circuit that outputs the above-mentioned area signal 125, and FIG. 12 (a) shows a configuration example thereof. In addition,
The area control circuit 126 shown in FIG.
In order to realize the control of the rectangular area, the control patterns are classified in line units, and the control patterns are classified in the main scanning direction as shown in FIG. 12 (c). Switching point coordinates xi and area number area
It is stored in the memory 1202 in the form of ai and used.

Referring to FIG. 12 (a), 1200 is a line synchronization signal 13
A counter that counts the pixel synchronization signal 1300 that is cleared in 01, and outputs a signal indicating the position in the main scanning direction to the comparator 1201.
Output to The switching point coordinate signal xi output from the RAM 1202 is input to the other input terminal of the comparator 1201, and when they match, the output of the comparator 1201 becomes L
Becomes As a result, the OR gate 1203 outputs the clock signal to the counter 1204, and the output of the counter 1204 advances by one.

As the address signal of the RAM 1202, the sum of the offset address signal Pj set by the control signal BUSo and the output of the counter 1204 is used. Accordingly, when the count position in the main scanning direction matches the switching point coordinates, the address signal of the RAM 1202 advances by one, and the switching point coordinate signal xi and the area number signal ai output from the RAM 1202 are updated. Further, by repeating this, the switching of the area in the main scanning direction is performed.

The counter 1204 has been cleared by the line synchronization signal 1301 input via the AND gate 1206. The offset address signal Pj is latched by a line synchronizing signal 1301 input via the AND gate 1207, and the system control unit 1503 sets the offset address set as the processing proceeds in the sub-scanning direction. The signal is changed at a predetermined timing to control switching in the sub-scanning direction.

The area number signal ai output from the RAM 1202 is input to the area processing register 1209.

The area processing register 1209 is a circuit for outputting an area signal pattern in each area, and a plurality of area signal patterns as shown in FIG. 12 (d) are set in advance for each area number by a control signal BUSo. When a pattern is selected by the above-mentioned area number signal ai, the set area signal pattern is output.

The area signal pattern output from the area processing register 1209 is input to the delay circuit 1210, where it is delayed by the same amount as the delay of the image signal in each image processing circuit. This allows the area signal to match the image signal delay
125 is output.

<Printer Unit> FIG. 17 (a) schematically shows the electrical components of the printer unit 1502.

In this printer unit, as shown in FIG. 17 (b), the laser light emitted from the LDs 1700-1, 2, 3, and 4 is scanned by the polygon mirror 1407 and the like on the same axis. There are two scanning directions on the surface. Therefore, as shown in FIG. 17 (c), the sensors 1701-1, 2, 3, and 4 also output signals at different timings in order to detect the writing start timing of the laser beam.

Referring to FIG. 17A, the image signals BKp, Mp, Yp, Cp output from the image processing unit 1501 and the image synchronization signal CLKp
Are input to the write processing circuits 1702-1, 2, 3, and 4. Since the write control circuits 1702-1, 2, 3, and 4 have the same configuration, only the write control circuit 1702-4 is shown in detail in FIG. 17 (a).

Focusing on the write control circuit 1702-4, the image signal Cp
The image synchronizing signal CLKp is input to a three-line buffer circuit 1703. Further, the synchronization signal generation circuit 1704 transmits an image synchronization signal used in the write control circuit 1702-4 to the sensor 17.
The three-line buffer circuit writes the image signal Cp sent from the image processing unit to the line memory based on the image synchronization signal CLKp, and outputs the signal from the synchronization signal generation circuit. The reading is performed according to the image synchronization signal to be read.

As described above, the read start timing of the image signal differs depending on the write control circuits 1702-1, 2, 3, and 4, and it is necessary to invert the read direction depending on the circuit. Therefore, the three-line buffer circuit has a memory for storing image signals for three lines, and FIG.
As shown in (1), control is performed so that the memory for writing and the memory for reading do not overlap.

The image signal output from the three-line buffer circuit 1703 is input to the pulse width modulation circuit 1705. The pulse width modulation circuit converts the input image signal into a pulse signal having a width corresponding to the signal value, and outputs the pulse signal to the LD drive circuit 1706.

The LD drive circuit 1706 determines the LD17 based on the input pulse signal and the control signal output from the power control circuit 1707.
00-4 is driven to make the LD emit laser light. Also, LD
Is output to the power control circuit, and the power control circuit controls the LD drive circuit so that the amount of laser light emitted from the LD becomes constant.

When the low-speed mode described above is selected, as shown in FIG. 17C, the transmission speed of the image signal and the like output by the image processing unit 1501 is reduced by half, but the reading speed from the line memory is reduced. Is constant and double reading is performed. However, the LD 1700-4 is driven once every two times under the control of the power control circuit 1707.

The line synchronization signal SY in the write control circuit 1702-4
The NCp is output to the image processing unit 1501 as a line synchronization signal representing the printer unit 1503.

The printer unit 1502 has a printer control circuit 1708 for controlling the entire unit.

The printer control circuit 1708 includes a CPU 1709, a ROM 1710, a RAM 171
1 is a micro computer system including a serial I / O circuit 1712, a parallel I / O circuit 1713, and the like for communicating with the system control unit 1503. Here, the parallel I / O circuit 1713 inputs various sensor signals such as the registration sensor 1714, and the write control circuits 1702-1, 2, 3, and 2.
4 is a circuit for outputting a setting signal to 4, inputting an abnormality detection result, outputting a signal for controlling the drive circuit 1719, and the like. The drive circuit 1719 includes a main motor 1715 for rotating and driving the photoconductor 1410 and the like, the transfer belt 1418 and the like, and a polygon motor 141 and the like.
4, paper feed clutch 1716, fixing heater 1717, high voltage power supply 1718
And a circuit for driving and controlling various loads. That is, the printer control circuit 1708 operates according to a program stored in the ROM 1710, and performs setting of each circuit and drive control of various loads in accordance with a command from the system control unit 1503 and various sensor signals.

For example, when a low-speed mode selection command is input by the system control unit 1503, the printer control circuit 1708
The low-speed mode is set in the write control circuit as shown in FIG. 17 (c) so that the output of the high voltage power supply 1718 which performs the rotational speed reading of the main motor 1715 and the constant current control is controlled to 1/2. The drive circuit 1719 is set at the same time.

<System and Operation Display Unit> FIG. 19 shows a schematic configuration example of the system control unit 1503 and the operation display unit 1504.

As shown in FIG. 19, the system control unit 1503
CPU1900, ROM1901, RAM1902, 1903 and 1904, timer 19
Starting with 05, scanning unit 1500, printer unit 15
02, a micro computer system including a serial I / O circuit 1906 for communicating with each control circuit of the operation display unit 1504 and the external device 1506, a parallel I / O circuit 1907, an interrupt controller 1909, etc. . Here, the parallel I / O circuit 1907 outputs the control signal BUSo for setting the image processing unit 1501 and the like, and outputs the image processing unit 1501
This is a circuit for capturing the detection result output from the
A part of the output signal is input to the decoder 1908, and the decoder 1908 outputs a selection signal 1603-1 for the RAM or the like in the image processing unit.
To n are output. Further, the line synchronization signal 1301 of the image processing unit is input to the interrupt controller 1909,
The system control unit 1503 manages the progress of the processing in the sub-scanning direction by this signal.

That is, the system control unit 1503 operates according to a program stored in the ROM 1901, and gives an instruction to the scanner unit 1500 and the printer unit 1502 and performs initial setting of the image processing unit 1501 in response to a request from the scanning display unit 1504. . During image processing, the progress of the processing in the sub-scanning direction is monitored, and the read start address of the processing circuit 102, the up / down control signal, the frame memory synchronization signal of the delay processing circuit 122, the area control The setting of the offset address signal and the like of the circuit 126 is changed as needed.

The RAMs 1904 and 1905 are battery-backed up and store the results of adjustments made on the operation display unit and past operation modes even after the power switch is turned off. In particular,
The RAM 1905 is a detachable IC card, and can register / call an operation mode and the like for each user.

An operation display unit 1504 includes a digitizer 1910 for inputting a predetermined range, position, and the like on a document, a touch panel display 1911 in which a display unit and an input unit are integrated, a numeric keypad 1912, a clear / stop key 1913, and an OHP mode key 191.
4. An operation display panel 1917 having an interrupt key 1915, a copy key 1916, etc., and an operation display control circuit 1918 for controlling the entire operation display unit.

Here, the operation display control circuit 1918 includes a CPU 1919 and a ROM 192.
0, starting with RAM 1921, serial I / O circuit 1922 for communicating with system control unit 1503 and digitizer 1910,
It is a micro computer system including a keyboard controller 1923 for detecting an input on the operation display panel 1917, a display controller 1924 for performing display control, and the like. The operation display control circuit 1918 operates according to a program stored in the ROM 1920, displays a message or the like on the display unit to prompt the user to set an operation mode or the like, and transmits the set result to the system control unit 1503. Etc. are sent.

<Description of Operation> FIG. 20 shows an example of a display screen of the touch panel display 1911.

When the power of the color copying machine is turned on, the operation display control circuit 1918 enters an initial state, and displays a standard screen as shown in FIG. "Photo", "Text",
The “standard” display portion is an area for selecting an image quality mode. When the operator presses this display portion, a photo mode suitable for a photo image, a character mode suitable for a character image, etc.
The standard mode for both photo and text images is selected.

For example, when the "character" display portion is pressed and detected by the operation display control circuit 1918, a screen in which the background of the "character" display portion is different as shown in FIG. The operator is notified of the recognition of the depression of the copy, and requests the system control unit 1503 to set the character mode.

When the “standard” or “photo” display area is pressed, the same display screen change and system control unit 1503
Make a request to

In response to this, the system control unit 1503 receives the circuit (coefficient selection register 415 of the first filter processing circuit 104-1, 2, 3 and the RAM 70 of the color correction circuit 110-1, 2, 3, 4) of the image processing unit 1501.
6, RAM 602 of the second γ conversion circuit 114-1, 2, 3, 4; F / F 1010, 1011, 1012, 1013, 101 of the second filter processing circuit 118-1, 2, 3, 4
4 etc., pattern selection register 1111 of multi-value dither processing circuit 120-1, 2, 3, 4; area processing register 1 of area control circuit 126
209 and RAM 1202) as necessary.

For example, when a request for the character mode is received, the setting of the coefficient selection register 415 of the first filter processing circuits 104-1, 2, and 3 is performed, and the edge-enhanced filter coefficients of the first filter processing circuits 104-1 and 104-3 are set to the first. 4 The filter coefficient for edge enhancement of the first filter processing circuit 104-2 is set to E0 at E1 shown in FIG. Generally, the MTF characteristics of color-separated image signals obtained by scanning a document or the like are not equal. Therefore, when the character mode is selected in the present color copying machine, filter coefficients E0, 1, 2, and 3 for edge enhancement as shown in FIG. 4B are appropriately selected for each image signal. As a result, even when a black thin line such as a black character is read, the levels of the image signals after the filter processing become uniform, and replacement with Bk toner is facilitated.

In addition, a full-color coefficient for character mode is converted to a color correction circuit.
110−1, 2, 3, 4
In the processing circuit 112, a process (the second expression) in which the UCA process is not performed is selected.

As shown in FIG. 7 (c), the data used to determine the coefficient for the character mode has a larger value of Bk in the achromatic color than the values of M, Y and C, and this and UCR
By the processing in the circuit, the color near the achromatic color is processed so as to be recorded only with Bk. The data for the character mode reproduces chromatic colors with higher saturation than the other modes, whereby color characters and the like are reproduced vividly.

Also, the filter coefficients selected for the character mode are set in the second filter processing circuits 118-1, 2, 3, and 4, respectively, and the pattern selection of the multi-value dither processing circuits 120-1, 2, 3, and 4 is performed. Data for the character mode dither pattern is set in the register 1111-1.

Further, the LUT data for each color corresponding to the character mode dither pattern is set in the RAM 602 of the second γ conversion circuits 114-1, 2, 3, and 4, respectively.

Further, the system control unit 1503 changes the contents of the area processing register 1209 and the RAM 1202 of the area control circuit 126 and copies the data so as to select the above-mentioned setting such as edge emphasizing the processing by the first filter processing circuit 104. During operation, the offset address signal Pj is applied to the area control circuit.
It outputs to 126 and controls so that the above-mentioned processing may be performed.

The same applies to the case where a request for the photograph mode or the standard mode is received, and the system control unit 1503 performs setting and control according to the mode.

For example, when the photograph mode or the standard mode is requested, the coefficient selection register 415 of the first filter processing circuit 104 is set so that the smoothing processing by the filter coefficient of S0 shown in FIG. 4B is performed. . By this smoothing process, moire generated when a halftone image or the like is read is removed, and a good copy is obtained. When the smoothing process is performed, the same filter coefficient is used in the present color copying machine because the influence of the difference in the MTF characteristics described above is reduced.

Further, in the RAM 706 of the color correction circuits 110-1, 2, 3, and 4, the coefficients obtained from the data shown in FIG. 7C are set according to the selected mode, and the UCR processing circuit 112 The process (the third formula) for performing the UCA process is selected.

As shown in FIG. 7 (c), in the data for the standard mode, the value of Bk in the achromatic color is equal to the values of M, Y and C. Processing is performed so that achromatic colors are recorded only with Bk.

On the other hand, in the data for the photograph mode, the recording amount of Bk is reduced, so that smooth gradation reproduction can be easily realized.

Also, the second γ conversion circuits 114-1, 2, 3, 4, the second filter processing circuits 118-1, 2, 3, 4 and the multi-value dither processing circuits 120-1, 2,
For 3 and 4, make settings according to each mode. The first
1 As shown in FIG. 1B, the present color copying machine has two types of standard mode dither patterns, but normally selects the standard 1 dither pattern.

As described above, in the present color copying machine, the data set in the image processing unit 1501 is changed according to the selected image quality mode so that the optimum image quality can be selected.

Further, in this color copying machine, the operator can select the filter coefficient set in the second filter circuit 118 and the LUT data set in the second γ conversion circuit 114 in each mode described above. Is the operation display panel 19
It becomes possible by pressing 17 image quality adjustment keys 1925.

That is, when the operation display control circuit 1918 detects the operation of the image quality adjustment key 1925, the operation display control circuit 1918 displays a screen as shown in FIG. 20 (c), a sharp / soft adjustment mode for adjusting the filter coefficient, and the LUT data. To select a color balance adjustment mode for adjusting the color balance.

When the sharp / soft adjustment mode is selected, the operation display control circuit 1918 displays a screen as shown in FIG. 20 (d) to enable selection of the filter coefficient of the second filter circuit 118 in each image quality mode. I do. As shown in FIG. 20 (d), in this color copying machine, it is possible to select 11 levels of filter coefficients for each image quality mode.
1918 transmits the selected result to the system control unit 1503, and the system control unit 1503 stores the result in the RAM 1903.

The correspondence between the filter coefficient shown in FIG. 10 (b) and this adjustment result is as shown in FIG. 10 (c). That is,
In the character mode, filter coefficients are selected mainly for smoothing, and in the standard mode, filter coefficients are selected mainly for edge enhancement. In the photo mode, a filter coefficient centering on the through is selected. As a result, in the character mode, moire generated by edge enhancement performed by the first filter processing circuit can be reduced.
Blur generated by the smoothing performed by the filter processing circuit can be corrected. Further, in the character mode and the standard mode, the filter coefficient on the edge emphasizing side for one stage is used only for Bk, whereby a thin line such as a black character is sharply copied.

When the color balance adjustment mode is selected, the operation display circuit 1918 displays a screen as shown in FIG. 20 (e) to enable selection of the LUT data of the second γ conversion circuit 114 in each image quality mode. I do. As shown in FIG.
The T data can be adjusted in 17 (−8 to 8) steps for each of the image quality mode and each color for each of shadow, middle, and highlight. The operation display control circuit 1918 compares the adjustment result with the system. Notify control unit 1503.

The system control unit 1503 stores this adjustment result in the RAM 190
3 and, if necessary, the RAM 60 of the second gamma conversion circuit.
Calculate the LUT data to be set to 2. That is, the ROM 1901 of the system control unit 1503 contains FIGS. 21 (a), (b),
2, 4, 6, and 8 LUT data for shadow adjustment, middle adjustment, and highlight adjustment as shown in (c) are stored in advance, and the LUT data is read out according to the adjustment result. Sign inversion, interpolation calculation, and the like are performed, and the LUT data to be set in the RAM is calculated by adding the LUT data for density adjustment as shown in FIG.

Here, referring to FIG. 20 again, the lower right part of the screen is an area for adjusting image density. Pressing the “dark” or “light” display portion makes the density of the recorded image darker or lighter, respectively. You can do it. That is, upon detecting the above-described operation, the operation display control circuit 1918 changes the display of the scale portion and transmits the result to the system control unit 1503. In response, the system control unit 1503 changes the selection of the density adjustment LUT data shown in FIG. 21D, recalculates the LUT data, and sets the LUT data in the RAM 602 of the second γ conversion circuit 114.

As described above, in the present color copying machine, the filter coefficient set in the second filter circuit 118 and the LUT data set in the second γ conversion circuit 114 in each mode can be selected. It is possible to copy.

〔The invention's effect〕

According to the first aspect of the present invention, the second filter means performs filter processing such as edge enhancement / smoothing / through depending on the type of image such as character / photo / standard. MT of image reading device
It is possible to perform processing for alleviating variations in the F characteristic and preventing problems such as coloring around black characters. Also,
It is possible to prevent moiré occurring between the image reading apparatus and the color correction processing and coloring of black characters caused by variations in MTF characteristics of the image reading apparatus. In addition, the image reading device
Coloring of black characters and the like due to the MTF characteristics can be prevented, whereby black characters and the like can be reproduced only with Bk toner.

[Brief description of the drawings]

1 is a block diagram of an image processing unit, FIG. 2 is a block diagram of a main scanning magnification unit, FIG. 1 (a) is a block diagram of each processing circuit, and FIG. FIG. 2C is an explanatory diagram showing the contents of the synchronization signal, FIG. 2C is an explanatory diagram showing the correspondence between the coefficient switching signal and the image signal, FIG. 2D is a block diagram of the scaling control circuit, and FIG. FIG. 3 is a diagram illustrating an interpolation calculation of image signal values at virtual sampling points after scaling, FIG. 3 shows a processing unit, and FIG. 3A is a block diagram of a processing circuit;
FIG. 2B is a block diagram of the memory control circuit, and FIG.
4 is a block diagram of the shadow area determination circuit, FIG. 4 shows a first filter processing unit, FIG. 4A is a block diagram of the first filter processing circuit, and FIG. 4B is an explanatory diagram showing the contents of filter coefficients. 5 shows an I / F section, FIG. 5A is a block diagram of an external I / F circuit, FIGS. 5B and 5C are timing charts of an image synchronizing signal, and FIG. 5A shows a block diagram of a first γ-conversion circuit, and FIG.
FIG. 7 shows a color correction / BP processing unit when data is written to M. FIG. 7 (a) is a block diagram of a color correction processing circuit, and FIG. 7 (b) is image signals R and G. , B. FIG. 8C is an explanatory diagram showing the relationship between chromatic and achromatic input image signals and their corresponding output image signals, and FIG. 8 is a diagram of the UCR processing circuit. FIG. 9 is a block diagram of a document size detection circuit, FIG. 9 (a) is a block diagram of a document size processing circuit, and FIG. 9 (b) is an explanatory diagram showing a state of document size detection, and FIG. 10 is a waveform diagram of the image synchronization signal and the line synchronization signal divided by 4, FIG. 10 shows a second filter processing unit, FIG. 10A is a block diagram of the second filter processing circuit, and FIG. FIG. 11C is an explanatory diagram showing the contents of each filter coefficient. FIG. 11C is an explanatory diagram showing the relationship between the filter coefficients and each mode. FIG. 1 shows a dither processing unit. FIG. 2A is a block diagram of a multi-valued dither processing circuit, and FIG.
FIG. 12 is an explanatory diagram showing the contents of a multivalued dither pattern, FIG. 12 shows an area processing section, FIG. 12 (a) is a block diagram of an area control circuit, and FIG. 12 (b) is an explanatory diagram showing a rectangular area; Figure (c)
Is an explanatory diagram showing the contents of memory data, FIG. 13 (d) is an explanatory diagram showing an area signal pattern for each area, FIG. 13 is a timing generator, and FIG. 13 (a) is a block diagram of a synchronous signal generating circuit. FIGS. 14 (b) and 14 (c) are timing charts of an image synchronizing signal, FIG. 14 is a block diagram of a digital color copying machine, FIG. 15 is a block diagram of the electrical unit, and FIG. 16 is a scanner unit. FIG. 17A is a block diagram of the electric unit, FIG. 17B is a block diagram of the filter, FIG. 17 is a printer unit, FIG. 17A is a block diagram of the electric unit, and FIG. Is an explanatory view showing a state of scanning by a polygon mirror, FIG. 18 (c) is a timing chart for starting writing of laser light, FIG. 18 is a delay processing section, and FIG. 18 (a) is a delay interval corresponding to the photosensitive drum. FIG. 4B is a block diagram of a delay processing circuit. Click view and FIG. (C) of RAM
(D) is a block diagram of a memory control circuit, (e) is an explanatory diagram of an effective image start position and an effective image width, and (f) is a connection diagram of a RAM block. (G) is an explanatory diagram of the operation, FIG. (H) is an explanatory diagram showing a line synchronization signal and its divided-by-2 waveform, FIG. 19 is a block diagram of a system control / operation display unit, and FIGS. b),
(C), (d) and (e) are explanatory diagrams showing examples of display screens of the touch panel display, and FIGS. 21 (a), (b),
(C), (d) is an explanatory view of LUT data in ROM. 104 filter processing means, 111, 112 color correction processing means, 1501 image processing apparatus, 1917 input means.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/46-1/64

Claims (1)

(57) [Claims] An image reading apparatus for scanning a document and outputting image signals separated into red, green, and blue, an image processing apparatus for processing an image signal output by the image reading apparatus, and an image processing apparatus In a color image forming apparatus having an image recording device that records an image based on an image signal output from a processing device, first filter means capable of setting an independent filter coefficient for each color-separated image signal, Color correction processing means for performing color correction processing on the image signal subjected to spatial filtering by the first filter means and outputting an image signal for cyan, magenta, yellow, and black color separation recording; After being converted to cyan, magenta, yellow, and black image signals by the correction processing means, the filter coefficients of the filter processing are changed by a plurality of processing modes to thereby obtain a previous image signal. Second filter means for performing filter processing suitable for each processing mode, wherein the plurality of processing modes include a processing mode for a character image, and a filter coefficient when a processing mode for a character image is selected. A color image forming apparatus which performs edge enhancement and uses different filter coefficients for each image signal.