JPH05137011A - Image processor - Google Patents

Abstract

PURPOSE:To decrease or prevent the color deciding mistakes when the colors are decided out of the input image information including two adding or more colors and the image information is outputted with a prescribed pattern. CONSTITUTION:A deciding means (color recognizing part 109) is provide to an image processor to decide the colors out of the input image information including at least two or more colors together with a pattern adding means (decoration circuit 1-14) which adds the pattern information to the input image information. In such a constitution, the image processor decides the input image information by the deciding means after smoothing the information in a smoothing part 108 and corrects the deciding result by majority through a majority part 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as FAX, digital copying machine, digital image scanner and the like.

[0002]

2. Description of the Related Art Conventionally, for example, in a digital copying machine, an original is illuminated with a halogen lamp or the like, and the reflected light is photoelectrically converted by using a charge-coupled device such as a CCD, then converted into a digital signal, and a predetermined process is performed. After going, laser printer,
Images are formed using recording devices such as liquid crystal printers, thermal printers, and inkjet printers.

By the way, in such a digital copying apparatus,
After performing color recognition using a color recognition circuit that recognizes specific color information of the input image from the input image information, perform image processing such as replacing with a different pattern for each color using the information,
Functions such as forming an image in a recording device have been proposed.

[0004]

However, for example, a color original represented by halftone printing has a different screen angle for each color, so it is assumed that the color original is 400 dpi (d).
When read with (ot / inch), color separation is completely performed in printing with a line number of about 175 lines. Therefore, taking a green printed matter as an example, it is composed of dots of cyan ink and yellow ink, and if the color is judged as it is, all three colors of cyan, yellow, and green are recognized, which is an erroneous recognition. Become. If these three colors are replaced as they are with different patterns and monochrome output is performed, it becomes very difficult to see.

The present invention has been made in view of the above circumstances, and an object thereof is to prevent misjudgment at the time of color discrimination.

[0006]

In order to solve the above-mentioned problems, the image processing apparatus of the present invention inputs the pattern information and the judging means for judging the color of the input image from the input image information of at least two colors. An image processing apparatus having pattern addition means for adding to image information, wherein the input image information is subjected to smoothing processing, then the determination means makes a determination, and the determination result is subjected to a majority correction process. Is characterized by.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 48 is a sectional view for explaining the construction of a copying machine showing an embodiment of the present invention.

In the figure, reference numeral 1 is a document feeder which serves as a document feeding means, and feeds the placed documents one by one or two in succession to a predetermined position on the platen glass surface 2. Reference numeral 3 denotes a scanner including a lamp, a scanning mirror 5 and the like. When the original feeding device 1 places the original on the glass surface 2 of the original, the scanner is reciprocally scanned in a predetermined direction to scan the reflected light of the original with the scanning mirrors 5. An image is formed on the image sensor unit 101 through the lens 8 via 7. Reference numeral 10 denotes an exposure control unit including a laser scanner, which irradiates the photoconductor 11 with a light beam modulated based on image data output from the image signal control unit of the controller unit CONT. 12 and 13 are developing devices,
The electrostatic latent image formed on the photoconductor 11 is visualized with a developer (toner) of a predetermined color. 14 and 15 are transfer paper stacking units,
A recording medium of a fixed size is stacked and stored, and is driven to the position where the registration rollers are provided by driving the feeding roller, and the photoconductor 1
The sheet is re-fed at the timing of aligning the leading edge of the image with the image formed in No. 1.

Reference numeral 16 denotes a transfer separation charger, which transfers the toner image developed on the photoconductor 11 to the transfer paper and then the photoconductor 11
It is further separated and fixed by the fixing unit 17 via the conveyor belt. A paper discharge roller 18 stacks and discharges the transferred paper on which the image has been formed on the tray 20. Reference numeral 19 is a direction flapper for switching the carrying direction of the transfer-receiving paper on which image formation has been completed to the paper discharge port and the internal carrying path direction to prepare for the multiplex / double-sided image forming process.

Image formation on a recording medium will be described below.

The image signal input to the image sensor unit 9, that is, the input signal from the reader 22 described later is C
Processing is performed by the image signal control circuit 23 controlled by the PU 25, and reaches the printer control unit 24. The signal input to the printer control unit 24 is converted into an optical signal by the exposure control unit 10 and irradiates the photoconductor 11 according to the image signal.
The latent image formed on the photoconductor 11 by the irradiation light is developed by the developing device 12 or the developing device 13. The transfer sheet is conveyed from the transfer sheet stacking unit 14 or the transfer sheet stacking unit 15 at the latent image timing, and the developed image is transferred to the transfer unit 16. The transferred image is fixed on the transfer target paper by the fixing unit 17, and then the paper output unit 1
8 is discharged to the outside of the apparatus.

During double-sided recording, after the non-transfer paper has passed the paper discharge sensor 19, the paper discharge roller 18 is rotated in the direction opposite to the paper discharge direction. At the same time, the flapper 20 is raised upward to store the copied transfer paper in the intermediate tray 24 via the transport paths 22 and 23. At the time of next back surface recording, the transfer paper stored in the intermediate tray 24 is fed and the back surface is transferred.

During the multiplex recording, the flapper 21 is moved upward to store the copied transfer paper in the intermediate tray 24 via the conveying paths 22 and 23. The transfer paper stored in the intermediate tray 24 is fed in the next multiplex recording,
Multiple transcription is performed.

FIG. 42 is a diagram showing an operating unit for making various settings such as editing and copying in the copying machine of this embodiment. First, the functions and the like of various keys on the operation panel will be described.

In FIG. 42, reference numeral 5001 is a power switch for controlling energization to the image forming apparatus. 5002
Operates as a key to return to the standard mode during standby with the reset key. Reference numeral 5003 is a copy start key. A clear key 5004 is used when clearing a numerical value. An ID key 5005 enables a copying operation for a specific operator by the ID key 5005, and the copying operation can be prohibited for an operator other than the above unless an ID is input by the ID key. It will be possible. A reference numeral 5006 is a stop key, which is used when the copying is interrupted or stopped. 5
Reference numeral 007 denotes a guide key, which is used when it is desired to know each function. An up cursor key 5008 is a key for moving the pointer up on each function setting screen. Reference numeral 5009 is a down cursor key, which is a key for moving the pointer downward on each function setting screen. A right cursor key 5010 is a key for moving the pointer to the right on each function setting screen. A left cursor key 5011 is a key for moving the pointer to the left on each function setting screen.
Reference numeral 5012 denotes an OK key, which is pressed on the respective function setting screens if this is acceptable. A 5013 presses this key when executing what is output at the lower right of the screen of 5052 on each function setting screen. 5014 is
This is the standard size reduction key and is used when reducing one standard size to another standard size. Reference numeral 5015 is used when selecting the same size copy. Reference numeral 5016 denotes a standard size enlargement key, which is used when expanding a standard size to another standard size. A cassette selection key 5017 is used to select a cassette stage to be copied. A copy density adjustment key 5018 reduces the density. An AE key 5019 automatically adjusts the copy density with respect to the density of the original. A copy density adjustment key 5020 is used to increase the density. Reference numeral 5021 denotes a sorter key, which is a key for designating the operation of the sorter. 5022 is a preheat key,
Used to turn on / off the preheat mode. Reference numeral 5023 is an interrupt key, which is pressed when interrupting during copying and copying is desired. Reference numeral 5024 is a ten-key pad, which is used when inputting a numerical value. A marker processing key 5025 sets trimming, masking, and partial processing (contour, mesh, shadow, negative / positive). Reference numeral 5026 is a patterning key for patternizing and expressing colors,
It is used when expressing colors with density differences. 5027
Is a color erasing key, and is used when it is desired to erase a specific color by the processing described later. An image quality key 5028 is used to set the image quality. Reference numeral 5029 is a negative / positive key, which is used when performing negative / positive. 5030
Is an image create key, and is pressed to perform contouring, shadowing processing, halftone processing, italics, mirror image, and image repeat. A trimming key 5031 is used when the area is designated and trimming is performed. 5032
Is a masking key, which is used to specify an area and perform masking. Reference numeral 5033 denotes a partial processing key for designating an area and then performing partial processing (contour, mesh,
Shadow, negative / positive, etc.). A frame erasing key 5034 is used when erasing the frame according to the mode.
The modes are: sheet frame erase (creates a frame for the sheet size), document frame erase (creates a frame according to the document size. The document size is specified.), Book frame erase (matches the book spread size. To create a blank in the frame and center. There is a book spread size specified.) A binding margin key 5035 is used when a binding margin is to be created at one end of the paper. Reference numeral 5036 denotes a move key, which is used when the user wants to move. The movement includes parallel movement (up and down, left and right), center movement, corner movement, and designated movement (point movement). A zoom key 5037 can be used to set the copy magnification from 25% to 400% in 1% increments.
Further, main scanning and sub scanning can be set independently. 5038 is
Auto scaling key that automatically enlarges or reduces according to the size of the copying machine. Further, the main scanning and the sub-scanning can be automatically scaled independently. Reference numeral 5039 denotes an enlarged continuous shooting key, which is used when an original is enlarged to a plurality of sheets and copied. 5040
Is a reduction layout key, which is used when enlarging or reducing two originals to make one copy. It is also used when enlarging / reducing four originals for copying. 5043
Is a continuous shooting key, which is used when the copying area on the platen glass surface is divided into left and right and automatic copying is performed (continuous copying of two pages). Fifty
Reference numeral 44 denotes a double-sided key, which is used when it is desired to output both sides (single-sided double-sided, page continuous shooting both-sided, both-sided both-sided). 5
Reference numeral 045 denotes a multiplex key, which is used when multiplexing is desired (multiplexing, page continuous shooting multiplex). Reference numeral 5046 is an MC key, which is used when using a memory card. 5
Reference numeral 047 denotes a projector key, which is used when using the projector. Reference numeral 5048 is a printer key, which is used when setting at the time of printing.
Reference numeral 5050 denotes a document mixed loading key, which is used when the document sizes are mixed when a copy is made using the feeder. Reference numeral 5051 denotes a mode memory key, which is used to call the registered copy mode in order to register the copy mode for which copying is set. A display screen 5052 displays the status of the apparatus, the number of copies, the copy magnification, and the copy paper size, and displays the set contents during the copy mode setting.

Next, the overall block configuration of the image processing apparatus of the present invention will be described with reference to FIG.

While exposing the original with an exposure lamp (not shown), the lamp is moved in the direction perpendicular to the lamp (subscanning) and the reflected light is imaged by a color (R, G, B) CCD image sensor, and the obtained analog is obtained. A / D image signal
An image signal is obtained by digitizing with a converter or the like, then processing and processing the image signal, and outputting it to a thermal transfer printer, an inkjet printer, a laser beam printer or the like not shown.

(Reading optical system) A document is first irradiated with an exposure lamp (not shown), and the reflected light is read as an image signal whose color is separated by a CCD image sensor 101 and amplified by an amplifier circuit 103 to a predetermined level. Where C
The CD image sensor 101 is driven by a CCD driver 102. FIG. 2 shows a 3-line solid-state image sensor used in this embodiment.

FIG. 2 shows a 3-line solid-state image pickup device used in this embodiment. In FIG. 2, 201 is
Base of solid-state image sensor. Reference numerals 202, 203, and 204 denote solid-state image pickup element arrays corresponding to the respective colors, and solid-state image pickup elements as indicated by 207 are arranged in an array. 20
Reference numerals 5 and 206 denote the intervals of the 3-line array.
The 3-line sensor interval corresponding to the three primary colors of R, G, and B is
Determined according to the angle of view. FIG. 3 shows an optical system of a color image reading apparatus using the solid-state image sensor shown in FIG. The image information on the document surface 301 is line-scanned (sub-scan section in the drawing) by a mirror (not shown) arranged between the document surface 301 and the imaging optical system 302, and the three-color separation is performed via the imaging optical system 302. After being separated into light fluxes of three colors in color image reading by the blazed diffraction grating for use 303, they are imaged on the corresponding line sensors 304. here,
The one-dimensional blazed diffraction grating for three-color separation will be outlined with reference to FIG. The one-dimensional blazed diffraction grating for three-color separation has a structure in which stepwise gratings are periodically repeated in the color separation direction. For example, the periodic pitch P = 60 um, the grating thickness d1 = d2 = 3100 um, and the medium refractive index n = 1. In the case of 5, the incident light is transmitted and diffracted and separated into three directions as shown in the figure. Although a diffraction grating is used for color separation here, a spectroscope such as a dichroic mirror or a prism may be used as long as it can be separated into color components.

FIG. 5 is a timing chart showing an example of the timing of drive pulses of the CCD image sensor shown in FIG. These drive pulses are generated by the CCD driver 102, and FIG. 6 shows the CCD driver 102.
It is a figure which shows the structure of.

All are generated by a clock output from one oscillation source and a divided clock generated in synchronization with each other with reference to the input sync signal.
The drive pulse group given to the CD sensor is given to the CCD sensor as a synchronized signal without any jitter. The color image signal photoelectrically converted by the CCD 101 is
The amplifier 103 independently amplifies to a predetermined voltage value for each color. The amplification level of the amplifier for each color is given to each amplifier as a voltage level by cpu (not shown).

Each color image signal amplified to a predetermined level is
A sample and hold circuit (S / H) 104 samples and holds a predetermined signal level. The sampled and held analog color image signal is sent to the A / D converter 105.
In the conversion from analog signal to digital signal,
It is sent to the black correction / white correction circuit 106.

(Black Correction / White Correction Section) FIG. 7 shows the circuit configuration of the black correction / white correction circuit 106.

As shown in FIG. 8, when the amount of light input to the sensor is small, the black level output is higher than the original output level in the dark part due to variations between pixels and flare. Therefore, if the image is read as it is, it will be read bright as a whole. In this apparatus, the CCD output level when the halogen lamp for illuminating the original is turned on is set in the A / D converter 10 with nothing on the original table.
Before 5, the offset is adjusted so that the average value is about 04H (when reading 8 bits), and the sum of the dark output level from the CCD with the halogen lamp turned off for each copying operation is copied. Subtracted from the signal of time. That is, in FIG. 7, prior to the normal copying operation, the halogen lamp for illuminating the original is turned off at the home position, and the data at that time is loaded into the RAM 706. Naturally, during this operation, 0 is set in the register 701 and the subtractor 702 is in the through state. Video data is sent through the selector 703 and the buffer 704,
It is input to the RAM 706. As for the address of the RAM 706, the output of the address counter 708 loaded by HSYNC is selected by the selector 707,
It is input to the address of 06. After the data is input to the RAM 706, the CPU (not shown) causes the register 7
A predetermined value is latched in 12, and the RAM 706 can access the CPU. The CPU performs black correction by setting a value obtained by adding the above-mentioned flare level Φ4H to the minimum value of the video signal written in the RAM 706 as black correction data, setting it in the register 701 and subtracting a predetermined value from the read video signal.

Next, white level correction (shading correction) will be described. The white level correction corrects the variations in the sensitivity of the illumination system, the optical system, and the sensor based on the white data that is obtained by moving the document scanning unit to a uniform white plate position and irradiating it. A specific operation will be described with reference to FIG. Prior to the copying operation or the reading operation, the halogen lamp for illuminating the original is turned on and one line of black image data having a uniform white level is stored in the RAM 706. The specific operation is the same as the operation described in the black correction, and thus the description thereof is omitted. Assuming that the first white plate data stored in the RAM 706 is Wi, the data is used in 8 bits in this apparatus, so that the correction such that the white plate becomes FFH is necessary.

That is, for the read value Di of the normal image of the first pixel, the corrected data Do = Di × FFH
/ Wi should be. Therefore, the CPU (not shown)
The values stored in the RAM 706 are subjected to the same arithmetic processing as that of FFH / Wi to sequentially replace the data. In the normal copying operation, the correction data accessed by the address counter 708 in the RAM 706 is passed through the buffer 705, multiplied by the signal after black correction is performed by the multiplier 709, and output. That is, the calculation of Do = Di × FFH / Wi is performed on the first pixel.
As described above, the black level and white level are corrected according to various factors such as the dark current variation of the image input system, the CCD dark current variation, the sensor sensitivity variation, the optical system light amount variation, and the white level sensitivity, and the main scanning is performed. Image data that is uniformly corrected for each color can be obtained for each color in all directions.
FIG. 9 shows a flowchart of the procedure of white correction.

(Luminance Signal Generation Unit) The white-corrected / black-corrected video signals of the respective colors are input to the luminance signal generation unit 107 which is to generate the monochromatic image data next. The luminance signal generator 107 will be described with reference to FIG.

The input R _in 1001, G _in 1002,
Each image signal of B _in 1003 is input to the adder 1004 and the addition of each color data is performed. The data added by the adder 1004 is then divided by a divider 1005 into 1/3. That is, the following calculation is performed.

D _out = 1/3 (R _in + G _in + B _in )

In the present embodiment, no weight is assigned to each color, but weighting can be performed if necessary.

(Smoothing Unit) Next, the smoothing unit 108 will be described. The smoothing unit 108 and the majority decision unit 110
This is a process for preventing an erroneous determination that occurs in a printed matter such as a halftone dot when performing the color recognition process described later. Taking the R (red) signal as an example, the smoothing circuit operation will be described with reference to FIG. The input R signal is stored in the FiFo memory 1100,
At 1101, each line is delayed by one line. The output signals 1107 and 1108 from the respective FiFo memories and the signal 1106 before being delayed are added by the adder 1102. The added output signals are delayed by a predetermined number of pixels in the flip-flop group 1103, and the output signals from the respective flip-flops are added in the adder 1104 and then divided in the divider 1105 to be output. Similarly, the G signal and the B signal are subjected to smoothing processing for a total of 15 pixels on 3 lines for 3 pixels on each line and output.

(Color Recognition Unit) The output from the smoothing unit 108 is input to the color recognition unit 109. The color recognition unit 109 is a block for detecting a color that has been recognized in advance from input image information. The color determination process used in this embodiment is
The judgment is made by detecting the hue of the color. FIG.
The configuration of the color determination processing unit will be described using.

The input color signals are input to the maximum / minimum value detecting section 1301 and the three comparators 1300a and 13300.
00b and 1300c. The comparator has
R _IN and G _IN are input to G _IN and B _IN , and B _IN and R _IN are input to R _IN and G _IN , respectively. The respective determination results are input to the maximum value / minimum value detection unit 1301 and the upper address of the hue ROM 1306. Here, the maximum value / minimum value detection unit 1301
It is composed of a decoder and a selector, and is configured to decode the output signals from the comparators 1300a, 1300b and 1300c and select the maximum value, the intermediate value and the minimum value with the selector. The output minimum value is then input to the subtracters 1302 and 1303. A maximum value and a value between the maximum value and the minimum value are input to each subtractor, and the minimum value is subtracted from each value. This is MIN (R _IN , G _IN ,
This is because G _IN ) is an achromatic color component and was not necessary for color determination. MAX _IN ′ and MIN which are subtraction results
_IN 'and the comparator result indicating the order of magnitude are input to the address of the hue ROM 1306 composed of ROM. Here, FIG. 12 shows the relationship between the hue plane and the order of magnitude of color. The hue ROM 1306 stores in advance a value corresponding to the hue angle. In this embodiment, 0-2
Values up to 39 are stored and calculated by the arithmetic expression shown below.

Θ = atan (MIN _IN / MAX _IN ) / π That is, in this embodiment, the hue angle of 360 ° is divided into 240, and this is used as the hue angle. Hue ROM1
The hue angle output from 306 is input to the window comparator 1304. The input hue value is determined by the window comparator 1304 to be a color to be detected. The number of judgment colors in this embodiment is 7, but it goes without saying that the number of detection colors increases by increasing the number of window comparators. In the window comparator 1304, the comparators 1304b and 1304c are respectively connected to the registers 1304a and 1304d, and the lower and upper limits of the hue value to be detected are set by the CPU (not shown). The outputs of these window comparators pass the AND gate 1304e and output hit signals. An output signal obtained by encoding the output signal from each window comparator by the encoder 1305 is output as a color determination signal as shown in Table 1.

[0035]

[Table 1] Further, the max-min data from the subtractor 1302 is input to the binarization unit 1307. Here, binarization is performed by a predetermined threshold value α set in the register 1308 by the CPU bus, and an achromatic signal that becomes “1” when max-min <α and color detection by inverting the achromatic signal. The signal is output. The achromatic color signal and the color detection signal are
It is used by the contour generation unit 113 described later.

(Majority Decision Circuit) Next, the judgment color code signal from the color recognition section 109 is input to the majority decision circuit 110. In the majority decision circuit, erroneous determinations such as those caused by the halftone dot printing and the like are eliminated in the present embodiment by performing a majority decision on peripheral pixels of 15 pixels of 3 lines × 5 pixels, thereby eliminating erroneous determinations of isolated points and the like. ing.

FIG. 14 shows the majority circuit used in this embodiment, and its operation will be described with reference to FIG.

The encoded judgment color code signal is output to the decoder 1402a and the FiFo (first-in,
First-out) After being delayed by one line and two lines via the memories 1401a and 1401b, the colors of the pixels input to the decoders 1402b and 1402c are divided into 0 to 7 and the total for each color code is calculated. Is calculated. The decoded 0 is the total calculation unit 1400a, 1 is 1400b, and 7 is 1400 in sequence.
Enter in h. Since the internal circuits from the total calculation units 1400a to 1400h are the same, the total calculation unit 1400a
Will be described only. Decoders 1402a to 140
In 2c, the bit of the input code value is 1, and the other is 0. The signals decoded by each of the decoders 1402a to 1402c to 0 are input to the total calculation unit 1400a, delayed by one clock in the flip-flop 1403, and then added in three pixels in the adder 1404. The output from the adder 1404 is output from the flip-flop 1405 from one clock to four.
There is a delay to the clock. That is, the sub-scanning direction 3
The sum of lines is calculated and delayed by the flip-flop 1405 in the main scanning direction to form a matrix of 3 lines × 5 pixels. Flip-flops 1403, 1405
Output signals from the adders 1406a, 1406b, 1
The sum is calculated in 407, and the total sum is calculated. The calculated 4-bit output signals 1408a to 1408h indicate the sum total of each code signal existing within a total of 15 pixels of 3 × 5. Sum code 1408a-1 for each color
408h is then input to the comparator shown in FIG. The configuration of the comparators 1501 to 1504 is shown in FIG.
The same as the configuration of the large / small / medium / small determination unit of the color recognition circuit 109 of 3
It is composed of one comparator, a selector, and a gate circuit that encodes the output of the comparator, and outputs the maximum value of three input signals. A detailed description of the comparators 1501 to 1504 will be omitted. The maximum value of the input 1408a to 1408c is output from the comparator 1501, and the comparator 15
It is input to 04. Similarly, input signals 1408d to 140
The maximum value of 8f is the input signal 1 from the comparator 1502.
The maximum value of 408g and 1408h is the comparator 1503.
Are output respectively and input to the comparator 1504. The signal of the maximum value among them is output from the comparator 1504. Input signals 1408d to 1408h and color code signals 1505a to 1505h corresponding to the respective signals of 3 bits are also input to the comparators 1501 to 1503.
In addition to the total sum value of 4 bits, the output of 3 is the color code signal 3bi.
A total of 7 bits of t are output. That is, comparator 1
From 504, the maximum sum value and its color code are output.

(Magnification Change, Mirror Image, Repeat, Italic Circuit) Next, the magnification change, mirror image, repeat, italic circuit will be described with reference to FIG.

Here, basically, two RAMs are used to form a double buffer. That is, while writing to the RAM1 shown in FIG. 23, reading from the RAM2 is performed. These processes are realized by the address control of the RAM at the time of reading.

The input video signal is input to the switching devices 2800a and 2800b. In the present embodiment, the output control signal using the buffer with output control is made by the flip-flop 2801, and as shown in FIG.
Is configured to toggle.

<During Writing> The video signals output from the respective buffers are input to the RAM1 and RAM2, respectively, and the writing is controlled by the write control pulses from the OR gates 2809 and 2810. OR gate 280
In Nos. 9 and 2810, the write pulse generated by the write pulse generator described later is applied to the RAM only while the buffers are enabled.
That is, the OR gates 2809 and 2810 also naturally output the write pulse by the toggle. Next, the RAM address signal is generated by the address counter 2802. The address counter 2802 is composed of an up counter, is cleared by the sync signal and has an output of 0, and the output is incremented in synchronization with the input of the clock. Light counter 28
02 output signals are selectors 2806 and 2807.
Entered in. Here, the write operation to the RAM 1 will be described as an example. Q of flip-flop 2801 at this time
The output becomes Lo, and the image signal is output from the buffer 2800a. The write signal is output from the OR gate 2809 and not output from 2810. Also, the select signal from the selector 2806 is
Since it is Lo, A input, that is, the light counter 280
The output signal from 2 is selected and supplied to the address input of RAM 1. Such an operation is performed in RAM1 and RAM2.

<At the time of reading> Next, the reading operation from the RAM 1 will be described as an example. Flip-flop 2 at this time
The Q output of 801 becomes Hi, and the output from the buffer 2800a becomes a high impedance state. As for the write signal, the output of the OR gate 2809 becomes Hi because the Q output of the flip-flop 2801 becomes Hi. Further, since the select signal is Hi from the selector 2806, the B input, that is, the output signal from the read counter 2803 is selected and supplied to the address input of the RAM 1. The read counter 2803 loads the value set by the cpu (not shown) into the register 2805 by the sync signal. This set value is the R of the effective image.
The address address written in the AM is set. After loading the value from the register 2805, it operates under the control of the AREA signal which is an enable signal of the read counter 2803. The AREA signal is generated by the area signal generator 116 shown in FIG. Although a detailed description of the area signal generator is omitted, this area signal is a signal that determines the image output area on the output paper. That is, when the output image is shifted on the paper, it is controlled by this signal. Also, the read counter 2803 is an up / down counter and is the register 2805.
It is controlled by the signal set to. Usually Hi
It is set to and operates as an up counter.
The output of the read counter controlled in this way is input to the B input of the selector 2806, and the select signal is Hi.
Therefore, the output signal from the read counter is RAM
It is output to the address input of 1. The read operation from the RAM 2 is also the same, so the description thereof is omitted. The output signals from the RAMs 2811 and 2812 are input to the selector 2813, and the output signals from the RAM are selected and sent to the subsequent stage.

(Variable magnification) It is realized by changing the moving speed of an optical unit such as an exposure lamp in the sub-scanning direction, and this processing block is executed only in the main-scanning direction.

1. Enlargement Enlargement processing is usually realized by writing to the RAM and slowly reading at the time of reading. This is realized by thinning out the clock by a rate multiplier (not shown) and giving it as the clock of the read counter 2803.

2. When performing reduction processing, contrary to the case of enlargement, by thinning out the video write signal at the time of writing to the RAM and the clock signal to the write counter 2802, the data is written to each RAM randomly, It is realized by reading it.

(Mirror image) When the mirror image processing is performed, the write operation to the RAM is normally performed and the read counter 2
The up / down control signal of 803 becomes Lo, and the counter is down-counted. Also, the load value is
The last pixel of the image area is set in the address value image register 2805 written in the RAM. That is, it is realized by writing the data in the RAM while incrementing the address and reading the data while decrementing the address.

(Repeat) When the repeat operation is performed, the write operation to the RAM is normally performed, and the Repeat signal is input to the AND gate as shown in FIG. 25 to load the read counter 2803, whereby the repeat operation is realized. Has been done.

(Italic) When performing italic, R
This is realized by performing a write operation to AM and shifting the AREA signal for each line. That is, the italic image is obtained by shifting the enable of the count operation of the read counter for each line.

(Cpu access) Next, the RAM 2 of the double buffer is constructed so that it can be accessed by cpu.

At the time of access by cpu, a Hi signal is set by cpu in a latch (not shown). This signal is connected to the select signal of the selector 2808 and the enable signal of the bidirectional buffer 2814 in FIG. 23, and the selector 2808 outputs the B input. Further, since the output from the OR gate 2815 becomes Hi in the buffer 2800b, the output is in a high impedance state, the bidirectional buffer 2814 connected to the cpu data bus is enabled, and when the cpu accesses the RAM, the read is performed. The direction of the bidirectional buffer is switched by the / write signal.

Access by cpu is performed by AE (auto
When performing exposure, the signal of the document image is sampled. Since it is not directly related to the present invention,
The description is omitted here.

(Filter Circuit) Next, the filter circuit 1
12 will be described with reference to FIG.

The output signal from the scaling circuit 111 is FiF
The signals for three lines are input to the secondary differentiation circuit and the primary differentiation circuit via the memories 1701 and 1702. Here, M due to the spatial frequency characteristic of the lens when reading the image
The level down of the high frequency component such as a thin line caused by the decrease of TF is corrected by the first derivative, and the line width is corrected by using the second derivative signal. That is, the processing as shown in FIG. 17 is performed.

In the secondary differentiating circuit 1703, a general Laplacian filter calculation using a 3 × 3 matrix is performed and an edge-enhanced signal is output. Next, in the primary differentiating circuit, the difference between the three-pixel total values in the main scanning direction and the difference between the three-pixel total values in the sub-scanning direction are calculated in matrices 1704 and 1705, respectively, and the absolute value is output. .. The output value is then added to the adder 170.
The value of the register 1708 that is added in 6 and then set by the cpu (not shown) is multiplied by the multiplier 1707, and then the edge-emphasized image signal is added by the adder 1709 and output.

(Contour signal generation unit) Contour signal generation unit 113
In, a signal for forming a contour inside the color area is generated at the boundary between the color area and the white area. FIG. 26 is a circuit block diagram of contour signal generation.

First, the brightness signal output from the brightness signal generation circuit 107 is binarized by the comparator 6801. Two
The slice level of the binarization is set by the register 68 by the CPU.
It is set to 02. Binary signal is AND gate 6
At 803, it is ANDed with the achromatic signal generated from the binarization unit 1307 of FIG. That is, the AND gate 6803 outputs 1 when the color is achromatic and has a predetermined density, and 0 otherwise.

Next, the output signal of the AND gate 6803 and the color detection signal generated from the binarizing unit 1307 of FIG.
It is ORed by the OR gate 6804. As a result, 0 is output for an achromatic color having a low density, and 1 is output for other colors. The output of the OR gate 6804 is input to a 7 × 7 pixel AND circuit, a 5 × 5 pixel AND circuit, a 3 × 3 AND circuit, and a 1 × 1 AND circuit 6807 after delaying a predetermined line by a line memory 6805, and a predetermined pixel thinning is performed. The signal is EXOR
The outputs of the AND circuit 6807 are compared by the gates 6809 to 6811. At this time, for example, if the 3 × 3 AND circuit outputs 1 and the 5 × 5 AND circuit outputs 0, EX
The OR gate 6810 outputs 1 to determine that it is the second pixel from the contour. Next, the color detection signal is delayed by a predetermined line in the line memory 6806 and the delay unit 6808 is used.
AND gates 6812 to 6 after being delayed by a predetermined number of pixels at
It is determined whether the contour signal input to 814 and detected is a chromatic color, and the color contour signals K1 to K3 are output. That is, K1 is 1 at the first pixel and K2 is at the second pixel and K3 is at the third pixel in the color region from the contour.

Next, a signal for providing a white outline between the black character and the pattern is generated.

FIG. 19 is a block diagram of a circuit for generating a white outline signal.

First, the brightness signal output from the brightness signal generation circuit 107 is binarized by the comparator 270. An example of this output is shown in FIG. The binarized slice level is set in the register 271 by a cpu (not shown). The binarized signal is then ANDed by the AND gate 287 with the achromatic signal generated from the binarization unit 1307 of FIG. That is, the AND gate outputs 1 when the color is achromatic and has a predetermined density, and 0 otherwise. The output signal is delayed by a predetermined line in the line memory 272, and is input to an or circuit 273 that performs or processing of 7 × 7 pixels. The signal expanded by a predetermined pixel in the OR circuit 273 and the target pixel signal delayed by a predetermined pixel in the delay circuit 274 are subjected to exclusive OR in the exor circuit 275 to obtain an image having an achromatic density. A contour signal indicating the contour portion is output. Next, the output signal of the AND gate 287 and the color detection signal generated from the binarization unit 1307 in FIG.
After being or-processed in the r circuit 277 and being delayed by a predetermined line in the line memory 278, a 7 × 7 pixel and circuit and 5
The signal is input to the × 5 pixel and circuit 279 to obtain a signal thinned by a predetermined pixel. Further, after the color detection signal is delayed by a predetermined line in the line memory 284 and delayed by a predetermined pixel in the delay circuit 285, the exor circuit 282 outputs 5 × 5 pixels an
The output signal from the d circuit is input, and the signal shown in FIG. 21 is output. The output signals from the exor gates 275 and 282 are input to the and gate 276 to obtain the color-internal black character contour signal. This signal is transmitted to the decorative circuit section 114.
22 and a white outline is added to the read image around the black characters in the pattern shown in FIG.

(Image decoration circuit) <Color contour synthesizing section> FIG. 46 shows the color density selecting section 41 of FIG.
13 shows detailed configurations of the coefficient selection unit 4114, the calculation unit 4116. Latch 6001 by the data bus of the microcomputer
Various parameters are set to 6006. Latch 60
Different density data is set in 01 to 6003, and the color detection signal den becomes “1” when a color is detected.
When any one of 1 to 3 becomes "1", the AND gate 6
007 to 6009 and the OR gate 6013 select one of the data set in the latches 6001 to 6003. Thereby, the density data corresponding to the detected color is input to the multiplier 6015.

The contour detection signals K1 to K3 indicate the positions of pixels from the contour in the color area. When the first pixel is detected from the contour, K1 becomes "1", and similarly, the second pixel from the contour is detected. Is detected, K3 becomes "1" in the third pixel. Coefficient data is set in the latches 6004 to 6006. AND gates 6010 to 6012, OR gate 60
When the contour detection signal K1 is "1", the data in the latch 6004 is selected by 14, and similarly, the data in the latches 6005, 6006 is selected by K2, K3. Here, the values of the coefficient data set in the latches 6004 to 6006 are set to decrease in the order of D1, D2, and D3. The outputs of the OR gates 6013 and 6014 are multiplied and divided by the calculator 6015 and output. The division is performed by bit shifting.

FIG. 47 shows the coefficient selection unit 4115 of FIG.
The detailed structure of the calculation unit 4117 is shown. Contour detection signal K1
3 are the same as those shown in FIG. Latch 610
Coefficient data are set in the data buses 1 to 6103, and when any of the contour detection signals K1, K2, and K3 becomes "1", AND gates 6105 to 6107, O
The coefficient data is selected by the R gate 6108. Here, the coefficient data of the latches 6101 to 6103 are D4 and D.
It is set to increase in the order of 5 and D6. The calculator 6110 calculates the video data and the selected coefficient data, and outputs the result from the OR gate 6111. K
When 1, K2 and K3 are all "0", the output of the NOR gate becomes "1" and the video data is output from the AND gate 6109 and the OR gate 6111.

Returning to FIG. 29, the arithmetic units 4116 and 4117 are used.
Are added by the adder 4118. In this way, the set density signal and video signal are mixed in the contour portion. The closer to the contour the mixing ratio is,
Since the ratio of the density signal is increased and the ratio of the video signal is decreased, the contour portion and the video signal portion change gently.

<Color Density Conversion Processing Unit> The input unit A of FIG. 29 is the luminance signal input unit of the decoration circuit 114, and the signal input from this is input to the 4102 selector unit. 410
Reference numeral 1 denotes a color density generation unit, which is configured to generate arbitrary multivalued fixed data according to the color code in accordance with the color code signal. Reference numeral 4127 is a color density conversion select signal which is set to "1" when a color code is generated and set to "0" when a color code is not generated (achromatic color etc.). That is, when the color code is generated, the fixed density corresponding to the color code is output instead of the normal image information (luminance signal).

<Color patterning processing section> In FIG.
Reference numeral 4129 is a binary pattern signal, which corresponds to a signal 4719 in FIG. 35 described later. Reference numeral 4131 is a color patterning select signal (details will be described later). The color patterning select signal 4131 is "1" when the color code is generated.
Then, the selector 4111 selects the A input.

Reference numeral 4104 denotes an information portion fixed density generating portion of the "1" portion of the binary pattern, which generates an arbitrary fixed density a. Reference numeral 4105 denotes a background fixed density generation portion of the binary pattern "0", which generates an arbitrary fixed density b different from the fixed density a. That is, multivalued pattern information is output from the 4106 selector in accordance with the pattern signal 4129.

Reference numeral 4107 is a 2-input AND circuit,
When the pattern signal 4129 becomes active (when it is the information portion (“1”) of the pattern), normal image information (41
The output of the 03 AND circuit) flows, and the background portion (“0”) of the pattern is configured so that the image information is “φ”, that is, white (00H) in the density image. That is 410
The image information output from 7 is an image output in which the density information of the original image is added to the pattern.

Reference numeral 4108 denotes a 2-input OR circuit,
When the 29 pattern signal becomes active (when it is the information part (“1”) of the pattern), all outputs are High.
("1") and black (FFH) is output as a density image. Further, when the pattern signal is inactive (background part of the pattern), normal image information (output of the 4103 AND circuit) flows. In other words, the image information output from 4108 has density information of the original image on the background portion of the pattern.

Reference numeral 4130 denotes a 3-input selector, which selects A, B or C according to the select signal 4130. That is, the patterning mode of color patterning is selected by the 4130 select signal. The select signal 4130 is a signal from the CPU bus and is generated based on the mode setting by the operator from the operation unit.

<White contour adding portion for black characters inside color> 4
Reference numeral 110 denotes a fixed density information generation unit for a white contour (hereinafter, color white contour) for a black character inside a color (a black character having a color in the periphery). 4132 is a select signal of a white-white contour, and 41
When 4132 becomes active “1” (color white outline portion) in the 12 selectors, the color white outline whose density is designated in 4110 is output from the 4112 selector. Further, when 4132 is inactive "φ" (other than the color white outline portion), normal image information flows.

<Image Decoration Processing Unit> The decoration image generation unit will be described in detail in a separate sheet.

The decoration processing in this embodiment is roughly divided into outer contour processing (outer contour of image) inner contour processing (inner contour of image), flat shadowing processing, and solid shadow casting processing.
It consists of types.

In FIG. 29, reference numeral 4119 is a fixed density generating portion for the flat shadow and the solid shadow portion, and 4121 is a fixed density generating portion for the inner contour and outer contour portions. Reference numeral 4136 is a select signal for the flat shadow and the solid shadow. For example, if the flat shadow is selected, only the area to which the flat shadow is added becomes active “1”, and the 4120 selector selects the B input, and the flat shadow fixed density is 4120 selector. Will be output from. Similarly, 4137 is a selection signal for the inner contour and the outer contour. For example, if the inner contour is selected, only the area to which the inner contour is added becomes active "1", and the 4122 selector selects the B input to set the inner contour fixed density. It is output from the 4122 selector. 413
Reference numeral 8 denotes a decoration addition processing select signal. For example, when the decoration addition processing is performed only in a certain area, the selection signal 4138 becomes active “1” only in that area, and the selectors 4120 and 4122 described above become active. Will be. Outside the area, the 4138 select signal becomes inactive "φ", and the 4123 selector selects the A input and kills the decoration processing. Select signal 413
8 is generated by the area signal generation circuit 116 based on the area information designated by the digitizer 117, and is sent via the CPU bus.

Next, the decoration signal generator will be described. The decoration signal generation unit will be briefly described with reference to FIG. A is a multi-valued image information input unit, to which the luminance signal from the filter circuit 112 is input. Reference numeral 4001 is a binarization processing unit. Although a detailed description of the binarization processing unit 4001 is omitted,
In the present embodiment, for the sake of simplicity, 2 is set by the fixed slice level.
It shall be valued. 4002 is an outer contour signal generation unit, 4
Reference numeral 003 is an inner contour signal generation unit, 4004 is a flat shadow signal generation unit, and 4005 is a stereoscopic shadow signal generation unit. 4002-4
The block 004 will be described later in detail.
Reference numerals 4006, 4007, 4008, and 4009 denote AND circuits, and various decoration signals are selected by the select signals of 4011, 4012, 4013, and 4014 set by the operation unit and sent through the CPU bus. 40
Reference numerals 15 and 4016 are OR circuits, and output signals 41 of the respective
37 and 4138 are binary decoration signals.

(1) Inner contour signal generator 4003 An inner contour signal generator will be described with reference to FIG. In the figure, reference numerals 4214 to 4220 are binarized image signals, which are signals obtained by holding the image signal binarized by the above-described 4001 binarization processing unit in a FiFo memory in a plurality of lines (7 lines). Although a detailed description is omitted here, the image signal read by the CCD for one line is repeated as the flow of the image signal for reading the image of the document by scanning the document in the line CCD in a certain direction. It will flow. Here, the CCD line direction is referred to as the main scanning direction, and the CCD scanning direction is referred to as the sub-scanning direction. At this time, the binarized image signals 4214 to 4220 are an input unit of image signals for 7 lines in the sub-scanning direction. Reference numerals 4201, 4202 are AND circuits of 7 inputs, 4205 to 4213 are D type flip-flops (DF.F.), 4203 is an inverter circuit, 4204.
Is a 2-input AND circuit. Reference numeral 4221 denotes an image transfer clock, and reference numeral 4222 denotes an output unit for the inner contour signal. As a basic idea, the DF. F. Is the pixel of interest, and the 4201 AND circuit, 4203 NOT circuit, and 4204 AND circuit generate the inner contour signal in the sub-scanning direction, and the 4202 AND circuit, 4203 NOT circuit, and 4204 AND circuit generate the inner contour signal in the main scanning direction. Will be done.

Next, the concept of generating the inner contour signal when the image is cut in the main scanning direction will be described with reference to FIG.
Reference numeral 4801 indicates an image transfer clock, and reference numeral 4802 indicates an image signal (output of 4213D.F.F.) Of the pixel of interest. At this time, the output of the AND circuit 4202 has a waveform of 4803. The output of the 4203NOT circuit is 4804, which is 4
The output of the 204 AND circuit is 4805. Here, it can be seen that for the target image 4802, 4805 has an inner contour signal.

(2) Outer Contour Signal Generation Unit The outer contour signal generation unit 4002 will be described with reference to FIG. In the figure, 4615 to 4621 are binarized image signals, which are the same as 4214 to 4220 described above. Four
Reference numeral 601 denotes an AND circuit, which is an erroneous determination prevention circuit, which will be described in detail later. 4602 is a 7-input OR circuit,
Reference numerals 4603 to 4608 and 4611 to 4613 are D type flip-flops, 4614 is a NOT circuit, 4609 is a 7-input OR circuit, and 4610 is an AND circuit.

Reference numeral 4623 denotes an image transfer clock input section, and 4624 is an outer contour signal output section. Also, 4622 is a control signal for the erroneous determination prevention circuit, which will be described in detail later. The basic idea is that D.4613. F. F. Is the image of interest, and the 4602OR circuit, 4614NOT circuit, and 4610AND circuit generate the outer contour signal in the sub-scanning direction, and the 4609OR circuit,
The 4614 NOT circuit and the 4610 AND circuit generate the outer contour signal in the main scanning direction.

Next, the concept of generating an outer contour signal when an image is cut in the main scanning direction will be described with reference to FIG.
As described above, since 4802 is the image of interest, 48
07 is the output of the 4614 NOT circuit. Also, 4609
The output of the OR circuit is 4806, so 4610 AND
The output of the circuit looks like 4808. Featured image 4 here
It can be seen that, with respect to 802, 4808 is an outer contour signal.

(3) Plain Shadow Signal Generating Unit 4004 The plain shadow signal generating unit will be described with reference to FIG. Reference numeral 4308 in the drawing is an input unit of a binarized image of interest. Further, 4309 is an image binarization signal which is delayed by, for example, 3 lines in the present embodiment with respect to the sub-scanning direction. Again 4310
An image transfer clock 4307 is a flat shadow mode select signal. Reference numerals 4303, 4304, and 4305 are D-type flip-flops. Now mode select signal 4307
Is “φ”, the output of the NOT circuit 4302 is “1”.
And AND circuit 4306 outputs DF. F. The output signal of the 4305 is passed as it is.

Here, 4309 is a signal delayed by 3 lines in the sub-scanning direction, and the output of 4305 is a signal delayed by 3 clocks with respect to the main scanning direction. An image signal that is shifted by 3 pixels both in the main and in the sub-image is output.

Next, the 4307 mode select signal is "1".
At the time of, the output of the NOT circuit 4302 is
Inversion of 08, the image signal in which both the main and sub pixels are shifted by 3 pixels is output from the flat shadow signal output unit 4311 only in a portion other than the target image. Regarding the above two modes, the mode selector signal 4307 whose concept will be described with reference to FIG. 37 is 4901 when it is “0” and 4902 when it is “1”.

(4) Solid Shadow Signal Generation Unit The solid shadow signal generation unit 4005 will be described with reference to FIG. Reference numeral 4410 is an input unit of the image of interest,
An image signal 413 is delayed by one line in the sub-scanning direction by the FiFo memory. The image signal is a binarized signal as in the other decoration processing. An image transfer clock 4415 is an output unit of a stereoscopic shadow signal 4415. Four
401 to 4406 are DF. F. Reference numeral 4407 is a 4-input OR circuit, 4408 is a NOT circuit, and 4409 is an AND circuit. A conceptual diagram of the stereoscopic shadow signal is shown in FIG.

<Erroneous Judgment Prevention Circuit> 4601 described above
The generation unit of the control signal 4622 of the erroneous determination prevention circuit will be described with reference to FIG. The purpose of the erroneous determination prevention circuit will be briefly described. The outer contour generating circuit is composed of an OR circuit as described above. That is, for example, if there is a small dust (for example, a dust of one pixel) on the document table, and if this is determined to be an image after the binarization processing, an outer contour is generated for this dust. In particular, in the case of hardware for generating a large outer contour, a large number of outer contours are generated where there are no images on the document, so that the image becomes very difficult to see. So, for example, 3
An image that is smaller than the × 3 pixel block is determined to be dust and the generation of the outer contour signal is stopped by the erroneous determination prevention circuit. Although FIG. 33 has a circuit configuration for determining dust of 1 × 1 pixels, it is easy to implement a dust determination circuit of 3 × 3 pixels or 5 × 5 pixels with the same idea if the circuit scale is increased. it can.

Reference numeral 4510 is an input portion of the image of interest, 4509 is an image signal one line before in the sub-scanning direction, and 4511 is an image signal input portion one line after in the sub-scanning direction. 4512 is an image transfer clock, and 4501 to 4506 are D.I. F. F.
4507 is an 8-input NOR circuit, 4508 is an AND circuit, and 4513 is an erroneous determination prevention signal. When it is determined that the dust is 1 × 1 pixel, 4513 outputs “1”. As an idea, when the image of 8 pixels around the pixel of interest is white (“φ”) and the pixel of interest is black (“1”),
“1” is output from the 4513, and it is determined that it is dust. Actually, by inputting the inverted signal of 4513 to 4622 of FIG. 34, it is possible to prevent the outer contour generation when 4513 is "1".

<Negative / Positive Reversal Processing Section> In FIG.
The EXOR circuit 4124 is the negative / positive inversion processing unit, and
39 is this control signal, which is input via the CPU bus based on the mode setting from the operation unit. When 4139 is "1", it is inverted.

<Trim Mask Processing Unit> In FIG. 29, the selector 4126 is a trim mask processing unit. 4125
Is a fixed density generator for the trim mask, and normally produces white (“0”). 4140 is the control signal, and when trimming, 4140 becomes "0" only in the image area to be left, B side is selected, and conversely, when masking, 4140 is set to "1" only in the image area to be erased. It is realized by selecting the side.

The above-mentioned color density generator 4101 and other density data generators 4104, 4105, 4110, 411.
3, 41109, 4121, and 4125 can be configured by, for example, a RAM, and a CPU can be connected via a CPU bus.
Can set arbitrary data. The data may be changed by the operator or service person.

Further, the selection signal 4127 selects the A side of the selector 4102 when the color code is generated in the case of a mode in which different density levels are generated corresponding to the color code, and in other cases. Always selects the B side of the brightness data. The selection signal 4130 is set to the A side in the pattern output mode, the B side in the halftone dot mode, and the C side in the halftone dot mode.
Select the side. The selection signal 4131 selects the A side in the pattern processing mode and the B side in the normal output mode. The selection signal 4132 appropriately selects the A side and the B side in the white contour mode, and always selects the B side in the normal mode. The selection signal 4138 is flat shadow / stereo shadow, outer contour /
The B side is selected in the inner contour mode, and the A side is selected in other cases. The above selection signals are generated by the CPU based on the mode designation by the operation unit.

Next, the erase color detection circuit 4141 will be described with reference to FIG.

The color code corresponding to the color code to be erased is registered from the CPU (not shown) via the CPU bus to the register 3
Set to 902. The equal-surface comparator 3901 detects whether or not the color code signal input to the decoration unit matches the set color code, and outputs Hi when they match. There are 3906 to 3911 similar to the detection circuit 3905, and a total of 7 colors can be detected. When a color is detected from these outputs via the OR gate 3904, the selector 4126 via the OR gate 4142 in FIG. 29 operates in the same manner as the masking process.

As described above, in the present embodiment, it is possible to specify an arbitrary color code among N color (6 colors) color codes and erase the color corresponding to the color code.

<Pattern Generating Unit> A pattern generating unit used in the above-described color pattern processing or the halftone / halftone processing which will be described later will be described with reference to FIG.

Reference numeral 4716 is a CPU address bus, 471
Reference numeral 7 is a data bus of the CPU. Reference numeral 4703 denotes a selector, which is a rewritable memory 4 when 4714 is “φ”.
The address bus of the CPU is input to the address 705 (here, RAM). CP for 4721
The U write signal (COW active) is input. That is, when the address bus of the CPU is input to the address of the RAM 4705, the CPU performs the write operation in the RAM 47
05, the write signal is input to the RAM 4705, and at the same time, the data bus of the CPU is input to the data portion of the RAM 4705. That is, by setting 4714 to "0", the CPU can rewrite the contents of 4705 RAM.

Reference numeral 4701 is a main scanning up counter, 47
Reference numeral 02 is a sub-scanning up counter, and 4714 is set to "1".
As a result, the address for reading the pattern is R
It is input to AM4705. The pattern read at this time is input to the AND circuit 4708 via the 4707 buffer. In this embodiment, if the RAM 4705 has a byte structure, for example, eight kinds of patterns are simultaneously output for each bit of the data bus.
Is selected by a 3-bit pattern selection signal 4718 from and output from the OR circuit 4709. The OR circuit 4709 is used to convert an 8-bit signal into a 1-bit signal. In the figure, 4719 is a pattern signal. Reference numeral 4711 is a main scanning direction up counter, 4712 is a sub scanning direction up counter, and 4713 is an adder. Reference numeral 4710 is a comparator, and “4” is output from the 4720 only when A ≦ B. The output signal of 4720 will be a gradation signal, which will be described in detail later.

<Gradation Processing> The gradation pattern has a concept as shown in FIG. In other words, it is a pattern in which the size of the pattern changes with constant synchronization. The generation principle of the gradation pattern will be briefly described. In FIG. 39, 5101 is a slice level to be written in the RAM 4705 in advance. At the same time, since the normal pattern described above is also written in the RAM 4705, half of the RAM 4705 is actually used to write the slice level of the pattern and the gradation. This switching signal is 4715. As indicated by reference numeral 5101, one gradation is generated by a 7 × 7 slice level. The number written in the figure is the slice level. If the data of Aφ _H is input to this slice level at one time (specifically, B of the 4710 comparator is input).
5102 dots are output from 4720. If C8 _H is input, the 5103 dot becomes 5
If 0H is input, 5104 dots are output. That is, it can be seen that the dots themselves become larger as the input image signal becomes larger. That is, FIG. 35 described above.
Since the output of the 4713 adder is an image signal to be input, it is possible to create various gradation synchronization and directions by changing this value variously. For example, a gradation pattern whose size changes in the main scanning direction is created by moving only the main scanning counter 4711, and a gradation pattern whose size changes in the sub scanning direction can be created by moving only the sub scanning counter 4712. It is also easy to imagine that a gradation pattern that changes diagonally can be created by moving two at the same time. When changing the synchronization of changing size, the speed of the counter of 4711 or 4712 may be changed.
By switching up / down of the counter, it is possible to select whether to start from a large size or a small size. The gradation slice level is RAM
Since it is written in 4705 and rewritable, the shape and size of the gradation dots can be changed depending on the case.

<Shading processing> In FIG. 40, when the original image is 5203, processing for adding a pattern only to the image portion like 5201 is called shading processing. The realization method is realized by binarizing the image signal and flowing the above-described pattern or gradation only where "1" is determined (where image is determined). Specifically, the mode of the select signal 4130 may be set so that the selector 4109 of FIG. 29 described above selects B.

<Screening Process> In FIG. 40, when the original image is 5203, a process of adding a pattern only to the non-image portion like 5202 is called a screening process. The realization method is realized by binarizing the image signal and flowing the above-described pattern or gradation only at a portion determined to be “0” (a portion determined to have no image). Specifically, the mode may be set for the select signal 4130 so as to select C in the selector 4109 of FIG.

<Banded White Contour Processing> When 5301 whose concept is described with reference to FIG. 41 is the original image, the case where a white contour is added to the pattern-based hatching is 5303. Is 5303 when is added. The white contour can be realized by the outer contour signal in the decoration processing described above. Since it can be easily realized from the outer contour signal, the white density generating portion of the outer contour portion, and the halftone processing described above, the description thereof is omitted here.

A method of setting a color to be erased at the time of color erase will be described with reference to FIGS. 42 and 43.

When the color erase key 5027 is pressed, 50
The screen 52 is as shown in FIG. Select the color you want to erase here. If you want to erase the red color, move the pointer to the "red" position with the cursor keys 5008 to 5011 and press the OK key on 5012. When the OK key of 5012 is pressed, a line (e) is displayed on the "red" display as shown in the screen of FIG. 43 (B). In addition, if there is a color you want to delete, move the pointer to the color you want to delete with the cursor keys 5008 to 5011 again. If you want to erase the blue color, the screen is
Move the cursor as shown in (C) and press the 5012 OK key. When the OK key is pressed, the screen shown in Fig. 43 appears.
It becomes like (D). When the setting is completed, "End" is displayed at the lower right of the screen, so if the key 5013 is pressed, the setting is completed.

After the setting is completed, as shown in FIG. 44, the start button 5003 is pressed, and after the copy start is turned on,
Check if the color erasing mode is set (S10
1), if set, the register of the window comparator 1304 of the color recognition circuit of FIG. 13 and FIG.
The erasing color detection circuit 4141 of 9, namely the color code shown in FIG. 27 is set to a predetermined value in the setting register 3902 by the CPU (S102), and the copy operation is started (S10).
3). When the color erasing mode is not set, the setting in each register is not performed and the copy operation starts immediately.

(Density Conversion and Gradation Correction) Next, the density conversion and gradation correction unit 115 will be described.

Here, a gradation correction process for correcting the gradation of the density and the gradation of the output device is performed using an LUT (look-up table). First, as a density conversion process, the read luminance signal is converted into a density signal, which is generally called log conversion. The log conversion table is
It is calculated from the following formula.

D _OUT = −255 / D _MAX * LOG (D _IN / 255) Next, the gradation correction table will be described.

The gradation correction table is for correcting the gradation characteristic of the output device. For example, the gradation characteristic of the electrophotographic printer is shown in FIG. The characteristics of the correction table corresponding thereto are shown in FIG.

In the present embodiment, the correction processing is carried out in the same ROM, and conversion table data obtained by a formula such as correction data = gradation correction (−255 / Dmax ^* Log (Din / 255)) is stored in the ROM. It has been written. In this embodiment, a ROM is used as the look-up table.
It goes without saying that a storage element such as a RAM may be used instead of the above.

As described above, according to the embodiment of the present invention, it is possible to delete the specific color by replacing the input image of the same color as the preset color with the white information. In addition, this allows not only one color but also information of a plurality of colors to be deleted, and even if an original in which a plurality of colors are used to emphasize characters is copied in black and white, the character information of the original is not lost. Can be output.

Further, it is possible to perform color recognition patterning processing on an original such as halftone printing without causing erroneous recognition due to the fact that it is composed of halftone dots.

That is, the input image information is first smoothed, the color is recognized using the smoothed signal, and the isolated points are removed. By performing majority decision processing and determining the most recognized color as the judgment result, erroneous judgment that occurs when recognizing colors and patterning is eliminated for the colors used on the original such as halftone printing, and the number of lines Even in rough halftone printing, it is possible to solve the difficulty of only the image.

In the above embodiment, the color space is divided into six, so that the six colors are recognized and any one of them is erased.
It is also possible to recognize N (N ≧ 2) colors such as two colors.
The color recognition method is not limited to the above example.

Since the color erasure of this embodiment is performed corresponding to the color code generated by dividing the color space into N,
It is possible to collectively erase colors having a wide range of hues and saturations.

The input color components are not limited to R, G and B, but may be data in other color spaces such as L ^* a ^* , b ^* , Y, I and Q. In the case of data divided into luminance (brightness) and chromaticity, N colors can be recognized by dividing the a ^* b ^* space and IQ space into N, for example.

Further, in the above embodiment, the electrophotographic copying machine is taken as an example, but the printer may be a thermal transfer or ink jet type. In particular, a so-called bubble jet method of discharging droplets by utilizing film boiling due to thermal energy may be used.

[0117]

As described above, according to the image processing apparatus of the present invention, it is possible to prevent misjudgment at the time of color discrimination.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an image processing apparatus of the present invention.

FIG. 2 is a diagram showing a 3-line solid-state image sensor.

FIG. 3 is a diagram showing a color image reading optical system.

FIG. 4 is a sectional view of a one-dimensional blazed diffraction grating for three-color separation.

FIG. 5 is a drive pulse timing chart of the CCD image sensor.

FIG. 6 is a configuration diagram of a CCD driver.

FIG. 7 is a black / white correction circuit diagram.

FIG. 8 is a diagram showing a concept of black correction.

FIG. 9 is a flowchart showing white correction processing.

FIG. 10 is a luminance signal generation circuit diagram.

FIG. 11 is a smoothing circuit diagram.

FIG. 12 is a diagram showing a pseudo hue plane.

FIG. 13 is a color recognition circuit.

FIG. 14 is a majority circuit diagram 1.

FIG. 15 is a majority circuit diagram 2.

FIG. 16 is a filter processing circuit diagram.

FIG. 17 is a conceptual diagram of filter processing.

FIG. 18 is a diagram showing tone characteristics of a printer and characteristics of a correction table.

FIG. 19 is an outline contour generation circuit diagram.

FIG. 20 is a timing chart 1 for explaining the operation of a white outline circuit.

FIG. 21 is a timing chart 2 for explaining the operation of a white outline circuit.

FIG. 22 is a conceptual diagram of a white outline.

FIG. 23 is a buffer control timing chart of the scaling circuit.

FIG. 24 is a video signal scaling circuit diagram.

FIG. 25 is a control signal timing chart at the time of repeat.

FIG. 26 is a circuit block diagram of a color contour signal generation unit.

FIG. 27 is an erased color detection circuit shown in FIG. 41.

FIG. 28 is a simple explanatory diagram of an image decoration portion.

FIG. 29 is a circuit diagram of an image decoration section.

FIG. 30 is a circuit diagram of an inner contour generator.

FIG. 31 is a circuit diagram of a flat shadow signal generation unit.

FIG. 32 is a circuit diagram of a three-dimensional shadow generation unit.

FIG. 33 is an erroneous determination prevention circuit due to an isolated point.

FIG. 34 is a circuit diagram of an outer contour generator.

FIG. 35 is a circuit diagram of a pattern signal generator.

FIG. 36 is a timing chart of generation of an inner contour signal.

FIG. 37 is a conceptual diagram of a flat shadow image.

FIG. 38 is a gradation pattern diagram.

FIG. 39 is an explanatory diagram of a principle of forming gradation dots.

FIG. 40 is an example of an output image of halftone dot addition processing.

FIG. 41 shows an example of an output image of a halftone white outline.

FIG. 42 is an operation unit used in this example.

FIG. 43 is an erase color setting screen.

FIG. 44 is a color erasing process setting flow.

FIG. 45 is a conceptual diagram of a three-dimensional shadow.

FIG. 46 is an explanatory diagram 1 of a color contour generation unit.

FIG. 47 is an explanatory diagram 2 of a color contour generation unit.

FIG. 48 is a sectional view of the copying machine of this embodiment.

[Explanation of symbols]

 108 smoothing circuit 109 color recognition unit 110 majority decision unit 114 decorative circuit

[Procedure amendment]

[Submission date] May 14, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

[0004]

However, for example, a color original represented by halftone printing has a different screen angle for each color, so it is assumed that the color original is 400 dpi (dot).
/ Inch), complete color separation is performed in printing with a line number of about 175 lines. Therefore, taking a green printed matter as an example, it is composed of dots of cyan ink and yellow ink, and if the color is judged as it is, all three colors of cyan, yellow, and green are recognized, which is an erroneous recognition. Become. If these three colors are replaced as they are with different patterns and monochrome output is performed, it becomes very difficult to see. Further, in such a digital copying apparatus, there is a problem in that it is not possible to accurately read the original density of a thin line or the like due to a decrease in MTF which is a transfer function of the reading optical system. For example, if there is a black thin line on a white background, the thin line is read lightly with respect to the density of the document. Further, it is not possible to expect a sharp rise of the density even at the edge portion. For that reason,
For documents with many thin lines, output with a gamma is
Also, for photographs and the like, the processing had to be switched so that gamma-like output could be obtained. However, the processing must be switched according to the original such as characters and photographs, which is complicated in operation. Further, when the copy original is a mixed image of characters and photographs, in order to satisfy both images, it is proposed to recognize the original image and automatically switch the gamma according to the image.
There is a problem that the circuit scale becomes large and it is expensive.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction content]

The present invention has been made in view of the above circumstances, and an object thereof is to prevent misjudgment at the time of color discrimination. It is also intended to properly reproduce a mixed image of characters and photographs.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

In order to solve the above-mentioned problems, the image processing apparatus of the present invention inputs the pattern information and the judging means for judging the color of the input image from the input image information of at least two colors. An image processing apparatus having a pattern adding means for adding to image information, wherein the input image information is subjected to smoothing processing, then the determination means makes a determination, and the determination result is subjected to correction processing by majority decision. It is characterized by Also, 1 for the input image signal
It has a primary differential processing means for performing a secondary differential and a secondary differential processing means for performing a secondary differential on the input image signal, and inputs the primary differential processing and the secondary differential processing to the input. The feature is that it is performed in parallel with respect to the image signal.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0117

[Correction method] Change

[Correction content]

[0117]

As described above, according to the image processing apparatus of the present invention, it is possible to prevent misjudgment at the time of color discrimination. Moreover, a mixed image of characters and photographs can be reproduced well.

Continuation of front page (72) Inventor Yoshinori Abe 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (3)

[Claims] 1. An image processing apparatus comprising: a discriminating means for discriminating a color of an input image from input image information of at least two colors; and a pattern adding means for adding pattern information to the input image information. An image processing apparatus, characterized in that after the smoothing process is performed, the determination is performed by the determination unit, and the determination result is subjected to a correction process by majority decision. 2. The discrimination means divides the color space into N (N ≧
2) Then, the image processing apparatus according to claim 1, wherein the N colors corresponding to the respective colors are discriminated. 3. The image processing apparatus according to claim 1, further comprising output means for adding different patterns to the plurality of colors discriminated by the discrimination means and outputting them by the pattern addition means.