KR100211838B1 - Apparatus for reducing picture image - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A device for reducing an image image.

2. The technical problem to be solved by the invention

By subsampling the original image image in the spatial domain, the contour component is prevented from being lost when it is reduced.

3. Summary of Solution to Invention

According to the present invention, when the image image is reduced in the vertical direction and the horizontal direction according to a preset pixel selectivity, the line and the pixels determined to be unselected are determined temporarily after determining whether each line is selected and whether each pixel is selected. Provided is an image image reduction apparatus for outputting a logically operable operation of the temporarily stored lines and pixels when the lines and pixels which are stored and determined to be selected later are input.

4. Important uses of the invention

Fax or digital copier.

Description

Image Image Reduction Device

1 is a view showing that only a specific pixel is selected when an input pixel is reduced according to a general subsampling method.

2 is a view showing an example of an image image reduced according to a general subsampling method.

3 is a diagram showing a configuration of an image forming apparatus having an image image reduction apparatus according to the present invention.

4 is a view functionally showing the configuration of the vertical reduction unit included in the image reduction apparatus according to the present invention.

5 is a view showing in detail the configuration of the vertical reduction unit of the image image reduction device according to the present invention.

6 is an operation timing diagram of a vertical reduction unit according to the present invention.

7 is a view showing in more detail the configuration of the horizontal reduction unit of the image image reduction device according to the present invention.

8 is an operation timing diagram of a horizontal reduction unit according to the present invention.

9 is a view showing an example in which the image image is reduced in the vertical direction and the horizontal direction by the image image reduction apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

501,701: Conversion ratio register 502,702: Full adder

503,703: diffusion ratio register 504: line buffer memory

505,706,710: Inverters 506 to 509, 705,709,712

510,707,711: logical product gate 704,708: flip-flop

713: counter 714: serial-to-parallel converter

The present invention relates to an apparatus for reducing an image image, and more particularly, to an image image reduction apparatus that processes an outline image so that an outline component is not lost when the original image image is reduced by subsampling.

In general, when using an image forming apparatus that requires a scanner such as a facsimile or digital copier, users often feel the need to reduce the scanned image image. In order to satisfy this need, a method of transforming a scanned image into a frequency domain and inversely transforming the scanned image into a frequency domain, and subsampling each pixel of the image scanned in the spatial domain according to a conversion ratio There is a way to handle it. The present invention relates to the latter method.

According to the method of subsampling and processing the original image image 1 Conversion to the unit is possible, and assuming that the conversion ratio is a, if a is less than 1, the image image is reduced or compressed. For example, if a is 0.7, the image is 7 Compressed, but the image of one line of 10 input pixels is 70 according to the subsampling method In the case of compression, each pixel is selected as shown in FIG.

In FIG. 1, I (i) is the i-th input pixel, a is the conversion ratio (also called intrinsic probability), d (i) is the diffusion probability, S (i) is the pixel selectivity, and O (i Denotes an output pixel. Referring to FIG. 1, since a is 0.7, the intrinsic probability of each pixel for selection is 0.7. Then, the sum of the intrinsic probability a of each pixel and the diffusion probability d (i) becomes the selectivity S (i) of the pixel. According to the subsampling method as shown in FIG. 1, the first input pixel I (1) is not selected because the pixel selectivity S (i) is 0.7, and the second input pixel I (2) is the pixel selectivity S Since (i) is 1.4, it is selected and output as O (1). When this method is applied to the tenth input pixel I 10, the remaining pixels except for the first, fourth and seventh pixels among the ten input pixels are selected and output.

2 is a diagram showing an example of an image image reduced by the above-described subsampling method. Referring to FIG. 2, the original 10 × 10 picture image is reduced to 7 × 7 picture image, which is reduced to the 1st, 4th, 7th rows and 1,4 according to the pixel selectivity as shown in FIG. This is because the pixels in the seventh column are not selected.

However, according to the prior art, since the selection of the pixel is made regardless of the brightness value of the pixel, there is a problem in that the original image image cannot be identified from the reduced image image. For example, as shown in FIG. 2, the letter K represented by a 10 × 10 image image cannot be identified from a 7 × 7 image image which is a reduced image image. In other words, when the document, which is a representative image image represented by the outline components, is reduced according to the conventional method, the outline components may be discarded as shown in FIG. 2. This results in the loss of important information of the document and also in the deterioration of image quality.

A technique for compensating the above problems of the prior art is disclosed under Korean Patent Application No. 94-36623 Title Image Data Compression Method filed by the applicant of the present application. According to the patent, it is discarded after judging whether an unselected line (in the case of vertical reduction) and an unselected pixel (in the case of horizontal reduction) are boundary components, which are one of the important features of the image image. If a pixel (or line) corresponds to a boundary component, the problem of the prior art is solved by diffusing to the next pixel (or the next line) and logically computing the next pixel (or the next line). However, since all these operations are processed by the CPU (Central Processing Unit) in a software method, there is a problem that it takes a long time to reduce the image image. This problem will be particularly noticeable as the CPU is a slow CPU and there is more to be done.

Accordingly, it is an object of the present invention to provide an image image reduction apparatus that prevents the loss of important dullness of an image image when the image image is reduced by subsampling.

Another object of the present invention is to provide an image image reduction apparatus that prevents deterioration of image quality even by subsampling an image image.

It is still another object of the present invention to provide an image image reduction apparatus that shortens the processing time when the image image is subsampled and reduced.

Still another object of the present invention is to provide an image image reduction apparatus that reduces an image image at a short time even when using a low speed CPU.

According to the present invention for achieving the above objects, when the image image is reduced in the vertical direction and the horizontal direction according to the preset pixel selectivity, the line is determined not to be selected after determining whether each line is selected and whether each pixel is selected. And an image image reduction device for temporarily storing the pixels without temporarily discarding them and performing logical operation on the input lines and pixels and the temporarily stored lines and pixels when the lines and pixels determined to be selected thereafter are inputted. . Accordingly, important information of the image image may be prevented from being lost when the image image is subsampled and reduced.

An image image reduction apparatus according to the present invention may be classified into a device for reducing an image image in a vertical direction and a device for reducing an image image in a horizontal direction.

According to the present invention, an apparatus for reducing an image image in a vertical direction includes: a first register for storing a preset reduction ratio, a second register for storing a preset diffusion ratio, and a first register and a second register, respectively. It is made up of a full adder that adds the stored reduction ratio and the diffusion ratio and adds a full value to be used as the diffusion ratio to be stored in the second register and a carry value indicating whether the image image of each line is selected. Discriminating means for discriminating whether or not to select an image image of each line when is input on a line basis; Storage means for temporarily storing an image image determined as a line not selected by said discriminating means; And a logical sum gate that logically combines the image image and the image image temporarily stored in the storage means when the image image determined as the line to be selected by the discriminating means is input.

Preferably, the storage means may be a line buffer memory.

According to the present invention, there is provided an apparatus for horizontally reducing an image image: a first register for storing a preset reduction ratio, a second register for storing a preset diffusion ratio, and a first register and a second register, respectively. It is made up of a full adder which adds all the reduced reduction ratio and the diffusion ratio to use as the diffusion ratio to be stored in the second register, and outputs a carry value indicating whether each pixel is selected, and a predetermined image image is inputted. Discriminating means for discriminating whether or not to select each pixel of the visual image image according to the carry value; Storage means for temporarily storing a pixel determined as a pixel not selected by said discriminating means when it is input; When a pixel to be selected by the discriminating means is input, a logical sum gate for logically operating the pixel and the pixel temporarily stored in the storage means is configured.

Preferably, the storage means may be a flip-flop.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be obvious to those with ordinary knowledge in the field. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

3 is a diagram showing the configuration of an image forming apparatus having an image image reduction apparatus according to the present invention, showing the configuration of a facsimile as an example.

Referring to FIG. 3, the CPU 301 controls the overall operation of the fax. The scanning unit 302 scans an image and converts it into a digital signal. The image image reduction device 303 is composed of a vertical reduction unit 303A and a horizontal reduction unit 303B to reduce the image image in the vertical direction and also in the horizontal direction. The image memory 304 stores the image image scanned by the scanning unit 302 or the image image reduced by the image image reduction apparatus 303. The main memory 305 stores a program according to the overall operation of the image forming apparatus. The printing unit 306 prints the image image scanned by the scanning unit 302 or the image image reduced by the image image reduction apparatus 303. The communication unit 307 transmits the image image scanned by the scanning unit 302 or the image image reduced by the image image reduction apparatus 303 to the outside through a communication network.

The image image reduction device 303 includes a vertical reduction unit 303A and a horizontal reduction unit 303B to reduce the image image not only in the vertical direction but also in the horizontal direction. In a typical facsimile, the image image is scanned line by line, so the image image reduction apparatus 3030 according to the present invention first reduces the image image in the vertical direction by using the vertical direction reduction unit 303A.

FIG. 4 is a diagram functionally showing the configuration of the vertical reduction unit 303A. A pixel column in the form of serial data scanned line by line by the scanning unit is input to the vertical reduction unit 303A.

Referring to FIG. 4, the vertical reduction unit 303A determines whether to select a line image image or not, and generates a line selection signal indicating the determination result. If it is determined that the line is not selected (when the line selection signal is one level), the serial pixel sequence is sequentially stored in the line buffer memory implemented as a first-in first-out memory. Of course, all of the line buffer memories are initialized to a value of zero. The pixel located at the right end of the line buffer memory is the first input pixel, and the pixel located at the left end is the last input pixel. When the next line is input, it is also determined whether to select the line or not. If you decide not to select the line (the reduction ratio is 50 In the following case), the serial pixel sequence previously stored in the line buffer memory and the serial pixel sequence currently input are one-to-one logically operated and stored in the line buffer memory again. When the next line is input, it is determined whether or not to select it, and if it is determined that it is not selected, the processing is performed again in the manner described above.

However, when the current input line is the selection target (the line selection signal is at 0 level), all values input to the line buffer memory are zero. At the same time, the serial pixel sequence (information on the unselected lines) output from the line buffer memory is logically one-to-one with the serial pixel sequence currently input. In other words, the line buffer memory stores the information of the lines which are not selected and is discarded. The line buffer memory performs logical sum operation of two lines of information each time a selected line is generated. Value) can be preserved even when scaled down, resulting in the same results as in the traditional software method.

5 is a view showing in more detail the configuration of the vertical reduction unit 303a that functions as shown in FIG.

Referring to FIG. 5, the CPU stores, in the conversion ratio register 501, a conversion ratio (reduction ratio, intrinsic probability of FIG. 1) to reduce the image image through the data bus. The spreading rate register 503 is a register in which a spreading rate value is stored, and an initial value has all bits having a value of zero. The full adder 502 determines whether or not to select an arbitrary line, i.e., calculates the line selection value (the same concept as the pixel selection value shown by the concept of horizontal reduction). That is, the full adder 502 adds the value of the conversion ratio register 501 and the value of the diffusion ratio register 503 to generate sum and carry. At this time, if carry occurs (when the sum is greater than 1), the line is selected and a line select signal SEL is generated. The sum value is fed back to the diffusion ratio register 503 and stored. It can be seen that this concept is the same as the soft method described in FIG. In other words, the full adder 502 adds the intrinsic probability (value stored in the conversion ratio register) and the diffusion probability (value stored in the diffusion ratio register) of FIG. 1 to select a line when the addition value is larger than one. Output SEL. Subsequently, the operation of generating a new serial pixel sequence is performed by the line buffer memory 504, the logical sum gate 510, and the logical product gate 506, which are the same as described in FIG.

In FIG. 5, CLK_V2 and CLK_H2 are signals to be used as the vertical synchronization signal of the horizontal reduction unit 303B and the pixel transfer clock, and CLK_V2 is the vertical synchronization signal of the vertical reduction unit 303A by the logical product gate 507. The carry value of the CLK_V1 and the full adder 502 is a logical product and is output. The CLK_H2 is a carry signal of the pixel transfer clock CLK_H1 and the full adder 502 of the vertical reduction unit 303A by the logical multiplication gate 508. The value is the result of logical multiplication. CLK_V2 and CLK_H2 are vertical synchronization signals and pixel transfer clocks that are valid only in a section where a line is selected.

FIG. 6 is a diagram showing an operation timing of the vertical reduction unit 303A operating as shown in FIG.

In FIG. 6, CLK_H1 is a horizontal pixel transfer clock provided from the scanning unit 302 and is a reference clock for transmitting the serial pixel sequence scanned by the scanning unit 302. CLK_V1 is a vertical synchronization signal indicating the start of a new line. SP1 is a form in which 10 × 10 image images as shown in FIG. 2 are arranged in order from the first line. The scanning unit 302 scans a 10 × 10 image image line by line, converts the black portion to a value of 1 and the white portion to a value of 0, and then synchronizes the horizontal pixel transfer clock CLK_H1 with the vertical reduction portion 303A. ) Is a serial pixel sequence passed to). Carry is a signal used as a criterion for determining whether each line is selected, and represents the carry output of the full adder 502 of FIG. Here, the reduction ratio is 0.7, that is, the input image is 70 It is assumed from FIG. 1 that the first line is not selected, and the second and third lines are selected, assuming that it is reduced to. The SEL signal is a signal inverting the carry and functions as a line selection signal. If the SEL signal is 0, the current input line is selected. If the SEL signal is 1, the current input line is not selected and is stored in the line buffer memory 504. do.

CLK_V2 is a value obtained by performing a logical AND operation on the vertical synchronizing signal CLK_V1 and the full adder 502 provided from the scanning unit 302 by the logical AND gate 507, and is provided to the horizontal reduction unit 303B. CLK_H2 is a value obtained by performing a logical AND operation on the horizontal pixel transfer clock CLK_H1 supplied from the scanning unit 302 and the full adder 502 by the logical AND gate 508, and is provided to the horizontal reduction unit 303B. . The CLK_V2 and CLK_H2 are signals for validating the vertical synchronization signal CLK_V1 and the horizontal pixel transfer clock CLK_H1 only in a section where a line is selected. SP2 is a new pixel string provided to the horizontal reduction unit 303B after the carry output of the full adder 502 and the output of the logical sum gate 510 are logically multiplied by the logical multiplication gate 509. It can be seen that the second line of the SP2 is a result of logically combining the pixels of the first line and the pixels of the second line of SP1.

7 is a view showing in detail the configuration of the horizontal reduction unit 303B of FIG.

In FIG. 7, the conversion ratio register 701, the full adder 702, and the diffusion ratio register 703 are respectively the conversion ratio register 501, the full adder 502, and the diffusion of the vertical reduction part 303A of FIG. The same function as the ratio register 503 is performed. The conversion ratio register 701 receives and stores a conversion ratio for reducing the image image from the CPU. The diffusion ratio register 703 is a register that stores the diffusion ratio of each pixel, and its initial value is zero for all bit values. The full adder 702 adds the value of the conversion ratio register 701 and the value of the diffusion ratio register 703 to generate sum and carry. The carry signal is generated when the addition value of the two registers is larger than 1, and a pixel selection signal for determining whether or not to select the pixel for each pixel in the horizontal direction (corresponds to the line selection signal in the vertical reduction section). to be. If the carry signal value is 1, the pixel is selected. If the carry signal value is 0, the pixel is not selected. The sum value is then stored in the confidence ratio register 703 again to determine whether to select the pixel. This process gives the same result as the software process shown in FIG.

If it is determined that the current input pixel is not selected (when the carry signal value is 0), the pixel is stored in the flip-flop 708, and the value stored in the flip-flop 708 causes the logical sum gate 711 to be removed. It is provided to the data input terminal DATA_IN of the serial-to-parallel converter 714 through. However, since the clock is not provided to the clock terminal CLK of the serial-to-parallel converter 714, there is no substantial movement of the serial pixel sequence provided from the vertical reduction unit 303A and only stored in the deflip-floc 708. This is because the output of the AND gate 712 is provided as a clock of the serial-to-parallel converter 714 because a carry signal of 0 is applied to one input terminal of the AND gate 712. If the next inputted pixel is also determined to be non-selected (no carry occurs), the current pixel (non-selected pixel) and the non-selected pixel that occurred before are logically summed by the logic sum gate 707 to be deflected. Stored in flop 707.

On the other hand, if the next input pixel is judged to be a selection (a carry occurs), the pixel is stored in the flip-flop 704. The pixels stored in the flip-flop 704 are logically-computed by the logic sum gate 7111 with the output of the flip-flop 708 (the previously unselected pixel) and then the data input terminal of the deserial converter 714 ( DATA_IN). At this time, the output of the AND gate 712 is provided to the clock terminal CLK of the serial-to-parallel converter 714. This is because the carry from the full adder 702 is applied to the input terminal of the AND gate 712. The output of the AND gate 712 is also applied to the clock terminal CLK of the counter 713. The counter 713 is an octal counter that counts the number of serial data to make eight valid serial data into one byte of parallel data. Whenever the S1 signal, which is the output of the logic sum gate 712, is generated, the counter 713 increments and counts the counting value by one, so that the serial pixel sequence input to the serial-to-parallel converter 714 becomes effective. It should be noted that a pixel that is not selected and stored in the flip-flop 708 must be logically ORed once to the first pixel to be selected next. The inversion delay 710 receives an S1 signal for the flip-flop 708. Clear it. The serial / parallel converter 714 converts the serial pixel sequence S7 provided from the logic sum gate 711 in parallel and outputs the same to each output terminal DO through 07. The pixel columns output in this parallel conversion are stored in the image memory 304 through the data bus, and are printed by the printing unit 306 or transmitted to the outside by the communication unit 307.

FIG. 8 is a diagram showing the operation timing of the horizontal reduction unit 303B operating as shown in FIG.

CLK_H2 in FIG. 8 is the same as CLK_H2 in FIG. That is, this is a new horizontal pixel transfer clock generated in the vertical reduction unit 303A. The carry is a carry signal output from the full adder 702 of FIG. The full adder 702 adds the value of the conversion ratio register 701 and the value of the diffusion ratio register 703 in synchronization with the falling edge of CLK_H2. The carry has a conversion ratio of 0.7 (a conversion ratio of 70 throughout the present specification is In this case, the output value of the full adder 702 is used. The S1 and S2 signals are output as the CLK_H2 and the carry are ORed by the AND gate 712 and the AND gate 705. The octal counter 713, the deserializer 714, and the deflip are output. Provided by the clock of the flop 704. The S3 signal is a signal in which the S1 and S2 signals are output by being inverted by the power generation delay element 710 and used to clear the deflip-flop 708. The S4 signal is a signal inverting the carry, and the S5 signal is a signal obtained by performing an AND operation on the S4 signal and the CLK_H2 by the AND gate 709. The S6 signal is an output signal of the flip-flop 708, and when the S5 signal is a rising edge, the signal S2, which is a series of pixels provided from the vertical reduction unit 303A, and its own signal one clock before One result is output and the output is cleared every time the S3 signal has zero.

Referring to FIG. 8, it can be seen that the flip-flop 704 and the flip-flop 708 operate at different clocks. When the flip-flop 704 operates, the flip-flop 708 does not operate. When the flip-flop 708 operates, the de-flop flop 704 does not operate. This is because the deflip-flop 704 outputs only the pixels on which the carry occurs, and the deflip-flop 708 functions to temporarily store the pixels on which the carry does not occur. The signal S7 is a signal that is output when the output signal of the deflip-flop 704 and the output signal of the deflip-flop 708 are logically operated by the logic sum gate 711. The data input terminal of the serial-parallel converter 714 ( DATA_IN). Since the input of the serial-to-parallel converter 714 is valid at the falling edge of the S1 signal, the portion indicated by the hatched portion of the S7 signal has no effect. It can be seen that when the value of the pixels discarded without being selected in the S7 signal is 1 (indicated by the hatched in FIG. 8), the value is diffused into the next selected pixel to be ORed. Of course, even if the pixel value that is not selected and discarded is 0, the logical sum operation is performed, but the result of the logical sum operation has no effect.

9 is a view showing an example in which the image image is reduced in the vertical direction and the horizontal direction by the image image reduction apparatus according to the present invention. FIG. 9 (a) is a view showing the result of the image image being reduced by the vertical reduction unit 303A. FIG. 9 (b) is a horizontal reduction unit (the image image shown in FIG. 9 (a). Is a view showing the result reduced by 303B). Compared with FIG. 2 showing a reduction result according to the prior art, it can be seen that the image image reduction device according to the present invention reduces the distortion by preserving more of the outline components when the image image is reduced.

As described above, the present invention provides an apparatus for subsampling an image image to reduce it in the vertical direction and the horizontal direction. These devices can only use a low speed CPU because they only need to provide a conversion rate from the CPU. Accordingly, there is an advantage that the processing time can be shortened when the image image is reduced. In addition, since the outline component of the image image can be preserved using such a device, important information can be prevented from being lost and image quality can be prevented from being degraded.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (7)

An apparatus for reducing an image image in a vertical direction, the apparatus comprising: a first register for storing a preset reduction ratio, a second register for storing a preset diffusion ratio, and a reduction ratio stored in the first register and the second register, respectively And a full adder for totally adding the diffusion ratio and outputting a full addition value to be used as the diffusion ratio to be stored in the second register and a carry value indicating whether the image image of each line is selected. Judging means for judging whether or not to select an image image of each line when inputted to the camera; Storage means for temporarily storing an image image determined as a line not selected by said discriminating means; An image image configured to logically combine the image image and the image image temporarily stored in the storage means when the image image determined as the line to be selected by the discriminating means is output and output the image image reduced in the vertical direction. Shrinking device. 3. An image image reduction apparatus according to claim 2, wherein said storage means is a line buffer memory. An apparatus for horizontally reducing an image image, comprising: a first register for storing a preset reduction ratio, a second register for storing a preset diffusion ratio, and a reduction ratio stored in the first register and the second register, respectively And a full adder for totally adding the diffusion ratio and outputting a full addition value to be used as a diffusion ratio to be stored in the second register and a carry value indicating whether each pixel is selected, and an image image when a predetermined image image is inputted. Discriminating means for discriminating whether or not to select each pixel of the pixel according to the carry value; The image image reduction which consists of a logical sum gate which logically combines this pixel and the pixel temporarily stored in the said storage means when a pixel discriminated as a pixel which is not selected by the said discrimination means is input, and outputs the image image reduced in the horizontal direction. Device. 6. An image reduction apparatus according to claim 5, wherein said storage means is a flip-flop. An apparatus for reducing an image image, the apparatus comprising: a first register storing a preset first reduction ratio, a second register storing a preset first diffusion ratio, and a first stored in the first register and the second register, respectively. A first full-add value to be used as the first diffusion ratio to be stored in the second register by totally adding the first reduction ratio and the first diffusion ratio and a first carry value indicating whether to select an image image of each line; A first discriminating means comprising a full adder for discriminating, according to the first carry value, whether or not to select an image image of each line when a predetermined image image is input in line units; First storage means for temporarily storing an image image of a line determined to be a line not selected by the means when it is input; Outputting a vertically reduced image image by logically combining the image image and the image image temporarily stored in the first storage means when the image image of the line determined as the line to be selected by the first discriminating means is input; 1 logical gate; A third register storing a preset second reduction ratio, a fourth register storing a preset second diffusion ratio, and a second reduction ratio and a second diffusion ratio stored in the third register and the fourth register, respectively. And a second full adder for outputting a second full add value to be used as a second spreading ratio to be stored in the fourth register and a second carry value indicating whether to select each pixel, from the first logical sum gate. Second discriminating means for discriminating whether or not to select each pixel of the image image when the image image is inputted according to the second carry value; Second storage means for temporarily storing a pixel identified as a pixel not selected by said second discrimination means when it is input; And a second logic gate configured to output a horizontally reduced image image by logically combining the pixel and the pixel temporarily stored in the second storage means when the pixel determined as the pixel to be selected by the second discriminating means is input. Image image reduction device characterized in that. 6. The image image reduction device according to claim 5, wherein said first storage means is a line buffer memory. 6. An image reduction apparatus according to claim 5, wherein said second storage means is a flip-flop.