JP2000011088A - Method for exracting feature information of read image, image processor and mail address reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain feature extraction synchronized with a reading speed in character recognition for a mail address or the like and to make it unnecessary to prepare a frame memory for temporarily storing the whole pixel density information of a read surface. SOLUTION: The system consists of a scanner 101 for photoelectrically converting the address surface of a mail, a distortion correction part 102 for a read image, a feature extraction part 106, an image information processing part 103 having two feature memory groups and capable of dividing the image data of the address surface into horizontal strips and processing these divided strips in parallel, an address recognition part 104 for reading out an address based on plural feature information, and a line synchronizing part 108 for synchronizing the operation of each part with an image reading speed in each line of main scanning. The feature extraction part 106 has a function for outputting low accuracy multi-valued reduced data for recognizing an address area and high accuracy binary data for recognizing an address and an adjacent processing part for entering and temporarily storing the end part pixel data of adjacent strips.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus, and more particularly to a method for extracting characteristic information of an image read from a mailing address or the like for use in character recognition.

[0002]

2. Description of the Related Art A mail address automatic reading / sorting machine that sorts documents according to a delivery destination based on a read image has been put to practical use. In this apparatus, postal matters (electronic documents are converted into actual documents by a printing machine) are read one by one by a scanner, and a postal code, a destination address, and the like are automatically recognized, and sorted into sorting boxes corresponding to the destination address.

For example, Japanese Patent Application Laid-Open No. 9-75860 discloses a "separator, address recognition apparatus and address recognition method". An image of a mail is read by an optical reading apparatus, and an address area is detected.
A method is shown in which a character line is cut out from the area, quantization is performed on the portion, and recognition processing is performed after cutting out the character. Japanese Patent Application Laid-Open No. 7-311845 discloses a method in which an image processing area is divided into a plurality of strips and image processing is performed on each strip in parallel. At this time, the pixel data of the end of the adjacent strip is temporarily stored, and the pixel data of the adjacent strip that is temporarily stored when performing the filter operation on the pixels at the left and right ends of the strip is used.

[0004]

However, in the above-mentioned conventional method, in order to cut out the address area, first, a frame memory for temporarily storing the grayscale values of the pixels on the entire address surface of the postal matter is required. Further, in the sequential processing in which character lines are cut out and stored, and compression processing is performed for each line, a frame memory for storing a processing result each time is required. In addition, since a line including a character is cut out and then quantization is performed only on that portion, there is a problem that character recognition cannot be performed if the line is not cut out properly.

Further, the method of dividing an image region into strips and performing parallel processing requires a memory for temporarily storing image data at the end of an adjacent strip, and the number of pins of the processing unit is reduced in order to exchange the data. There is a problem of increasing.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the problems of the prior art and to extract characteristic information for character recognition in units of main scanning lines in synchronization with the speed of image reading, and thereby to extract characteristic information. An object of the present invention is to provide an image processing apparatus which does not require a frame memory in each process of extraction.

In addition, a method and an apparatus are provided for extracting characteristic information used for cutting out a character area and characteristic information for interpreting the meaning of characters for character recognition by parallel processing so as to synchronize with the image reading speed. Is to do.

Further, a method and an apparatus for providing a plurality of the above-described parallel processing functions so as to synchronize with a high image reading speed and sharing and processing an image area obtained by dividing a frame in the sub-scanning line direction are provided. is there. Further objects of the present invention will become apparent through the following description.

[0009]

According to the present invention, there is provided a method for extracting characteristic information for character recognition from image information read by scanning a target surface including character information. As first feature information for detecting a character region having a character, low-definition multi-value data obtained by performing multi-value reduction processing on the image information is acquired, and character information in the character region is recognized. Acquiring high-definition binary data obtained by binarizing the image information as second characteristic information, and extracting the first and second characteristic information by parallel processing in units of main scanning lines. I do.

[0010] Further, as third feature information for detecting a character string in the character area, after the binarization processing, two-dimensional information is obtained.
The method is characterized in that medium-definition binary data subjected to value reduction processing is extracted by parallel processing with the first and second feature information.

Further, the parallel processing for extracting each feature information is performed in synchronization with the image reading speed, that is, the main scanning line.

The threshold value used in the binarization processing is obtained by calculating an average value of pixel grayscale values in a block including a plurality of pixels adjacent to a pixel to be processed, and similarly calculating a plurality of blocks adjacent to the block. Multiplied by a constant to the maximum value among the average values obtained, the first binarization threshold candidate (TH1)
The value obtained by subtracting a constant from the maximum value is defined as a second binarized threshold candidate (TH2), and an arbitrary constant is defined as a third threshold candidate (TH3). Is selected to determine the final binarization threshold (TH). Here, TH3 is used when TH3 is maximum or minimum, and TH1 or TH1 is used otherwise.
Select the smaller of 2.

In the case where an image frame corresponding to the target surface is divided into a plurality of image regions in the main scanning direction and feature information extraction of each image region is performed in parallel, a main scanning line of the image region to be processed is provided. In addition to the above pixel data, pixel data at the end of the main scanning line in another adjacent image area is taken in. In this case, the threshold value used for the binarization processing is a threshold value of an adjacent block calculated based on the edge pixel data when the block including the processing target pixel is located at an edge adjacent to another image area. The determination is made based on the maximum value of the average value in a plurality of blocks including the average value.

An image processing apparatus according to the present invention includes a scanner for scanning and scanning a target surface including character information, a characteristic information processing apparatus for extracting characteristic information for character recognition from the read image information, and a characteristic extracting apparatus. A memory for storing information, and a recognition device for performing character recognition based on feature information in image frame units corresponding to the target surface, and performing an extraction process by the feature information processing device by scanning a main scanning line by the scanner. A line synchronizing means for synchronizing the image frame with the image data, and performing the character recognition by the recognition device after the extraction processing for all the main scanning lines of the image frame.

[0015] The information processing apparatus may further comprise: first feature information extracting means for extracting low-definition multi-value data subjected to multi-value reduction processing to detect a character area in the image frame;
A second feature information extracting means for extracting high-definition binary data which has been binarized for recognizing characters in the character area is provided so as to be capable of parallel processing.

Further, an output control means for making the output timings of the respective characteristic information different from each other is provided, and the information is output to the memory via one bus.

Furthermore, a plurality of sets of the memory connected to the feature information processing device and the bus are provided, and a plurality of image areas divided in the sub-scanning direction of the image frame are processed in parallel.

A mail address reading apparatus according to the present invention extracts characteristic information from image information obtained by reading a mail address surface,
In an apparatus for recognizing an address based on feature information in a frame unit, a plurality of the image processing apparatuses are provided, and images read from the scanner are sequentially distributed to the image processing apparatus in a frame unit or a fraction thereof. And perform parallel processing.

Alternatively, a plurality of the above image processing apparatuses are provided, processing parameters for each feature extraction processing are set differently, and images read from the scanners are simultaneously processed in parallel by each image processing apparatus. , Different image processing results corresponding to the image processing are obtained. Thereby, the accuracy of the automatic reader can be improved.

Further, from one of the plurality of image processing apparatuses,
The system is configured to output the binary fine-scaled medium-definition binary data to the display device without performing the compression process, so that when the automatic reading is not possible, the human can confirm the postal code written and input from the keyboard. To help.

The operation of the present invention will be described with reference to an example of a mail address reading device having the above configuration. The address plane is converted into digital image data by photoelectric conversion. In synchronization with the main scanning line, distortion correction of image data and extraction of feature information are performed. As the feature information of the image, high-resolution binary data, low-resolution binary data, low-resolution multi-value data, density histogram, and the like of pixels on the entire destination surface are extracted, and the results are stored in a feature memory.

Then, the character recognition of the postal code and the address is performed by the address recognition means using the characteristic data of the entire address surface. Here, since the photoelectric conversion, distortion correction, feature extraction, and data writing to the feature memory are performed completely in synchronization with each main scanning line, the pixel density data of the entire destination surface after the distortion correction is obtained. There is no need for a frame memory to temporarily store.

In order to perform the feature processing at the same image processing speed as the photoelectric conversion processing, the image frame is divided into a plurality of strips, and the image processing is performed on each of the strips in parallel. At this time, in addition to the main scanning pixel data to be processed by itself, pixel data at the end of an adjacent strip is fetched and used when pixel data at the other end is required, such as calculation of an average value at a boundary. This allows line-synchronous image processing and eliminates the need to exchange data between adjacent strips. Incidentally, the image processing speed when dividing into two right and left strips is such that 512 pixels on the left and right in one main scanning line (1024 pixels) are output in parallel at a speed of 16 MHz / pixel.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a mail address reading device according to an embodiment. The scanner 101 optically reads the address surface of a mail and converts it into an electric signal. This can be realized by a light source, a lens, and a CCD line sensor that illuminate the reading surface (not shown). Distortion correction unit 10
Numeral 2 corrects the light amount fluctuation of the light source at each pixel position in the main scanning direction and corrects the characteristics of the photoelectric conversion element of each pixel of the CCD line sensor, and normalizes white to 255 and black to 0, and outputs them.

The function of the destination image processing unit 103 includes a feature extracting unit 106 and a feature memory 107. Feature extraction unit 1
Reference numeral 06 extracts image information such as a destination address and a postal code from image data of a mail. The feature memory 107 stores a plurality of pieces of feature information output from the feature extracting unit 106.
The line synchronization unit 108 activates image processing for one line in the main scanning. The line synchronization unit 108 activates the scanner 101, the distortion correction unit 102, and the destination image processing unit 103 in units of main scanning lines, and each unit executes processing at the same speed as one main scanning line. The address recognition unit 104 uses the output of the address image processing unit 103 to cut out the address area, recognizes the address from the image information of the address, converts the address into code information, and outputs the code information. The VDT 105 is a backup when automatic reading is impossible, and displays an output from the address image processing 103-5 on a display.

The destination image processing unit 103 of this embodiment has two sets of a feature extraction unit 106 and a feature memory 107. Accordingly, for example, when the processing speed of the destination image processing unit 103 requires 32 MHz, one set of processing speed is set to 16 MHz.
z, and the image is divided into left and right halves in the main scanning direction and processed in parallel. That is, 1024 pixels in the main scanning direction are sequentially shifted to 32 MHz.
Instead of processing at z, the pixels are divided into 512 pixels on the left and right, and each of the pixels is processed at 16 MHz sequentially in 512 pixels in the main scanning direction.

Further, the address image processing unit 103 and the address recognition processing unit 104 are set as one set, and four sets are configured in parallel. For example, if the reading time per mail is 1 second and the processing time of the address recognition unit 104 takes 4 seconds, the distortion correction unit 10
Address image information output continuously from 2 to 1 second is distributed to the address image processing units 103-1 to 103-4 one by one in order and processed. Thereby, performance equivalent to one set processing in one second can be realized. Of course, the address image information is halved.
It is also possible to make a change such as distributing one by one.

Alternatively, in a parallel configuration of four sets, processing parameters such as binarization, binary reduction, and multi-value reduction of the feature extraction unit 106, which will be described later, are different for each set, and the same destination image information is simultaneously applied to each set. To be processed in parallel. Since the recognition accuracy of each set of destination characters differs depending on the character type and the shading value, the recognition rate of low-density characters and handwritten characters that are difficult to recognize can be improved as a system. Of course, the parameters may be changed in units of two of the four sets, and one piece of address image information may be transmitted in units of the two sets.

FIG. 2 shows a processing flow of the mail address reading apparatus. Scanner 101 reduces the mailing address to 20
The photoelectric conversion is performed at a resolution of 0 dpi (s101), and distortion correction is performed.
2 to perform shading distortion correction and gamma correction, and output multi-valued pixel data (8 bits / pixel) (s10
2). The number of pixels of the image per mail is the main scan 102
There are four pixels and 1920 pixels in the sub-scanning direction. At this time, one main scanning line (1024 pixels) is divided into left and right 512 pixels, and the signals are output in parallel at a speed of 16 Mhz / pixel from two signal output buses.

The feature extracting unit 106 extracts four types of image feature information in units of 512 pixels per main scanning line (s103).
It is stored in the feature memory 107 (s104). The feature information is a histogram showing the density frequency distribution of the image, low definition multi-value data of 33 dpi, medium definition binary data of 100 dpi, 200 dpi
Are four types of high-definition binary data.

Next, when the address image processing unit 103 detects that the processing of all lines of one mail has been completed (s1).
05), the image feature information of one mail stored in the feature memory 107 is transferred to the address recognition unit 104, and character recognition processing is performed by the address recognition software. First, the position where the address is described is estimated from the histogram (s
106), the address area is cut out from the low-definition multi-value image (s10).
7). Thereafter, a character string is cut out using the medium definition data (s108), and the character is recognized using the high definition binary data (s108).
109).

Since the character recognition process takes several seconds for one message, the multivalued image data of the next mail is transferred to the adjacent standby address image processing unit 103, where the recognition process is executed. Further, for mail that could not be addressed, the address image processing unit 103-5 executes the address processing in parallel with the recognition process.
Is operated in the binary data output mode, and the uncompressed binary data (10
0dpi). The binary image is displayed on the VDT 105 so that a human can read the postal code and input it from the keyboard.

Hereinafter, the function of the feature extracting unit 106 will be described in detail. FIG. 3 shows a functional block diagram of the feature extracting unit. The edge emphasizing unit 201 corrects blurring of an image outline at the time of image reading. The average value calculation unit 202 obtains the average value of the density values of a total of nine pixels of three main scanning pixels and three sub-scanning pixels adjacent to each other. The binarization unit 203 converts the pixel information represented by 8 bits into 1
Convert to bit pixel information. The noise removal unit 204
It removes isolated points that appear in the value output and irregularities that occur in the outline of characters. The binary reduction unit 205 converts image data having a resolution of 200 dpi into image data having a resolution of 100 dpi. Data compression unit 2
Reference numeral 06 encodes the binary image data and compresses the amount of information.
The multi-value reduction unit 207 converts 66 dpi average value data to 33 dpi. The histogram 208 detects the density distribution of the image data of the entire 33-dpi mail.

When the mail extraction is divided into two left and right strip regions by the two feature extraction units 106 and processed in parallel, the edge enhancement unit 201 and the binarization unit 203 determine the binarization threshold value by the peripheral pixels. An operation including the above data is required.
That is, in the case where image processing is performed on the pixels at the right end of the left strip and the left end of the right strip, image data of the ends of the adjacent strips are required. The adjacent processing unit 209 receives the image data of the end of the adjacent strip and causes the image processing of the end of the strip to be performed normally. The output control unit 210 controls the output timing of the image data output from each unit,
Output to the feature memory 107 via one input / output bus. This can be realized by a selector which is a logic circuit.

Next, the operation of the feature extracting unit 106 will be described. The feature extraction unit 106 of this embodiment has a feature data extraction mode including high-definition binary compression processing, medium-definition binary compression processing, low-definition multivalued data processing, and histogram extraction processing. 107 is stored. It also has a display mode and a through mode.

First, the compression processing of high definition binary data will be described. The high-definition binary data is used by the address recognition unit 104 for recognition of the destination address of the postal matter and the postal code in character units.
The 8-bit data per pixel from the distortion correction unit 102 is input to the edge enhancement unit 201 and the average value calculation unit 202, and the 3 ×
Edge enhancement and average value calculation are simultaneously processed through a three-pixel two-dimensional filter. When the input data is the left end or right end pixel, adjacent distortion correction data (vertical 3 pixels) is taken into the 3 × 3 pixel two-dimensional filter via the adjacent processing unit 209.

The output of the edge emphasizing section 201 is output to a binarizing section 2
At 03, the data is converted into binary data based on the threshold value (TH). The threshold value (TH) is obtained from the averaged multi-value data as described later. If the binarization results in a specific pattern, the noise is removed by the noise removing unit 204 as noise, and then high-resolution binary data of 200 dpi, which is the same as the resolution of the scanner, is obtained.

Thereafter, the data compression unit 206-1
The data is compressed by run-length encoding for each main scanning line, and output to the feature memory 107 via the output control unit 210. The compressed data of each line differs depending on the number of pixel changes. Therefore, the absolute address where the compressed data of each line is stored is output to the pointer storage area of the feature memory 107 so that the address of the memory where the compressed data of each line is stored can be immediately detected.

Next, the medium definition binary compression processing will be described. The medium-definition binary data is used by the address recognition unit 104 to detect an address line (character string) on the mail. This processing branches from the noise removal unit 204 of the high-definition binary compression processing, and the binary reduction unit 2
At step 05, four pixels of 200 dpi binary output main scanning two pixels and sub-scanning two pixels are converted into one pixel, and the characteristic memory 1 is set as 100 dpi.
07. As the output data, similarly to the high-definition binary data, the compressed data of each line and the storage start address are output.

Next, the low definition multi-value data processing will be described.
The low-definition multi-value data is used for detecting an address label area on a mail and extracting a histogram. The multi-value reduction unit 207 is 33
Outputs multi-level (8 bits / pixel) data of dpi. That is, an average value is calculated from 9 pixels of 3 pixels in the main scanning and 3 pixels in the sub-scanning, and the average value is determined as one pixel of 66 dpi.
The pixel is output as 33 dpi data.

Next, the histogram extraction processing will be described.
The histogram extracting unit 208 calculates the number of pixels for each of the 256 low-definition multi-valued pixel values (0 to 255) of the entire destination surface and outputs the number to the feature memory 107. When detecting the area of the address label from the low-definition multi-valued data, the address recognition unit 104 binarizes the low-definition multi-valued data of the entire address surface, and sets “1” of the binarization result to the label area and “0”. "
Is determined as a background area. When obtaining the binarization threshold value, a gray value histogram is used.

By the way, in the binary reduction unit 205, the binarization result of 100 dpi is directly processed without compression processing in the feature memory 10.
7 is provided. When operating in this mode, the output control unit 210 does not output the results of feature extraction in other modes. Then, the image of the address side of the postal matter for which the address could not be recognized is converted into V by high-resolution binary data.
The zip code is displayed on the DT 105 so that a human can recognize the zip code written on the DT 105 and input it from the keyboard.

The 200 dpi multi-valued (8 bits / pixel) input data, which is distortion correction data, is directly stored in the feature memory 1.
07 has a through mode. Even when operating in this mode, no other feature extraction result is output. This through output is input to a simulator (not shown), which performs distortion correction processing and feature extraction processing, and compares the result with the output result of the actual machine to facilitate debugging.

Hereinafter, the configuration and operation of each function of the feature extraction unit 106 will be described in detail. FIG. 4 shows an embodiment of the edge enhancing unit. In the configuration of the edge emphasizing unit 201 shown in (a), a line buffer 301 is a line memory for storing image data for three continuous main scanning lines. The configuration of the replacement buffer is such that when image data of n lines is input, data of lines n-1, n-2, and n-3 are output. The line memory 301 can be realized by an SRAM.

The latches 302 to 307 have a function of temporarily holding image data, and can be realized by flip-flops.
The multiplication 308 has a function of increasing the input data value by five times, the addition 309 has a function of adding two input data, and the subtraction 311
Is a function of subtracting the data input to the lower part from the data input to the upper part of the two inputs, and can be realized by a logic circuit. Select 312 is one mail left and right 2
When processing is performed on pixels belonging to the end of the block in charge when processing is performed in parallel by dividing the image into two blocks, the function is to select and input image data at the end of an adjacent block.

With the above configuration, it becomes possible to multiply the pixel value by 5 for each pixel on the n-2 line and to subtract the total value of the four pixels vertically and vertically adjacent thereto from the target pixel value. Is obtained.

FIG. 4B shows an operation example of the edge emphasizing unit. The image data a to i represent nine pixels adjacent to each other. Here, e located at the center is the target pixel of the edge enhancement processing, and the edge enhancement filter calculation for the pixel e executes Expression (1) with the edge enhancement result as E (e).

[0048]

E (e) = 5 · e−1 · a−1 · c−1 · g−1 · i (1) The above processing is sequentially performed one pixel at a time in the main scanning direction, so that each pixel is obtained. Is obtained.

FIG. 5A shows an embodiment of the average value calculating section. The line buffer 401 of the average value calculation unit 202 is a line memory that stores image data for three consecutive main scanning lines. When inputting n-line image data, n-
An alternate buffer is used to output data of 1, n-2 and n-3 lines. Latches 402 to 405 function to temporarily hold image data, and adders 406 to 409 and 4
Reference numeral 12 denotes a function for adding two input data.

The 1/8 conversion 410 is a function of dividing input data by 8, and can be realized by shifting data represented by a binary number to lower 3 bits and filling upper 3 bits with 0.
The 1/64 conversion 411 is a function of dividing input data by 64, and can be realized by shifting data represented by a binary number to lower 6 bits and packing 0 into upper 6 bits. The addition 412 adds the outputs of the 1/8 conversion 410 and the 1/64 conversion 411.

That is, 1/9 operation is reduced to 1/8 and 1/64
Therefore, the circuit scale is reduced as compared with the case where 1/9 is realized by a logic circuit. With this unique configuration, an average value of a total of 9 pixels of 3 pixels in the main scan × 3 pixels in the sub-scan can be output as an approximate value.

In the case where one mail is divided into two right and left strips and processed in parallel, the selection 413 is input via the adjacent processing unit 209 when processing is performed on the pixels belonging to the end of the strip in charge. This function selects the average value of the nine pixels at the end of the adjacent strip. In other words, if it is in charge of the left strip, the average value of the right strip end is selected immediately after the processing of one main scanning line. In addition, when it is in charge of the right strip, the average value of the left strip end is selected immediately before the processing of one main scanning line.

FIG. 5B shows an operation example of the average value calculating section. The image data a to i represent nine pixels adjacent to each other. The averaging filter operation for these nine pixels is
The average value output of the image data a to i is A (e),
Execute equation (2).

[0054]

A (e) = 1/9 · (a + b + c + d + e + f + g + h + i) (2) The above process is sequentially performed in the main scanning direction and the sub-scanning direction for every three pixels, thereby obtaining an average value output for every nine pixels.

FIG. 6 shows an embodiment of the binarizing section. The line buffer 501 is a line memory that stores image data for three consecutive main scanning lines. When image data of n lines is input, a replacement buffer is provided so that data of lines n-1, n-2, and n-3 is output.

The latches 502 to 506 have a function of temporarily holding image data, and can be realized by flip-flops.
The maximum values 507 and 508 are a function of outputting the maximum value of the three input values, and the maximum value 509 is a function of outputting the larger of the two input values. These can be configured by a comparator and a selector.
Threshold rate 510 and threshold difference 5 as processing parameters
15 and the lower limit 511 are set in each register from the control side before the operation starts. The multiplication 512 is a function of multiplying two inputs and can be realized by a multiplier.

The 1/256 conversion 513 converts the input data into 256
This function can be realized by shifting data represented by a binary number to the lower 8 bits and filling the upper 8 bits with 0. The subtraction 516 is a function of subtracting the value of the threshold difference 515 from the output of the latch 504. The minimum value 517 is 2
This function outputs the smaller of the two inputs. Comparison 5
14 compares two input values, and when the upper value is large, 1
(Black), and 0 (white) otherwise.

According to the above configuration, the vertical maximum value which is the maximum value of three consecutive average values in the vertical direction at the maximum value 507 is detected first. Next, 3 continuous in the horizontal direction at the maximum value 508
Detects the maximum of the two vertical maximums. As a result, the maximum value of a total of nine average values composed of three average values in the vertical direction and three average values in the horizontal direction is obtained.

Next, by using the threshold rate 510, the multiplication 512 and the 1/256 conversion 513, the maximum value of the 9 average values is
One candidate T of the binary threshold value obtained by multiplying the value multiplied by the threshold rate
H1. At this time, the original threshold ratio is a number of 1 to 0, but for hardware reasons, it is set to an integer value of 255 to 0, and after multiplication with the maximum value of 9 average values, it is 1/256.
It was realized by doing.

Further, a value obtained by subtracting the value of the threshold value difference 515 from the maximum value of the nine average values in the subtraction 516 is set as another candidate TH2 for the binarization threshold value. Then, the smaller one of TH1 and TH2 is selected with the minimum value 517, and is set to TH12.
Next, the value TH set to the lower limit value 511 with the maximum value 509
Compared with 3, when the binarization threshold TH12 is large, it is set as the final binarization threshold TH. Otherwise T
H3 is adopted as the binarization threshold TH. The reason is that when the binarization threshold value is obtained from the black image area on one side, the binarization threshold value is smaller than the value of the black image data. This is to prevent the binarization result from being changed to 0 (white).

FIG. 7 shows an operation example of the binarizing unit. In FIG. 5A, a to i each indicate an average value of nine pixels obtained by the averaging unit 202 in FIG. (B) is an example of an operation for obtaining a threshold value, and obtains a maximum value from a to i. Here, c
Becomes the maximum value. Next, the threshold value 510 is multiplied by the pixel value of c to obtain threshold value candidates TH1 and TH2. In this case, since TH1 <TH2 and TH1> TH3, the final threshold value TH = TH1. (C) is another calculation example, in which TH obtained from the maximum value f among a to i is set.
1 and TH2 are both lower than TH3.
In this case, TH = TH3.

The binarizing section 203 compares the threshold value TH obtained by the above calculation with the edge emphasis data, outputs '1' (black) when the edge emphasis value <TH, and outputs '1' (black) otherwise. Outputs 0 '(white). Note that TH1, TH2, TH
Automatically select TH from two of the three candidates,
A method in which one candidate is fixedly selected as TH from the beginning is also possible.

FIG. 8 shows an embodiment of the noise removing section. The line buffer 601 is a line memory that stores image data for three consecutive main scanning lines. When image data of n lines is input, a replacement buffer is provided so that data of lines n-1, n-2, and n-3 is output. Latch 6
02 to 607 are functions for temporarily holding image data, and the noise removal logic 609 is a function for performing noise removal processing using patterns of the binary data a to i.

FIG. 9 shows an operation example of the noise elimination unit.
(A) shows the pixel positions of the binarized data a to i held in the latches 602 to 607. (B) shows the dot patterns of the binarized data a to i before and after the noise removal processing, and reflects the logic pattern of the noise removal logic 609. The first from the left is a pattern for removing black isolated points, and the second is a pattern for removing white isolated points. The remaining four are patterns for removing the concave portions on the contour lines in the horizontal and vertical directions. This processing can be realized by a combination of a logical product and a logical sum.

FIG. 10 shows an embodiment of the binary reduction section.
In the configuration of the binary reduction unit 205 shown in (a), a line buffer 701 is a line memory for storing image data for three consecutive main scanning lines. When image data of n lines is input, a replacement buffer is provided so that data of lines n-1, n-2, and n-3 is output. Latch 702-70
Reference numeral 7 temporarily stores image data. Reduction operations 709 to 71
Reference numeral 2 denotes a function for reducing and converting data of two consecutive pixels into one pixel, which can be realized by a logical product, a logical sum, and an inverter.

In the above configuration, first, two pixels, pixel c and pixel b, are converted into pixel x in the (n-1) th line. At this time, the pixel a next to the pixel b is referred to, and the reduction operation 709 is performed.
Execute In this calculation, when the pixel c is 1 (black), the pixel x outputs 1 (black). If the pixel c is 0 (white) and both the pixels a and b are 1 (black), there is a high possibility that the pixel c is a white thin line in a black area, and the pixel x outputs 0 (white). Calculation. At the same time, pixels d, e, f and g,
The same reduction operation is performed for h and i. By the above processing, the 縮小 reduction in the main scanning direction is simultaneously performed for three lines,
You have done it.

Next, a reduction conversion 712 is performed on the outputs x, y, and z. This is a 縮小 reduction operation in the sub-scanning direction, and the reduction logic is the same as in the main scanning.
As a result of the above processing, a total of 4 pixels of 2 pixels for main scanning and 2 pixels for sub-scanning
Processing for converting a pixel into one pixel can be realized.

FIGS. 10B to 10E show examples of the operation of the binary reduction section. (B) shows the output before and after the reduction when the reduction logic 709 in the main scanning direction is executed, and is a process for converting two pixels of the pixel b and the pixel c into one pixel bc.
When both b and c have the same color, bc naturally has that color. As an example of a different case, in (c) and (d), the color becomes black, and when there is a black pixel among the white pixels, black is prioritized. However, when c is white and a and b are black as shown in (e), the logic is to give priority to white.

FIG. 11 shows an embodiment of the data compression section.
The configuration of the data compression unit 206 shown in FIG.
1 to 805 are functions for temporarily holding image data. The change point detection 806 is a function of outputting 1 when the binary output of two consecutive pixels is different. The constant 807 is a function for outputting 0. When the data value is represented by 8 bits, 8 is used.
All bit signal lines are fixed to the ground level. The run length counter 808 has a function of counting the number of pixels of the same output that are continuous in the main scanning direction. The counter 808 is reset each time the output of the change point detection 806 becomes 1.

The selection 809 is “0” from the constant 807 or
This function selects and outputs the input from the run length counter 808. This can be realized by a selector of a logic circuit. The output control 810 has a function of outputting a data write command to the feature memory 107 when a change point detection signal is input, a constant 807 and a run length counter 808 as output data to the memory.
And the latches 803 and 80 for outputting two bytes of data in parallel from the selection 812.
This is a function for selecting whether to output a set of 4 or a set of 804 and 805.

The address counter 811 controls the output control 810
This function outputs the write address to the memory by counting the number of write commands from the memory. The selection 812 is a function of selecting whether to output a pair of latches 803 and 804 or to output a pair of 804 and 805 when outputting 2-byte data in parallel. In this process, since the data bus width is 2 bytes, the memory access speed is 1/1 of the case of 1 byte.
Can be 2.

The operation according to the above configuration is described as (b-1) to (b-
This will be described in 3). In (b-1), an output example is shown in which five consecutive white (0) pixels are input from the beginning of one line, and then 12 consecutive black (1) pixels are input. First, 1
When white is input at the beginning of the line, the run length counter 80
8 counts the number of consecutive white pixels. Next, when a black pixel is input, the change point detection 806 outputs 1 and the output control 810 latches the output '5' of the run length counter 808 via the selection 809 in the latch 803.

Further, the run length counter 808 is initialized to a count value "1" by the output of the change point detection 806, and counts subsequent black pixels. When 12 consecutive black pixels are input and then white pixels are input, the change point detection 806 outputs 1 and the output control 810 outputs the output '1' of the run length counter 808 via the selection 809.
2 'is latched by the latch 803. At this time, the latch 8
The white run length '5' is shifted to 04. Latch 803
And when 804 stores 2 bytes of data,
If it is a write timing to the feature memory 107, the output control 810 outputs the two bytes.

(B-2) is black (1) from the beginning of one line.
Shows an example in which 16 pixels are continuously input, and then white (0) is continuously input in 58 pixels. When a black pixel is input at the beginning of one line, the output of the leading black detection 813 becomes 1, and the output control 810 causes the latch 803 to latch the output '00H' of the constant 807 via the selection 809. Then, the run length counter 808 counts the number of continuous black pixels. Next, when a white pixel is input, change point detection 806 is performed.
Output 1 and the output control 810 latches the output '16' of the run length counter 808 via the selection 809 in the latch 803. Further, the run length counter 806 detects a change point.
Is initialized to the count value '1'. Then, subsequent white pixels are counted.

When 58 white pixels are successively input and then black pixels are input, the change point detection 806 outputs 1 and the output control 810 controls the output of the run length counter 808 via the selection 809. 58 'is latched by the latch 803. The white run length '16' is shifted to the latch 804. Further, the data "0" indicating the leading black is latched by the latch 805.
Is shifted to At the time when two bytes of data are stored in the latches 803 and 804, if it is a timing to write to the feature memory, the output control 810 outputs the two bytes.

(B-3) shows an example in which a white run length of 268 pixels is continuously input. When the number of white pixels continuously reaches 255, the output control 810 outputs the output '255' of the run length counter 808. If white pixels continue,
The output control 810 controls the constant 807'00 via the selection 809.
H ′ is output to the latch 803. This indicates that the number of black pixels is 0 consecutively. Then, the run length counter is initialized to 1, and the counting of white pixels is continued. And
When the black pixel is input, the change point detection 806 outputs “1”, and the output control 810 latches the count value “13” of the white pixel in the latch 803.

FIG. 12 shows an embodiment of the multi-value reduction unit and the histogram extraction unit. In the configuration shown in FIG.
902, a function for temporarily holding image data, selection 903,
A function 904 selects one of the two inputs. The reduction control 905 includes four pixels of two pixels for main scanning and two pixels for sub-scanning.
This function reduces a pixel to one pixel, and latches multilevel data in the latch 901 every other main scanning line. Further, the multi-level reduction unit 207 generates a clock so that pixel data of the line to be latched is latched every other pixel, thereby latching one of four adjacent pixels to perform a reduction function. Realize. This can be realized by a combination of logic circuits.

The function of detecting the histogram of the gray value of a pixel in one frame according to the present embodiment is unique. The function of writing 0 to the histogram storage area in the memory, the function of outputting the gray value of the pixel as an address of the memory, and It has a function of reading data at the address and writing the result of adding 1 to the value to the address.

That is, in the histogram extracting unit 208, the address counter 906 increments the output value by +1 according to the pixel clock. Constant setting 907,
908 always outputs '0' or '1',
Adds two inputs. The operation control 910 performs control such that the output of the address counter 906 is first selected by the selection 903, and the output “0” of the constant setting 907 is selected by the selection 904. Then, while counting up the address counter 906 from 0 to 255, the feature memory 1
Data '0' is written from address 0 to address 255 of 07. This is because the value of the history memory is initialized to 0 each time a mail is read one by one.

Next, when the input of the mail image data is started, the input of the selection 903 is set as the multi-value reduced data from the latch 901 and is output to the feature memory 104 as an address. Then, the read data from the address in the feature memory 107 is stored in the latch 902. Further, the output “1” of the constant 908 is added to the output of the latch 902 by the addition 909, and the result is written to the corresponding address of the feature memory 107 via the selection 904.

By the above processing, the data in the address having the same value as the pixel data value is incremented by one every time the access is made.
When the image processing for one mail is completed, 0
The total number of pixels for each pixel data of ~ 255 is stored in the feature memory 107, and a histogram is obtained.

FIG. 12B shows the correspondence between the address of the feature memory and the histogram. Multi-value reduction 207
Is output to the feature memory 107 as an address of the multi-valued reduced data input from the CPU, and when the memory data is read, the number of pixels having that gray value is detected. Then, 1 is added to the number, and data is written again to the address, thereby obtaining each gray scale value (0 to 2).
55 (256 patterns) are accumulated. A histogram is obtained in the feature memory 107 by performing the above processing on the entire postal matter.

FIG. 13 shows an embodiment of the adjacent processing section. With the configuration of the adjacent processing unit 209, the shifters 1001 and 1002 have a function of latching pixel data, sequentially shifting the data, and outputting data of three pixels, and can be realized by a shift register. Selections 1003, 1010 and 1014 output one of two inputs. Latches 1004 to 1008 hold pixel data, and additions 1009 and 1013 add two input data. 1/9 conversion 1011 is a function for obtaining an approximate value of 1/9 of the input data, and is a combination of 1/8 conversion of input data by 8 and 1/64 conversion of 64 by an adder. The configuration is the same as in the case of

Here, input of adjacent distortion correction data of two right and left strips to shifters 1001 and 1002 and latch 1004 is performed in parallel. In other words, the first pixel of the right strip is input at the same timing as the input of the first pixel of the left strip, and the 512th pixel of the right strip is input at the same timing as the input of the 512 pixel of the left strip.

If the mail is divided into two strips on the left and right (512 pixels in the main scanning direction), and if the mail itself is processed on the right strip, the shifter 1001 selects the last pixel (51) on each main scanning line of the left strip.
The second pixel) is sequentially latched, and the 512th pixel for three consecutive lines is output. In the case of processing the left strip itself, the shifter 1002 uses the first pixel (1) on each main scanning line of the right strip.
) Are sequentially latched, and the first pixel of three consecutive lines is output.

That is, the feature extraction units 106-1 and 106-
Each of 2 is latched by adding the first or last one pixel adjacent to 512 pixels of the main scan and three lines of one adjacent pixel as one set to form adjacent vertical three-pixel data. . According to this, since there is no need to exchange data between the feature extraction units 106, the number of pins for input / output is not increased.

The adjacent vertical three-pixel data output from the shifter 1001 or 1002 is input to the edge emphasizing unit 201 shown in FIG. At this time, the pixel data of the first pixel of the main scanning of the right strip is input to the latch 302 and the addition 309 via the selection 312. In the edge enhancement of the right strip, the pixel data of the 512th pixel in the main scan of the left strip is selected during the edge enhancement of the first pixel in the main scan.
The signal is input to the latch 302 and the adder 309 via the counter 12.

On the other hand, the latch 1004 has three pixels of 510 to 512 pixels in the main scanning direction of the left strip, and 1 pixel in the main scanning direction of the right strip.
３3 pixels are latched one pixel at a time. In other words, it is latched by adding three pixels from adjacent strips.

Then, the addition 1009, the latch 1005, and the selection 1010 are used to select 51
The sum of the values of a total of 9 pixels for 3 × 3 lines of 0 to 512 pixels is obtained and latched by the latch 1005. Also, by addition 1009, latch 1006 and selection 1010,
An addition value of a total of 9 pixels for 3 × 3 lines of 1 to 3 pixels of three consecutive lines of the right strip is obtained.
Latch to 6.

Next, the average value (approximate value) of the output data of the latch 1005 is obtained by the 1/9 conversion 1011 and latched by the latch 1007. Similarly, the average value of the latch 1006 is obtained and latched by the latch 1008.

As a result, the latch 1007 latches the average value of the nine pixels at the rear end of the left strip in the main scanning direction. The latch 1008 latches the average value of the nine pixels at the leading end of the right strip in the main scanning direction. Accordingly, there is no need to exchange data between strips, and the storage capacity can be reduced as compared with a case where pixel data of another strip is temporarily stored. Latch 1
The output of 007 or 1008 is input to the average value calculation unit 202 of FIG. 5 via the selection 1012, and is input to the binarization unit 203 of FIG. 6 via the selection 413.

In this example, the feature extracting unit 106 determines that the left strip,
It is configured so that it can be used for processing the right strip, but it is fixed for the left strip or the right strip, and only the three pixels at the end of the other strip are latched to obtain the average value of 9 pixels. Is also good.

FIG. 14 illustrates the operation of the adjacent processing unit using the end data of the adjacent strip. (A) shows a pixel block necessary for performing edge enhancement processing on the end pixel e of the right strip, and pixels a, d, and g are pixels belonging to the left strip. For this reason, it is latched in the shifter 1001 and is output to the edge emphasizing unit 201 at the time of edge emphasizing processing of the pixel e of the right strip.

FIG. 9B shows the average value data (A0 to A8) of 9 blocks when the threshold value is calculated by the binarization unit 203 when the end pixel (eg, pixel e) of the right strip is binarized. The positions are shown, and A0, A3, and A6 are average values of the left strip. Therefore, when the binarization threshold value at the left end of the right strip is obtained by latching in the latch 1007,
The value is output to the value conversion unit 203.

FIG. 15 shows an example of a memory map of the feature memory. Register setting unit 1 of output control unit 210 (FIG. 3)
In 101 and 1102, a storage start address of the feature memory 107 for storing the image processing result is set. The register setting units 1101 and 1102 can be realized by flip-flops,
Arbitrary setting values A and B are set in advance from an external CPU.

Since the first histogram stores the number of pixels of each of the 256 gradations, the feature memory 107 requires a 2-byte memory area for each gradation.
Therefore, since the capacity is fixed at 512 bytes, the storage address is fixed at 000H to 1FFH. The low-resolution multi-value data is stored at 200H to 2000H, the middle-resolution binary line head address is stored at 4000H to 42FFH, and the high-resolution binary line head address is stored at 4300H to the address obtained by subtracting 1 from the register setting value A. . Since the output addresses of the storage addresses of the medium resolution binary compressed data and the high resolution binary compressed data vary depending on the image data, the storage areas can be changed by register settings 1101 and 1102, respectively.

FIG. 16 shows an operation time chart of the output control unit. (A) shows the transition of the image processing in the sub-scanning direction, and one section indicates the processing cycle of one line in the main scanning. The write data to the feature memory 107 is high-resolution binary compressed data every line, and medium-resolution binary compressed data is 2
The low-definition multi-value data and the histogram are performed on one line in a line cycle and one line in a six-line cycle. The writing of other feature data other than the high definition binary compressed data is controlled so as not to occur on the same line.

(B) shows the transition of the image processing in the main scanning direction. One section indicates the processing cycle of one pixel. The interface with the feature memory 107 is performed via one bus having a width of 16 bits. One memory cycle is 16 MHz. By making the bus 16 bits wide, the most frequently accessed 8-bit wide high-definition binary run-length data is accessed in an even-numbered cycle when two are ready. Other image feature information is accessed in memory in odd cycles. As described above, by controlling the access cycles of the four types of image characteristic data so as not to overlap in both the sub-scanning direction and the main scanning direction, memory access by one bus is realized.

[0099]

According to the present invention, a low-resolution multi-value reduction and a high-definition binarization are performed on a read image, a character area is cut out by the multi-value reduction data, and the character area is converted into a character by binary data. Since feature extraction for recognition is performed in parallel, character recognition synchronized with the image reading speed can be performed in units of one line of main scanning. This eliminates the need for a frame memory for temporarily storing pixel grayscale data of the entire read screen, pixel grayscale data after character region clipping, and pixel grayscale data after line clipping.

Further, since the image frame is divided into a plurality of image areas (strips) and the image processing is performed on each strip in parallel, the feature processing is performed at the same image processing speed as the photoelectric conversion processing. Can be.

Further, when dividing into a plurality of strips, pixel data at the end of an adjacent strip is added and latched in addition to its own main scanning pixel, so that data is exchanged between the strips during edge processing. And the number of pins and storage capacity of the processing device can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an image information processing apparatus of the present invention and a mail address reading system to which the image information processing apparatus is applied in parallel.

FIG. 2 is a flowchart illustrating a schematic operation of the image information processing apparatus according to the embodiment;

FIG. 3 is a configuration diagram illustrating an embodiment of a feature extraction unit of the image information processing apparatus.

FIG. 4 is a configuration diagram illustrating an embodiment of an edge enhancement unit of the image information processing apparatus.

FIG. 5 is a configuration diagram showing an embodiment of an average value calculation unit of the image information processing apparatus.

FIG. 6 is a configuration diagram illustrating an embodiment of a binarization unit of the image information processing apparatus.

FIG. 7 is an explanatory diagram illustrating an operation of a binarization unit.

FIG. 8 is a configuration diagram illustrating an embodiment of a noise removing unit of the image information processing apparatus.

FIG. 9 is an explanatory diagram illustrating an operation of a noise removing unit.

FIG. 10 is a configuration diagram showing an embodiment of a binary reduction unit of the image information processing apparatus.

FIG. 11 is a configuration diagram showing an embodiment of a data compression unit of the image information processing apparatus.

FIG. 12 is a configuration diagram illustrating an embodiment of a histogram extraction unit of the image information processing apparatus.

FIG. 13 is a configuration diagram illustrating an embodiment of an adjacent processing unit of the image information processing apparatus.

FIG. 14 is an explanatory diagram illustrating the operation of an adjacent processing unit.

FIG. 15 is an explanatory diagram showing an example of a memory map of a feature memory.

FIG. 16 is a time chart illustrating an operation of an output control unit of the image information processing apparatus.

[Explanation of symbols]

101 scanner, 102 distortion correction unit, 103 image information processing unit, 104 address recognition unit, 105 VDT (video data terminal), 106 feature extraction unit, 107 feature memory, 108 line synchronization unit, 201 … Edge enhancement part,
202: Average value calculation unit, 203: Binarization unit, 204: Noise removal unit, 205: Binary reduction unit, 206: Data compression unit, 207: Multi-value reduction unit, 208: Histogram extraction unit, 209: Adjacent processing Unit, 210 ... output control unit, 30
1, 401, 501, 601, 701 line buffer, 609 noise removal logic, 709 to 712 reduction logic, 806 change point detection, 807 constant setting, 808
Run length counter, 809 selection, 810 output control, 8
11: address counter, 812: selection, 905: reduction control, 906: address counter, 907, 908: constant setting, 910: operation control, 1001, 1002: shifter, 1101, 1102: register setting unit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keisuke Nakajima 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Shinichi Shinoda 7-1 Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Inside Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Seiji Oyama 3-10-22 Sakae, Naka-ku, Nagoya-shi, Aichi Japan Sun Inside Chubu Software Co., Ltd. 3-10-22 Sakae Nikkachibu Software Co., Ltd. (72) Inventor Yoshiharu Konishi 4-6-1 Kanda Surugadai, Chiyoda-ku, Tokyo Inside Hitachi, Ltd. 280 Hitachi Central Research Laboratory Co., Ltd. (72) Inventor Tatsuhiko Kagehiro 1-chome Higashi Koigabo 280 Hitachi Central Research Laboratory F term (reference) 3F079 AA01 CA02 CB08 EA19 5B029 BB02 CC07 CC27 DD06 DD09 5B057 AA02 BA30 CD05 CE02 CE03 CG04 CH04 CH11 DA08 DA20 DB02 DB08 DB09 DC23

Claims (15)

[Claims] 1. A method for extracting characteristic information for character recognition from image information read by scanning a target surface including character information, wherein a first characteristic for detecting a character region having the character information is provided. As information, low-definition multi-value data obtained by performing multi-value reduction processing on the image information is obtained, and as the second feature information for character recognition of the character information in the character area, 2 A method of extracting feature information of a read image, comprising obtaining high-definition binary data subjected to a value process, and extracting the first and second feature information by parallel processing in units of main scanning lines. 2. The medium-definition binary data obtained by performing a binary reduction process after the binarization process as the third feature information for detecting a character string in the character region. 1. A method for extracting feature information of a read image, wherein the feature information is extracted by parallel processing with the second feature information. 3. The method according to claim 1, wherein the parallel processing for extracting each piece of feature information is performed in synchronization with a reading speed of the image. 4. The memory write address according to claim 1, wherein when the first characteristic information is stored in a memory through code compression processing, code compression data for each main scanning line and pointer information thereof are provided. A method for extracting feature information of a read image, characterized by outputting information. 5. The method according to claim 1, wherein the threshold value used in the binarization processing is obtained by calculating an average value of pixel grayscale values in a block including a plurality of pixels adjacent to the processing target pixel. The maximum value among the average values similarly obtained for a plurality of blocks adjacent to the block is multiplied by a constant to obtain a first value.
, A constant obtained by subtracting a constant from the maximum value is set as a second binarization threshold candidate, and an arbitrary constant is set as a third threshold candidate. 3. A method for extracting characteristic information of a read image, wherein one of the two methods is selected to determine a final binarization threshold value. 6. The method according to claim 1, wherein an image frame corresponding to the target surface is divided into a plurality of image regions in a main scanning direction and feature information extraction of each image region is performed in parallel. A feature information extraction method for a read image, wherein pixel data of an end of a main scanning line of another adjacent image region is taken in addition to pixel data of a main scanning line of an image region to be processed. 7. The method according to claim 1, wherein an image frame corresponding to the target surface is divided into a plurality of image regions in a main scanning direction, and feature information extraction of each image region is performed in parallel. The pixel data obtained by dividing the main scanning line and including the edge pixel data of another adjacent image area are captured. When located at an end adjacent to the region, the determination is made based on the maximum value among the average values of a plurality of blocks including the average value of the adjacent block obtained based on the end pixel data of another image region. A feature information extraction method for a read image characterized by the following. 8. A scanner for scanning and scanning a target surface including character information, a characteristic information processing apparatus for extracting characteristic information for character recognition from the read image information, and a memory for storing the extracted characteristic information. An image processing apparatus including a recognition device that performs character recognition based on feature information in image frame units corresponding to the target surface, wherein an extraction process by the feature information processing device is synchronized with main scanning line scanning by the scanner. An image processing apparatus for performing character recognition by the recognition device after extracting all the main scanning lines of the image frame. 9. The information processing apparatus according to claim 8, wherein the information processing apparatus includes a first feature information extracting unit configured to extract low-definition multi-valued data subjected to multi-value reduction processing to detect a character area in the image frame; An image processing apparatus, comprising: a second feature information extracting unit that extracts high-definition binary data that has been binarized to recognize characters in the character area, in a parallel processing manner. 10. The information processing apparatus according to claim 9, wherein the information processing apparatus is provided with output control means for making output timings of the respective characteristic information different from each other, and outputting the characteristic information to the memory via one bus. Image processing device. 11. The image processing apparatus according to claim 8, 9 or 10, wherein a plurality of sets of the feature information processing device and the memory connected to the bus are provided, and a plurality of image areas divided in a sub-scanning direction of the image frame are processed in parallel. An image processing apparatus comprising: 12. A scanner for scanning and reading an address surface of a postal matter, a feature information processing apparatus for extracting feature information for character recognition from the read image information, a memory for storing the extracted feature information, In a mail address reading device provided with an address recognition device for recognizing an address based on feature information in image frame units corresponding to an address surface, the feature information processing device includes a multi-valued First characteristic information extracting means for extracting low-definition multivalued data subjected to reduction processing, and second characteristic information extraction for extracting medium-definition binary data subjected to binary reduction processing for detecting a character string in the address area Means, and third feature information extracting means for extracting high-definition binary data which has been binarized in order to recognize the characters of the character string are provided in a parallel-processable manner; Postal matter address reading apparatus characterized by the extraction process by symptoms information processing apparatus provided with a line synchronization means for synchronizing the scanning of the main scan line by the scanner. 13. A mail address reading apparatus for extracting feature information from image information obtained by reading the address surface of a mail and recognizing the address based on the feature information in frame units. A mail address reading device, comprising: a plurality of image processing devices according to (1), wherein the read image from the scanner is sequentially distributed to the image processing devices in a frame unit or a fraction thereof and processed in parallel. 14. A mail address reading apparatus for extracting feature information from image information obtained by reading the address surface of a mail, and recognizing the address based on the frame-based feature information. And a plurality of image processing devices described in the above, and setting the processing parameters of each feature extraction process differently, parallelly process the image read from the scanner by each image processing device simultaneously, different according to the processing parameters A mail address reading device characterized by obtaining an image processing result. 15. The third feature information extracting unit according to claim 13, wherein the feature information processing device extracts medium-definition binary data subjected to a binary reduction process to detect a character string in the character area. Wherein the result of the binary reduction processing in one image processing apparatus is directly output to the display apparatus without compression processing.