KR100238027B1 - Apparatus and method for decimation transform of image in image system - Google Patents

Abstract

The present invention relates to an image reduction conversion apparatus and method of an image system, and according to the image reduction conversion apparatus and method of an image system according to the present invention, in an image system, image quality processing is performed when the image is reduced and transmitted. The image quality processing is performed by minimizing image quality deterioration by applying the reduction conversion technique to the grayscale data before the image quality processing is performed. Based on the reduction conversion technique, the image data is reduced to suppress specific clocks of the pixel clock to reduce the image, thereby removing the binary data from the already processed image. With the exception of follow up to compensate for the The problem of propagation of degraded image data can be effectively solved.

Description

Image reduction conversion apparatus and method of an image system {APPARATUS AND METHOD FOR DECIMATION TRANSFORM OF IMAGE IN IMAGE SYSTEM}

The present invention relates to an image reduction conversion apparatus and method, and more particularly, to an image system such as a facsimile, etc., in which a reduction conversion technique is applied to binary data when the image is reduced and transmitted. The present invention relates to an image reduction conversion apparatus and method capable of minimizing image quality degradation by applying a reduction conversion technique to pixel graylevel data.

The image reduction conversion technique is a basic image processing technique used in the field of Computer Supported Cooperative Work (CSCW) and a wide range of fields such as computer graphics, computer aided design (CAD), and television broadcasting. It is also usefully used in PIP (Picture In Picture) technology, which is recently applied to fields such as video editing and simultaneous TV broadcasting.

In particular, in an image system in which an image needs to be enlarged or reduced in size, such as a facsimile, the image reduction conversion technique provides a function of converting the image size and resolution downwardly. For example, converting paper size from B4 (257mm × 364mm) format to A4 (210mm × 297mm) format, or converting the resolution of documents from 300dpi (dot per inch) to 203dpi. Enabling output gives a wide range of degrees of freedom for the use of limited resources.

On the other hand, if the image is simply reduced in general, image quality is degraded due to the loss of main data of the image, resulting in image quality deterioration by removing and reducing the data of the original image using the correlation and spatial characteristics of the pixels included in the original image. The technique of minimizing the s is used to improve the quality of the reduced image.

The image reduction conversion apparatus of the conventional image system will be described with reference to FIG. 1 as follows.

As shown in FIG. 1, an image reduction converter of an image system according to the related art converts an analog image signal converted into an electrical signal through a charge coupled device (CCD) / contact image sensor (CIS) or the like into a digital image signal. An analog-to-digital converter (ADC) 10 to convert and an output of the analog-to-digital converter 10 to perform image processing for image quality improvement based on an appropriate image quality processing technique. When the output of the processing unit 20 and the image quality processing unit 20 are required to perform a reduction conversion, a reduction conversion that reduces an image by suppressing specific clocks of the pixel clock PIXCLK according to a reduction conversion technique according to a predetermined rule. It is comprised by the part 30.

Hereinafter, the operation of the image reduction conversion apparatus of the image system according to the related art configured as described above will be described with reference to FIG.

In the case of a facsimile, an example is described. First, a document, a photo, a printed matter, etc. are converted into an electrical signal in an analog form through a CCD (Charge Coupled Device) / CIS (Contact Image Sensor) and the like. Allocate 8 bits per pixel to convert analog video signals into digital video signals.

Although converting an analog signal into a digital signal has many objectives, the primary purpose of the digital signal is easier to apply various Digital Signal Processing (DSP) techniques than the analog signal. This is because the transmission is less susceptible to errors, and even in the event of an error, it has an advantage in terms of signal processing that can easily detect and recover an error through a conventional error correction technique.

In general, while converting an image to digital, each pixel is represented by 256 gray levels by allocating 8 bits per sample, that is, one pixel. The image quality processing unit 20 improves image quality using a general image quality processing technique. Promote

Here, various examples of image quality processing techniques may be mentioned, and representative image quality processing techniques may include image binarization processing techniques. In devices with a built-in scanner capable of reading documents, such as a facsimile machine or a multifunction printer, after reading an image having multiple levels of gradation through the scanner, the characteristics of image binarization of the read data may be used to determine the performance of the scanner. In the evaluation, it is a major evaluation item.

Subsequently, when the reduction conversion is required, the reduction conversion unit 30 reduces the image by suppressing specific clocks of the pixel clock PIXCLK based on a predetermined reduction conversion rule.

For example, in the case of image binarization processing, this means that a reduction conversion technique is applied to binary data after performing image quality processing for improving image quality, for example, the third of a bit string such as "0101000111". And when the reduction conversion technique is applied to the fifth time, the bit string to be transmitted becomes "1100111", and since the binary data is removed from the bit string that has already been processed, the important image data is removed while applying the reduction conversion technique. The degree of deterioration in image quality may be increased. In this case, as the image quality processing is preceded, the possibility of compensating for the deteriorated image quality at the rear end is eliminated, and thus, the distorted image is likely to be transmitted through the channel without taking action to improve the image quality.

As described above, the image reduction conversion apparatus of the image system according to the prior art reduces image by suppressing specific clocks of the pixel clock PIXCLK based on a reduction conversion technique for image data subjected to image quality processing. Since the binary data is removed from the bit stream subjected to the image quality processing, there is a problem that the deteriorated image data is propagated without the subsequent measures to compensate for the important image data being removed during the image reduction conversion process.

Accordingly, the present invention has been made to solve such a problem, and in the image system, image quality deterioration is performed by performing image quality processing that can compensate for image quality deterioration after applying the image reduction conversion technique to image data to be transmitted. It is an object of the present invention to provide an apparatus and method for reducing images of an image system that can be minimized.

1 is a block diagram showing an image reduction conversion device of a conventional image system;

2 is a block diagram showing an image reduction and conversion device of an image system according to the present invention;

3 is a detailed circuit diagram illustrating an embodiment of the image reduction and changing unit of FIG. 2;

FIG. 4 is a waveform diagram showing output waveforms of respective main parts of FIG. 3; FIG.

* Explanation of symbols for main parts of the drawings

10: analog-to-digital converter 20: image quality processing unit

100: reduction converter 110: modulo operation unit

111 counter reset unit 120 counter unit

121: first T-flip flop 122: second T-flip flop

123: third T-flip flop 130: modulo operation output unit

131: first modulo calculating unit 132: second modulo calculating unit

133: multiplexer 140: combination cycle setting unit

141: fourth T-flip flop 142: fifth T-flip flop

143: sixth T-flip flop 144: D-flip flop

145: Combination period reset unit 150: Reduced clock output unit

151: AND logic gate

In order to achieve the object of the present invention as described above, the image reduction conversion apparatus and method of the image system according to the present invention, in the image system, the reduction conversion of the binary data subjected to the image quality processing at the time of reducing the image transmission The image quality deterioration can be minimized by applying the reduction conversion technique to the pixel grayscale data before the image quality processing is performed, and then performing the image quality processing to improve the image quality.

A preferred embodiment of the image reduction and conversion apparatus of the image system according to the present invention will be described with reference to FIG.

Fig. 2 is a block diagram showing a preferred embodiment of the image reduction conversion apparatus of the image system according to the present invention. The same reference numerals are given to the same components as those of the prior art shown in FIG.

According to a preferred embodiment of the image reduction conversion apparatus of the image system according to the present invention, as shown in Fig. 2, in the image reduction apparatus for performing reduction conversion on input image data to generate reduced image data, a CCD / An analog-to-digital converter 10 for converting an analog video signal converted into an electrical signal through an image input device such as a CIS into a digital video signal, and the output of the analog-to-digital converter 10 is reduced and converted. If necessary, according to a predetermined rule by suppressing specific clocks from the pixel clock (PIXCLK) by reducing the conversion clock 100 for generating a reduced pixel clock (DPIXCLK) to reduce the image data to reduced image data, and the reduction conversion unit Composed of an image processing unit 20 that receives the output of the (100) and performs image processing to improve the image quality using the image quality processing technique do.

Here, the reduction converter 100 performs one or more modulo operations on the pixel clock PIXCLK to divide the plurality of pixel clocks PIXCLK, which clock each pixel of the input image data, into one or more clock blocks. The modulo operation unit 110 and the output operation (LDB) of the modulo operation unit 110 to perform the respective counts of the number of iterations of the modulo operation to generate a selection signal for multiplexing the modulo operation By receiving the combination period setting unit 140, the pixel clock (PIXCLK) and the output (LDB) of the modulo operation unit 110 to determine a predetermined modulo period, and performs an AND logic operation. The reduced clock output unit 150 generates the reduced pixel clock DPIXCLK by suppressing one or more pixel clocks PIXCLK per clock block.

The modulo operation unit 110 performs one or more modulo operations through a NAND logic operation of the counter unit 120 that counts the pixel clock PIXCLK and the output of the counter unit 120. Modulo operation output unit 130 for multiplexing and outputting the signal according to the selection signal, AND logic operation by receiving the output LDB and power on reset signal PORB of the modulo operation unit 130. The counter reset unit 111 is configured to reset the counter unit 120 at the time points at which the modulo operation cycles are completed.

The counter unit 120 inverts the pixel clock PIXCLK and receives a first T-flip flop 121 and a sub-output of the first T-flip flop 121. ) Is applied as a clock to the second T-flop flop 122 and the sub-output of the second T-flop flop 122 ) Is configured as a third T-flip flop 123 which is applied as a clock to perform octal counting.

The modulo output unit 130 may output a sub-output of the first T-flip flop 121. ) And the positive power of the second T-flip flop 122 ) And the positive power of the third T-flip flop 123 ( ) And a first modulo arithmetic unit 131 for performing a six-modulo operation by performing a NAND logic operation, and a positive output of the first T-flop flop 121. ) And the positive power of the second T-flip flop 122 ) And the positive power of the third T-flip flop 123 ( ) Is a second modulo operation unit 132 for performing a 7-module operation by performing a NAND logic operation, an output of the first modulo operation unit 131 and an output of the second modulo operation unit 132. It is composed of a multiplexing unit 133 to receive the multiplexed and output in accordance with the selection signal (SEL) of the combination period setting unit 140.

The combination period setting unit 140 may further include a fourth T-flop flop 141 that receives the output LDB of the modulo operation unit 110 as a clock and a fourth T-flop flop 141. Negative output ) And a sub-output of the fifth T-flop flop 142 and the fifth T-flop flop 142 ) Is applied as a clock to the sixth T-flip flop 143 and the output LDB of the modulo calculating unit 110 is used as a clock to output a positive output of the sixth T-flip flop 143. ) Is applied to the input (D), and the power-on reset signal (PORB) to the reset (R) De-flip flop (Delay-flip flop) 144, the power-on reset signal (PORB) and the D- Negative output of flip flop ) Is inputted to perform the AND logic operation to reset the combination period to apply to the reset (R) of the fourth T-Flop flop 141, the fifth T-Flop flop 142, and the sixth T-Flop flop 143. It consists of a part 145.

Hereinafter, the operation of the preferred embodiment of the image reduction and conversion apparatus of the image system according to the present invention will be described with reference to FIG.

Referring to the operation of the preferred embodiment of the present invention in terms of the prior art similar to the description, first of all, in the form of an analog form through a CCD (Charge Coupled Device) / CIS (Contact Image Sensor), etc. After conversion to an electrical signal, an analog video signal is converted into a digital video signal by allocating 8 bits per pixel.

Accordingly, when the reduction converter 100 receives the output of the analog-digital converter 10 and reduces the conversion, the reduction converter 100 suppresses specific clocks from the pixel clock PIXCLK according to a predetermined rule to reduce the reduction pixel clock ( DPIXCLK) to reduce the image.

That is, in the reduction converter 100, the modulo calculator 110 divides the pixel clocks PIXCLKs into one or more clock blocks including a plurality of pixel clocks PIXCLKs. Each of the at least one modulo operation is performed, wherein the counter unit 120 counts the pixel clock PIXCLK, and the modulo operation output unit 130 performs the counter unit 120. When the output of the multiplexed operation is performed after one or more modulo operations through a NAND logic operation, the counter reset unit 111 outputs the output LDB and the power-on reset of the modulo operation unit 130. By performing the AND logic operation by receiving the on reset signal PORB, the counter unit 120 is reset to periodically perform the unit modulo operation constituting the modulo operation unit 130 according to a predetermined rule. Performing, and also The sum period generating unit 140 counts the output LDB of the modulo operation output unit 130 to multiplex the modulo operation unit 130 so that the combined operation of the unit modulo operation can be periodically performed. It provides a selection signal (SEL) for.

Accordingly, the reduced clock output unit 150 receives the pixel clock PIXCLK and the output LDB of the modulo operation unit 110 and performs an AND logic operation using an AND logic gate 151. Thereby suppressing one or more pixel clocks PIXCLK per clock block to generate a reduced pixel clock DPIXCLK.

An operation of an embodiment of the image reduction converter 100 of the present invention will be described in detail with reference to FIGS. 3 and 4.

FIG. 3 shows an embodiment of the image reduction conversion unit 100 for converting the size of the paper from the B4 (257 mm x 364 mm) format to the A4 (210 mm x 297 mm) format.

First, when the power is turned on, a power-on reset signal that is activated in a low state is applied to reset the modulo operation unit 110 and the combination period setting unit 140, and the pixel clock PIXCLK. As applied, the counter unit 120 composed of the first T-flop flop 121, the second T-flop flop 122, and the third T-flop flop 123 is octal with respect to the pixel clock PIXCLK. Perform counting.

Accordingly, the first modulo calculating unit 131 outputs the sub output of the first T-flip flop 121 ( ) And the positive power of the second T-flip flop 122 ) And the positive power of the third T-flip flop 123 ( ) By performing a NAND logic operation, and performing a 6-modulo operation, and the second modulo operation unit 132 outputs the positive output of the first T-flop flop 121. ) And the positive power of the second T-flip flop 122 ) And the positive power of the third T-flip flop 123 ( When the 7-module operation is performed by performing NAND logic operation, the multiplexer 133 receives the output of the first modulo operation unit 131 and the output of the second modulo operation unit 132. The signal is multiplexed and output according to the selection signal SEL of the combination period setting unit 140.

On the other hand, in the combination period setting unit 140, a fourth T-flop flop 141 that receives the output (LDB) of the multiplexer 133 as a clock, and the fourth T-flop flop 141 Negative output of ) And a sub-output of the fifth T-flop flop 142 and the fifth T-flop flop 142 ) Is applied to the sixth T-flop flop 143 and the output (LDB) of the modulo operation unit 110 as a clock as a clock to output the positive output (6) of the sixth T-flop flop (143). ) Is a binary counter portion consisting of a delay-flip flop (144) that is applied as an input (D), when the output (LDB) of the multiplexer 133 is applied five times, the AND gate 145 Resets the binary counter by an AND logic operation of < RTI ID = 0.0 >),< / RTI > By using) as the selection signal SEL of the multiplexer 133, the output of the multiplexer 133 is controlled so as to satisfy a certain modular combination period.

That is, as shown in FIG. 4, the pixel clock PIXCLK sets the combination period of 6-modulo operation of the first modulo operation unit 131 and 7-modulo operation of the second modulo operation unit 132. According to the selection signal (SEL) generated from the unit 140, the output is multiplexed in the order of "6-module, 7-module, 6-module, 7-module, 6-module", and 5 times. When counting of the combination period setting unit 140 is performed over, the binary counter unit is reset, resulting in " 6-module, 7-module, 6-module, 7-module, 6-module. Will be repeated.

Here, "6-modulo, 7-modulo, 6-modulo, 7-modulo, 6-modulo" means that the number of pixel clocks (PIXCLK) is "6, 7, 6, 7 Dog, 6 "units.

At this time, the reduced clock output unit 150 receives the output of the pixel clock PIXCLK and the modulo operation unit 110 and performs an AND logic operation to generate the reduced pixel clock DPIXCLK. As a result of the 6-modulo operation by the first modulo operation unit 131 and the 7-modulo operation result by the second modulo operation unit 132, a signal form in which the modulo operation is completed has a high state.

That is, when the modulo operation is selected by the selection signal SEL, and if the 6-modulo operation is performed, the first to fifth calculation results output a high state signal. The sixth operation outputs a low state signal.

Therefore, the reduced clock output unit 150 receives the output of the pixel clock PIXCLK and the modulo operation unit 110 and performs an AND logic operation to generate the reduced pixel clock DPIXCLK. If the result of the sixth operation of the modulo operation and the pixel clock (PIXCLK) is an AND logic operation, the end operation results in a low state signal, resulting in one pixel clock (PIXCLK) out of the six pixel clocks (PIXCLK). ) Is suppressed, and when the seventh operation result of the 7-modulo operation and the pixel clock (PIXCLK) become the AND logic operation, the AND operation result is a low state signal, and as a result, among the seven pixel clocks (PIXCLK), Since an effect of suppressing one pixel clock PIXCLK occurs, a reduced conversion clock DPIXCLK is used to form reduced image data.

That is, the 32 pixel clocks PIXCLK including the six, seven, six, seven, and six pixel clocks PIXCLK are each one by the reduction converter 100 of the present invention. As the pixel clock PIXCLK is suppressed, it becomes " five, six, five, six, five " to generate a reduced conversion clock DPIXCLK reduced to 27 pixel clocks PIXCLK.

As described above, one embodiment of the image reduction conversion unit 100 of the present invention is an example of an image reduction conversion for converting a paper size from the B4 (257 mm x 364 mm) format to the A4 (210 mm x 297 mm) format. .

Typically, B4 format papers include 2048 pixels, and in order to express them on A4 format papers, a reduction ratio of about 1.185 to 1 (i.e., ) Is required.

In the embodiment of the present invention, the number of pixel clocks PIXCLK is reduced to 27 by using 32 pixel clocks PIXCLK as one cycle. ) Is to satisfy.

This reduced image conversion is not limited to reduced conversion from B4 format paper to A4 format paper, but also reduced conversion from A4 format paper to B5 format paper, reduced conversion from B4 format paper to B5 format paper, and 203dpi at 300dpi resolution. It can be easily applied to reduction conversion to resolution and the like, and it is apparent that the claims of the present invention include such modifications as modifications to the present invention utilizing the above concept are easy.

Thereafter, the image quality processing unit 20 improves image quality by using a general image quality processing technique for the reduced image data.

Here, various examples of image quality processing techniques may be mentioned, and representative image quality processing techniques may include image binarization processing techniques.

On the other hand, another representative image quality improvement technique is slicing through histogram analysis to adjust the overall brightness of the image or to apply the stretching (stretching). A histogram technique that composes an image in which natural objects are clearly expressed by increasing contrast, and an edge enhancement technique and space that provides accurate identification of an object as the edge of the object is strengthened. Spatial filtering or smoothing, which is a spatial filtering technique for removing noise components, is an example of an image quality improvement technique that is frequently used.

In the present invention as in the prior art, while performing the image reduction transformation, visually important data may be lost by the application of the reduction transformation.

However, in the related art, since image reduction conversion is applied after performing image quality improvement, the room for compensation for image data that may be lost in the image reduction conversion process is excluded, but the present invention reduces image after performing image reduction conversion. There is an advantage in terms of image quality improvement by considering compensation for image data that may be lost in the conversion process.

For example, in the case of image binarization, in consideration of the continuity, correlation, and the like of image data, if the 8-bit image gradation data is lost rather than the binary data loss, and image quality processing is applied to the image data, important data is lost. The chance of being reduced.

Meanwhile, a front-end image quality processing unit, which is an additional image quality processing unit, is added between the analog-to-digital conversion unit 10 and the reduction conversion unit 100, so that the image quality processing unit of the reduction conversion unit 100 according to the present invention. After performing the first image quality processing at the front end, the reduction conversion unit 100 receives the output of the front end image quality processing unit and applies the reduction conversion. Then, the image quality processing unit 20 performs the reduction conversion unit 100. The image processing may be performed again by receiving the output.

As is well known to those skilled in the art, a representative pre-processing image quality improvement algorithm used in the shear image processing unit may be one example of edge enhancement filtering.

An image reduction conversion method of the image system according to the present invention will be described below.

An image reduction conversion method of an image system according to the present invention is an image reduction method for generating reduced image data by performing reduction conversion on input image data, wherein the analog image is converted into an electrical signal through an image input device. An analog-to-digital conversion step of converting a signal into a digital video signal, and a reduced pixel clock by suppressing specific clocks from the pixel clock according to a preset image reduction ratio when the input image data including the digital image signal is received and reduced conversion is required. A reduction conversion step of generating reduced image data which has been reduced-converted by generating a; The image processing step includes receiving the reduced image data and applying an image quality processing technique to perform image processing for image quality improvement.

Here, the step of reducing conversion is a module that performs one or more modulo operations on the pixel clocks to divide the plurality of pixel clocks that clock each pixel of the input image data into one or more clock blocks. A combination period setting step of determining a predetermined modulo combination period by generating a selection signal for multiplexing the modulo operation according to a predetermined rule by counting a repetition count of the modulo operation, respectively; And a reduced clock output step of generating the reduced pixel clock by suppressing one or more pixel clocks per clock block by receiving an output of the modulo operation unit and performing an AND logic operation.

The modulo operation may include a counting step of counting the pixel clock using a counter and performing at least one modulo operation through a logic operation on the counting result of the counting step, and then multiplexing and outputting the modulated signal according to the selection signal. A modulo operation output step, and a counter reset step for resetting the counter at a time point at which each of the modulo operations is completed by performing a logic operation by receiving a result of the modulo operation and a power-on reset signal. do.

The modulo operation output step may include a first modulo operation step of performing a first modulo operation through a logic operation using a coefficient value of the counter, and a second module through a logic operation using a coefficient value of the counter. And a second modulo operation step of performing a raw operation, and a multiplexing step of receiving a result of the first modulo operation and a result of the second modulo operation and multiplexing and outputting the result according to the selection signal.

The combining period setting step may include a repetition counting step of counting the repetition count of the modulo operation, and a selection signal for multiplexing the modulo operation with a signal of the least significant bit of binary data indicating the repetition count. And a period determining step of determining a modulating combination period according to a predetermined number of occurrences of the selection signal.

The procedure of the image reduction conversion method of the image system according to the present invention will be described below.

First, in the analog-to-digital conversion step, if an analog video signal converted into an electrical signal through an image input device is converted into a digital video signal, in the reduction conversion step, the digital image signal is received and a reduction conversion is required. By reducing specific clocks from the pixel clock according to the reduction ratio, a reduced pixel clock is generated to reduce and convert the image data into reduced image data.

Thereafter, in the image quality processing step, the reduced image data is input to apply image quality processing to perform image processing for image quality improvement.

Here, various examples of image quality processing techniques may be mentioned, and representative image quality processing techniques may include image binarization processing techniques.

In general, "image binarization" refers to a gray level image represented by a multi-step gray level in an image system, and a binary image of one bit, that is, '1' and '0'. Image quality, which is used to express the image, or a binary image), based on a signal processing characteristic capable of preserving the characteristic information of the target image while significantly reducing the amount of processing data. It is widely used in the field of recognition. Due to this wide range of applications, various image binarization methods are known.

The most common image binarization method is to obtain a binarized image by determining an arbitrary threshold, assigning " 1 " to pixel values that are larger than this threshold, and assigning " 0 " to pixel values that are smaller than the threshold. Thus, image binarization processing is a kind of threshold processing for classifying gray levels up and down based on a threshold value. The most important thing in the threshold processing is the determination of a threshold value. There are also ways to determine more precise thresholds through concentration histograms.

On the other hand, in order to properly binarize the edge regions of the visually important image, there is a method of performing binarization after emphasizing the outline of the original image through a predetermined edge enhancement filter. It is known that a good binarization image can be obtained as compared with the method that does not include the emphasis process.

An example of this is as follows. If the gradation value of the original image is given in Table 1,

78 77 76 93 152 176 227 222

When spatial filtering is performed using a 1 × 3 edge enhancement mask as shown in Table 2,

-One 3 -One

You can get the result with the outline outlined in Table 3.

77 58 51 187 149 255

Hereinafter, the procedure of the reduced conversion step according to the present invention will be described in detail.

In the modulo operation step, when the one or more modulo operations are performed on the pixel clock to divide a plurality of pixel clocks that clock each pixel of the input image data into one or more clock blocks, the combination period setting step In order to determine the predetermined modulo combination period by counting the number of iterations of the modulo operation to generate a selection signal for multiplexing the modulo operation according to a predetermined rule.

At this time, the reduced clock output step receives the pixel clock and the output of the modulo operation unit and performs an AND logic operation to suppress one or more pixel clocks per clock block to generate the reduced pixel clock.

That is, in the modulo operation step, the counting step counts the pixel clock using a counter, and at least one modulo operation is performed through a logic operation on the counting result of the counting step in the modulo operation output step. After performing the multiplication according to the selection signal and outputting the data, in the counter reset step, a logic operation is performed by receiving a result of the modulo operation step and a power-on reset signal and completing the period of the modulo operation, respectively. Reset the counter.

In the modulo operation output step, a first modulo operation is performed through a logical operation using a counter value of the counter in a first modulo operation step, and a coefficient value of the counter is adjusted in a second modulo operation step. Perform another second modulo operation different from the first modulo operation through a logical operation, and receive the result of the first modulo operation and the result of the second modulo operation in the multiplexing step; Multiplex it according to the selection signal and output it.

The combining cycle setting step may include: counting the number of repetitions of the modulo operation in the number of repetition counts, and multiplexing the modulo operation by the signal of the least significant bit of binary data representing the number of repetitions in the selection signal generation step; And a modulating combination period according to a predetermined number of occurrences of the selection signal in the period determining step.

Meanwhile, an additional shear image quality processing step is added between the analog-to-digital conversion step and the reduction conversion step, so that the reduction of the image quality after the shear image quality processing step performs the first image quality processing prior to the reduction conversion step according to the present invention. In the converting step, the result of the previous image quality processing step may be input to apply the reduced transform. Thereafter, in the image quality processing step, the result of the reduction conversion step may be received and image quality processing may be performed again.

As is well known to those skilled in the art, a representative pre-processing image quality improvement algorithm used in the shear image quality processing step is one example of edge enhancement filtering.

Terminologies used herein are terms defined in consideration of functions in the present invention, which may vary according to the intention or customs of those skilled in the art, and the definitions should be made based on the contents throughout the present application. will be. Although specific embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

In addition, since the present invention has been described through the preferred embodiment of the present invention, in view of the technical difficulty aspects of the present invention, those having ordinary skill in the art can easily be different from another embodiment of the present invention. As modifications may be made, it is obvious that both the embodiments and modifications cited in the above description belong to the appended claims.

As described in detail above, according to the image reduction conversion apparatus and method of the image system according to the present invention, in the image system, a reduction conversion technique is performed on binary data subjected to image quality processing when the image is reduced and transmitted. Instead of applying the reduced-conversion technique to the pixel gradation data before the image quality processing is performed, the image quality processing for image quality is minimized by performing the image quality processing to improve the image quality. By suppressing certain clocks of the pixel clock based on this, the image is reduced so that binary data is removed from the bit stream that has already been processed. Therefore, when important image data is removed during the image reduction conversion process, it is possible to compensate for this. Statements that propagate deteriorated image data with no action taken It can solve the problem effectively.

Claims (8)

In the image reduction conversion method of the image system, An analog-digital conversion step of converting an analog video signal converted into an electrical signal through an image input device into a digital video signal; In the case of receiving input image data consisting of the digital image signal and performing a reduction conversion, a reduction conversion step of generating reduced reduction pixel data by generating reduced pixel clocks by suppressing specific clocks from the pixel clock according to a predetermined image reduction ratio. Wow; A quality processing step of receiving the reduced image data and applying an image quality processing technique to perform image processing for image quality improvement; The reduced conversion step, A modulo operation step of performing one or more modulo operations on the pixel clocks to divide the plurality of pixel clocks that clock each pixel of the input image data into one or more clock blocks; A combination period setting step of determining a predetermined modulo combination period by counting the number of repetitions of the modulo operation and generating a selection signal for multiplexing the modulo operation according to the image reduction ratio; And a reduced clock output step of generating the reduced pixel clock as a result of receiving the pixel clock and the result of the modulo operation and performing a first logic operation to suppress one or more pixel clocks per clock block. The image reduction conversion method of the image system. The image reduction conversion method of claim 1, wherein the digital reduction signal is applied between the analog-digital conversion step and the reduction conversion step to perform edge enhancement filtering to perform preprocessing for image quality improvement. An image reduction conversion method of an image system, further comprising the step of processing a front-end image quality. The method of claim 1, wherein the modulo operation comprises: counting a pixel clock count using a counter for the pixel clock; A modulo operation output step of performing one or more modulo operations using the pixel clock number and then multiplexing and outputting the modulated signals according to the selection signal; And a counter reset step of performing a second logic operation by receiving a result of the modulo operation step and a power-on reset signal to reset the counter when the period of the modulo operation is completed, respectively. How to convert image reduction on your system. The method of claim 3, wherein the modulo output step comprises: a first modulo operation of performing a first modulo operation through a third logical operation using a count value of the counter; A second modulo operation step of performing another modulo operation different from the first modulo operation through a fourth logical operation; a result of the first modulo operation and a result of the second modulo operation; And a multiplexing step of multiplexing and outputting the signal according to the selection signal. 5. The method of claim 4, wherein said modulo output step further comprises at least one said second modulo operation step. The method of claim 1, wherein the combining period setting step comprises: a repetition counting step of counting the number of repetitions of the modulo operation, and multiplexing the modulo operation with a signal of the least significant bit of binary data representing the repetition number; An image reduction conversion of the image system, characterized in that it comprises a selection signal generating step of providing as a selection signal for determining and a period determining step of determining a modulating combination period of a predetermined number of signal occurrences of the selection signal based on the image reduction ratio. Way. The image reduction conversion method according to claim 1, wherein the image reduction ratio is a value obtained by dividing the total number of bits of the input image data by the total number of bits of the reduced image data. An image reduction apparatus for generating reduced image data by performing reduction conversion on input image data, A modulo operation unit which performs one or more modulo operations on the pixel clocks to divide the plurality of pixel clocks that clock each pixel of the input image data into one or more clock blocks; A combination period setting unit for determining a predetermined modulo combination period by receiving an output of the modulo operation unit and counting the number of repetitions of the modulo operation to generate a selection signal for multiplexing the modulo operation according to an image reduction rate Wow; And a reduced clock output unit configured to receive the pixel clock and the output of the modulo operation unit to perform a first logic operation to suppress one or more pixel clocks per clock block to generate the reduced pixel clock. Image reduction conversion device of the system.