KR920001619B1 - Image processing apparatus - Google Patents

Abstract

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Description

Image processing device

1 is a block diagram showing an overall configuration of an image processing apparatus according to an embodiment of the present invention.

2 and 3 show display states of the CRT display device.

4 is a block diagram schematically showing a configuration of a vertical / horizontal conversion circuit.

5 is a block diagram showing the configuration of an input circuit.

Fig. 6A is a block diagram showing the configuration of the address counter.

6B is a view for explaining the operation of the selection circuit.

7 is a block diagram showing the configuration of a buffer memory control circuit.

8 is a diagram showing a configuration of data replacing means.

9 is a block diagram showing the configuration of a control circuit.

10 is a block diagram showing a configuration of a selection circuit.

11 is a block diagram showing the configuration of an output circuit.

12 and 13 are timing charts for explaining the operation of the main parts of the vertical / horizontal conversion circuit.

Fig. 14 is a block diagram showing another configuration of the buffer memory control circuit when the horizontal / vertical conversion operation is executed.

15A, 15B, 16A, and 16B illustrate an example of vertical / horizontal conversion by the vertical / horizontal conversion circuit.

17 is a view for explaining the read state of the injection apparatus.

18A and 18B are diagrams for explaining the contents of the buffer memory.

19A, 19B, 20A, and 20B illustrate an example of vertical / horizontal conversion by a vertical / horizontal conversion circuit.

21A and 21B are timing charts for explaining the operation of the main part of the horizontal / vertical conversion circuit.

Fig. 22 is a block diagram showing another configuration of the buffer memory control circuit when the vertical / horizontal conversion operation is executed.

23A and 23B are views for explaining an example of vertical / horizontal conversion by the vertical / horizontal conversion circuit.

24 is a diagram explaining a data reading mode from a page memory or a display memory.

25A and 25B are diagrams for explaining the contents of the buffer memory.

26A and 26B are views for explaining an example of vertical / horizontal conversion by the vertical / horizontal conversion circuit.

27A, 27B, 28 and 29 are timing charts for explaining the operation of the main part of the vertical / horizontal conversion circuit.

30 is a diagram for explaining the relationship between the document glass and the arrangement direction of the document.

* Explanation of symbols for main parts of the drawings

10: memory module 11: control module

12: CPU 14: Page Memory

14a: buffer memory 15: display memory

16: display control device 17: interface

20: scanning device 22: optical disk device

23: keyboard 24: CRT display device

24a: image display area 24b: icon

24c: Image control icon 24d: Windows

25: printer 27, 28: magnetic disk device

29: mouse 30: image processing module

31: communication control module 34: enlargement / reduction circuit

35: vertical / horizontal conversion circuit 36: compression / extension circuit

37: scanning device interface 38: printer interface

39: internal bus 41: system bus

42: image bus 43: UCP

44: BCP 51: input circuit

52: output circuit 53a, 53b: buffer memory

54a, 54b: buffer memory control circuit 55: serial / parallel conversion circuit

56: selection circuit 57: control circuit

61: right / left reverse circuit 62: parallel / serial conversion circuit

63: input timing control circuit 64: counter

71: serial / parallel conversion circuit 72: output timing control circuit

73: counter 74: right / left reverse circuit

80: data holding means 81: data replacing means

82: upper address control circuit 83: address counter control circuit

84: input / output control circuit 85: substitution control circuit

86: bidirectional buffer 91: counter

92, 93: selection circuit 100: line termination determination means

101: line mode counter 102: mode regulation decoder

103,104: counter 103: endgate

106: start circuit 121 ~ 125: selection circuit

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an image processing apparatus, for example, to an image processing apparatus such as an image information editing apparatus for displaying image information read by a two-dimensional scanning apparatus on a display device to perform an editing process.

[Traditional Technology and Problems]

Recently, image processing apparatuses for processing image information such as documents (documents) generated in large quantities have been developed. Such image processing apparatuses use a two-dimensional scanner to transfer information to an optical two-dimensional scan. Is read out to display the read image information on a display device (CRT display device). Then, the displayed image is rotated, enlarged, reduced or extracted and combined with other documents to be edited into a desired document, and the edited document as described above is continuously stored in a storage medium such as an optical disc or a CRT display device. Or by an output device such as a printer. In this case, when the scanner carries out vertical scanning (scanning in the direction corresponding to the longitudinal direction of the document), for example, the document of A4 is conveyed in the longitudinal direction by one line (in the horizontal direction of the document). Corresponding) The scanning operation is executed. As a result of this scanning operation, a vertically extending (vertical length) image is displayed on the CRT display.

On the other hand, when horizontal scanning is executed, A4 size documents are conveyed in the horizontal direction and scanning operations are performed one line at a time (corresponding to the vertical direction of the document). An image extending (horizontal length) is displayed.

Therefore, when vertical scanning is performed, only the vertical length image can be displayed on the CRT display device, while when vertical scanning is performed, only the horizontal length image can be displayed on the CRT display device. As a result, the image cannot be rotated on the display device. Moreover, when the document is scanned in the horizontal direction, the vertical length image is recorded on the optical disk, so that the image is printed in the vertical length direction, whereas when the document is scanned in the vertical direction, the horizontal length image is recorded on the optical disk. This will be printed in the horizontal length direction. As a result, the image processing apparatus as described above cannot generate information indicating the rotated state other than describing the input information stored in the memory, so that it takes a relatively long time to generate and output the information representing the rotated image. There is a problem.

[Purpose of invention]

Accordingly, the present invention has been made to solve the above problems, and inputs in a direction in which the image is extended without storing the input information before the input information is converted or without storing the converted image information of the memory before this information is output. It is an object of the present invention to provide an image processing apparatus capable of generating information indicating a rotation direction within a relatively short time by converting image information into image information representing an image rotated at an arbitrary angle.

[Configuration of Invention]

회전된 화상을 나타내는 화상정보데이터를 기억시켜 두기 위한 수단을 구비하여 구성된다.An image processing apparatus according to the present invention for achieving the above object comprises means for reading out an image from an original and outputting the image information data in the order in which the image is read, and processing the image information data output from the image reading means. Means for outputting image information data representing an image rotated by degrees, and 90 outputted from the processing means

And means for storing image information data representing the rotated image.

EXAMPLE

EMBODIMENT OF THE INVENTION Hereinafter, the image processing apparatus of this invention is demonstrated in detail based on an illustration.

1 shows an image information editing processing apparatus as an image processing apparatus according to the present invention. The image information editing processing apparatus includes a control module 11, a memory module 10, an image processing module 30, and a communication control module ( 31), scanning device 20, optical disk device 22, keyboard 23, CRT display device 24, printer 25, magnetic disk mounts 27, 28, mouse 29 And a system bus 41 and an image bus 42.

The control module 11 is composed of a CPU 12 and an interface 17 for performing various control operations, wherein the interface 17 is a CPU 12, the optical disk device 22 and It is employed to connect the magnetic disk devices 27, 28 and the like. The keyboard 12 and the mouse 29 are connected to the CPU 12.

The memory module 10 includes a main memory 13, a page memory 14, a display memory 15, a display control device 16, etc., each having a storage capacity corresponding to image information for an A4 sized original page. Among them, the display memory 15 and the display control device 16 function as a display interface, and the page memory 14 includes a buffer memory 14a.

The image processing module 30 further includes an enlargement / reduction circuit 34, a vertical / horizontal (V / H) conversion circuit 35, a compression / extension circuit (CODEC) 36, and scanning for the scanning device 20. It consists of a device interface 37, a printer interface 38 for the printer 25, and an internal bus 39, wherein the enlargement / reduction circuit 34 enlarges or reduces image information. The vertical / horizontal conversion circuit 35 rotates the image information (90 ° (90 ° right), 180 or 270 (90 left)) by vertically / horizontally converting the image information. The compression / expansion circuit 36 performs compression (to reduce redundancy) and expansion (to restore reduced redundancy) of image information, and the internal bus 38 expands the expansion. The reduction / contraction circuit 34 and the vertical / horizontal conversion circuit 35 are connected to the compression / expansion circuit 36, the scanning device interface 37, and the printer interface 38.

In addition, the communication control module 31 is composed of a universal communication processor (UCP) 43 and a business communication processor (BCP) 44, among which the UCP 43 is an interface (RS-232C, GPIB, SCSI, etc.) Is connected to an external device such as a facsimile device, and the BCP 44 is connected to a local area network (LAN).

The system bus 41 is a control signal bus that connects the control module 11, the memory module 10, the image processing module 30, and the communication control module 31. The image bus 42 is an image information bus which connects the memory module 10, the image processing module 30, and the communication control module 31 to each other.

On the other hand, in the display memory 15, the image information displayed in the window of the actual CRT display device, that is, the image information of the page memory 14 is obtained by enlarging, reducing, rotating inserting or converting the image information into white-black. Image information is stored.

The scanning device 20 is, for example, a two-dimensional scanning device that scans a document two-dimensionally with a laser beam to obtain an electrical signal corresponding to image information of the document. The optical disk device 22 continuously stores the image information read by the scanning device 20 on the optical disk, and the keyboard 23 performs various operation commands such as a unique search code corresponding to the image information. Used to enter

In addition, the CRT display device 24 displays image information read by the scanning device 20 as an output device or image information read out from the optical disc autonomous 22, and the CRT display device 24 Since four documents can be displayed simultaneously using up to four windows, for example, four images extending vertically can be displayed. In this case, image editing such as zooming in, zooming out, rotating, and scrolling can be performed. Processing will be performed independently for each window.

The initial display state of the CRT display device 24 is, for example, as shown in FIG. 2. More specifically, the display screen in the initial state is indicated by an image display area 24a and a function key. It is composed of an icon (24b) and an image control icon (24c) which also display contents and also function as an icon.

The display state of the CRT display device 24 is changed as shown in FIG. 3 when a read condition (scanning device property) of the scanning device 20 is input. In detail, settings such as document size, paper feed mode, document density, read density, read setting, picture mode, add-on designation, rotation direction and input area designation are displayed in the window 24d. have.

Here, as the document size, for example, B4 size, A4 size, B5 size, A5 size when the longitudinal direction of the document is located at right angles to the scanning direction on the document glass (not shown) of the scanning apparatus 20. A document can be selected, and the A4H size (or A4 horizontal) can be selected when the horizontal direction of the document is located at right angles to the scanning direction of the document target of the scanning device 20 (horizontally extending). , Documents of B5H size (B5 horizontal), A5H size (A5 horizontal) can be selected.

In addition, as the direction (angle) for rotating the image read out by the scanning device 20, it is possible to select 90 ° left rotation, no rotation, 90 ° right rotation, and 180 ° rotation.

The printer 25 prints, i.e., hard copies, image information read by the scanning device 20, image information read from the optical disk device 22, image information displayed on the CRT display device 24, and the like. The magnetic disk device 27 is a hard disk device, which is a search code input by the keyboard 23 and the size and image information of one piece of image information corresponding to the search code. The search data made up of the storage address of the optical disk (not shown) in which the memory is stored is stored in the magnetic disk (not shown) for each piece of image information. Here, the search data includes a search code (image name) consisting of a plurality of search keys, an image memory sheet rack address, an image memory sector address, an image memory sector number (image length), and an image size of image information corresponding to a search code of an optical disc. , Read density, and direction of rotation. The magnetic disk device 28 is a floppy disk device.

The mouse 29 is a pointing device, for example, the cursor on the screen of the CRT display device 24 is randomly moved in the vertical and horizontal directions to give an instruction at a desired position, thereby displaying the point at the point where the cursor is located. The contents (e.g., various modes, edited images, edit ranges and icons) are selected.

Next, the vertical / horizontal conversion circuit 35 will be described in detail with reference to FIG.

The vertical / horizontal conversion circuit 35 can operate in two modes, HV mode and VH mode. First, in the HV mode, the vertical / horizontal conversion circuit 35 converts data representing a horizontal length image into data representing a vertical length image. (This data is data representing a horizontal length image obtained by scanning a document in the horizontal direction and stored in a memory.) In the VH mode, the vertical / horizontal conversion circuit 35 displays data representing a vertical length image. Is converted into data representing an image of a horizontal length. (This data is data representing a vertical length image obtained by scanning a document in a vertical direction and stored in memory.)

The vertical / horizontal conversion circuit 35 includes an input circuit 51 and an output circuit 52, buffer memory 53a and 53b, buffer memory control circuits 54a and 54b, serial / parallel conversion circuit 55, It consists of the selection circuit 56, the control circuit 57, and the address counters 58a and 58b.

Among them, the input circuit 51 receives the input image data supplied through the image bus 42 or the internal bus 39, converts the input image data from the parallel input image data to serial image data, and then performs serial / parallel conversion. It outputs to the circuit 55 sequentially, and outputs a 1-line end signal to the control circuit 57 whenever the transmission of input image data on each line is completed.

The input circuit 51 is composed of a right / left inversion circuit 61, a parallel / serial conversion circuit 62, an input timing control circuit 63, and a counter 64 as shown in the drawing. Among them, the right / left inversion circuit 61 receives n-bit input data in-dta supplied from the image bus 42 or the internal bus 39 according to a control signal reversed from the control circuit 57. The right / left inversion operation by the right / left inversion circuit 61 is performed when the image information is converted into vertical / horizontal 180 degrees or 270 degrees, that is, the control signal 57 from the control circuit 57. is executed when reverse) is supplied. The parallel / serial conversion circuit 62 converts n-bit data into a serial bit data and outputs the serial / parallel conversion circuit 55. The input timing control circuit 63 is an image bus 42 or an internal circuit. The protocol related to the input operation with the bus 39 is controlled. The counter 64 counts the number of words in the input data and outputs the count to the control circuit 57.

The serial / parallel conversion circuit 55 converts the serial image data supplied from the input circuit 51 into parallel image data and supplies it to the buffer memory control circuits 54a and 54b. The buffer memories 53a and 53b and the address counters 58a and 58b are provided externally. As the buffer memories 53a and 53b, a RAM having an address space corresponding to 64K words is used. The buffer memories 53a and 53b output the image data stored in the other when the image data is written in one of them, so that the processing time can be shortened by such parallel processing. .

The address counters 58a and 58b are constituted by the counter 91 and the selection circuits 92 and 93 as shown in FIG. 6A. Among them, the counter 91 outputs the lower 14 bits of address data, and the selection circuits 92 and 93 are configured as a 4: 1 multiplexer for outputting the upper two bits of address data for address switching. When the bit width is 4 bits, 8 bits, 12 bits and 16 bits, respectively, the data of the output terminals A, B, C, and D are selectively output.

The buffer memory control circuits 54a and 54b divide the buffer memories 53a and 53b into 16 areas A to P, each of which is divided into four areas in the data width direction and the address direction. The data is stored in a distributed manner. The data is then written to the buffer memory as well. As a result, this data is recorded and read out in units of 4 bits.

The buffer memory control circuit 54a or 54b includes data holding means 80, data replacing means 81, upper address control circuit 82, address counter control circuit 83, and input / output as shown in FIG. It consists of an output (I / O) control circuit 84, a replacement control circuit 85, and a bidirectional buffer 86. Among them, the data holding means 80 temporarily holds the data buf-dta read out from the buffer memory 53a or 53b and outputs the data to the data replacing means 81 or the selection circuit 56. The data replacing means 81 supplies data br-dta held in the data holding means 80 from the input circuit 51 via the serial / parallel conversion circuit 55 to supply data (dw). -dta), and the upper address control circuit 82 generates an upper address (2 bits (adr-ho, adr-hl)) of the buffer memory 53a or 53b, and controls the address counter. The circuit 83 generates two control signals of the count up clock signal ac-upe and the clear signal ac-clr of the address counter 58a or 58b. The input / output control circuit 84 Write enable and output enable control of the buffer memory 53a or 53b. Run hereinafter and will in addition to controlling the data holding means 80 and bi-directional buffer 86, the replacement control circuit 85 is for controlling the data replacement unit 81.

As shown in FIG. 8, the data replacing means 81 is composed of logic circuits 114,... Which are composed of end gates 110, 111, 112 and ora gate 113. Accordingly, the data replacing means 81 is read out from the buffer memory 53A or 53B and held by the data holding means 80 by the data A0 to A15 and by the serial / parallel conversion circuit 55. The input pixel data B0 to B3 converted into 4-bit data is received. When the input terminal S0 becomes active, the input pixel data B0 to B3 is converted into data A0, A4, A8 and A12. When the input terminal S1 becomes active, the input pixel data B0 to B3 are replaced with data A1, A5, A9, and A13. When the input terminal S2 becomes active, When the pixel data B0 to B3 are replaced with the data A2, A6, A10 and A14, and the input terminal S3 is made active, the input pixel data B0 to B3 are converted to the data A3, A7, A11, When the input terminal S4 becomes active, the input pixel data B0 to B3 are replaced with the data A0, A1, A2, and A3, and the data A4 to A15 are replaced with the data A0. Replace with ~ A11) It is good.

The control circuit 57 controls the entire operation of the vertical / horizontal conversion circuit 35 to control rotation of various modes (0 °, 90 °, 180 °) according to the vertical / horizontal conversion or the horizontal / vertical conversion. 270 °), and the control circuit 57 has a line termination determination means 100, a line mode counter 101, a mode regulation deck 102 and a counter 103, 014 as shown in FIG. And an AND gate 105 and a starter circuit 106. The line end determining means 100 receives the 1-line end signals (in-cup, ot-cup) from the input and output circuits 51 and 52 to synchronize both sides to control the sequence of sequence. The line mode counter 101 counts the number of output lines according to the bit width of the input data in the vertical / horizontal mode or inputs the bit line of the output data based on the determination result from the line terminating determining means 100. The number of lines is counted to determine the operation mode of the input and output circuits 51 and 52 and the pair of buffer memory control circuits 54a and 54b. The mode regulation decoder 102 is provided from the line mode counter 101. The mode signals (buf Ar-mode, buf Aw-mode, buf Br-mode, buf Bw-mode, in-exc, and ot-exc) are output in accordance with the count value of. The counter 104 counts the total number of output lines, and the AND gate 105 Is a logical AND of the count-up outputs from the counters 103 and 104 to output an end signal. The start circuit 106 is enabled in response to the control signal (start signal) from the CPU 12 to start each circuit, and initializes each circuit at the end of operation of each circuit. Initialized by the end signal from 105, the operation is terminated. The control circuit 57 further includes a register group (not shown) for storing various control signals from the CPU 12, and supplies the control signal to each circuit as necessary.

The selection circuit 56 selects which of the read data from the buffer memories 53a and 53b is output to the output circuit 52. This selection circuit 56 is shown in FIG. Similarly, it is composed of the selection circuits 121, 122, 123, 124, and 125.

The output circuit 52 converts 1-bit serial data supplied from the selection circuit 56 into 16-bit parallel data and outputs it to the image bus 42 or the internal bus 39. 52, a serial / parallel conversion circuit 71, an output timing control circuit 72, a counter 73, and a right / left inversion circuit 74 are shown. The serial / parallel conversion circuit 71 converts one-bit serial data (in-dta) supplied from the selection circuit 56 into m-bit output data, and the right / left inversion circuit 74 The image bus 42 or the internal bus 39 are reversed by right / left inverting the m-bit output data supplied from the serial / parallel conversion circuit 71 according to a control signal (reverse) from the control circuit 57. To output The output timing control circuit 72 controls a protocol relating to the output operation with the image bus 42 or the internal bus 39. The counter 73 counts the number of words in the output data and counts the number of words in the output data. It outputs to the control circuit 57. In this case, the right / left inversion operation by the right / left inversion circuit 74 is performed when a horizontal / vertical 90 ° or 180 ° conversion of image data is performed, that is, a control signal (reverse) is supplied from the control circuit 57. It is supposed to run when

As described above, since the image processing apparatus according to the present invention includes two sets of buffer memories and two sets of buffer memory control circuits, the other buffer memory is outputted while one buffer memory is subjected to data write access. The processing can be executed and the processing can be executed at high speed without delay. In this case, in the vertical / horizontal mode, one buffer memory terminates the write access to one line of data, while the other buffer memory terminates the output of the line corresponding to the number of input bit widths, or one buffer memory. At the time when the buffer memory terminates the write access to the line corresponding to the output bit width and the other buffer memory finishes outputting the one-line data, the control circuit considers the termination determination from both buffer memory control circuits. The buffer memory is switched so that the input and output timing of the image data and the recording or reading mode of the buffer memory are defined accordingly.

In the horizontal / vertical mode, the number of divided regions of the buffer memory 53a or 53b corresponds to the number of input lines, so that the repeating unit is equal to the bit width of the output data as shown in FIG. 12 and FIG. . In this case, when the output bit width is small, the number of partitions of the buffer memory 53a or 53b is reduced, so that the number of pixels for one line increases even if a buffer memory having the same address space size is used. In the example, a case having a 16-bit width will be described as an example. For example, when the output bit width is reduced to 8 bits, the number of pixels per line can be doubled at most. In this case, the upper 1 bit of the buffer memory 53a or 53b must be supplied from the address counter 58a or 58b, and this control is performed by the address switching selector circuits 92 and 93 (see FIG. 6). do.

On the other hand, when the buffer memory control circuit 54a or 54b performs horizontal / vertical conversion, it can be configured as shown in FIG. 14. In FIG. 14, the replacement control circuit, the address counter control circuit, and the upper address are shown. A configuration corresponding to the control circuit, the buffer input / output control circuit is shown, and the other circuits are configured the same as in FIG.

In FIG. 14, in the case of writing data to the buffer memory 53a or 53b, when the signal in-exc is supplied from the control circuit 57, an orifice for counting up the address counter 58a or 58b. A clear output (ac-clr) supplied from 138 is enabled, the counter 134 is activated, and a buffer memory; a read enable output (buf-rd) and a write enable for the 53a or 53b. The output buf-wr starts to be output from the decoder 135 and the NAND gate 145, respectively. Carrying out every four counts of the counter 134 causes the address generation programmable counter 132 to count up. The programmable counter 132 is an output bit width counter, and a carry is generated for each number, so that the buffer selection circuit counter 131 counts up. In this case, since the upper address is 2 bits, the programmable counter 132 also has a 2-bit configuration. When the output bit width is 4 bits, 8 bits, 12 bits, or 16 bits, respectively, the programmable counter 132 operates as a binary, binary, ternary, and ternary counter, respectively. Therefore, when the input bit width corresponds to 16 bits, a clock ac-upe for counting up the address counter 58a or 58b every 16 cycles of write / read access to the buffer memory 53a or 53b is executed. Since it is generated, the address counter 58a or 58b is counted up.

Subsequently, in the case of reading data from the buffer memory 53a or 53b, the buffer memory control circuit 54a or 54b is enabled in response to the output ot-exc from the control circuit 57 to output the buf. Instead of -wr), an output (ac-upe) is generated for each cycle. In this case, the upper address is preferably updated every four-line output, so it is updated by the output (ot-cup) from the control circuit 57. do.

In the above configuration, the horizontal / vertical conversion operation of the vertical / horizontal conversion circuit 35 in the HV mode will be described. For example, the image information read out by the scanning device 20 as shown in FIG. 15A and FIG. 16A is rotated 90 degrees to the left as shown in FIG. 15B and FIG. 16B, and displayed on the CRT display device 24. The case is explained. In FIG. 15 and FIG. 16, an arrow R indicates a reading direction and an arrow W indicates a recording direction. First, image data in 16-bit units corresponding to 16 pixels supplied via the scanning device interface 37 and the internal bus 39 from the scanning device 20, for example, the first line of the first line shown in FIG. Data "P000000 to 0000015" for words is supplied to the serial / parallel conversion circuit 55 via the input circuit 51, and the image information converted into parallel data by the serial / parallel conversion circuit 55 is buffered. It is supplied to the memory control circuit 54a. Then, in this buffer memory control circuit 54a, as shown in FIGS. 18A and 18B, the data supplied from the serial / parallel conversion circuit 55 is transferred into the areas A to D of the buffer memory 53a by one bit. It will be distributed and memorized. For example, data "000000" is in the area A, data "000001" in the area B, data "000002" in the area C, data "000003" in the area D, and data "000004" in the area D. In area A, data “000005” is in area B, data “000006” is in area C, data “000007” is in area D, and data “000015” is in area ( It is memorized sequentially in D). In this case, data in the same area is stacked in order in the direction of the high address.

When data "P000100-P000115" for the second word of the first line is supplied, data "000100" is in the area A, data "000101" is in the area B, and data "000102" is in the area. In (C), the data "000115" is stored in the area D sequentially. In this case, data of the same area is stored on the data of the first word in the direction of the high address.

When data "P010000 to P010015" for the first word of the second line is supplied, data "010000" is in the area A, data "010001" is in the area B, and data "010002" is in the area. In (C), data "010003" is stored in the area D, ..., and data "010015" in the area D sequentially. In this case, data in the same area is stacked adjacent to data of the first word in the direction of the high address.

In the case where the output data width is 4 bits or more, after filling the lowest address area with input 4-line data, the data “040000” for the first word of the fourth line is set in the area E, and the data “040001” is set in the area F. FIG. ), Data "040002" is stored in the area G, data "040003" in the area H, and data "040015" in the area H. The same operation as in the case of the regions A, B, C, and D is performed.

When image data corresponding to one frame is stored in the buffer memory 53a, the buffer memory control circuit 54a stores 4-bit data in the lowest address of the areas A to D of the buffer memory 53a. 4 bit data in the lowest address of the areas E to H, 4 bit data in the lowest address of the areas I to L, 4 bit data in the lowest address of the areas M to P, and areas A to D Data is read in the order of 4 bit data in the second sub-address of the subband, 4 bit data in the second sub-address of the areas E to H, and the read data is converted into the selection circuit 56. The output circuit 52 is output to the image bus 42 as output image data and output to the display memory 15.

19A and 20A, the image information read out by the scanning device 20 is rotated 90 degrees to the right as shown in FIGS. 19B and 20B, respectively, and displayed on the CRT display device 24. As shown in FIG. Even in this case, by changing the order of the storage areas for the buffer memories 53a and 53b, the same operation as that in the case of rotating 90 degrees to the left side is performed.

In the main part of the vertical / horizontal conversion circuit, the operation is performed by the processing timing shown in FIGS. 12, 13, 21a, and 21b, where the 12 and 13 are buffer memories 53a and 53b. Fig. 21A and Fig. 21B show the timing of the data reading process for the buffer memories 53a and 53b.

Meanwhile, in the VH mode, the buffer memory control circuit 54a or 54b may be configured as shown in FIG. 22. In FIG. 22, the replacement control circuit, the address counter control circuit, the upper address control circuit, and the buffer input are shown. A configuration corresponding to the / output control circuit is shown, and other circuits are configured in the same manner as in FIG.

In such a configuration, when data is first written to the buffer memory 53a or 53b, when a signal in-exc is applied from the control circuit 57, the address counter 58a or 58b is outputted from the oragate 150. ), The clear output (ac-clr) for counting up increases, and the counter 154 is enabled, and the read enable output (buf-rd) and the write to the buffer memory 53a or 53b are lost. The navel output buf-wr starts to be output from the decoder 156 and the NAND gate 157, respectively. Then, the address generation programmable counter 152 is counted up by a carry every four counts of the counter 154. The programmable counter 152 is an input bit width counter, and a carry is generated for each number so that the buffer selection circuit counter 151 counts up. In this case, since the upper address is 2 bits, the programmable counter 152 also has a 2-bit configuration. When the input bit width is 4 bits, 8 bits, 12 bits, or 16 bits, respectively, the programmable counter 152 operates as a binary, binary, ternary, and ternary counter, respectively. Therefore, when the input bit width corresponds to 16 bits, a clock output (ac-upe) that counts up the address counter 58a or 58b each time read / write access to the buffer memory 53a or 53b is executed in 16 cycles. Is generated, the address counter 58a or 58b is counted up.

Next, in the case of reading data from the buffer memory 53a or 53b, the buffer memory control circuit 54a or 54b is enabled in response to the output ot-exc from the control circuit 57 and output ( Instead of buf-wr, an output (ac-upe) is generated for each cycle. In this case, the upper address is preferably updated every four line outputs, so it is updated by the out-cup of the control circuit 57. do. The read or write mode of the buffer memory 53a or 53b is specified by the control circuit 57 mode signal (buf Ar-mode or buf Aw-mode).

Next, the vertical / horizontal conversion operation of the vertical / horizontal conversion circuit 35 will be described. For example, as shown in FIG. 23A, the image information stored in the page memory 14 or the display memory 15 is rotated 90 degrees to the right as shown in FIG. 23B, and the rotated image information is rotated by the page memory 14. The case where the data is stored in the printer or printed out by the printer 25 will be described.

First, image data in 16-bit units corresponding to 16 pixels supplied from the page memory 14 via the image bus 42, for example, data ″ P0000 to P0015 for the first word of the first line shown in FIG. Is supplied to the serial / parallel conversion circuit 55 via the input circuit 51, and the image information converted into parallel data by the serial / parallel conversion circuit 55 is supplied to the buffer memory control circuit 54a. do. Then, in the buffer memory control circuit 54a, as shown in FIG. 25A and FIG. 25B, one bit is sequentially stored in the areas A to P in the buffer memory 53a. For example, data "0000" is stored in the area A, data "0001" in the area B, data "0002" in the area C, and data "0003" in the area D. . In the case where the input data width is 4 bits or more, subsequent data in the same word is stored in the upper region of the buffer memory by increasing the upper address every 4 bits of storage processing. ), The data "0015" is stored in the area P.

When data "P0100 to P0115" for the second word of the first line is supplied, data "0100" is in the area A, data "0101" is in the area B, and data "0102" is in the area. In (C), the data "0115" is stored in the area P sequentially. In this case, the data of the second word in each area is stored adjacent to the data of the first word.

When the image data corresponding to one frame is stored in the buffer memory 53a, the buffer memory control circuit 54a stores 4-bit data in the lowest address of the areas A to D of the buffer memory 53a. 4-bit data in the second lower address of the areas A to D, 4-bit data in the third lower address of the areas A to D, and 4-bit data in the fourth lower address of the areas A to D. , The 4-bit data in the fifth sub-address of the areas A to D, the 4-bit data in the sixth sub-address of the areas A to D, and so on. The data is output to the internal bus 39 as output image data via the 56 and the output circuit 52, and then output to the printer 25 via the printer interface 38.

In contrast, as shown in FIG. 26A, the image information stored in the page memory 14 is rotated 90 degrees to the left as shown in FIG. 26B, and the rotated image information is displayed on the CRT display device 24. As shown in FIG. Even in this case, by changing the order of the storage areas for the buffer memories 53a and 53b, the same operation as in the case of rotating 90 degrees to the right side is performed.

In the main part of the vertical / horizontal conversion circuit, the operation is performed by the processing timing as shown in FIGS. 27A, 27B, 28, and 29, wherein the 27A, 27B are stored in the buffer memory. Fig. 28 and Fig. 29 show timings of the data key lock processing for the buffer memory.

Next, an operation of displaying the chemical information read by the scanning device 20 on the CRT display device 24 will be described.

First, as shown in FIG. 3, in the state where the read condition of the scanning device 20 is set, the operator selects a document size of “A4H (horizontal length image)” as the read condition and selects “90 ° left turn”. Choose. In this state, the operator sets the A4 size document in the horizontal length direction (horizontal direction) with respect to the scanning direction of the document glass (not shown) of the scanning apparatus 20 as shown in FIG. Then, the scanning device 20 reads the document two-dimensionally by scanning the document and converts it into image information. This image information is supplied to the vertical / horizontal conversion circuit 35 via the interface 37 and the internal bus 39, which are scanning devices. In this case, since the rotation angle is 90 ° left rotation, the image information supplied from the internal bus 39 is rotated 90 ° leftward as described above by the vertical / horizontal conversion circuit 35, and then the image bus 42 ) To be supplied to the page memory 24. As a result, the image read out by the scanning device 20 is rotated by 90 degrees to the left as shown in FIG. 16A in the page memory 14 so as to be stored.

Image information stored in the page memory 14 is supplied to the display memory 15 via the image bus 42. Accordingly, the image information stored in the display memory 15 is supplied to the CRT display device 24 via the display control circuit 16. As a result, the image information read out by the scanning device 20 is rotated 90 degrees to the left and displayed on the CRT display device 24. In addition, the image read out by the scanning device 20 can be performed in the same manner as described above even when the image is rotated 90 degrees right, 180 degrees or without being rotated.

Next, the operation in the case where the optical disk device 22 stores the image information stored in the page memory 14 in various rotation states as described above will be described.

First, if a recording command is applied while the unrotated image information (vertical length image) supplied from the scanning device 20 is stored in the page memory 14 as described above, it is stored in the page memory 14. The existing image information is supplied to the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35 via the image bus 42. In this case, since the rotation angle is 0 degrees, the image information supplied from the image bus 42 is supplied to the buffer memory 14a via the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35. As a result, the image information stored in the buffer memory 14a is supplied to the optical disk device 22 via the interface 17. As a result, the image information supplied by the optical disc apparatus 22 is stored in the optical disc (not shown).

Next, an operation of printing out the image information stored in the page memory 14 by the printer 25 in various rotation states will be described.

First, when a print output command is applied in a state in which 90 ° left turn or 90 ° right rotated image information (vertical length image) supplied from the scanning device 20 is stored in the page memory 14 as described above, the page memory Image information stored in (14) is supplied to the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35 via the image bus 42. In this case, since the rotation angle is 0 °, the image information supplied from the image bus 42 passes through the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35 to the internal bus 39 and the printer interface 38. It is supplied to the printer 25 via the medium. Accordingly, the printer 25 prints out the supplied image information.

When a print output command is applied in a state in which vertical length image information that is not rotated (or rotated 180 °) is stored in the page memory 14, the image information stored in the page memory 14 is stored in the image bus ( 42 is supplied to the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35. In this case, since the rotation angle is 90 ° left turn, the image information supplied from the image bus 42 is rotated 90 ° to the right (vertical / horizontal conversion) by the vertical / horizontal conversion circuit 35, and then the internal bus 39 And the printer interface 38 via the printer interface 38. Accordingly, the printer 25 prints out the supplied image information.

In this way, the printer 25 can print out various sizes of documents in the same direction (horizontal direction), so that the directions of the information can be arranged in the same direction, thereby providing compatibility.

Next, the operation in the case of transferring image information stored in the page memory 14 to various external devices such as a LAN and a facsimile device in various rotation states will be described.

First, if a transfer command to an external device is applied while the unrotated image information supplied from the scanning device 20 is stored in the page memory 14 as described above, it is stored in the page memory 14. The image information is supplied to the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35 via the image bus 42. In this case, since the rotation angle is 0 °, the image information supplied from the image bus 42 is compressed / extended via the internal bus 39 via the enlargement / reduction circuit 34 and the vertical / horizontal conversion circuit 35. To the circuit 34. Accordingly, the image information compressed by the compression / expansion circuit 34 passes through the image bus 42 via the compression / expansion circuit 34 and the vertical / horizontal conversion circuit 35 via the internal bus 39. Via the buffer memory 14a, it is supplied. As a result, the image information stored in the buffer memory 14a is transmitted to an external device (not shown) via the UCP 43 or the BCP 44.

Also, the image information read out from the optical disk by the optical disk device 22 is displayed on the CRT display device 24, printed out by the printer 25, or transmitted to external devices such as LAN and facsimile device. In the same case, the same operation as described above is performed. In this case, however, the image information is rotated according to the rotation direction and the document size added to the search code.

Also, the image information supplied from an external device such as a LAN or a facsimile device is displayed on the CRT display device 24, printed out by the printer 25, or recorded on an optical disc. Even in this case, the image information is rotated according to the size (vertically and horizontally extending image) and rotation direction of the document attached to the search code.

As described above, since the image read out by the scanning device 20 can be directly or rotationally converted and recorded in the page memory or displayed on the CRT display device 24, the horizontal direction (horizontal direction) of the scanning device is changed. The image information read out from the document thus placed can be displayed as a vertical length image, and the image information read out from the document placed along the vertical direction (vertical direction) of the scanning device can be displayed as a horizontal length image. That is, the image information can be rotated in any direction regardless of the direction of the document placed on the scanning apparatus.

Further, the image read out from the optical disc can be displayed on the CRT display device 24 in a state extending vertically regardless of the direction recorded on the optical disc, and furthermore, the horizontal / vertical conversion process is read out to the buffer memory. / Because the recording access is performed in units of a plurality of bits rather than in units of bits, the circuit configuration can be miniaturized.In addition, even when the image is rotated, the image is rotated before displaying rather than displaying the image once and then rotating it. This can shorten the processing time.

As described above, since the data read out from the page memory 14 can be rotated and output directly to the printer 25 (without rotating), the image output from the printer 25 is output to the page memory 14. It can be rotated arbitrarily regardless of the direction of the stored state. For example, data can be printed by setting the paper feed direction to match the horizontal direction of the paper. Therefore, the printing direction of the printer 25 can be set to match the horizontal direction (horizontal direction), thereby reducing the processing time of the printer output by 40% or more, and using ordinary paper (A4 size). Further shortening can be achieved, and compatibility can be maintained.

On the other hand, in the above embodiment, the horizontal / vertical conversion operation in the case of transferring the image information from the scanning apparatus to the page memory has been described. However, the present invention is not limited thereto, and for example, image information read by the scanning apparatus is read. It can be stored in page memory without conversion, and then horizontally / vertically converted. That is, the image information from the scanning device 20 is connected to the interface 37, the internal bus 39, the vertical / horizontal conversion circuit 35, the enlargement / reduction circuit 34, and the image bus 42, which are scanning devices. Image information stored in the page memory 14 through the image bus 42 is supplied to the vertical / horizontal conversion circuit 35 via the image bus 42, and the vertical / horizontal conversion circuit 35 Is converted into the page memory 14 via the image bus 42. In this case, the page memory 14 requires two address control circuits. .

On the other hand, as the recording medium, an optical disc has been described as an example. However, the present invention is not limited thereto, and an optical memory card or a laser card may be used.

[Effects of the Invention]

As described above, according to the present invention, it is possible to arbitrarily rotate irrespective of the direction of the input image, to shorten the processing time in the case of rotating the image information, and to rotate the image arbitrarily when outputting the image. It is possible to provide an image processing apparatus.

Claims (16)

Means 20 for reading out an image from an original and outputting image information data in the order in which the image is read, and image information data representing an image rotated by 90 ° by processing the image information data output from the image reading means 20. Means (35) for outputting an image, and means (15) for storing image information data representing a 90 degree rotated image output from the readout output means (54a, 54b) of the processing means (35). The processing means 35 includes means 51 and 55 for sequentially reading out the image information data supplied from the image reading means 20 in predetermined bit units and for storing the image information data. The means 53a and the storage area of the storage means 53a are divided into a plurality of storage areas A to P, and image information data read out in predetermined bit units is stored in the divided storage areas A to P. Bit by bit, sequential, distributed memory Means (54a, 58a) and means (54a, 58a) for outputting image information data read out sequentially by predetermined bit units from the divided storage areas (A-P). An image processing apparatus. 2. The processing means (35) according to claim 1, wherein said processing means (35) is composed of two sets each having said sequential reading means, said storing means, said dividing means, and said readout output means, while one set outputs image information. And an image processing apparatus characterized by storing image information. The apparatus of claim 1, further comprising means (24) for displaying image information, wherein said processing means (35) rotates the image information sequentially supplied from said image reading means (20) by 90 DEG to 90 degrees. An image processing apparatus characterized by displaying an image rotated 90 degrees on the image display means (24) by supplying the image data indicating the rotated image to the image display means (24). 4. The processing unit (35) according to claim 3, wherein said processing means (35) includes means (51, 55) for sequentially reading out image information data supplied from said image reading means (20) in predetermined bit units, and said image information data. The storage area (A-A) which divides the image information data read out in predetermined bit units by dividing the storage area (53a) for storing the data and the storage area of the storage means (53a) into a plurality of storage areas (A-P). Means 54a, 58a for storing the data sequentially in P by 1 bit, and image information is sequentially read out from the divided storage areas A to P in predetermined bit units, and the image display means 24 is read. And means (54a, 58a) for outputting the image information data read out in " 5. The processing means (35) according to claim 4, wherein said processing means (35) is comprised of two sets each having said sequential reading means, said storing means, said dividing means, and said reading output means, so that one set of the other sets is output while image information is output. And an image processing apparatus characterized by storing image information. An image processing apparatus according to claim 1, further comprising means (57) for designating whether or not to perform a rotation operation on the image information in said processing means (35). Means (14) for storing image information data, means (35) for processing image information data supplied sequentially from the image storage means (14) and outputting image information data representing an image rotated by 90 degrees; And means (25) for printing and outputting an image rotated by 90 degrees represented by image information data output from the readout output means (54a, 58a) of the processing means (35), and the processing means (35). Means (51, 55) for sequentially reading out image information data from said image storage means (14) in predetermined bit units, means (53a) for storing said image information data, and said storage means ( 53a) is divided into a plurality of storage areas A to P, and image information data read out in predetermined bit units is sequentially and distributedly stored one bit at a time in the divided storage areas A to P. Giving means 54a, 58a and the divided Image processing, characterized in that it comprises means (54a, 58a) for sequentially reading out image information from the storage areas A to P in predetermined bit units and sequentially reading and outputting image information data to the printing means 25. Device. 8. The processing means (35) according to claim 7, wherein said processing means (35) is composed of two sets each having said sequential reading means, said storing means, said dividing means, and said reading output means, so that one set of the other means outputs image information. An image processing apparatus characterized in that the pair is configured to store image information. 8. The apparatus according to claim 7, further comprising means (24) for displaying image information, wherein said processing means (35) rotates the image information read out sequentially from said image storage means (14) by 90 degrees. And an image rotated by 90 degrees on the image display means (24) by supplying image information data indicating a 90 'rotated image to the image display means (24). 10. The apparatus according to claim 9, wherein said processing means (35) stores means (51, 55) for sequentially reading out image information data from said image storage means (14) in predetermined bit units, and said image information data. The storage area (A-P) is divided into a plurality of storage areas (A-P) for storing the means 53a and the storage area of the storage means 53a into a plurality of storage areas A-P. (A) means for sequentially and distributedly storing the data bit by bit, and image information is sequentially read out from the divided storage areas A to P in predetermined bit units, and the image information is displayed in the arrow direction. And means (54a, 58a) for reading out and outputting the means (24). 11. The processing means (35) according to claim 10, wherein the processing means (35) is composed of two sets each having the sequential reading means, the storing means, the dividing means, and the reading output means, so that one set of the other sets is outputted while the other sets And an image processing apparatus characterized by storing image information. 8. An image processing apparatus according to claim 7, further comprising means (57) for designating whether or not to perform a rotation operation on the image information in said processing means (35). Means for sequentially receiving image information data in units of a first predetermined number of bits, and means for sequentially reading out image information data in units of a first predetermined number of bits received by the receiving means in units of a second predetermined number of bits; Means for storing the image information data, and means for storing the storage area of the storage means sequentially and distributed one bit at a time in the divided memory area in which a plurality of storage areas are divided and read out by the predetermined number of bits. And means for sequentially reading out image information from the divided storage area in units of a second predetermined number of bits and outputting the read information, and means for sequentially transmitting the image information in units of a third predetermined number of bits. A vertical / horizontal conversion device, characterized in that for converting image information data representing image rotated by 90 °. 14. The apparatus according to claim 13, further comprising a first device comprising the read means, the storage means, the divide means and the read output means, and a second device composed of the read means, the memory means, the divide means and the read output means, And the other device stores the image information while one of the two devices outputs the image information. The vertical / horizontal conversion device according to claim 13, wherein the first predetermined number of bits is an integer multiple of the second predetermined number of bits. The vertical / horizontal conversion device according to claim 13, wherein the third predetermined number of bits is an integer multiple of the second predetermined number of bits.

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