JP2000242446A - Memory control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of a line buffer. SOLUTION: This unit 10 is provided with a memory controller 12, a page memory 14, a line buffer controller 16, an odd line buffer 18 and an even line buffer 20 or the like. The line buffer controller 16 performs control so as to write odd-numbered pixel data in pixel data, which are outputted from the page memory 14, into the odd line buffer 18, simultaneously, to read even- numbered pixel data written in the even line buffer 20, to read the pixel data out of the odd line buffer 18 and simultaneously to write the even-numbered pixel data in the even line buffer 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device, and more particularly to a storage control device used for a printer capable of performing double-sided printing.

[0002]

2. Description of the Related Art In recent years, as personal computers have become widespread, printers as output devices have been required to have higher functions. One example is double-sided printing. FIG.
FIG. 6A shows an example of duplex printing on A4 size (vertical) paper, and FIG. 6B shows an example of duplex printing on A4 size (horizontal) paper. The arrow indicates the direction of page turning. As shown in FIGS. 6 (A) and 6 (B), the printing method of the characters (Iroha) to be printed on the back surface 52 with respect to the characters (ABC) to be printed on the front surface 50 is as follows: Depends on

For example, consider a case in which A4 size (vertical) paper is conveyed in the longitudinal direction of the paper and the front side is printed, and then the paper is turned over in the longitudinal direction and the back side is printed. FIG.
As shown in FIG. 7, when the same character (ABCDEF) is printed on the front surface 54 and the back surface 56 on A4 size (vertical) paper, as shown in FIG. It is sufficient to print from the pixel corresponding to the upper left portion of the paper, but when printing on the back surface 56, as shown in FIG. 7B, the printing is performed from the pixel corresponding to the lower right portion of the paper. There must be. That is, the transfer (printing) direction of pixels when printing on the back surface is opposite to the main scanning and sub-scanning directions.

For this reason, when printing on the back side of a sheet, the image information is inverted and read from the memory in which the image information is stored, so that the upper and lower sides of the recording sheet are on the same side. (See JP-A-61-4364).

[0005] However, the printer described in the above publication has a problem in that the operation speed is reduced because image information is written and read from the line memory separately.

In order to solve this problem, for example, there is a printer that improves the operation speed by reading image information from the other line buffer while writing image information to one line buffer.

FIG. 8 shows an example of a storage control device of a printer that performs such double-sided printing. Storage control device 6 shown in FIG.
0 is a page memory (or 1) for storing image data.
Band buffer memory for storing image data obtained by dividing pages) 62, odd number for storing image data for one line
A line buffer 64 (hereinafter referred to as Odd), an even number (hereinafter referred to as Even) line buffer 66, a line buffer controller 68 for controlling read / write of the Odd line buffer 64 and the Even line buffer 66,
An address up counter 70 and an address down counter 7 for incrementing or decrementing the address of reading or writing of image data with respect to the odd line buffer 64 or the even line buffer 66.
2, the selectors 74 and 76 for switching read / write addresses of the Odd line buffer 64 and the Even line buffer 66, a memory controller 78 for controlling the page memory 62 and the line buffer controller 68, and a print control unit 80.

First, normal printing, that is, printing on the front surface will be described. The memory controller 78 outputs an image data transfer request and a read start address signal to the page memory 62, that is, an address corresponding to an upper left pixel of a sheet to be printed. The page memory 62
The data transfer signal is output to the line buffer controller 68 and is also output to the image data Odd line buffer 64 and the even line buffer 66 at the designated addresses. When receiving the data transfer signal, the line buffer controller 68 sets the selector switching signal 82A to, for example, a low level (selects the address up counter 70) and outputs a write signal 84A to the odd line buffer 64. As a result, in the Odd line buffer 64, the address (1) output from the address up counter 70 is output.
The image data for one line is written in order from the address (see FIG. 9 (1) (A)).

Next, the line buffer controller 68 outputs a read signal 86 A to the odd line buffer 64 and outputs a transfer signal to the print control unit 80. Also,
At the same time, the selector switch signal 82B is set to the high level (the address up counter 70 is selected), and the write signal 84B is output to the even line buffer 66.
Thereby, the 1 stored in the Odd line buffer 64
The image data of the line is read and output to the print control unit 80, and the image data of the second line is written in the even line buffer 66 in order from the address (address 1) output from the address up counter 70 (FIG. 9 (1) (B)).

In the same manner, writing and reading are alternately repeated. That is, when the image data is being written to the odd line buffer 64, the image data is read from the even line buffer 66, and when the image data is being read from the odd line buffer 64, the image data is written to the even line buffer 66 (FIG. 9). (1)
(C)).

Next, printing on the back surface will be described. The memory controller 78 outputs an image data transfer request and a read start address signal to the page memory 62. When printing on the back side, since the front and back sides of the sheet are upside down, the address corresponding to the lower left pixel of the sheet to be printed is output. The page memory 62 outputs a data transfer signal to the line buffer controller 68 and outputs image data at a designated address. When receiving the data transfer signal, the line buffer controller 68 sets the selector switching signal 82A to low level and outputs the write signal 84A to the odd line buffer 64. Thus, in the Odd line buffer 64, one line of image data is written in order from the address output from the address up counter 70 (FIG. 9 (2)).
(A)).

Next, the line buffer controller 68 sets the selector switching signal 82A to high level, outputs the read signal 86A to the odd line buffer 64, and outputs the transfer signal to the print control unit 80. At the same time, the selector switching signal 82B is set to the high level, and the write signal 84B is output to the even line buffer 66. As a result, in the Odd line buffer 64, the address down counter 72 is selected, and the image data for one line is read out in the opposite direction to that on the front side, and the print control unit 8
0 and 2 in the Even line buffer 66.
The image data of the line is written (FIG. 9B)
(B)). Hereinafter, writing and reading are alternately repeated in the same manner. That is, the Odd line buffer 64
When the image data is written in the even line buffer 66, the image data is read from the even line buffer 66 in the opposite direction to the front surface, and when the image data is read from the odd line buffer 64 in the opposite direction to the front surface, the even line buffer 66 is read. The image data is written in (2) (C) of FIG.

As described above, two line buffers in the main scanning direction are provided so that writing and reading are performed alternately, and in the case of backside printing, the reading direction is reversed from the writing direction to support double-sided printing. .

[0014]

However, in the above-mentioned prior art, 256 colors, 60
When printing at 0 dpi, a relatively large 8 kbyte line buffer is required. In order to increase the speed, it is necessary to access the line buffer every two or four pixels (two clock access, four clock access). In this case, 32 kbytes or 64 kbytes are required.
A line buffer with a large capacity of bytes is required.

The present invention has been made to solve the above problem, and has as its object to provide a storage control device capable of reducing the capacity of a line buffer.

[0016]

According to another aspect of the present invention, there is provided a storage control device for storing pixel data of an odd-numbered pixel among pixels in a main scanning direction of an input image. 1 storage means, second storage means for storing pixel data of even-numbered pixels among pixels in the main scanning direction of the input image, and storing pixel data of the input image in odd-numbered pixels and even-numbered pixels. Next to the address where the pixel data alternately written to the first storage means and the second storage means and read from the first storage means and the second storage means are alternately stored. Control means for sequentially repeating alternately writing pixel data of
It is characterized by having.

According to the first aspect of the present invention, two storage units are provided, and the first storage unit stores pixel data of an odd-numbered pixel among pixels in the main scanning direction of the input image. The pixel data of the even-numbered pixel is stored in the second storage means. The control means divides the pixel data of the input image into odd-numbered pixels and even-numbered pixels and writes them alternately in the first storage means and the second storage means, and the first storage means and the The alternate writing of the next pixel data to the address where the pixel data alternately read from the second storage means is stored is sequentially repeated.
That is, when the pixel data is being written to the first storage means, the pixel data is read from the second storage means, and then the next pixel data is stored at the address where the pixel data read from the second storage means is stored. Is written, and the pixel data written in the first storage means is read. By repeating this sequentially, all input images are read out and printed by the print control unit. As described above, by providing two storage units and performing writing and reading alternately for each pixel instead of for each line, the storage capacity of the storage unit can be reduced.

When the writing speed is different from the reading speed, for example, when the writing speed is higher than the reading speed, there is a possibility that data which has not been read is erroneously overwritten.

Therefore, a second aspect of the present invention is the storage control device according to the first aspect, wherein the read timing is performed at a timing different from the write timing.

According to the second aspect of the invention, the read speed is higher than the read speed by setting the read timing to be different from the write timing, for example, by waiting for the write to be performed. Even in such a case, printing can be performed normally.

According to a third aspect of the present invention, in the storage control device according to the first aspect, the first storage means and the second storage means are provided.
The pixel data stored in the storage means is read out in the direction opposite to the writing direction of the pixel data and sequentially recorded on the back surface of the sheet.

According to the third aspect of the present invention, the first
The pixel data stored in the storage means and the second storage means are read in the direction opposite to the writing direction of the pixel data, and are sequentially recorded on the back surface of the sheet. For example, in the case of a printer that prints the front side and then reverses the paper and prints the back side, when printing on the back side, the direction of the paper is reversed. It is necessary to print from the pixel data on the opposite side. Therefore, when reading the pixel data, the pixel data is read in the direction opposite to the writing direction, so that when printing on the back surface, the pixel data is sequentially printed from the pixel data on the opposite side in the main scanning direction. Matches.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a storage control device 10 according to the present embodiment. The storage control device 10 shown in FIG.
Are the memory controller 12, page memory 14, line buffer controller 16, Odd line buffer 1
8, Even line buffer 20, write address up counter 22U, write address down counter 22D, read address up counter 23U, read address down counter 23D, selector 24A,
24B, 26A and 26B, and a print control unit 28.

The memory controller 12 controls the page memory 14 and the line buffer controller 16.
The page memory 14 stores one page of image data. Note that a band buffer memory for storing image data obtained by dividing one page may be used instead of the page memory.

The line buffer controller 16 includes an Odd line buffer 18 for storing odd-numbered line data of the image data output from the page memory 14 and an Even line buffer 2 for storing even-numbered line data.
For 0, a write signal 40 (write at low level),
A read signal 42 (read at low level) is output to control read / write. Further, the line buffer controller 16 outputs the counter switching signal 36 to the selector 24A,
24B, and outputs the selector switching signal 38 to the selector 26B.
A, 26B and output to the Odd line buffer 18 and E
The address for reading / writing to the ven line buffer 20 is controlled.

Write address up counter 22U,
The write address down counter 22D outputs write address signals (address values) 44U and 44D to the Odd line buffer 18 and the Even line buffer 20, respectively. For example, assuming that 1 byte / 1 pixel, the write address up counter 22U increments the address value by one in order from 1, and the final address value (the Odd line buffer 18 and the Odd line buffer 18 Ev
When the size of the en line buffer 20 is incremented to 4096 when the size of the en line buffer 20 is 4 kbytes, the process returns to 1. Pixel data is written into the count value, that is, the address. Conversely, the write address down counter 22
D indicates that the address value is the final address value (the size of the odd line buffer 18 and the even line buffer 20 is 4).
In the case of k bytes, it is decremented by one in order from 4096), and when decremented to 1, the process returns to the final address value.

The read address up counter 23U,
The read address down counter 23D outputs read address signals 46U and 46D to the Odd line buffer 18 and the Even line buffer 20. Like the write address up counter 22U and the write address down counter 22D, the read address up counter 23U and the read address down counter 23D increment, for example, the address value by one in order from 1 in the case of the read address up counter 23U, After incrementing to the value, it returns to 0. Pixel data is read from the counted address. Conversely, the read address down counter 2
In 3D, for example, the address values are sequentially set to 1 from the last address value.
The address is decremented one by one, and when decremented to 0, returns to the final address value.

The increment or decrement is performed each time writing or reading to the same address in both the odd line buffer 18 and the even line buffer 20 is completed.

When the counter switching signal 36 output from the line buffer controller 16 is at a low level, the selector 24A outputs the write address up counter 22U.
The address signal 44U output from the write address down counter 22D is selected when the address signal 44U is high, and the selector 26
A, 26B.

When the counter switching signal 36 output from the line buffer controller 16 is at a low level, the selector 24B reads out the read address up counter 23U.
The address signal 46U output from the write address down counter 23D is selected when the address signal 46U is high level.
A, 26B.

The selector 26A selects the address signal output from the selector 24A when the selector switching signal 38 output from the line buffer controller 16 is at a low level, and selects the address signal output from the selector 24B when the selector switching signal 38 is at a high level. And outputs it to the Odd line buffer 18.

The selector 26B selects the address signal output from the selector 24B when the selector switching signal 38 output from the line buffer controller 16 is at a low level, and selects the address signal output from the selector 24A when the selector switching signal 38 is at a high level. And outputs it to the Even line buffer 18.

Table 1 shows the Odd line buffer 1 based on the combination of the counter switching signal 36 and the selector switching signal 38.
8 and the address signal selected by the Even line buffer 20.

[0035]

[Table 1]

The writing of pixel data to the Odd line buffer 18 is performed when the write signal is at a low level and the selector switching signal 38 is at a low level.
Writing of pixel data to the en line buffer 20 is performed as follows.
This is performed when the write signal is at a low level and the selector switching signal is at a high level. Conversely, reading of pixel data from the Odd line buffer 18 is performed when the read signal is at a low level and the selector switching signal 38 is at a high level. Reading of pixel data from the even line buffer 20 is performed when the read signal is This is performed when the selector switching signal 38 is at the low level and at the low level.

The print controller 28 has a register 28A for storing the image data output from the odd line buffer 18 or the even line buffer 20, and controls the printing of the image data output to the register 28A.

Next, the operation of this embodiment will be described.

First, normal printing, that is, printing on the front surface will be described. The transfer request signal of the image data to be printed on the front side from the memory controller 12 to the page memory 14 and the read start address signal 30, that is, the address corresponding to the top pixel (left end pixel) of the top line of the print image is Is output. Page memory 1
4 outputs the data transfer signal 32 as shown in FIG. 2 to the line buffer controller 16 (enables it (makes it high level)) and sequentially outputs the image data 34 of the designated read start address. The image data 34 is output from the first line to the last line (n-th line) when the front side is printed. When the data transfer signal 32 is at a low level, only reading can be performed, and when the data transfer signal 32 is at a high level, reading can be performed with a write priority.

The write address up counter 2
2U and the read address up counter 23U
dd line buffer 18 and Even line buffer 2
The address value is incremented by one from 1 each time writing or reading to both the same addresses of 0 is completed. Conversely, the write address down counter 22
D and the read address down counter 23D decrement the address value by one from the final address value (for example, 4096).

Upon receiving the data transfer signal 32, the line buffer controller 16 sets the counter switching signal 36 and the selector switching signal 38 as shown in FIG. 2 to low level, and outputs the write signal 40 as shown in FIG. Output to Thereby, the selector 24
A selects the write address up counter 22U,
The selector 26A selects the selector 24A. Therefore,
As a write address signal to the odd line buffer 18, an address signal 44U output from the write address up counter 22U is selected, and a corresponding address (1
The pixel data of the first pixel is written to the address. In addition,
Although the write signal is also output to the even line buffer 20, the pixel data is not written because the selector switching signal 38 is at the low level.

Next, the line buffer controller 16 sets the selector switch signal 38 to high level and outputs a read signal 42 as shown in FIG. As a result, the selector 26B selects the selector 24A.
The address signal 44U output from the write address up counter 22U is selected as the write address signal to the n-line buffer 20, and the pixel data of the second pixel is output at the timing when the write signal 40 becomes low level at the corresponding address (address 1). Is written.

At this time, the selector 26A selects the selector 24B because the selector switching signal 38 is at the high level, and the selector 24B outputs the counter switching signal 36.
Is low level, the address signal 46U output from the read address up counter 23U is selected. Therefore, one of the Even line buffers 20
At the same time when the second pixel is written to the address, the first pixel from the first address of the Odd line buffer 18 is read at the timing when the read signal 42 becomes low level as shown in FIG. You. At this time, a print data transfer signal 33 is output to the print control unit 28. The print controller 28 controls the read pixel data to be printed on recording paper.

Thereafter, similarly, the Odd line buffer 18
Pixel data is read from the even line buffer 20 when pixel data is being written into the
The writing and reading of pixel data are performed alternately, such as writing pixel data to the n-line buffer 20, as shown in FIG.
The timing is as shown in FIG. Note that no data is written in the shaded portion in FIG.

FIG. 3 shows a print image at this time. As shown in FIG. 3, the arrangement of the pixel data in the main scanning direction on the first line is “abc, d, e, f,.
.W.x.y.z], and the arrangement of pixel data in the main scanning direction of the second line is "a ', b', c ', d'.
e '・ f' ・ ・ ・ u '・ v' ・ w '・ x' ・ y '・
z ′], first, the pixel data a of the first pixel of the first line is added to the Odd line buffer 18 by Odd.
The data is written to address 1 of the line buffer 18.

Next, the pixel data b of the second pixel of the first line is written to the address 1 of the even line buffer 20, and at the same time, the pixel data a is read from the address 1 of the odd line buffer 18 and recorded. It is printed at the first pixel on the first line of the paper. Next, the pixel data c of the third pixel of the first line is stored in the odd line buffer 18.
And at the same time, the pixel data b is read from the address 1 of the even line buffer 20 and is printed on the second pixel of the first line of the recording paper. This is repeated up to the pixel data z, and when the printing of the first line is completed, the processing of the second line is started and repeated until the end of one page. In this example, the first pixel of the first line is printed when the second pixel of the first line is written to the even line buffer 20. The printing start timing is set after the pixel data is written. Any time you want. For example, it may be after reading all the pixel data for one line.

Next, printing on the back surface will be described. The transfer request signal and read start address signal 30 of the image data to be printed on the back side from the memory controller 12 to the page memory 14, that is, the read start address signal 30 corresponds to the first pixel (left end pixel) of the last line (n-th line) of the print image. The address is output. The page memory 14 outputs the data transfer signal 32 to the line buffer controller 16 and sequentially outputs the image data 34 at the designated read start address. The image data 34 is output from the last line (n-th line) to the first line when printing the back surface.

When receiving the data transfer signal 32, the line buffer controller 16 sets the counter switching signal 36 and the selector switching signal 38 to low level, and outputs the write signal 40 to the Odd line buffer 18. Thereby, the selector 24A selects the write address up counter 22U, and the selector 26A selects the selector 24A. Therefore, the write address signal to the Odd line buffer 18 is equal to the write address up counter 22.
The address signal 44U output from U is selected, and the pixel data of the first pixel is written to the corresponding address (address 1).

Next, the line buffer controller 16 sets the selector switching signal 38 to a high level. Thus, the selector 26B selects the selector 24A,
As the write address signal to the even line buffer 20, the address signal 44U output from the write address up counter 22U is selected, and the pixel data of the second pixel is generated at the timing when the write signal 40 becomes low level at the corresponding address (address 1). Is written.

In the same manner, the Odd line buffer 18
And one line of pixel data is written into the even line buffer 20. The read signal is kept at a high level until one line of pixel data is written. Therefore, the reading operation is not performed while the pixel data for one line is written.

Next, the line buffer controller 16
Sets the counter switching signal 36 to a high level and the selector switching signal 38 to a low level, and outputs a read signal. Thus, the selector 24B selects the read address down counter 23D, and the selector 26B selects the selector 24B. Therefore, as a read address signal for reading pixel data from the even line buffer 18, the address signal 46D output from the read address down counter 23D is selected, the pixel data of the first pixel from the final address is set to the low level, and the read signal 42 is set to the low level. And is output to the print control unit 28.

Next, the line buffer controller 16
Sets the selector switching signal 38 to high level. Thereby, the selector 26A selects the selector 24B. Accordingly, a read address signal for reading pixel data from the Odd line buffer 20 is an address signal 46D output from the read address down counter 23D.
Is selected, and the pixel data of the first pixel from the final address is read at the timing when the read signal 42 becomes low level, and is output to the print control unit 28. At this time, since the counter switching signal 36 and the selector switching signal 38 are at the high level, the even line buffer 2
At 0, the address signal 44D output from the write address down counter 22D is selected, and the head pixel data of the (n-1) th line is written to the last address.

Next, the line buffer controller 16
Sets the selector switching signal 38 to low level. As a result, in the Even line buffer 20, the address signal 46D output from the read address down counter 23D is selected, and pixel data is read from the address of (last address -1) and output to the print control unit 28. At the same time, the Odd line buffer 18
Then, the address signal 44D output from the write address down counter 22D is selected, and the pixel data of the second pixel on the (n-1) th line is written to the final address. The above operation is repeated until the printing of the first line is completed.

FIG. 4 shows a print image at this time. As shown in FIG. 4, the arrangement of the pixel data in the main scanning direction of the n-th line is “abc, d, e, f,.
.W.x.y.z], and the arrangement of pixel data in the main scanning direction of the (n-1) th line is "a'.b'.c '."
d ', e', f '... u', v ', w', x ', y'
· Z ′], first, the pixel data a of the first pixel in the n-th line is stored in the Odd line buffer 18 as Od.
The data is written to address 1 of the d-line buffer 18.

Next, the pixel data b of the second pixel on the n-th line is written to the address 1 of the even line buffer 20. Hereinafter, the Odd line buffer 18 is similarly operated.
And writing to the even line buffer 20 are alternately repeated, and the last pixel of the n-th line is written to the last address of the even line buffer 20.

Next, the pixel data z is read from the last address of the Even line buffer 20 and printed.
Then, the pixel data y is read from the last address of the odd line buffer 18 and printed, and at the same time
The head pixel data a ′ of the (n−1) th line is written to the last address of the n-line buffer 20.

Next, the pixel data x is read from the address of the (last address -1) address of the Even line buffer 20 and printed, and the Odd line buffer 1 is read out.
The pixel data b ′ of the second pixel on the (n−1) th line is written to the last address of No. 8. Similarly, reading and writing of pixel data are performed alternately in the same manner. This is repeated until the printing of the first line is completed. Accordingly, in the case of back side printing, if n is an even number, reading of pixel data of even lines from the line buffer and writing of pixel data of odd lines to the line buffer are performed from right to left in FIG. Is written, and the writing of the pixel data of the even lines to the line buffer and the reading of the pixel data of the odd lines are performed from left to right in FIG. 4, that is, by incrementing the address. That is, the increment and decrement of the addresses output to the Odd line buffer 18 and the line buffer 20 are performed alternately for each line. As a result, printing is sequentially performed on the back surface from the pixel data at the lower right of the page memory in FIG. 4 to the upper left of the paper, so that the printing direction matches on the front surface and the back surface.

When the write and read timings are different, for example, when write speed ≧ read speed, the write and read timings are as shown in FIG. 5 as an example. In this case, the register 28A of the print control unit 28 is a register capable of storing pixel data of several pixels, and when the register becomes free, the read request signal 48 is sent to the line buffer controller 1.
6 (to high level). Thereby, Od
d line buffer 18 or Even line buffer 2
From 0, pixel data can be read. If there is no free space in the register, the read request signal is set to low level, and reading is prohibited. When the data transfer signal 32 is at a low level, writing is not performed. Therefore, when the read request signal is at a high level, pixel data can be read from the Odd line buffer 18 or the Even line buffer 20 unconditionally. When the signal 32 is at the high level, the read request signal 48 is at the high level. When writing to one line buffer is being performed, reading can be performed from the other line buffer. Can be printed normally even if the numbers are different.

As described above, by providing two line buffers and alternately writing and reading one pixel at a time, the capacity of the line buffer can be reduced to half that of the conventional one, and printing is performed to a larger size. It is possible to cope with a case or a case where a high-density image is printed.

[0060]

As described above, according to the first aspect of the present invention, the control means divides the pixel data of the input image into the odd-numbered pixels and the even-numbered pixels so that the first data is divided into the first and second pixels.
Alternately writing to the storage means and the second storage means, and alternately writing the next pixel data to the address where the pixel data read alternately from the first storage means and the second storage means was stored. Are sequentially repeated, so that the storage capacity of the storage means can be reduced.

According to the second aspect of the present invention, by performing the read timing at a timing different from the write timing, normal printing can be performed even when the write speed is higher than the read speed. It has the effect of being able to.

According to the third aspect of the present invention, the first
The pixel data stored in the storage means and the second storage means are read out in the direction opposite to the writing direction of the pixel data and are sequentially recorded on the back side of the sheet. Can be matched.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a storage control device.

FIG. 2 is a timing chart for explaining the operation of the storage control device.

FIG. 3 is an image diagram for explaining an operation at the time of normal printing.

FIG. 4 is an image diagram for explaining an operation at the time of back side printing.

FIG. 5 is a timing chart for explaining an operation when a writing speed and a reading speed are different.

FIG. 6 is a diagram for explaining duplex printing.

FIG. 7 is a diagram for describing duplex printing.

FIG. 8 is a block diagram illustrating a schematic configuration of a conventional storage control device.

FIG. 9 is a diagram for explaining conventional duplex printing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Storage control device 12 Memory controller 14 Page memory 16 Line buffer controller (control means) 18 Odd line buffer (first storage means) 20 Even line buffer (second storage means) 22U Write address up counter 22D Write address down counter 23U read address up counter 23D read address down counter 24A, 24B selector 26A, 26B selector

Claims (3)

[Claims] A first storage unit that stores pixel data of an odd-numbered pixel among pixels in the main scanning direction of the input image; and a pixel data of an even-numbered pixel among pixels in the main scanning direction of the input image. A second storage unit for storing pixel data of the input image into odd-numbered pixels and even-numbered pixels, and the first storage unit and the second storage unit.
Control means for alternately writing alternately to the storage means, and alternately writing the next pixel data alternately to the address where the pixel data alternately read from the first storage means and the second storage means are stored. , A storage control device. 2. The storage control device according to claim 1, wherein said read timing is performed at a timing different from said write timing. 3. The method according to claim 1, wherein the reading of the pixel data stored in the first storage means and the second storage means is performed in a direction opposite to the writing direction of the pixel data, and the data is sequentially recorded on the back surface of the sheet. The storage control device according to claim 1.