JP2006092506A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor capable of quickly performing mirror processing or turning processing and the line correction of image data. <P>SOLUTION: This image processor 200 is provided with a transfer control part 218 for acquiring image data from an image memory 215, acquiring the number of lines included in a transfer unit from a first receiving part 214, swapping the image data in each swap unit composed of the number of bits included in one pixel of the image data and transferring the image data to a first system memory 212 while decrementing the address of the image data within the transfer unit composed of the number of lines, and a line correcting part 210 for acquiring the image data stored in the first system memory 212, acquiring the number of lines from the first receiving part 214, acquiring the number of line gaps from a second receiving part 204 and rearranging the image data within an area composed of lines on the basis of the number of lines and the number of line gaps. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus.

  As a color image processing apparatus, for example, a copy, a scanner, a printer, a facsimile, and a complex machine of these are conventionally known. Such an apparatus uses the scan function to generate monochrome image data or color image data having a method such as RGB or YMCK.

  As a conventional image processing apparatus, for example, there is one described in Patent Document 1. FIG. 9 shows an image filing apparatus described in this document. In this image filing device, the disk device 50 stores a plurality of image data in a tiled state. The CPU 32 reads image data from the disk device 50 via the interface 44 one tile at a time. The DMA controller 40 rotates or mirror-inverts the read image data for each tile, for example, in units of 90 °, writes the tile data in the tile line buffer, and then reads the image data. The CPU 32 transfers the read image data to the plate making processing workstation 52 via the interface 46.

  According to Patent Document 1, according to this image filing device, when image conversion is performed on image data read from a disk device, the processing burden on the CPU in the plate making workstation is reduced, and the inside of the plate making workstation is It is described that the use efficiency of the main memory can be improved.

  Further, as a conventional image processing apparatus, there is one described in Patent Document 2. A color image processing apparatus described in this document is shown in FIG. The color image processing apparatus includes an R signal processing unit, a G signal processing unit, a B signal processing unit, and a line correction unit 34.

  The R signal processing unit includes a CCD (R) sensor 31a, an analog front end circuit 32a, and an A / D converter 33a. The G signal processing unit includes a CCD (G) sensor 31b, an analog front end circuit 32b, and an A / D converter 33b. The B signal processing unit includes a CCD (B) sensor 31c, an analog front end circuit 32c, and an A / D converter 33c.

  In the above-described color image processing apparatus, for each of R, G, and B colors, line image sensors composed of CCDs are provided in parallel while being slightly shifted in the sub-scanning direction. Since this type of color image processing apparatus is provided with line image sensors for each color in parallel, it is difficult for each color to simultaneously read the same line on the document at the same time. Therefore, conventionally, a line correction memory for delaying image data is provided, the image data is taken out from the line correction memory with a delay amount corresponding to the enlargement / reduction ratio, and the same line on the original is read. The image data of B is aligned.

According to Patent Document 2, since this color image processing device controls the delay amount based on a predetermined calculation formula, color image processing that can achieve a predetermined scaling factor at low cost without increasing the circuit scale. It is stated that a device is provided.
Japanese Patent Laid-Open No. 8-44855 JP 2004-72369 A

  However, the prior art described in the above literature has room for improvement in the following points.

  According to the image filing device of Patent Document 1, when performing mirror processing (processing that converts left-right center line as a reference) or rotation processing of multi-value (8-bit) color image data, each line of RGB The arrangement order of is disturbed. Further, when reading color image data, a line gap occurs in each line of RGB. However, Patent Document 1 does not describe means for suppressing disorder in the arrangement order of RGB lines or line gaps.

  According to the color image processing apparatus of Patent Document 2, it is not possible to perform mirror processing or rotation processing of image data. If the CPU of the control unit operates based on the read software to perform mirror processing or rotation processing of the line-corrected image data, the mirror processing or rotation processing is realized based on the software. Therefore, it takes too much time and the burden on the CPU increases.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing apparatus capable of quickly performing mirror processing or rotation processing of image data and line correction.

  According to the present invention, a first storage unit that stores image data including a plurality of lines, a second storage unit that stores image data including a plurality of lines, and a transfer unit for transferring image data A first receiving unit that receives an instruction about the number of lines included; a second receiving unit that receives an instruction about the number of line gaps included in the image data; and The number of lines is acquired from the reception unit, and the image data is swapped for each swap unit including the number of bits included in one pixel of the image data, and set for each bit number corresponding to the transfer bus width for the image data. Transfer control means for transferring to the second storage means while decrementing the address to be transferred within the transfer unit consisting of the number of lines, and image data stored in the second storage means A line for acquiring, acquiring the number of lines from the first receiving unit, acquiring the number of line gaps from the second receiving unit, and rearranging the image data within a region composed of lines based on the number of lines and the number of line gaps An image processing apparatus including a correction unit is provided.

  According to this configuration, the image data stored in the first storage unit is swapped for each swap unit including the number of bits included in one pixel of the image data, and the image data according to the transfer bus width. Since the address set for each bit number can be transferred to the second storage means while being decremented within the transfer unit consisting of the number of lines received by the receiving unit, the second storing unit can perform an inversion process or The rotated image data is stored.

  Further, according to this configuration, the image data stored in the second storage unit can be rearranged within the area formed by the lines by the rearrangement unit, and thus is generated by the inversion process or the rotation process. It is possible to correct the disturbance of the line arrangement of the image data and the line gap. For this reason, according to this configuration, mirror processing or rotation processing of image data and line correction can be performed quickly.

  According to the present invention, there is provided an image processing apparatus capable of quickly performing mirror processing or rotation processing of image data and line correction.

  In the image processing apparatus according to the present invention, the transfer control means obtains a read address from the read address generation means, a read address generation means for generating a read address of the image data read from the first storage means, and reads out the read address. Data reading means for reading image data from the first storage means based on the address; swap means for swapping image data read for each swap unit comprising the number of bits included in one pixel of the image data; Write address generation means for generating a write address of image data to be written to the storage means, and an image obtained by acquiring the write address from the write address generation means and swapped to the second storage means based on the write address Data writing means for writing data, and one of the read address generating means or the write address generating means Can be the receiving unit acquires the number of the line from constituting an address of the image data so as to generate an address decrement in the transfer unit composed of the number of lines.

  According to this configuration, one of the read address generation unit or the write address generation unit acquires the number of lines from the first receiving unit, and decrements the address of the image data within the transfer unit including the number of lines. Therefore, the image data can be reversed or rotated while suppressing the load on the CPU.

  The image processing apparatus according to the present invention further includes an image type determination unit that determines whether the image data is color image data or monochrome image data, and the swap means includes the image type determination unit that stores the image data. When it is determined that the image data is color image data, the image data is swapped for each 8-bit swap unit. When the image type determination unit determines that the image data is monochrome image data, the image data is 1 bit. The image data can be swapped for each swap unit.

  According to this configuration, based on the determination of the image type determination unit, the image data is swapped for each 8-bit swap unit in the case of color image data, and the 1-bit swap unit in the case of monochrome image data. Each image data can be swapped. For this reason, it is possible to transfer the image data by a method according to the image type. As a result, with either a simple configuration, either color image data or monochrome image data can be selected and inverted or rotated.

  In the image processing apparatus according to the present invention, the read address generation means can be configured to generate an address of image data read from the first storage means every 16 bits.

  According to this configuration, it is possible to invert or rotate image data at high speed by effectively using a bus having a 16-bit width often used in an image processing apparatus such as a FAX.

  In the image processing apparatus according to the present invention, the line correction unit obtains the number of lines from a first receiving unit, and a line arrangement reversing unit that reverses the arrangement of the lines of the image data within an area composed of the number of lines. Line gap correction means for obtaining the number of line gaps from the second receiving unit and moving the arrangement of the individual lines in one direction by the number of line gaps corresponding to the individual lines may be included.

  According to this configuration, the hue arrangement of the image data in which the hue arrangement is reversed by the line arrangement reversing means for reversing the arrangement of the lines in the region composed of the number of lines acquired from the first receiving unit. Even if it is reversed again, it can be restored. Further, the line gap of the image data can be eliminated by the line gap correction means that moves the arrangement of the individual lines in one direction by the number of line gaps corresponding to the individual lines.

  In the image processing apparatus according to the present invention, the image data is image data including a plurality of blocks composed of a plurality of lines having different hues, and the line correction unit is configured to arrange the hues in the blocks by the transfer control unit. May be configured to rearrange the lines of image data formed by reversing the image data and to reverse the color arrangement in the block.

  According to this configuration, the image data can be decremented within a transfer unit consisting of the number of lines received by the receiving unit while being swapped for each swap unit consisting of the number of bits included in one pixel of the color image data. For this reason, the arrangement of each color line such as RGB is disturbed during transfer, but the arrangement of each color line can be corrected when performing line correction. As a result, it is possible to quickly perform color image mirror processing or rotation processing and line correction while suppressing deterioration in image quality.

  In the image processing apparatus according to the present invention, the first receiving unit presents to the operator to select either mirror processing or rotation processing of the image data, and receives an instruction from the operator to select the mirror processing. When the transfer unit is set to a line of multiples of 3 and an instruction to select the rotation process is received from the operator, the transfer unit can be set to one page of image data.

  Alternatively, in the image processing apparatus according to the present invention, the first receiving unit presents to the operator to select either mirror processing or rotation processing of the image data, and instructs the operator to select the mirror processing. Can be configured such that the transfer unit is set to one line, and the transfer unit is set to one page of image data when an instruction to select rotation processing is received from the operator.

  Alternatively, in the image processing apparatus according to the present invention, the first receiving unit presents to the operator to select either mirror processing or rotation processing of the image data, and instructs the operator to select the mirror processing. Can be configured such that the transfer unit is set to one page of image data, and the transfer unit is set to one page of image data when an instruction to select rotation processing is received from the operator.

  According to these configurations, when either mirror processing or rotation processing is received, appropriate image processing according to the received instruction can be performed by simple processing for setting the number of lines.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a functional block diagram showing the configuration of the image processing apparatus according to this embodiment. In the present embodiment, the image processing apparatus 200 is a color image processing apparatus and has a scanner function and a copy function. FIG. 1 shows the main elements relevant to the present invention.

  Although not shown, the image processing apparatus 200 has a configuration provided in a normal complex type copying machine such as a paper feeding unit or a printing unit. Further, the image processing apparatus 200 may further include a communication function such as a fax communication function, and a configuration for that purpose may be provided. The image processing apparatus 200 performs mirror processing of multi-value (8-bit) color data (processing to convert left-right symmetrically with respect to the left-right center line) or rotation processing (processing to rotate 180 ° with respect to the center point). The image processing apparatus 200 can also perform mirror processing or rotation processing of binary (1 bit) monochrome data. Note that the bus width of the image bus 201 and the system bus 203 is 16 bits. That is, the amount of data (bus width) that can be transferred simultaneously on the image bus 201 and the system bus 203 is 16 bits.

  More specifically, the image processing apparatus 200 includes an image memory 215 (first storage unit) that stores image data including a plurality of lines, and a first system memory 212 that stores image data including a plurality of lines. (Second storage means). The image processing apparatus 200 also includes a first receiving unit 214 (operation panel) that receives an instruction about the number of lines included in a transfer unit when transferring image data, and an instruction about the number of line gaps included in the image data. And a second receiving unit 204 (line gap number setting unit).

  The image processing device 200 acquires image data from the image memory 215, acquires the number of lines from the first reception unit 214, and stores the image data for each swap unit including the number of bits included in one pixel of the image data. A transfer control unit 218 that swaps and transfers the image data to the first system memory 212 while decrementing the address set for each bit number corresponding to the transfer bus width within the transfer unit consisting of the number of lines. Prepare. Further, the image processing apparatus 200 acquires image data stored in the first system memory 212, acquires the number of lines from the first reception unit 214, and acquires the number of line gaps from the second reception unit 204. A line correction unit 210 is provided for acquiring and rearranging image data within an area composed of lines based on the number of lines and the number of line gaps. In addition, the image processing apparatus 200 includes a spare second system memory 216 and the like.

  The image data acquisition unit 202 has a scanner function and reads an original to generate RGB color image data (hereinafter, RGB data). Here, the image data acquisition unit 202 reads an image within an area composed of predetermined lines. As will be described later, the image data acquisition unit 202 is provided with a line image sensor composed of a CCD for each color of R, G, and B that is slightly shifted in the sub-scanning direction in parallel. Since this type of image data acquisition unit 202 is provided with line image sensors of each color in this way, it is difficult to physically read the colors of the same line on the document simultaneously. For this reason, in the image data acquired by the image data acquisition unit 202, a line gap is generated in an area composed of lines of each color.

  The image memory 215 receives and stores the RGB data read by the image data acquisition unit 202 via the image bus 201. The image memory 215 is, for example, an SDRAM.

  The transfer control unit 218 transfers the RGB data stored in the image memory 215 to the first system memory 212. When the image data is color image data and mirror processing is performed, the transfer control unit 218 transfers each of the RGB data in units of transfer composed of three lines. Note that data transfer from the image memory 215 to the first system memory 212 is performed via the image bus 201 and the system bus 203. The first system memory 212 is, for example, an SDRAM. The first system memory 212 has a plurality of banks each storing R data, G data, and B data transferred from the image memory 215.

  The first reception unit 214 presents to the operator via a liquid crystal screen (not shown) or the like to select either image data mirror processing or rotation processing. When the first receiving unit 214 receives an instruction to select mirror processing from the operator, the first receiving unit 214 sets the transfer unit to one line or more (for example, three lines including one line for each of RGB), and transfers the set value. To the unit 218. When the first receiving unit 214 receives an instruction from the operator to select the rotation process, the first receiving unit 214 sets the transfer unit to the number of lines included in the image data (that is, for each page of the image data) and transfers the set value. It transmits to the control part 218.

  FIG. 2A is a functional block diagram illustrating a detailed configuration of the transfer control unit 218 of the image processing apparatus according to the embodiment. The transfer control unit 218 acquires a read address from the read address generation unit 221 and a read address generation unit 221 that generates an address of data to be read from the image memory 215, and reads out image data from the image memory 215 based on the read address A reading unit 231. Further, the transfer control unit 218 obtains a write address from the write address generation unit 223 and a write address generation unit 223 that generates an address of data to be written to the first system memory 212, and based on the write address A data writing unit 233 that writes image data to the first system memory 212.

  In the transfer control unit 218, one of the read address generation unit 221 or the write address generation unit 223 obtains the number of lines included in the transfer unit from the first reception unit 214, and sets the address of the image data as the number of lines. The decremented address is generated within the transfer unit consisting of:

  The read address generation unit 221 reads R data, G data, and B data stored in the same bank in the image memory 215 as a series of RGB data. The write address generation unit 223 writes the RGB data to the same bank in the first system memory 212. At this time, the read address generation unit 221 and the write address generation unit 223 generate the address of the image data read from the image memory 215 every 16 bits.

  The data reading unit 231 and the data writing unit 233 constitute a DMA controller 219 (direct memory access controller). In addition, when the central processing unit 225 receives an instruction about the inversion or rotation process from the first reception unit 214, the central processing unit 225 transmits the instruction to the read address generation unit 221 and the write address generation unit 223 to transmit these components. To control.

  Note that Direct Memory Access (DMA) means a technique for moving data from one place in the computer to another place without interference from the central processing unit (CPU). The DMA controller 219 can increment or decrement the address at each DMA transfer or not change it, so the memory block is cleared with a specific value, such as memory-to-memory transfer with the data order reversed. Or data transfer with a memory mapped I / O is possible.

  FIG. 2B is a functional block diagram illustrating a detailed configuration of the line correction unit 210 of the image processing apparatus according to the embodiment. The line correction unit 210 includes an RGB line inversion processing unit 241 that inverts the arrangement of three lines each composed of one RGB line included in the image data. The line correction unit 210 includes a line gap correction unit 243 that reduces the RGB line gap by moving the lines downward by the number of line gaps for each of the RGB lines. When the central processing unit 245 receives an instruction from the first receiving unit 214 regarding the number of lines in the unit for decrementing the address, the central processing unit 245 instructs the RGB line inversion processing unit 241 to specify the number of lines (for example, from one RGB line). Control is performed by transmitting an instruction to invert the line every three lines. When the central processing unit 245 receives an instruction set in advance for the number of line gaps of the image data acquisition unit 202 from the second reception unit 204, the central processing unit 245 transmits this instruction to the line gap correction unit 243 to control it.

  FIG. 3 is a functional block diagram showing a detailed configuration of the image data acquisition unit 202 of the image processing apparatus 200 according to the present embodiment. The image data acquisition unit 202 includes a B signal processing unit, a G signal processing unit, and an R signal processing unit.

  The R signal processing unit includes a CCD (R) sensor 301a, an analog front end (AFE) circuit 302a, and an A / D converter 303a. The G signal processing unit includes a CCD (G) sensor 301b, an analog front end (AFE) circuit 302b, and an A / D converter 303b. The B signal processing unit includes a CCD (B) sensor 301c, an analog front end (AFE) circuit 302c, and an A / D converter 303c.

  The operation of the image processing apparatus according to this embodiment will be described below. FIG. 4 is a flowchart for explaining the operation of the image processing apparatus 200 according to the embodiment. When the operator of the image processing apparatus 200 inputs an instruction to perform copying to the first reception unit 214, the first reception unit 214 transmits this instruction to the image data acquisition unit 202. Upon receiving this instruction, the image data acquisition unit 202 scans a sheet or the like placed on the document table, acquires RGB format image data, and stores it in the image memory 215.

  If the first reception unit 214 has received an instruction to perform mirror processing or rotation processing before receiving an instruction to perform copying, the first reception unit 214 transmits the instruction to the central processing unit 225 of the transfer control unit 218. To do. When the central processing unit 225 receives an instruction to perform mirror processing or rotation processing (S101), the central processing unit 225 controls the read address generation unit 221 and stores it in the image memory (image memory 215). A read address in which the image data write end address (Bm-n address) is set as the transfer source address (transfer start address) N is generated (S102). On the other hand, the case where the mirror process or the rotation process is not performed will be described later.

  Next, the data reading unit 231 of the transfer control unit 218 acquires the read address from the read address control unit, and reads image data from the image memory 215 based on the read address. At this time, the image data is read from address N (S103). Thus, in order to read the image data from the end address, the address of the image data is decremented. Specifically, when the image data read from the image memory 215 is DMA-transferred, R0-1 to Bm-n in FIG. 7, which will be described later, is one line, and the address where Bm-n is stored is set. This is the transfer start address.

  Specifically, the central processing unit 225 of the transfer control unit 218 acquires an instruction regarding the number of lines in the transfer unit from the first reception unit 214. The central processing unit 225 transmits to the read address generation unit 221 an instruction to decrement the address of the image data within the area composed of the acquired number of lines in the transfer unit. The read address generation unit 221 that has acquired the instruction decrements the address of the image data within an area having the specified number of lines. The data reading unit 231 that has acquired the decremented address in the area having the designated number of lines reads the image data from the image memory 215 based on the acquired address.

  At this time, the first accepting unit 214 presents to the operator via the liquid crystal screen (not shown) or the like to select either image data mirroring or rotation (S105). Then, when receiving an instruction to select mirror processing from the operator, the first receiving unit 214 sets the transfer unit to three lines including one line for each of RGB (S107). In addition, when the first reception unit 214 receives an instruction to select rotation processing from the operator, the first reception unit 214 sets the transfer unit to the total number of lines constituting the page of image data (S109).

  Next, the DMA controller 219 performs byte swap for the read image data for each predetermined number of bits or bit swap for each bit. At this time, the central processing unit 225 determines whether the read image data is color image data or monochrome image data (S104). When the central processing unit 225 determines that the read image data is color image data, the image data is byte-swapped for each byte (swap unit) consisting of the number of bits (8 bits) constituting the RGB pixel. (S106). On the other hand, when the central processing unit 225 determines that the read image data is monochrome image data, the central processing unit 225 converts the image data into bits for each bit (swap unit) consisting of the number of bits (1 bit) constituting the monochrome pixel. Swap (S108).

  In summary, the swap processing and the DMA unit at the time of transfer are processed by a combination as shown in Table 1 below according to the processing contents.

  As described above, the image data is structured in such a manner that the image data is byte-swapped for each predetermined number of bits or bit-swapped for each bit, and the address is decremented within the area composed of the number of lines in the transfer unit. FIG. 7 shows a change as shown in FIG. FIG. 7 is a data structure diagram showing changes in the data structure of the image data due to the operation of the transfer control unit of the image processing apparatus according to the present embodiment. That is, when color image data is mirrored, the address of the image data is decremented within a three-line area consisting of one RGB line, and the RGB pixels of the image data are byte-swapped every 8 bits. It is a figure which shows the change of a data structure.

  In FIG. 7, Rm-n, Gm-n, and Bm-n represent red, green, and blue color component signals of the mth and nth pixels from the left in the case of multi-valued color data. Here, the address of the image data is decremented within an area consisting of a predetermined number of lines (3 lines each consisting of RGB), and the RGB pixels of the image data are byte-swapped every 8 bits, so that each of the RGB data The relative positions of the RGB lines in the block consisting of three lines are reversed. In any line, the left and right arrangements of the pixel data are inverted.

  The bit / byte swap function means a function for switching the data order in bit units / byte units. That is, the data is defined as D [15: 0] (D [15, 14,..., 1, 0]). In this case, if this data is bit-swapped, D [0:15] is obtained. On the other hand, when byte swapping is performed with 8 bits as 1 byte, D [7: 0, 15: 8] is obtained.

  Next, the central processing unit 225 controls the write address generation unit 223 to read out the byte-swapped or bit-swapped image data read by the address decremented within a predetermined transfer unit. Write addresses that remain in address order are generated. Further, the data writing unit 233 that has acquired the write address transfers the image data to the transfer destination (S111). That is, the image data is written into the first system memory 212.

  The central processing unit 225 checks whether image data for which DMA transfer is no longer completed remains in the image memory 215, and ends DMA transfer if it does not remain (S113). On the other hand, if image data for which DMA transfer has not been completed still remains, N = N−1 (S115), that is, the address to be read is decremented, and the data reading unit 231 of the transfer control unit 218 is further decremented. Reads out the N address (N-1 address) of the image data from the image memory 215 (S103). Thereafter, similar steps are repeated until the DMA transfer is completed. In this case, when proceeding to the next RGB, the DMA transfer may be temporarily ended, the next Bm-n address may be newly input to N, and the DMA transfer may be started again.

  FIG. 5 is a flowchart for explaining the operation of the image processing apparatus according to the embodiment. On the other hand, in the case where the mirror process or the rotation process is not performed in step 101, the write start address (R0-1) of the image memory is set as the transfer source address (transfer start address) N (S121). Similarly to the above, the data reading unit 231 of the transfer control unit 218 reads the N address of the image data from the image memory 215 (S123), and the data writing unit 233 writes the image data to the first system memory 212. Thus, the image data is transferred to the transfer destination (S125). In this transfer process, the image data is transferred in the same address order without decrementing the address.

  Then, when the DMA transfer ends, the central processing unit 225 ends the operation of the transfer control unit 218 (S127). On the other hand, if image data for which DMA transfer has not been completed still remains, N = N + 1 is set (S129), and the data reading unit 231 of the transfer control unit 218 further stores the image data N from the image memory 215. The address (N + 1 address) is read (S123). Thereafter, similar steps are repeated until the DMA transfer is completed. At this time, when proceeding to the next RGB, the DMA transfer is once ended, the address of the next R0-1 is newly input to N, and the DMA transfer is started again.

  After performing the DMA transfer operation as described above, the line correction operation is performed as follows. FIG. 6 is a flowchart for explaining the operation of the line correction unit 210 of the image processing apparatus according to the embodiment. The line correction unit 210 sequentially performs line correction processing for each block including three lines of one RGB. When the central processing unit 245 of the line correction unit 210 acquires information indicating that the image data has been transferred to the first system memory 212 by the transfer control unit 218 by searching the first system memory 212. The line correction processing for the first block (n = 1) in the first system memory 212 is started (S301).

  When the line correction processing is started, the central processing unit 245 reads out the 3n-th row data from the image data bank in the first system memory 212 (S303), and the RGB line inversion processing unit 241 and the line gap correction are read out. In cooperation with the unit 243, data is written to the 3n-2th row of the bank in the second system memory 216 (S305).

  The RGB line inversion processing unit 241 and the line gap correction unit 243 are program modules loaded in a memory provided adjacent to the central processing unit 245. The two modules are combined to form one program, and the central processing unit 245 executes the algorithm shown in FIG. 6 based on the algorithm of this program.

  Regarding the R line as a reference for eliminating the line gap, the central processing unit 245 and the RGB line inversion processing unit 241 cooperate to move to a line on two lines, thereby reversing by transfer and BGR. The hue array that has become the array is returned to the position corresponding to the original RGB array.

  Next, the central processing unit 245 reads the 3n-1 line data from the bank of image data in the first system memory 212 (S307), and cooperates with the RGB line inversion processing unit 241 and the line gap correction unit 243. Then, data is written in the (3n-1) + 6th row of the bank in the second system memory 216 (S309).

  From the beginning when the image data acquisition unit 202 has acquired, the G line has a line gap of two blocks (the text of the line 6) with respect to the R line. As for the G line, even if the RGB array is inverted to the BGR array, the relative position in the block is maintained. For this reason, the central arithmetic processing unit 245 and the line gap correction unit 243 cooperate to move to the line 6 lines below, thereby eliminating the line gap for the G line.

  Next, the central processing unit 245 reads the 3n-2nd row data from the image data bank in the first system memory 212 (S311), and cooperates with the RGB line inversion processing unit 241 and the line gap correction unit 243. Then, data is written to the (3n−2) + 2 + 12th row of the bank in the second system memory 216 (S313).

  From the beginning when the image data acquisition unit 202 has acquired, the B line has a line gap of four blocks (the text of the line 12) with respect to the R line. As for the B line, the relative position in the block is inverted as the RGB array is inverted to the BGR array. For this reason, the central processing unit 245, the RGB line inversion processing unit 241 and the line gap correction unit 243 cooperate to move to the line 2 lines + 12 lines, thereby eliminating the line gap for the B line. The hue array that has been inverted by transfer to become the BGR array is returned to the position corresponding to the original RGB array.

  As described above, when the image data is transferred while being inverted by the transfer control unit 218, and the lines are rearranged by the line correction unit 210, the data structure of the image data changes as shown in FIG. FIG. 8 is a data structure diagram showing a change in the data structure of the image data due to the operation of the image processing apparatus according to the present embodiment.

  In FIG. 8, R (Ri-Lj), G (Gi-Lj), and B (Bi-Lj) are arranged in accordance with the order (i-th) acquired in the image data initially acquired by the image data acquisition unit 202. Thereafter, in a state in which the line gap is eliminated as a result of the line correction processing by the line correction unit 210, it is the jth line from the top, and represents a line composed of signals of red, green, and blue color components of the pixel.

  Here, by the transfer process of the transfer control unit 218, the address of the image data is decremented within an area consisting of a predetermined number of lines (three lines each consisting of one RGB line), and the RGB pixels of the image data are byte converted every 8 bits. As a result of the swapping, the relative positions of the RGB lines in the block composed of three lines for each of RGB are reversed. In any line, the left and right arrangements of the pixel data are inverted.

Then, the transferred image data is restored to the original relative position of the RGB line by appropriately inverting the relative position of the RGB line or correcting the line gap by the line correction unit 210. The entire line gap has been eliminated.
The effects of the image processing apparatus of this embodiment will be described below.

  First, according to the image processing apparatus 200, mirror processing or rotation processing of image data and line correction can be quickly performed. That is, in the transfer control unit 218, if the address of the image data is decremented within an area consisting of a predetermined number of lines (three lines each consisting of RGB), and the RGB pixels of the image data are byte-swapped every 8 bits, Mirror processing can be performed. In addition, the transfer control unit 218 decrements the address of the image data within the area of the page unit (for every total number of lines constituting the page), and byte swaps the RGB pixels of the image data every 8 bits. It can be carried out. In the mirror process, the RGB array is inverted to become a BGR array, but the line correction unit can return the BGR array to the RGB array to eliminate the line gap that the image data originally has. Therefore, according to the image processing apparatus 200, it is possible to suppress the deterioration of the image quality of the image data associated with the DMA transfer process, and to improve the image quality by eliminating the line gap.

  Secondly, according to the image processing apparatus 200, it is possible to quickly execute the inversion processing or rotation processing of the image data. That is, the transfer control unit 218 causes the DMA (direct memory access controller) to perform transfer processing substantially, so that bit swap or byte decrementing is performed more quickly than transfer of image data using a CPU and software. Can be swapped. Therefore, high-speed and accurate image data inversion processing or rotation processing can be performed.

  Third, according to the image processing apparatus 200, the circuit arrangement can be simplified. That is, the line correction unit 210 is a mechanism in which an image data correction program that is a combination of two types of components, the RGB line inversion processing unit 241 and the line gap correction unit 243, and the central processing unit 245 cooperate. For this reason, the central processing unit 245 can read the image data correction program and execute the image data correction program, so that the image data can be rearranged within an area composed of lines. Therefore, since line correction is performed by software, a complicated circuit arrangement for performing line correction is not required, and the circuit arrangement of the image processing apparatus 200 can be simplified.

  Also, at this time, the LSI DMA function provided in a normal composite type copier has a 16-bit width decrement function in address control and a byte / bit swap function in data control. Realizes high-speed mirror processing or rotation processing of color data. For this reason, the function provided for general purposes can be used effectively for mirror processing of color data. Also from this viewpoint, the circuit arrangement of the image processing apparatus 200 can be simplified. Further, according to the image processing apparatus 200, the same effect can be obtained even in the case of monochrome data.

  On the other hand, in order to explain the operational effects of the image processing apparatus 200, an image processing apparatus having a structure different from that of the present embodiment will be described as follows. That is, in the image processing apparatus having a structure different from that of the present embodiment, the line gap of the image data is first eliminated, and then the address is decremented while transferring the image data.

  In this case, the line-corrected image data from the image memory 215 is converted from a video signal from the CCD into multi-value data of 8 bits per pixel, and the converted data is stored in the first system memory 212 in units of 2 pixels (16 bits). When data is transferred (because the bus width is 16 bits), when data is read from the image memory 215, the RGB array of the image data is inverted to the BGR array. For this reason, when a means for returning the BGR arrangement to the RGB arrangement after the transfer of the image data is provided as a circuit configuration, the entire apparatus configuration becomes complicated. Further, when the same means is provided as software for realizing the mirror process, the processing time of the image data becomes longer.

  On the other hand, the image processing apparatus 200 has a function of storing color data read in units of 16 bits of 2 pixels in the image memory 215 when performing mirror processing of multi-value (8 bits) color data. The DMA controller 219 provided in the LSI has a decrement function for address control with respect to the image memory 215 having a 16-bit width, and a bit / byte swap function for data control.

  Then, DMA transfer is performed using the line end address (line end address when RGB is one line) as a transfer start address to the image memory 215 in which RGB data is stored in a state where there is a line gap. DMA transfer is performed while the address is decremented. In DMA transfer, data is byte-swapped.

  Thereby, mirror processing can be realized in each line of RGB. However, the RGB order is reversed in the sub-scanning direction. That is, since the RGB including the line gap is mirrored, the BGR including the line gap is obtained. This needs to be RGB data in which the main scanning data is a mirror and there is no line gap.

  The order reversed in the sub-scanning direction can be returned to the original order in the post-process line gap correction. That is, the line operation is performed in consideration of the line order changing process of BGR → RGB (sub-scanning direction) and the line gap correction process. Any of these line operations can be processed by software. For this reason, it is not necessary to add a new circuit for correcting the order in the sub-scanning direction.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, in the above-described embodiment, data read from the image memory 215 (on the image bus 201) is transferred to the first system memory 212 (on the system bus 203) as it is without being encoded, and line correction processing is performed. Is done. Then, the data is transferred to an external terminal (PC) as it is (unencoded), displayed on a liquid crystal display, etc., color printed by a printing unit, or transmitted over the Internet. However, after line correction, it is not intended to exclude encoding or the like, but after encoding or JPEG compression through JPEG LSI, encoded image data may be used similarly. .

  In the above-described embodiment, the transfer unit by DMA in the case of performing color image mirror processing is a transfer unit of three lines of one RGB, but there is no particular limitation. For example, the transfer unit by DMA may be one line for each of RGB instead of three lines for RGB. That is, the start address of the transfer unit by the first DMA can be set as the last address of the R line. In this case, when writing the image data transferred from the transfer source image memory 215 to the transfer destination first system memory 212, if an address considering the line gap is set as the transfer destination address, the written image data is The image data is subjected to line gap correction. Therefore, the line correction process by software can be omitted.

  Alternatively, the transfer unit by DMA may be an integral multiple (two times or more) of the RGB, instead of the three RGB lines. That is, the transfer unit by DMA may be a total of 6 lines of RGBRGB or a total of 9 lines. At this time, the start address of the transfer unit by the first DMA can be the last address of the second B line in the case of a total of 6 lines of RGBRGB. In this case, since the number of times of transfer by DMA is reduced, the transfer process is simplified. Therefore, it is possible to invert or rotate the image data even faster and more accurately.

  Further, the transfer unit by DMA may be the number of lines constituting one page of image data instead of the three lines including RGB. That is, the start address of the transfer unit by the first DMA can be the last address of the last B line of one page of image data. In this case, by configuring the transfer source image memory 215 and the transfer destination system memory 212 to have a capacity of one page, DMA transfer of data of one page of image data can be performed smoothly. In this case, since the number of times of transfer by DMA is only once per page, the transfer process is simplified. Therefore, it is possible to invert or rotate the image data even faster and more accurately.

1 is a functional block diagram illustrating a configuration of an image processing apparatus according to an embodiment. 3 is a functional block diagram illustrating a detailed configuration of a transfer control unit and a line correction unit of the image processing apparatus according to the embodiment. FIG. It is a functional block diagram which shows the detailed structure of the image data acquisition part of the image processing apparatus which concerns on embodiment. 5 is a flowchart for explaining an operation of a transfer control unit of the image processing apparatus according to the embodiment. 5 is a flowchart for explaining an operation of a transfer control unit of the image processing apparatus according to the embodiment. It is a flowchart for demonstrating operation | movement of the line correction part of the image processing apparatus which concerns on embodiment. FIG. 6 is a data structure diagram showing a change in the data structure of image data by the operation of the transfer control unit of the image processing apparatus according to the embodiment. It is a data structure figure which shows the change of the data structure of the image data by operation | movement of the image processing apparatus which concerns on embodiment. It is a functional block diagram for demonstrating the structure of the conventional image filing apparatus. It is a functional block diagram for demonstrating the structure of the conventional color image processing apparatus.

Explanation of symbols

31a CCD (R) sensor 31b CCD (G) sensor 31c CCD (B) sensor 32 CPU
32a Analog front end circuit 32b Analog front end circuit 32c Analog front end circuit 33a A / D converter 33b A / D converter 33c A / D converter 34 Line correction unit 40 DMA controller 44 Interface 46 Interface 50 Disk device 52 Plate making process Workstation 200 Image processing device 201 Image bus 202 Image data acquisition unit 203 System bus 204 Second reception unit 210 Line correction unit 212 First system memory 214 First reception unit 215 Image memory 216 Second system memory 218 Transfer Control unit 219 DMA controller 221 Read address generation unit 223 Write address generation unit 225 Central processing unit 231 Data read unit 233 Data write unit 241 RGB line inversion processing unit 2 3 Line gap correction unit 245 Central processing unit 301a CCD (R) sensor 301b CCD (G) sensor 301c CCD (B) sensor 302a Analog front end (AFE) circuit 302b Analog front end (AFE) circuit 302c Analog front end (AFE) ) Circuit 303a A / D converter 303b A / D converter 303c A / D converter

Claims (9)

First storage means for storing image data including a plurality of lines;
Second storage means for storing image data including a plurality of lines;
A first receiving unit that receives an instruction about the number of lines included in a transfer unit when transferring the image data;
A second receiving unit for receiving an instruction about the number of line gaps included in the image data;
The image data is acquired from the first storage means, the number of lines is acquired from the first receiving unit, and the image data is acquired for each swap unit including the number of bits included in one pixel of the image data. Transfer control means for swapping and transferring the image data to the second storage means while decrementing an address set for each bit number corresponding to the transfer bus width within the transfer unit consisting of the number of lines. ,
The image data stored in the second storage means is acquired, the number of lines is acquired from the first reception unit, the number of line gaps is acquired from the second reception unit, and the number of lines And line correction means for rearranging the image data in an area consisting of the lines based on the number of line gaps,
An image processing apparatus comprising: The image processing apparatus according to claim 1.
The transfer control means includes
Read address generation means for generating an output address of image data read from the first storage means;
Data read means for obtaining the read address from the read address generating means and reading the image data from the first storage means based on the read address;
Swap means for swapping the read image data for each swap unit comprising the number of bits included in one pixel of the image data;
Write address generation means for generating a write address of image data to be written to the second storage means;
Data writing means for acquiring the write address from the write address generating means, and writing the swapped image data in the second storage means based on the write address;
Including
One of the read address generation unit or the write address generation unit obtains the number of lines from the first reception unit, and decrements an address of the image data within the transfer unit including the number of lines. An image processing apparatus configured to generate the image processing apparatus. The image processing apparatus according to claim 2,
An image type determination unit for determining whether the image data is color image data or monochrome image data;
When the image type determination unit determines that the image data is color image data, the swap means swaps the image data for each swap unit of 8 bits, and the image type determination unit An image processing apparatus configured to swap the image data for each swap unit of 1 bit when determining that the image data is monochrome image data. The image processing apparatus according to claim 2 or 3,
The image processing apparatus, wherein the read address generation means is configured to generate an address of image data read from the first storage means every 16 bits. The image processing apparatus according to claim 1,
The line correction means includes
Line arrangement reversing means for obtaining the number of lines from the first receiving unit, and reversing the arrangement of the lines of the image data in an area consisting of the number of lines;
Line gap correction means for acquiring the number of line gaps from the second receiving unit and moving the arrangement of the individual lines in one direction by the number of line gaps corresponding to the individual lines;
An image processing apparatus comprising: The image processing apparatus according to claim 1,
The image data is image data including a plurality of blocks composed of a plurality of mutually different hue lines,
The line correction unit is configured to rearrange the lines of the image data obtained by reversing the hue arrangement in the block by the transfer control unit, and to reverse the hue arrangement in the block. An image processing apparatus. The image processing apparatus according to claim 1,
The first reception unit is
When the operator is instructed to select either mirror processing or rotation processing of image data and receives an instruction to select mirror processing from the operator, the transfer unit is set to a number of lines of multiples of 3. An image processing apparatus configured to set the transfer unit to one page of the image data when receiving an instruction to select rotation processing from an operator. The image processing apparatus according to claim 1,
The first reception unit is
When the operator is instructed to select either mirror processing or rotation processing of image data and receives an instruction to select mirror processing from the operator, the transfer unit is set to one line, and rotation processing is performed from the operator. An image processing apparatus configured to set the transfer unit to one page of the image data when receiving an instruction to select. The image processing apparatus according to claim 1,
The first reception unit is
When the operator is instructed to select either mirror processing or rotation processing of image data and receives an instruction from the operator to select mirror processing, the transfer unit is set to one page of the image data, and the operator An image processing apparatus configured to set the transfer unit to one page of the image data when receiving an instruction to select a rotation process from.

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